Sony CXD1958Q Datasheet

MMDS TCM/QAM Demodulator + FEC + ADC

Description

The CXD1958Q is an integrated TCM/QAM demodulator for MMDS systems using the DAVIC MMDS standard. This highly integrated device incorporates an internal 8-bit ADC, image rejection and root-raised cosine filters, all-digital symbol timing recovery PLL, adaptive decision feedback equalizer (DFE) with 10 feedforward and 30 feedback taps, 4-D TCM decoder, and DAVIC/DVB compliant forward error correction comprising (204,188) Reed Solomon decoder, a programmable de-interleaver with I = 12 and I = 204, and a de-randomiser. All internal clocks are generated from a single external 30MHz reference crystal.

Device functionality also includes 3-wire bus interface for configuring up to 2 tuner synthesizers, a sigma delta tuner IF-AGC output, a user programmable RFAFC sigma delta output, spectrum inversion of the received signal for tuner compatibility, and a highly configurable MPEG2-TS interface. An I2C bus interface provides on-board configuration and status monitoring of various functions including access to the equalizer tap values and constellation points. JTAG provides boundary scan test compatibility.

Features

• DAVIC MMDS V1.1 and V1.3 compliant

• Supports 16, 64 and 256QAM

• Supports 16, 64 and 256 TCM

• Internal 8-bit ADC

• Interface for 10-bit external ADC

• 36.125MHz nominal IF input

• Symbol rate range 5 – 5.304Mbaud in 6MHz

channels

• Integrated matched filtering with 0.15 roll-off factor

• ±400KHz internal carrier offset compensation with

negligible losses @ 5Mbaud 6MHz channel

• Symbol timing loop designed to acquire with large

offsets. Negligible losses for ±100ppm offsets

• All internal clocks derived from single fixed frequency crystal (30MHz)

• Supports fast re-acquisition mode

• 6µs echo cancellation @ 5Mbaud

• Constellation points and equalizer tap values

readable via I2C bus

• C/N estimation readable via I2C bus

• Low implementation loss for AWGN only:

0.5dB @ 64QAM (using internal 8-bit A/D);

0.3dB @ 256QAM (excluding A/D); measured at BER of 3x10–4Pre R/S

• I = 12 and I = 204 de-interleaving

• Fast I2C bus compatible control interface

• Tuner IF-AGC output

• User programmable tuner RF-AGC output

• Dedicated 3-wire bus interface to configure up to 2

tuner synthesizers

• 3.3V CMOS technology

• Supports JTAG boundary scan

• 100-pin QFP package

Applications

MMDS set-top boxes

– 1 –

PE99906-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD1958Q

100 pin QFP (Plastic)

Preliminary

– 2 –

CXD1958Q

Pin Configuration

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

8182

8384

8586

878889

9091

929394

969798

100

50494847464544434241403938

363534333231

TEVAL9 TEVAL8 TEVAL7 TEVAL6 TEVAL5

DVSS TEVAL4 TEVAL3 TEVAL2 TEVAL1 TEVAL0

DVSS

TDO

TSVALID

TSLOCK

DVSS

TSERR TSDATA7 TSDATA6 TSDATA5 TSDATA4

26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

TSDATA3 TSDATA2 TSDATA1 TSDATA0

DVSS

SCL

SDA

DVDD

SDATA

SCLK

SEN0

SEN1

INTRPTN

TWR_N

TDATA

TCLK

TEN

TSDISABLE

DVDD

TSSYNC

TSCLK

AVSS

DVSS

DVDD

DVSS

DTCLK

AGC

RFAGC

DVSSDVDD

RESETN

TRST

TDI

TMS

TCK

DVDDDVSS

VIN VRT VRTS AV

AVDD

AVSS AVDD AVDD VRBS VRB

AVSS AVSS DVSS XTALI XTALO

DT9 DT8 DT7 DT6 DT5 DV

DVDD

DT4 DT3

DT0 DV

DT2 DT1

Fig. 1. Pin Configuration

– 3 –

CXD1958Q

Pin Description Table 1. Pin Description

Name Pin No. Type Drive Function

XTALO

XTALI

RESETN

VRTS

VRT

VIN

VRB

VRBS

TSVALID

TSLOCK

TSERR

TSDATA[7:0]

21, 22, 23, 24, 27, 28, 29, 30

Crystal oscillator output

Crystal oscillator input

Digital Schmitt-trigger 5V tolerant Input

Analog output

Analog input

Analog output

Digital tristate output

Digital output

Digital tristate output

N/A

4mA

8mA

4mA

Crystal oscillator cell output.

Crystal oscillator cell input.

Active low hardware reset.

ADC internally generated top reference bias. This pin connects to VRT to self bias the top reference.

ADC top reference voltage. Connects to VRTS for self bias.

Analog IF input. ADC bottom reference voltage.

Connects to VRBS for self bias. ADC internally generated bottom

reference bias. This pin connects to VRB to self bias the bottom reference.

Identifies data portion of the MPEG2 transport stream packet (excludes parity bytes). The polarity and timing of this signal is programmable. Tristate following hardware reset. External pullup or pull-down resistor required.

MPEG2 transport stream lock indicator. The polarity of this signal is programmable.

MPEG2 transport stream error flag. Indicates uncorrectable errors in current packet. The polarity and timing of this signal is programmable. Tristate following hardware reset. External pullup or pull-down resistor required.

MPEG2 transport stream parallel data output. Tristate following hardware reset. External pull-up or pull-down resistor required.

Clock and Reset

ADC Interface

MPEG2 Transport Stream Interface

– 4 –

CXD1958Q

Name Pin No. Type Drive Function

TSCLK

TSSYNC

TSDISABLE

AGC

RFAGC

TEN

TCLK

TDATA

TWR_N

SEN1

SEN0

Digital tristate output

Digital Schmitt-trigger 5V tolerant input

Digital output

Digital Schmitt-trigger 5V tolerant input

Digital open-drain output

4mA

N/A

2mA

N/A

12mA

MPEG2 transport stream byte clock. The polarity and timing of this signal is programmable. Tristate following hardware reset. External pull-up or pulldown resistor required.

Indicates MPEG2 47H sync byte in transport stream packet. The polarity and timing of this signal is programmable. Tristate following hardware reset. External pull-up or pulldown resistor required.

Input to disable MPEG2-TS interface outputs. MPEG2 transport stream output pins TSDATA[7:0], TSCLK, TSSYNC, TSVALID, TSERR to be put into tristate mode if this input is asserted high. The same outputs may also be set tristate via I2C bus control.

External IF AGC control.

External RF AGC control. Host CPU control input. Can be used to

control 3-wire bus outputs SEN0 and SEN1.

Host CPU control input. Can be used to control 3-wire bus output SCLK.

Host CPU control input. Can be used to control 3-wire bus output SDATA.

Host CPU control input used to register TEN, TCLK, TDATA on rising edge and update SEN, SCLK and SDATA outputs in one mode of the 3-wire bus operation.

3-wire bus interface enable output. Polarity programmable and equivalent to polarity of SEN0. Must be pulled up by external resistor to 3.3V or 5V if used.

3-wire bus interface enable output or pass-FET contol for tuner I2C bus. Programmable polarity. Must be pulled up by external resistor to 3.3V or 5V if used.

MPEG2 Transport Stream Interface (Cont.)

Tuner Interface (Control and AGC)

– 5 –

CXD1958Q

Name Pin No. Type Drive Function

SCLK

SDATA

SDA

SCL

INTRPTN

DT[9:0]

DTCLK

TRST

TDO

TDI

TMS

TCK

TEVAL[9:0]

63, 62, 61, 60, 59, 56, 55, 54, 53, 52

96 1, 2, 3, 4,

5, 8, 9, 10, 11, 12

Digital open-drain output

Digital bi-directional open-drain output Schmitt trigger 5V tolerant input

Digital Schmitt trigger 5V tolerant input

Digital CMOS input

Digital open-drain output

Digital bi-directional tristate output 5V tolerant input

Digital output

Digital input with pull-up

Digital tristate output

Digital input with pull-up

Digital input

Digital output

12mA

3mA

N/A

12mA

IOL = 4mA

IOH = –2mA

8mA

N/A

4mA

N/A

4mA

3-wire bus interface clock output. Must be pulled up by external resistor to 3.3V or 5V if used.

3-wire bus interface data output. Must be pulled up by external resistor to 3.3V or 5V if used.

I2C bus data. Must be pulled up by external resistor.

I2C bus clock. Must be pulled up by external resistor.

I2C bus address (variable part)

I2C bus address (variable part) Programmable general interrupt pin.

Must be pulled up by external resistor to

3.3V or 5V.

ADC digital bypass port for connection of an external ADC.

ADC clock for use with DT[9:0].

JTAG test reset input.

JTAG test data output.

JTAG test data input.

JTAG test mode select.

JTAG test clock.

Test data bus.

Tuner Interface (Control and AGC) (Cont.)

Host Control Interface

Testability and Evaluation Interface

– 6 –

CXD1958Q

Name Pin No. Type Drive Function

DVDD

DVSS

AVSS

AVDD

6, 13, 18, 25, 33, 46, 51, 57, 64, 84, 85, 91, 99

7, 14, 19, 26, 34, 40, 47, 50, 58, 67, 83, 86, 90, 100

68, 69, 80, 81, 82

70, 71, 72, 78, 79

Power

Ground

Power

Digital supply. (+3.3V)

Digital ground. (0V)

Analog ground. (0V)

Analog supply. (+3.3V)

Power Supplies

– 7 –

CXD1958Q

Description of Functions

Symbol Number

Equalized Q

Equalized I

SCLK

RAM

SDATA SEN0 SEN1

TCLK

TDATA

TEN

XTALI

VIN

RESETn

30MHz

OSC

XTALO

RFAGC

AGC

SCL

SDA

TMS

TCK

TDI

TDO

TSDISABLE

MPEG-2 Data

Symbol Number

FEC Lost Lock

Symbol Valid

TSVALID TSCLK TSSYNC

TSLOCK TSERR INTRPTN

FEC

3-Wire Bus

Interface

Config Data

I2C bus Register

Interface

JTAG

Clock & Test

Control

Sigma

Delta

Modulator

Trellis

Decoder

40-Tap

Equalizer

Pre-

Processor

Preproc Lock

ADC

DA[9:0]

Fig. 2. Block Diagram

1. ADC

Input to the CXD1958Q is a single-ended IF signal centred at 36.125MHz. An integrated 8-bit ADC is clocked at 30MHz and used to directly band-pass sample the IF signal. The 8-bit ADC is self biased by connecting reference pins VRTS to VRT and reference pins VRBS to VRB. An option is provided to allow bypass of the internal ADC if an external converter up to 10 bits is desired.

2. Pre-Processor and Equalizer

Fig. 3. Pre-Processor and Equalizer Block Diagram

IF to

Baseband

(ITB)

From ADC

To VGA

digitised IF

Image/

Decimation

Filters

Decision

Feedback

Equalizer

To FEC Differential Decoder

To Trellis Decoder

Interpolator

PRE-PROCESSOR EQUALIZER

Matched

Filter

Decision

Device

Equalizer

Adaption

Carrier

Recovery

PLL

Various Control Signals

Automatic

Gain Control

Timing

Recovery

PLL

Correction

– 8 –

CXD1958Q

2-1. Automatic Gain Control – External

This block monitors the signal level at the output of the ADC and provides a pulse width-modulated control signal (IF-AGC) to drive an external (analog) variable gain amplifier (VGA). The polarity of this signal is I2C bus programmable. This circuit operates as an automatic gain control loop and is normally configured to maximize ADC dynamic range. Only a single external RC filter is required. It is possible to read the level being output on the IF-AGC signal via I2C bus to allow a separate RF-AGC sigma-delta output to be programmed for dual loop AGC systems.

2-2. IF to Baseband Conversion

The IF to Baseband block translates the received digitized IF signal to a complex baseband signal. Subsequent processing is performed in parallel on in-phase (I) and quadrature (Q) data paths.

2-3. Decimation Filter

Sample rate conversion in the Decimation Filter block is used to optimize the operation of the timing loop over the symbol rate range.

2-4. Timing Recovery Loop

Symbol timing recovery is implemented using an all-digital PLL comprised of Interpolator, Matched Filter and Timing Recover PLL blocks in Fig. 3. This allows the sample rate to be unrelated to the symbol rate – sampling is asynchronous. The loop operates over the range (5 – 5.304) Mbaud with minimal performance degradation, surpassing the capability of an equivalent analog loop. The matched filter implements a square-root raised cosine function, matched to the equivalent transmitter filter for rejection of intersymbol interference (ISI).

2-5. Decision Feedback Equalizer

Adaptive equalization is performed using a Decision Feedback Equalizer implementation to remove echoes arising from channel multipath characteristics and any remaining ISI not removed by the matched filter in the pre-processor. The DFE filter structure has a feedforward (10 tap) and feedback (30 tap) section. The 30 tap feedback section removes post-cursive ISI up to 6ms delay which is sufficiently robust to remove long echoes in MMDS. During acquisition of the QAM constellation, the adaptive equalizer steps through several modes of operation to achieve lock. The equalizer initially operates using a blind error signal to converge tap coefficients as no training sequence is provided in the QAM input data stream. The equalizer then switches to a decision-directed mode of operation where QAM data is used to generate the error signal to optimize convergence of tap coefficients. An all-digital PLL is implemented for removal of carrier frequency and phase offsets.

2-6. DC Correction

Modulator carrier leakage appears as a DC component in the QAM constellation which must be removed before correct decisions can be made in Decision Device block. The DC Correction block completely removes this offset.

– 9 –

CXD1958Q

2-7. Decision Device

The Decision Device block performs data slicing and symbol/bit mapping for 16, 64 and 256 QAM constellations. This block can also automatically or manually compensate for an inverted IF spectrum under I2C bus control. Modulation scheme recognition can be preset via I2C bus for fast acquisition.

2-8. Configuration and Control

Configuration and control is handled by a register bank accessible to an external processor over an I2C serial bus. A pre-processor state machine controls the initial acquisition process until synchronisation is achieved. Once the pre-processor has acquired lock to the input symbol rate the equalizer section is enabled. Once enabled, Equalizer operation is also controlled by a state machine. Once Equalizer acquisition is achieved the condition is then maintained based upon acquisition and mode control information, supplied from the configuration registers, and MPEG Transport Stream status data from the FEC block.

3. Post-Processor

Post-processing on the demodulated QAM/TCM signal implements the DAVIC MMDS standard. This includes differential decoding of the two most significant symbol bits (QAM mode only), mapping of decoded symbols onto bytes, Forney convolutional de-interleaving of the bytes (I = 12, and I = 204) to remove burst errors, Reed-Solomon (255, 239) error correction, MPEG-2 sync byte inversion and data stream de-randomization. Finally a baseband interface is included that provides an MPEG-2 compliant transport stream to the device output.

FEC Register Bank

(FRB)

Differential

Decoder

Reed Solomon Decoder

Energy

Dispersal

Removal

Baseband

Interface

BB3BB2BB1BB0

Transport

Stream Data

TCM Decoder

Sliced

Symbols

from

Equalizer

Unsliced I Q Values from

Equalizer

m-tuple mapper

& SYNC Detect

De-

Interleaver

SYNC Flag

Lost Lock

Flag

Inverted SYNC Flag

Lock Flag

BER

Figures

SYNC Detect & Loss

ISYNC Detect

BER

Measurement

Fig. 4. Post-Processor Block Diagram

– 10 –

CXD1958Q

3-1. Differential Decoder

In QAM mode, this decodes the MSB of the received QAM signal according to the equations given in the DAVIC MMDS standard. In TCM mode, the differential decoding is performed by the TCM decoder block.

3-2. TCM Decoder

The TCM decoder reduces the signal power required for robust reception in difficult channels whenever trellis coded modulation is used at the transmitter. TCM mode is selected by an I2C bus register bit. The TCM decoder block takes the equalized I/Q symbols as input data, and provides 7-bit (16-TCM), 11-bit (64-TCM), and 15-bit (256-TCM) outputs for each TCM symbol. Two I/Q pairs are required for each TCM symbol. The TCM block performs an internal synchronization sequence to ensure that the correct pair of QAM symbols is selected. There are several I2C bus registers to allow user configuration and monitoring of the synchronization sequence.

3-3. Symbol to Byte Mapper

The postprocessor maps differentially decoded symbols to bytes. The byte boundaries are determined by correlating the input symbols with the expected locations of the sync bytes. The number of consecutive successful correlations is compared against a threshold (SYNC_LADDER_LENGTH), and the symbol stream is flagged as locked when that threshold is achieved.

3-4. De-interleaver and Reed Solomon Error Correction

DAVIC compatible forney type convolutional de-interleavering (I = 12, N = 204, M = 17) or (I = 204, N = 204, M = 1), where M = N/I) is applied to the bytes. I = 12 is used for 16/64 QAM/TCM modes. Either I = 12 or I = 204 can be programmed for 256 QAM/TCM modes. The resulting byte stream is corrected by a standard DAVIC/DVB (204, 188) Reed Solomon decoder (GF generation polynomial p (x) = x8+ x4+ x3+ x2+ 1) which can correct up to 8 erroneous bytes per MPEG2 packet.

3-5. Sync Detection and Sync Loss

After R/S correction, the byte stream is checked for the occurrence of n MPEG-2 sync bytes, where n is programmable from 2 to 7 via an I2C bus register. This sync byte detection is used to indicate transport stream lock by activation of the TSLOCK pin. There are two methods used to indicate loss of Transport Stream Lock, selectable by an I2C bus register. One method indicates loss of lock immediately a sync byte is lost. The other method decrements the sync byte counter down by 1 from n, and only indicates loss of lock when the counter reaches zero, thus providing a filtering capability to allow easier sync locking.

– 11 –

CXD1958Q

3-6. Energy Dispersal De-randomiser

The error-corrected bytes are de-randomized with a 15-stage PRBS (Pseudo Random Binary Sequence) generator, with polynomial 1 + X14+ X15and start-up sequence “100101010000000”. Sync bytes are not descrambled, and when an inverted sync byte is detected, every 8th packet, the PRBS resets to the start-up sequence and the sync byte is re-inverted. The de-scrambled data is output through the TSDATA pins, along with a data clock and synchronization signal.

3-7. BER Calculation

In addition to the above functionality, the postprocessor includes comprehensive signal quality measurement logic. The Bit Error Rate (BER) of the received signal (before and after R/S correction) and a measure of the long-term signal quality are available via I2C bus registers. The calculated Bit Error Rate (BER) of the received signal is accurate for pre R/S BER figures better than 1 × 10–3.

3-8. MPEG2 Baseband Interface

Fig. 5 illustrates the relationship between the CXD1958Q MPEG2 transport stream interface signals. The transport stream clock (TSCLK) can be programmed for the external device to sample on the rising or falling edge (only rising edge sampling is shown here). The interface supports a number of additional signals, which indicate the integrity of the output data. Once the demodulator has achieved lock to the MPEG2 sync byte, the transport stream interface is activated. Fig. 5 shows a complete MPEG2 packet consisting of a sync byte (47h) data bytes (dd) and Reed Solomon bytes (rr). Note that all the interface control signals have individual programmable polarity; active high signals are shown in the diagram.

TSCLK has two operating modes selected via I2C bus:

• Whole Packet Mode, where the clock is activated for all 204 bytes of the packet, requiring the external

interface to use TSVALID to distinguish between data and 16 Reed Solomon bytes.

• Data Only Mode, where the clock is activated only for each of the 188 sync and data bytes, and remains inactive during the 16 Reed Solomon bytes.

TSDATA[7:0] is the byte wide MPEG2-TS data with programmable MSB/LSB ordering. The default is TSDATA7 being the MSB.

TSVALID has two operating modes selected via I2C bus:

• Data Only Mode: where TSVALID is set active during the 188 byte data portion of the packet, and reset

inactive during the 16 Reed Solomon bytes. It is used by the external device as a clock enable to qualify when data is valid on TSDATA[7:0].

• Pulsed Mode: where TSVALID is set active during the MPEG2 sync byte and reset inactive for the remainder of the packet, and thus becomes equivalent to a sync byte indicator.

TSSYNC is set active during the MPEG2 sync byte and reset inactive for the remainder of the packet. TSERR is only set active if the Transport Stream Error flag is set. This signal indicates that the Reed Solomon

decoder was unable to correct all errors in the packet. There are 3 programmable modes for this signal:

• Whole Packet Mode: Active during the entire 204-byte packet

• Data Only Mode: Active during the 188 byte data portion of packet and inactive during the 16 Reed Solomon

bytes

• Pulsed Mode: Pulsed active during sync byte period only

– 12 –

CXD1958Q

rr dd dd dd dd rr rr rr rr dd

47h

Tsu

TSCLK Whole Packet

TSCLK Data Only

TSDATA[7:0]

TSVALID Data Only

TSVALID Pulsed

TSSYNC

TSERR Whole Packet

TSERR Data Only

TSERR Pulsed

Fig. 5. MPEG2 Transport Stream Output Configurations

4. Tuner 3-Wire Bus Interface

The interface allows two tuner synthesizers to be configured through the use of separate SEN0 and SEN1 enable output signals. The polarity of SEN0 and SEN1 can be programmed both active high or both active low by the SEN_POL I2C bus register bit. There are two operating modes selected by I2C bus.

• Mode 0 : The host CPU drives the 3-wire bus pins via the CPU interface pins TCLK, TDATA and TEN. These pins are connected to the CPU data bus and a decoded active low strobe is connected to the TWR_N input pin. On each rising edge of TWR_N, the data on TCLK, TDATA, and TEN is registered by the CXD1958Q demodulator, and driven out on the SCLK, SDATA and SEN0 or SEN1 pins respectively. The I2C bus register bit SEL selects whether SEN0 or SEN1 is activated during this transfer. Thus the transfer rate on the 3-wire bus interface in this mode is determined by the rate of CPU accesses. The operation of this mode is shown in Fig. 6.

– 13 –

CXD1958Q

• Mode 1 :The CPU loads 4 I2C bus registers inside the TCM demodulator with 28 bits of data. The CPU selects which SEN0 or SEN1 output should be used by programming the I2C bus register bit (SEL), and then commands (by setting an I2C bus register bit SEND) the 3-wire bus state machine to transmit these 28 bits out of the 3-wire interface as shown in Fig. 7. When the transmission is complete, the I2C bus register bit (SEND) is reset to zero by the 3-wire bus state machine. This allows the CPU to poll the SEND bit to determine when it is able to write further data to the 3 I2C bus registers if it is necessary to send more data. The rate of transmission is fixed at 10.67µs per bit when using a 30MHz crystal oscillator on the CXD1958Q demodulator IC. The bit ordering of transmission starts with bit 27.

TCLK

sampling of CPU pins

TDATA

TEN

TWR_N

SCLK

SDATA

SEN0[1]

Fig. 6. 3-Wire Bus : Mode 0 Operation

27 26 25 24

–305µs

23 22 21 7 6 5 4 3 2 1 0

SCLK

SDATA

SEN0[1]

Fig. 7. 3-Wire Bus : Mode 1 Operation

– 14 –

CXD1958Q

5. I2C Bus Interface

The CXD1958Q includes an I2C bus compatible host interface, to enable access to the internal control registers. This supports accesses via an offset register at bit rates of up to 400Kbit/s. The 7-bit slave address for this device is [0, 0, 1, 1, 1, A1, A0], where A1 and A0 are set externally via device pins.

A summary of the CXD1958Q internal register set which can be accessed via I2C bus is defined in Table 2. A full description of the registers is presented in "Control Register Definitions".

Table 2. I2C bus Interface Registers

Subaddress

Name R/W

Width

bytes

Description

Device version/revision information

Device reset register

Interrupt source register

Pre-processor status

Equalizer status FEC status QAM level

configuration Detected

frequency offset Detected QAM

level Symbol rate at

which locked Bit Error Rate

estimate Codeword reject

count Interrupt mask

configuration External AGC

control Equalizer

configuration

3 4

5 6

9 – 0AH

0BH – 0DH

0EH – 0FH

10H

11H

12H

13H

CHIP_INFO

RST_REG

INTERRUPT_SOURCE

TSMSTATUS ESMSTATUS

FEC_STATUS QAMCONFIG

CARRIEROFFSET

DETECTEDQAM

DETECTEDSYMRATE

BER_EST

CWRJCT_CNT

INTERRUPT_MASK

PRECONFIG

AGCCTRL

EQUCONFIG

R R

1 1

20h

F4h

01h 10h

84h

89h

03h

20h

F4h

01h 10h

84h

89h

—

03h

20h

F1h

—

— —

—

H/W Cold Warm

Value on reset of type

– 15 –

CXD1958Q

Subaddress

Name R/W

Width

bytes

Description

FEC configuration Symbol rate

table entry Symbol rate

table entry FEC sync detect

thresholds Long term

quality threshold Bit error rate

measurement period

Not used in this application

Nominal frequency of receive local oscillator

Equalizer tap address number

In-phase component of equalizer tap

Quadrature component equalizer tap

In-phase equalizer output

Quadrature-phase equalizer output

14H 15H – 16H

17H – 18H

19H – 1AH

1BH – 1CH

1DH – 1EH

1FH – 20H

21H – 22H

23H – 24H

25H

26H

27H

28H

29H – 2AH

2BH

2CH

2DH

2EH

2FH

FEC_PARAMS SYMRATETRIAL0

SYMRATETRIAL1

SYMRATETRIAL2

SYMRATETRIAL3

SYMRATETRIAL4

SYMRATETRIAL5

SYMRATETRIAL6

SYMRATETRIAL7

SET_SYNC_DETECT

LT_QLTY_THRESHOLD

BER_EST_PERIOD

ADC_CAL_PERIOD

ITBFREQ

EQUTAPSELECT

EQUTAPI

EQUTAPQ

CONSTELLATIONI

CONSTELLATIONQ

RW RW

1 2

32h

0AABh

5Msym/s

1Dh

04h

0Eh

FFh

32EFh

36.125MHz

—

0AABh

5Msym/s

1Dh

04h

0Eh

FFh

32EFh

36.125MHz

— —

—

H/W Cold Warm

Value on reset of type

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