Sony CXD1915R Datasheet

Digital Video Encoder

Description

The CXD1915R is a digital video encoder designed for DVDs, set top boxes, digital VCRs and other digital video equipment. This device accepts ITUR601 format Y, Cb and Cr data and ITU-R656 format Y, Cb and Cr data, and the data are encoded to composite video and separate Y/C video (S-video) signals and converted to RGB/YUV signals.

Features

• NTSC, PAL, MPAL and 4.43NTSC encoding modes

• Composite video and separate Y/C video (S-video)

signal output

• R, G, B/Y, U, V (BetaCam/SMPTE level) signal

output

• 8/16-bit pixel data input modes

• 13.5Mpps pixel rate

• 12.27 and 14.75Mpps square pixel rates

• External synchronization using HSYNC, VSYNC

and FID inputs, or internal synchronization

• Supports interlace and non-interlace modes

• On-chip 100% color bar generator

• OSD function

• ITU-R656 code signal EAV decoding

• Supports I2C bus (400kHz) and Sony SIO

• Closed Caption (line 21, line 284) encoding

• VBID encoding

• WSS encoding

• 10-bit 6-channel DAC

• Macrovision Pay-Per-View copy protection system

Rev. 7.1.L1

∗1

• Monolithic CMOS single 3.3V power supply

• 80-pin plastic LQFP

Absolute Maximum Ratings

• Supply voltage VDD VSS – 0.5 to +4.6 V

• Input voltage VI VSS – 0.5 to +7.0 V

• Output voltage VO VSS – 0.5 to VDD + 0.5 V

• Operating temperature

Topr –20 to +75 °C

• Storage temperature Tstg –55 to +150 °C (VSS = 0V)

Recommended Operating Conditions

• Supply voltage VDD 3.3 ± 0.3 V

• Input voltage VIN VSS to 5.5 V

• Operating temperature

Topr 0 to +70 °C

I/O Capacitance

• Input capacitance CI 9 (Max.) pF

• Output capacitance CO 11 (Max.) pF

Note) Test conditions: VDD = VI = 0V, fM = 1MHz

– 1 –

E99422-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD1915R

80 pin LQFP (Plastic)

∗1

This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only. Reverse engineering or disassembly is prohibited.

– 2 –

CXD1915R

Block Diagram

687069

PIXCON

PD0 to 7

XRST

ROSD

BOSD

GOSD

OSDSW

FID

VSYNC

HSYNC19CSYNC

XIICEN

XCS/SA

SI/SDA

6SO

SCK/SCL

XVRST

SYNCM

PDCLK Internal CLK

BURST FLAG

CSYNC

SYSCLK

B/U-OUT

G/Y-OUT

R/V-OUT

IREF

VREFVBTDI

TMS

TDO

TCK

TRST

TVSYNC

TD8 to 10

XTEST

XTEST5

10bit

DAC

10bit

DAC

10bit

DAC

Delay

LPF

Selector

Modulator

YUV/RGB

translator

Interpolater

C-OUT

Y-OUT

CP-OUT

10bit

DAC

10bit

DAC

10bit

DAC

Interpolater

Y, U, V

CROMA

1/2

Demultiplex,

Level

translator

and

Interpolator

4:2:2 to 4:4:4

OSD

Gen.

Sub Carrier

Gen.

SYNC Slope

Gen.

Closed Caption Encoder

(for NTSC)

MACRO VISION

Signal Gen.

VBID & WSS

Gen.

SYNC Gen.

and

Timing Controller

C Bus

and

SIO Controller

62 to 64

22 to 25,

27 to 30

PD8 to 15

32 to 35,

37 to 40

– 3 –

CXD1915R

Pin Description

No.

9 10 11 12 13

XVRST

XIICEN

XCS/SA

SI/SDA

VSS1

SCK/SCL

VSS2 SYSCLK VSS3 XRST VSS4

PDCLK

VDD1

FID

I/O

—

I/O

Symbol I/O Description

Field ID input. This signal indicates the field ID when resetting the vertical sync. High indicates 1st field. Low indicates 2nd field.

Vertical sync reset input in active Low. This pin is pulled up. This is used for synchronizing the phases of the external and internal vertical sync signals. When XVRST = Low, the internal digital sync generator is reset according to the F1 status.

Serial interface mode select input. This pin is pulled up. When XIICEN = Low, Pins 4, 5, 6 and 8 are I2C bus mode. When XIICEN = High, Pins 4, 5, 6 and 8 are Sony SIO mode.

This pin's function is selected by XIICEN (Pin 3). This pin is pulled up. When XIICEN = High, this pin is Sony SIO mode; XCS chip select input. When XIICEN = Low, this pin is I2C bus mode; SA slave address select input signal which selects the I2C bus slave address.

This pin's function is selected by XIICEN (Pin 3). When XIICEN = High, this pin is Sony SIO mode; SI serial data input. When XIICEN = Low, this pin is I2C bus mode; SDA input/output.

This pin's function is selected by XIICEN (Pin 3). When XIICEN = High, this pin is Sony SIO mode; SO serial output. When XIICEN = Low, this pin is not used and output is high impedance.

Digital ground. This pin's function is selected by XIICEN (Pin 3).

When XIICEN = High, this pin is Sony SIO mode; SCK serial clock input. When XIICEN = Low, this pin is I2C bus mode; SCL input.

Digital ground. System clock input.

To generate the correct subcarrier frequency, precise 27MHz is required. Digital ground. System reset input in active Low.

Set to Low for 40 clocks (SYSCLK) or more during power-on reset. Digital ground. Pixel data clock signal output for 13.5MHz.

A 13.5MHz signal frequency divided from the system clock (SYSCLK) is output and used as the clock signal when 16-bit pixel data is input.

Digital power supply. Field ID input/output.

When SYNCM (Pin 72) = High, the CXD1915R is set to master mode and outputs as follows.

When control register bit "FIDS" = "1":

Low indicates 1st field and High indicates 2nd field.

When control register bit "FIDS" = "0":

High indicates 1st field and Low indicates 2nd field. When SYNCM (Pin 72) = Low, the CXD1915R is set to slave mode and this pin becomes the field ID input.

– 4 –

CXD1915R

19 20 21

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

44 45

VSYNC

HSYNC

CSYNC BF VSS5

PD0 PD1 PD2 PD3 VDD2 PD4 PD5 PD6 PD7 VSS6 PD8/TD0 PD9/TD1 PD10/TD2 PD11/TD3 VSS7 PD12/TD4 PD13/TD5 PD14/TD6 PD15/TD7 VDD3 NC

IREF

VREF CP-OUT

I/O

O O

—

I I I I

—

I I I I

— I/O I/O I/O I/O

—

Vertical sync signal input/output. When SYNCM (Pin 72) = High, this pin is the vertical sync signal output. When SYNCM = Low, this pin is the vertical sync signal input, and the falling edge is detected during the 1st field to reset the internal circuits.

Horizontal sync signal input/output. When SYNCM (Pin 72) = High, this pin is the horizontal sync signal output. When SYNCM = Low, this pin is the horizontal sync signal input, and the falling edge is detected during the 1st field to reset the internal circuits.

Composite sync output when using RGB output. Burst flag output. The burst flag is synchronized with the composite video signal

(CP-OUT) and indicates its color burst signal position. Digital ground.

8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is input. [PD0 to PD7] When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr signal inputs. When control register bit "PIF MODE" = "1", these are Y signal inputs.

Digital power supply. 8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is

input. [PD0 to PD7] When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr signal inputs. When control register bit "PIF MODE" = "1", these are Y signal inputs.

Digital ground. Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]

When control register bit "PIF MODE" = "0", these inputs are not used. When control register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs. In test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor.

Digital ground. Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]

Digital power supply. Not connected inside the IC. DAC reference current output.

Connect resistance "16R" which is 16 times output resistance "R". DAC reference voltage input.

Sets the DAC output full-scale width. 10-bit DAC output. This pin outputs the composite signal.

No.

Symbol I/O Description

– 5 –

CXD1915R

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

70 71

73 74

AVDD1 AVSS1 C-OUT VB VG Y-OUT AVDD2 AVSS2 B-OUT AVSS4 G-OUT AVDD3 AVSS3 R-OUT VSS8 TVSYNC TD8 TD9 TD10 VDD4

XTEST OSDSW/

XTEST1 ROSD/

XTEST2 GOSD/

XTEST3 BOSD/

XTEST4 XTEST5

SYNCM

PIXCON VSS9

TDI

—

O O O

O — —

O —

O — —

O —

I I/O I/O I/O

—

Analog power supply. Analog ground. 10-bit DAC output. This pin outputs the chroma (C) signal. Connect to ground via a capacitor of approximately 0.1µF. Connect to analog power supply via a capacitor of approximately 0.1µF. 10-bit DAC output. This pin outputs the luminance (Y) signal. Analog power supply. Analog ground. 10-bit DAC output. This pin outputs the B and U signals. Analog ground. 10-bit DAC output. This pin outputs the G and Y signals. Analog power supply. Analog ground. 10-bit DAC output. This pin outputs the R and V signals. Digital ground. Test pin. This pin is pulled up. Normally this pin should be open.

Test data inputs/outputs. These pins should be open. In test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor.

Digital power supply. Test mode control. This pin is pulled up.

Normally this pin should be open.

These pins are pulled up. The functions of these pins are selected by XTEST (Pin 66). When XTEST = High, these are OSD data inputs. When XTEST = Low, these are test mode control inputs. The test mode is available only for the device vendor.

Test pin. This pin is pulled up. Normally this pin should be open. Master/slave switching. This pin is pulled up.

When SYNCM = High, the CXD1915R is set to master mode. When SYNCM = Low, the CXD1915R is set to slave mode.

Control register bit "PIX_EN" default value control. This pin is pulled up.

Digital ground. Test mode control input. This pin is pulled up.

No.

Symbol I/O Description

– 6 –

CXD1915R

76 77 78

79 80

TMS TDO TCK

TRST VDD5

—

Test mode control input. This pin is pulled up. Test output. This pin should be open. Test mode control input. Fix to High. Test mode reset input. Set to Low for 40 clocks (SYSCLK) or more during power-

on reset. Digital power supply.

No.

Symbol I/O Description

– 7 –

CXD1915R

Electrical Characteristics

DC Characteristics (Ta = 0 to +70°C, VSS = 0V)

Item

Input High voltage Input Low voltage Input High voltage Input Low voltage

Output High voltage

Output Low voltage

Output High voltage

Output Low voltage

Output High voltage

Output Low voltage

Input leak current

Input leak current Supply current

VIH1 VIL1 VIH2 VIL2

VOH1

VOL1

VOH2

VOL2

VOH3

VOL3

IIL1

II2 IDD

VDD = 3.3 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.3 ± 0.3V IOH = –8.0mA

VDD = 3.3 ± 0.3V IOL = 8.0mA

VDD = 3.3 ± 0.3V IOH = –4.0mA

VDD = 3.3 ± 0.3V IOL = 4.0mA

VDD = 3.3 ± 0.3V IOH = –2.0mA

VDD = 3.3 ± 0.3V IOL = 4.0mA

VDD = 3.3 ± 0.3V VI = 0V

VDD = 3.3 ± 0.3V VI = 0 to 5.5V

VDD = 3.3 ± 0.3V VDD = 3.3 ± 0.3V

0.7VDD

VDD – 0.4

2.4

–240

–40

–100

∗8

0.2VDD

∗8

0.3VDD

0.4

–40

∗9

V V V V

µA

∗1 ∗1 ∗2 ∗2

∗3

∗4

∗5

∗6

∗7

Symbol

Measurement conditions

Min.

Typ. Max. Unit Measurement pins

Notes:

∗1

F1, XVRST, XIICEN, XCS/SA, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TVSYNC, TD8 to TD10, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON, TDI, TMS, TCK, TRST

∗2

SI/SDA, SCK/SCL

∗3

SO, PDCLK, CSYNC, BF

∗4

TDO

∗5

FID, VSYNC, HSYNC, TD0 to TD10

∗6

XVRST, XIICEN, XCS, TVSYNC, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON, TDI, TMS

∗7

F1, SI/SDA, SCK/SCL, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TD8 to TD10, TCK, TRST

∗8

The CXD1915R supports input from 5V devices.

∗9

Not including analog current

– 8 –

CXD1915R

DAC Characteristics (AVDD = 3.3V, R = 200Ω, VREF = 1.35V, Ta = 25°C)

Item Resolution Linearity error Differential linearity error Output full-scale current Output offset voltage Output full-scale voltage Precision guaranteed output

voltage range

n EL ED IFS VOS VFS

VOC

–2.4 –0.9

6.25

1.20

6.75

1.35

2.4

0.9

7.25 2

1.50

bit LSB LSB

mA mV

V V

Symbol Measurement conditions Min. Typ. Max. Unit

– 9 –

CXD1915R

AC Characteristics

1. Serial port interface

SCK

XCS

tPWLSCK

tSIS

tSOD

tSIH

tCSS

fSCK

tPWHSCK

tCSH

tSOH

SCK clock rate SCK pulse width Low SCK pulse width High Chip select setup time to SCK Chip select hold time to SCK Serial input setup time to SCK Serial input hold time to SCK Serial output delay time from SCK Serial output hold time from SCK

fSCK

tPWLSCK tPWHSCK tCSS tCSH tSIS tSIH tSOD

∗

tSOH

∗

DC 100 100 150 150

50 10

MHz

ns ns ns ns ns ns ns ns

∗

CL = 35pF

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Item Symbol Min. Typ. Max. Unit

– 10 –

CXD1915R

2. F1

F1 setup time to SYSCLK F1 hold time to SYSCLK

tFS tFH

ns ns

SYSCLK

tFS tFH

3. OSDSW, ROSD, GOSD, BOSD

OSD setup time to SYSCLK OSD hold time to SYSCLK

tOS tOH

ns ns

SYSCLK

OSDSW ROSD GOSD BOSD

tOS tOH

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Item Symbol Min. Typ. Max. Unit

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Item Symbol Min. Typ. Max. Unit

– 11 –

CXD1915R

4. SYSCLK, PDCLK, BF, CSYNC, HSYNC, VSYNC, FID

SYSCLK

fSYSCLK

tPWHCLK

tPDCLKD

tPWLCLK

PDCLK

VSYNC

∗

HSYNC

∗1

FID

∗1

CSYNC BF

tCOH

tPDCLKD

tCOD

∗1

In master mode

SYSCLK clock rate SYSCLK pulse width Low SYSCLK pulse width High PDCLK delay time from SYSCLK Control output delay time from SYSCLK Control output hold time from SYSCLK

fSYSCLK

tPWLCLK tPWHCLK tPDCLKD

∗

tCOD

∗

tCOH

∗

11 11

20 26

MHz

ns ns ns ns ns

∗

CL = 35pF

5. 8-bit mode

(1) Pixel data interface

SYSCLK

PD0 to PD7

tPDS tPDH

Pixel data setup time to SYSCLK Pixel data hold time to SYSCLK

tPDS tPDH

ns ns

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Item Symbol Min. Typ. Max. Unit

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Item Symbol Min. Typ. Max. Unit

– 12 –

CXD1915R

(2) XVRST

SYSCLK

XVRST

tVS tVH

XVRST setup time to SYSCLK XVRST hold time to SYSCLK

tVS tVH

ns ns

(3) HSYNC, VSYNC, FID

SYSCLK

HSYNC

∗

VSYNC

∗1

FID

∗1

tSYS tSYH

∗1

In slave mode

Sync signal setup time to SYSCLK Sync signal hold time to SYSCLK

tSYS tSYH

ns ns

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Item Symbol Min. Typ. Max. Unit

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Item Symbol Min. Typ. Max. Unit

– 13 –

CXD1915R

6. 16-bit mode

(1) Pixel data interface

PDCLK

PD0 to PD15

tPDS tPDH

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Pixel data setup time to PDCLK Pixel data hold time to PDCLK

tPDS tPDH

ns ns

(2) XVRST

PDCLK

XVRST

tVS tVH

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

XVRST setup time to PDCLK XVRST hold time to PDCLK

tVS tVH

ns ns

Item Symbol Min. Typ. Max. Unit

– 14 –

CXD1915R

(3) HSYNC, VSYNC, FID

PDCLK

HSYNC

∗

VSYNC

∗1

FID

∗1

tSYS tSYH

∗1

In slave mode

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Sync signal setup time to PDCLK Sync signal hold time to PDCLK

tSYS tSYH

ns ns

Item Symbol Min. Typ. Max. Unit

– 15 –

CXD1915R

Description of Functions

The CXD1915R converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A) or PAL (ITU-R624; B, G, H, I) format. The CXD1915R first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr signals into the U and V signals, respectively, interpolates 4:2:2 to 4:4:4, and then modulates the signals with the digital subcarrier inside the CXD1915R to create the chroma (C) signal. The Y and chroma (C) signals are oversampled at double speed to reduce SIN (X)/(X) roll-off, and then added to become the digital composite signal. The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals.

1. Pixel input format

The pixel input format is selected according to the value of bit 4 (PIF MODE) of control register address 01H as shown in Table 1-1 below. When "PIF MODE" is "0", the image data (multiplexed Y, Cb, and Cr data) input from PD0 to PD7 are sampled at the rising edge of SYSCLK as shown in the chart on the following page. When "PIF MODE" is "1", the image data (PD0 to PD7: Y data, PD8 to PD15: multiplexed Cb and Cr data) input from PD0 to PD15 are sampled at the rising edge of PDCLK.

PIF Mode 0 (8 bit mode) 1 (16 bit mode)

Cb/Cr

Y/Cb/Cr

PD15 to 8 PD7 to 0

Table 1-1

Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register address 01H as shown in Table 1-2 below.

When "PIF MODE" is "0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to PD7 is sampled at the respective rising edge of SYSCLK after the fall of HSYNC. (Default: Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.)

When "PIF MODE" is "1", Y0 and Y1 data are input to PD0 to PD7, multiplexed Cb0 and Cr0 data are input to PD8 to PD15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC. (Default: Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.)

PIX TIM 0 0 1 1

#0 #1 #2 #3

Timing phase

Table 1-2

0 1 0 1

(default)

+ 35 hidden pages