Sony CXA1782CQ Datasheet

CXA1782CQ/CR
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RF Signal Processing Servo Amplifier for CD players
Description
The CXA1782CQ/CR is a bipolar IC with built-in RF signal processing and various servo ICs. A CD player servo can be configured by using this IC, DSP and driver.
Features
Low operating voltage (VCC – VEE = 3.0 to 11.0V)
Low power consumption (39mW, VCC = 3.0V)
Supports pickup of either current output, voltage
output
Automatic adjustment comparator for tracking
balance gain
Single power supply and positive/negative dual
power supplies
Applications
• RF I-V amplifier, RF amplifier
• Focus and tracking error amplifier
• APC circuit
• Mirror detection circuit
• Defect detection and prevention circuits
• Focus servo control
• Tracking servo control
• Sled servo control
• Comparators of tracking adjustment for balance
and gain
CXA1782CQ
48 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage VCC 12 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –65 to +150 °C
Allowable power dissipation
PD 833 (CXA1782CQ) mW
457 (CXA1782CR) mW
Recommended Operating Condition
Operating supply voltage
VCC – VEE 3.0 to 11.0 V
CXA1782CR
48 pin LQFP (Plastic)
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95908C78
Block Diagram
CXA1782CQ/CR
FE_BIAS
V
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
LD
PHD2
36
APC
RF IV AMP2
37
38
F
F IV AMP
39
E
40
EI
EE
41 42
43
44
45
46
47
48
E IV AMP
BAL2
BAL1
TOG2
TOG1
•WINDOW COMP.
PHD1
35
RF IV AMP1
FE AMP
TE AMP
BAL3
TOG3
ATSC
34
DFCT
PHD
33
FOK
TTL
I IL
DFCT
FS4
RF_M
32
LEVEL S
FZC COMP
TZC COMP
TM1
RF_O
RF_I
31
30
MIRR
•I IL DATA REGISTER •INPUT SHIFT REGISTER
•ADRESS.DECODER
LPF COMPHPF COMP
•FCS PHASE COMPENSATION
FS2
CP
CB
29
•OUTPUT DECODER
TOG1 to 3
FS1 to 4 TG1 to 2 TM1 to 7 PS1 to 4
BAL1 to 3
•TRACKING PHASE COMPENSATION
TG1
FS1
DFCT
TG2
TM7
CC1
TM6
TM5 TM4
TM3
CC2
262728
•F SET
25
I IL
TTL
TTL
I IL
•I SET
FOK
TM2
SENS
24
C.OUT
23
XRST
22
DATA
21
XLT
20
CLK
19
Vcc
18
ISET
17
SL_O
16
SL_M
15
14
SL_P
13
TA_O
1
FEO
2
3
FEI
FDFCT
4
FGD
FLB
FE_O
7
FE_M
8
SRCH
9
6
5
TGU
10
11
12
TG2
FSET
TA_M
The switch state in Block Diagram is for initial resetting.
Switch turns to side for 1 and to side for 0 in Serial Data Truth Table.
DFCT switch turns to side when defect signal generates for DEFECT = E in Serial Data Truth Table.
TG1 switch turns to side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.
°
°
°
– 2 –
Pin Description
CXA1782CQ/CR
Pin No.
1 FEO
2
FEI
FDFCT
3
Symbol
I/O
O
I
I
Equivalent circuit
25p
1
3
147
174k
51k
300µ
2
147
147
10k
100k
9k
Focus error amplifier output. Connected internally to the FZC comparator input.
Focus error input.
Capacitor connection pin for defect
Description
time constant.
4
5
6
13
16
FGD
FLB
FE_O
TA_O
SL_O
40k
68k
130k
20µ
147
I
I
4
5
Ground this pin through a capacitor when decreasing the focus servo high-frequency gain.
External time constant setting pin for increasing the focus servo low­frequency.
O
6
O
O
13 16
250µ
Focus drive output.
Tracking drive output.
Sled drive output.
FE_M
7
I
7
147
90k
Focus amplifier inverted input.
50k
– 3 –
CXA1782CQ/CR
Pin No.
8
9
10
Symbol
SRCH
TGU
TG2
I/O
Equivalent circuit
147
I
I
8
50k
110k
20k
9
11µ
External time constant setting pin for generating focus servo waveform.
External time constant setting pin for switching tracking high-frequency
Description
gain.
82k
External time constant setting pin for
I
10
470k
switching tracking high-frequency gain.
11
12
14
FSET
TA_M
SL_P
I
11
147k
High cut-off frequency setting pin for focus and tracking phase compensation amplifier.
15k 15k
147
100k
Tracking amplifier inverted input.
11µ
Sled amplifier non-inverted input.
I
12
I
147
14
15
SL_M
I
15
147
22µ
Sled amplifier inverted input.
– 4 –
CXA1782CQ/CR
Pin No.
17
Symbol
ISET
19 CLK
20
XLT
DATA
21
XRST
22
C. OUT
23
SENS
24
I/O
I
I
I
I
I
O
O
17
19 20
21 22
Equivalent circuit
147
147
147
23 24
1k
20k
100k
15µ
Description
Setting pin for Focus search, Track jump, and Sled kick current.
Serial data transfer clock input from CPU. (no pull-up resistance)
Latch input from CPU. (no pull-up resistance)
Serial data input from CPU. (no pull-up resistance)
Reset input; resets at Low. (no pull-up resistance)
Track number count signal output.
Outputs FZC, DFCT, TZC, gain, balance, and others according to the command from CPU.
25
26
27
28
FOK
CC2
CC1
CB
20k
O
25
147
I
147 147
28
O
I
40k
100k
147
Focus OK comparator output.
Input for the DEFECT bottom hold output with capacitance coupled.
27
DEFECT bottom hold output.
26
Connection pin for DEFECT bottom hold capacitor.
– 5 –
CXA1782CQ/CR
Pin No.
29
30
31
32
Symbol
I/O
CP
RF_I
RF_O O
RF_M
Equivalent circuit
147
29
I
Connection pin for MIRR hold capacitor. MIRR comparator non-inverted
Description
input.
I
147
30
Input for the RF summing amplifier output with capacitance coupled.
RF sunning amplifier output. Eye-pattern check point.
147
31
147
I
RF summing amplifier inverted
32
input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin.
33
34
35 36
LD
PHD
PHD1 PHD2
10k
147
147
1k
10k
17µ
100µ
11.6k
APC amplifier output.
APC amplifier input.
RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins.
O
I
I I
33
34
35 36
– 6 –
CXA1782CQ/CR
Pin No.
37
38 39
Symbol
FE_BIAS
F E
I/O
Equivalent circuit
32k
I
I I
37
38 39
164k
25p
12p
260k
147
513
10µ
Bias adjustment of focus error amplifier.
F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E.
Description
40
42
43
EI
TEO
LPFI
O
6.8k
102k 57k 28k
I-V amplifier E gain adjustment. (When not using automatic balance adjustment)
Tracking error amplifier output. E-F signal is output.
Comparator input for balance adjustment.
147
260k
12k
10k
147
20.3k
23k 11k 4.8k
150k
150k
40
42
I
43
(Input from TEO through LPF)
– 7 –
CXA1782CQ/CR
Pin No.
44
47
45
Symbol
TEI
TDFCT
ATSC
I/O
Equivalent circuit
I
44
I
I
47
10k
45
147
147
100k
1k
100k
Tracking error input.
Capacitor connection pin for defect time constant.
100k
Window comparator input for ATSC detection.
1k
Description
46
48
TZC
VC
VC
10k
50
75k
120
120
I
O
46
48
Tracking zero-cross comparator input.
(VCC + VEE)/2 DC voltage output.
– 8 –
Unit
mV
dB
CXA1782CQ/CR
V
V
mV
dB
dB
dB
V
V
mV
dB
dB
dB
dB
Max.
Typ.
Ratings
10 14 20 mA
Min.
CC = 1.5V, VEE = –1.5V, Ta = 25°C)
–20 –14 –10 mA
(V
Measurement conditions
18
ment pin
Measure-
SD
17 18
41
RST
–50 0 50
25.1 28.1 31.1
1kHz input ratio
31
1.3
1.2
V1 = 100mVDC
–0.9 –0.3
V1 = –100mVDC
33.0
27.0 30.0 33.0
–120 0 120
1
27.0 30.0
V1 = 1kHz I/O ratio
V1 = 1kHz I/O ratio
–3.0 0 3.0
1.0 1.3
V1 = 100mVDC
–1.0
–1.3
V1 = 100mVDC
–3.43 –2.93
0.5 3.5 6.5
–25 0 25
42
–2.33 –1.83 –1.33dB–3.93
V1 = 1kHz TOG1, 2, 3: OFF
V1 = 1kHz TOG1: ON
Reference to F0
V1 = 1kHz TOG2: ON
3F
3E
3D
–0.6 2.4 5.4 dB
–6.69 –6.19 –5.69 dB
Reference to F0
V1 = 1kHz TOG3: ON
Reference to F0
V1 = 1kHz TOG1, 2, 3: OFF
37
3B
0.7
1.0
0.4
0.1
V1 = 1kHz BAL1: ON
0.7
0.4
Reference to E0
V1 = 1kHz BAL2: ON
Reference to E0
36
35
14 15 16 13 12 11 10
9
SW conditions
8 7 6
5 4 3 2 1
Item
O
O
O
O
O
O
O O
O
O
O
O
O
O
0
O
Offset
Voltage gain
Current consumption 1
Current consumption 2
T1
T2
T3
T4
Electrical Characteristics
Max. output voltage-High
Max. output voltage-Low
Offset
Voltage gain 1
RF amplifier
T5
T6
T7
Voltage gain 1
T8
T9
Voltage gain difference
Max. output voltage-High
Max. output voltage-Low
Offset
Voltage gain F
Voltage gain F1
T15
Voltage gain F2
T16
FE amplifierTE amplifier
T12
T13
T10
T11
T14
Voltage gain F3
T17
– 9 –
Voltage gain E0
T18
Voltage gain E1
T19
Voltage gain E2
T20
Unit
dB
CXA1782CQ/CR
V
V
mV
mV
mV
mV
mV
dB
dB
dB
V
V
mV
mV
mV
dB
dB
dB
V
1.68
Max.
0.6
1.38
Typ.
Ratings
1.08
0.5
Min.
Measurement conditions
V1 = 1kHz BAL3: ON
Reference to E0
V1 = 1VDC BAL2: ON
42
ment pin
Measure-
33
SD
3F
17 18
16
–0.5
–480
–0.6
–900
V1 = 1VDC BAL2: ON
V2 = 120mV
33
3F
O
380
–900
V2 = 145mV
O
500
1120
–180
–200
V2 = 170mV
0.8mA sink
O
O O
100
–100
48
24
53
51
21.0
18
49
T29 + T8 (or T9)
6
08
–35
Output gain difference between
SD = 00 and SD = 08.
00
1.3
1.0
V1 = 200mVDC
08
–1.0
–1.3
V1 = –200mVDC
08
–360
–500
–640
02
640
500
360
03
265
17.6
225
14.6
185
12.25
Pin 1 threshold (preliminary)
24
13
00
25
–39
20.1
18.1
16.1
T37 + T14
1.3
1.0
Output gain difference between
SD = 20 and SD = 25.
V1 = –0.5VDC
14 15 13 12 11 10
9
SW conditions
8 7 6
5 4
O 3 2 1
3
Item
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Voltage gain E
Max. output voltage-High
Max. output voltage-Low
TE amplifierAPCFCS servoTRK servo
T21
T22
T23
Output voltage 1
Output voltage 2
Output voltage 3
T24
T25
T26
Output voltage 4
Center amplifier output
offset
DC voltage gain
T27
T28
T29
FCS total gain
Feed through
T30
T31
– 10 –
Max. output voltage-High
Max. output voltage-Low
Search voltage (–)
Search voltage (+)
FZC threshold
T32
T33
T34
T35
T36
DC voltage gain
TRK total gain
Feed through
T37
T38
T39
Max. output voltage-High
T40
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