Sony CXA1734S Datasheet

US Audio Multiplexing Decoder

For the availability of this product, please contact the sales office.

Description

The CXA1734S is an IC designed as a decoder for the Zenith TV Multi-channel System also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation and dbx noise reduction. Various kinds of filters are built in while adjustment and mode control are all executed through I2C BUS.

CXA1734S

30 pin SDIP (Plastic)

Features

• Audio multiplexing decoder and dbx noise

reduction decoder are all included in a single chip.

Almost any sort of signal processing is possible

through this IC.

• All adjustments are possible through I2C BUS to

allow for automatic adjustment.

• Various built-in filter circuits greatly reduce external

parts.

Standard I/O Level

• Input level

COMPIN (Pin 11) 245 mVrms

• Output level

LOUT (Pin 29) 490 mVrms

ROUT (Pin 28) 490 mVrms

Pin Configuration (Top View)

Absolute Maximum Ratings (Ta=25°C)

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 1.35 W

Range of Operating Supply Voltage 9 ± 0.5 V

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

VCATC

VGR

VCAWGT

25

6

IREF

VCAIN

24

7

MAININ

23

8

LOUT

NC

28

29

30

1

2

3

SCL

SDA

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

ROUT

DGND

27

4

ITIME

26

5

SAD

VEOUT

22

MAINOUT

VETC

9

PLINT

VEWGT

21

10

STFIL

20

11

—1—

VE

COMPIN

SAPIN

19

12

SAPTC

SAPOUT

18

13

SUBOUT

GND

17

14

STIN

E94612B5Z-TE

NOISETC

16

15

CC

V

Block Diagram

CXA1734S

LOUT

ROUT 28

29

26

VCA

25

RMSDET

MATRIX

24

23

MAININ

7

VE

MAINOUT

8

SUBOUT

13

VCA

NRSW/FOMO/SAPC/M1

LOGIC

DeEm

RMSDET

HPF

SPECTRAL

LPF

22 21

20

VCATC

VCAWGT

VCAIN

VEOUT

VETC

VEWGT

VE

WIDEBAND

STIN

"SAPVCO"

1/2

LPF

AMP

(+4dB)

SW

14

19

SAPIN

+6dB

1/4

PLINT

9

FLT

DeEm

"STEREO"

VCO

STFIL

10

LFLT

LPF

STLPF

VCA

"STLPF"

11

COMPIN

SAPVDET

LPF

"NOISE"

"SAP"

STIND

SAPVCO

DET

NOISE

BPF

ATT

15

CC

V

17

GND

16

NOISETC

"SAPLPF"

C BUS I/F

2

SAPIND

SAPLPF

STLPF

SAPVCO

STVCO

12

SAPTC

I

SAPFDET

F

IRE

27

ITIME

18

"PONRES"

1

2

3

4

6

5

SAPOUT

SDA

SCL

DGND

SAD

IREF

VGR

—2—

CXA1734S

Pin Description (Ta = 25°C, VCC = 9 V)

Pin No. voltage

Symbol

1

2

SDA

SCL

—

7.5k

19.5k

×2

4.5k

Equivalent circuit Description

CC

V

7.5k

↓ 35µ

2.1V

Serial data I/O pin. VIH > 3.0 V

×5

4k

3k

VIL < 1.5 V

1

VCC

7.5k

↓ 35µ

4k

2.1V

Serial clock input pin. VIH > 3.0 V

×4

3k

VIL < 1.5 V

2

3

DGND

—

VCC

3

2V

Digital block GND.

Slave address control

4

SAD

—

80k

40k

switch. The slave address is selected by changing the

10k

3k

147

5

VGR

1.3V

11k

9.7k

19.4k

×4

2.06k

VCC

11k

5

1.3V

voltage applied to this pin.

Band gap reference output pin. Connect a 10 µF capacitor between this pin and GND.

11k

—3—

CXA1734S

No. voltage

Symbol

6

7

IREF

MAININ

1.3V

4.0V

Equivalent circuit Description

40k 40k 30k

30p 1.8k

6.3k 16k

VCC

147

7

VCC

47k

30k 15k 30k

VCC

147

23k

×2

6

23k

Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 kΩ ±1%) resistor between this pin and GND.)

↓ 10µ

Input the (L + R) signal from MAINOUT (Pin 8).

8

9

MAINOUT

PLINT

4.0V

6.3V

4V

VCC

×4

147

8

↓

200µ

12k

15k

(L + R) signal output pin.

1k

VCC

Pilot cancel circuit loop

147

9

filter integrating pin. (Connect a 1 µF capacitor between this pin and

20k

GND.)

26µ

20k

↓

50µ

10k

↓

—4—

CXA1734S

Pin No. voltage

10

11

Symbol

STFIL

COMPIN

5.3V

4.0V

75k 75k

12k

Equivalent circuit Description

VCC

Stereo block PLL loop filter integrating pin.

10

VCC

14750k

11

1k

4k

3k

150k

4k

147

1k

Audio multiplexing signal

3V

20k

3k

input pin.

22k

12

13

SAPTC

SUBOUT

4.5V

4.0V

4k 4k 16k4k

8k

2k 2k

24k

V

CC

Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.)

(L - R) signal output pin.

3k

2k2k

14.4k

10 k

VCC

12

500

1k

10P

4k

147

4k

50µ

↓

Vcc

13

2k 4k 1k

—5—

CXA1734S

No. voltage

14

19

15

16

Symbol

STIN

SAPIN

VCC

NOISETC

4.0V

—

3.0V

14

147

47k

×2

Equivalent circuit Description

23k

Input the (L - R) signal from SUBOUT (Pin 13).

11.7k

8k

4V

15

20k

147

47k

4V

3.3k

19

Vcc

Input the (SAP) signal from SAPOUT (Pin 18).

Supply voltage pin.

Set the time constant for

10k

3k

1k

Vcc

2k

3k

the noise detection circuit.

4k

(Connect a 4.7 µF capacitor and a 200 kΩ

4V

resistor between this pin and GND.)

17

18

20

GND

SAPOUT

VE

—

4.0V

16

17

5P

24k

↓ 10µ ↓ 50µ

147

20

4k

500

4V

7.5k

7.4k

147

17k

Analog block GND.

Vcc

SAP FM detector output pin.

18

Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 kΩ resistor in series between this pin and GND.)

—6—

CXA1734S

Pin No. voltage

21

22

Symbol

VEWGT

VETC

4.0V

1.7V

21

147

Equivalent circuit Description

Vcc

Weight the variable deemphasis control effective

500

2.9V

4V

36k

value detection circuit. (Connect a 0.047 µF capacitor and a 3 kΩ resistor in series between this pin and GND.)

8k

30k ↓ 8µ

Vcc

4k ↓ 50µ

Determine the restoration time constant of the variable de-emphasis control effective value

×4

22

×4

detection circuit. The specified restoration time constant can be obtained

50µ

20k

4V

↓

7.5µ

by connecting a 3.3 µF capacitor between this pin and GND.

23

24

VEOUT

VCAIN

4.0V

23

Vcc

VCC

500

20k

VCC

24

47k

10k

5P

47k

Variable de-emphasis output pin. (Connect a 4.7 µF nonpolar capacitor between Pins 23 and 24.)

VCA input pin. Input the variable deemphasis output signal from Pin 23 via a coupling capacitor.

—7—

CXA1734S

Pin No. voltage

25

26

Symbol

VCAWGT

VCATC

4.0V

1.7V

↓

50µ

2.9V 36k

4k

↓

8µ

↓

50µ

Equivalent circuit Description

40k 40k

3p

VCC

Weight the VCA control effective value detection

500

147

25

circuit. (Connect a 1 µF capacitor and a 3.9 kΩ resistor in series between this pin and

30k

8k

VCC

GND.)

Determine the restoration time constant of the VCA

×4

26

×4

control effective value detection circuit. The specified restoration time constant can be obtained by connecting a

4k

↓

7.5µ

20k

10 µF capacitor between this pin and GND.

27

ITIME

1.3V

2.6V

47k

×4

40k 40k 30k

30p 1.8k

25k

147

20k 40k 10k

VCC

Set the reference current for the effective value detection timing current. The reference current is adjusted with the BUS DATA “SPECTRAL” based on the current which flows to this pin. The timing current determines the restoration

27

time constant of the detection circuit and the variable de-emphasis characteristics. Connect a 43 kΩ (±1%) resistor between this pin and GND.

—8—

CXA1734S

Pin No. voltage

28

Symbol

ROUT

4.0V

29

30

LOUT

NC

—

28 29

Equivalent circuit Description

VCC

3k

Right channel output pin.

500

15k

3p

Left channel output pin.

30

—

—9—