Sony CXA1386P, CXA1386K Datasheet

8-bit 75MSPS Flash A/D Converter

CXA1386P/K

Description

The CXA1386P/K are 8-bit high-speed flash A/D converter ICs capable of digitizing analog signals at the maximum rate of 75MSPS. The digital I/O levels of these A/D converters are compatible with the ECL 100K/10KH/10K.

The CXA1386P/K is pin-compatible with the earlier models CXA1056P/K, CXA1016P/K, respectively. They can be replaced by the CXA1386P/K without any design changes, in most cases. Compared with the earlier models, these new models have been greatly improved in performance, by incorporating advanced process, new circuit design and carefully considered layout.

Features

• Differential linearity error: ±1/2LSB or less

• Integral linearity error: ±1/2LSB or less

• High-speed operation with maximum conversion

rate of 75MSPS (Min.)

• Wide analog input bandwidth: 150MHz (Min. for

full-scale input)

• Low Power consumption: 580mW (Typ.)

• Single power supply: –5.2V

• Low input capacitance: 17pF (Typ.)

• Built-in integral linearity conpensation circuit

• Low error rate

• Operable at 50% clock duty cycle

• Good temperature characteristics

• Capable of driving 50Ω loads

CXA1386P

28 pin DIP (Plastic)

CXA1386K

44 pin LCC (Ceramic)

Structure

Bipolar silicon monolithic IC

Applications

• Digital oscilloscopes

• HDTV (high-definition TVs)

• Other apparatus requiring high-speed A/D

conversion

Pin Configuration

Pins with name are NC pins (not connected).

LINV

1

DVEE

2

DGND

(LSB) D0

(MSB) D7

DGND

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

D1 D2 D3 D4 D5 D6

DV

EE

MINV

10 11 12 13 14

3 4

5 6 7 8 9

CXA1386P

26 25

20 19 18 17 16 15

28 27

24 23 22 21

AVEE

RT

V AVEE AGND

IN

V AGND

RM

V AGND

IN

V AGND

EE

AV VRB CLK CLK

AV

EE

AVEE

VRT

AVEE

LINV

DV

EE

DGND1 DGND2

RM

39

38 37 36 35 34 33 32 31 30 29

40 41 42 43 44

1 2 3 4 5 6

8 9 10 11 12 13 14 15 16 17

7

IN

AGND

V

CXA1386K

D2

D1

(LSB) D0

V

AGND

D3

D4

AGND

D5

IN

AGND

V

D6

(MSB) D7

28 27 26 25 24 23 22 21 20 19 18

DGND2

EE

AV AVEE VRB

CLK CLK MINV DV

EE

DGND1

– 1 –

E90114C54-ST

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage AVEE, DVEE –7 to +0.5 V

• Analog input voltage VIN –2.7 to +0.5 V

• Reference input voltage VRT, VRB, VRM –2.7 to +0.5 V

I VRT – VRB I 2.5 V

• Digital input voltage CLK, CLK, MINV, LINV –4 to +0.5 V I CLK – CLK I 2.7 V

• VRM pin input current IVRM –3 to +3 mA

• Digital output current ID0 to ID7 –30 to 0 mA

• Storage temperature Tstg –65 to +150 °C

Recommended Operating Conditions Min. Typ. Max. Unit

• Supply voltage AVEE, DVEE –5.5 –5.2 –4.95 V

AVEE – DVEE –0.05 0 +0.05 V AGND – DGND –0.05 0 +0.05 V

• Reference input voltage VRT –0.1 0 +0.1 V

VRB –2.2 –2.0 –1.8 V

• Analog input voltage VIN VRB VRT

• Pulse width of clock TPW1 6.6 ns

TPW0 6.6 ns

• Operating temperature Tc (CXA1386K) –20 +100 °C

Ta (CXA1386P) –20 +75 °C

CXA1386P/K

– 2 –

Block Diagram

CXA1386P/K

MINV

r1

V

RT

Comparator

r/2

r

VIN

VRM

VIN

63

64

65

126

127

128

129

191

192

193

254

1

2

•

OUTPUT

ENCODE LOGIC

•

D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

r

r2

r

VRB

CLK CLK

r3

r/2

CLOCK

DRIVER

255

LINV

– 3 –

Pin Description and I/O pin Equivalent circuit

CXA1386P/K

Pin No

DIPLCC

31, 33,

35, 37

27, 28, 40, 41,

44

23 CLK

19, 21,

23, 25

18, 26,

28

16

Standard

Symbol I/O

voltage

level

AGND — 0V

AVEE — –5.2V

Equivalent circuit Description

Anlog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND or DGND 1/2.

Analog VEE –5.2V (Typ.). Internally connected with DVEE (resistance: 4 to 6Ω). Ceramic chip capacitors of at least

0.1µF should be used to connect to AGND and be placed near the pins.

DGND (DG ND1)

CLK input

22 CLK

15

3, 12— DGND — 0V

—5, 19 DGND1 — 0V

—6, 16 DGND2 — 0V

I ECL

CL K

DV

EE

r r r r

r r

Input complementary to CLK. With open connection, kept at threshold voltage (–1.3V). Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain the stable highspeed operation.

Digital GND (Used for internal circuits and output transistors)

Digital GND (Used for internal circuits)

Digital GND (Used for output buffers)

– 4 –

CXA1386P/K

Pin No

Symbol I/O

Standard

voltage

DIPLCC

2, 134, 20 DVEE — –5.2V

8D0

9 10 11

4

5 6 7

D1 D2 D3

O ECL

12 13

8 9

D4 D5

level

Equivalent circuit Description

Digital VEE Internally connected with AVEE (resistance: 4 to 6Ω) Ceramic chip capacitors of at least

0.1µF should be used to connect to DGND and be placed near the pins.

DGND (DG ND2)

LSB of data outputs. External pull-down resistor is required.

Di

Data outputs. External pull-down resistors are required.

14

15 D7

3 LINV I ECL

10

11

1

D6

1421 MINV I ECL

DGND (DG ND1)

LINV

or

MIN V

DVEE

MSB of data outputs.

DV

EE

External pull-down resistor is required.

Input pin for D0 (LSB) to D6 output polarity inversion (see output code table).

r r r

–1.3V

With open connection, kept at "L" level.

Input pin for D7 (MSB) output polarity inversion (see output

r

code table). With open connection, kept at "L" level.

– 5 –

CXA1386P/K

Pin No.

Symbol I/O

DIPLCC

32, 36 VIN I

26 VRB

34

42

20, 24

17

22

27

VRM IVRB/2

VRT I0V

I

Standard

voltage

level

VRT

to

VRB

–2V

VIN

VRT

VRM

VRB

Equivalent circuit Description

AGND

Analog input pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions.

AVEE

Reference voltage (bottom) Typically –2V

r1

r/2

r

Comparator 1

r

Comparator 2

r

r2

3

r

Comparator 127

r

Comparator 128

r

Comparator 129

r

Comparator 130

r

Comparator 255

r/2

A ceramic capacitor of at least 0.1µF and a tantalus capacitor of at least 10µF should be used to connect to AGND and be placed near the pins.

•

Reference voltage mid

•

point be used as a pin for integral linearity compensation

Reference voltage (top) Typically 0V When a voltage

•

different from AGND is

•

applied to this pin, a

•

ceramic capacitor of at

•

least 0.1µF and a tantalus capacitor of at least 10µF should be used to connect to AGND and be placed near the pins.

1, 2,

7, 17, 18, 24, 25, 29,

30, 38 39, 43

NC — —

Unused pins No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended.

– 6 –

CXA1386P/K

Electrical Characteristics (Ta = 25°C, AVEE = DVEE = –5.2V, VRT = 0V, VRB = –2V)

Item

Resolution DC characteristics

Integral linearity error Differential linearity error

Analg input

Analog input capacitance Analog input resistance Input bias current

Reference inputs

Reference resistance Offset voltage VRT

VRB

Digital inputs

Logic H level Logic L level Logic H current Logic L current Input capacitance

Switching characteristics

Maximum conversion rate Aperture jitter Sampling delay Output delay H pulse width of clock L pulse width of clock

Symbol Condition Min. Typ. Max. Unit

n

EIL EDL

CIN RIN IIN

RREF EOT EOB

VIH VIL IIH IIL

Fc Taj Tds Tdo TPW1 TPW0

Fc = 75MSPS Fc = 75MSPS

VIN = –1V + 0.07Vrms VIN = –1V

Input connected to –0.8V Input connected to –1.6V

Error rate 10–9TPS

∗1

75

8 0

–1.13

0

–50

75

4.0

6.6

8

±0.3 ±0.3

17

390

110

18 10

7

10

3.0

6.5

±0.5 ±0.5

200

155

32 24

–1.50

50 50

9.0

bits

LSB LSB

pF kΩ µA

Ω

mV mV

V

V µA µA pF

MSPS

ps ns ns ns ns

Digital outputs

Logic H level Logic L level Output rising time Output falling time

Dynamic characteristics

Input bandwidth S/N ratio

Error rate

Differential gain error Differential phase error

Power supply

Supply current Power consumption

∗1

TPS: Times Per Sample

∗2

Pd = IEE · VEE +

(VRT – VRB)

∗2

RREF

VOH VOL Tr Tf

DG DP

IEE Pd

2

RL = 620Ω to DVEE RL = 620Ω to DVEE RL = 620Ω to DVEE, 20% to 80% RL = 620Ω to DVEE, 80% to 20%

VIN = 2Vp-p Input frequency at –3dB

Input = 1MHz, FS

{

Clock = 75MHz Input = 18.75MHz, FS

{

Clock = 75MHz Input = 18.749MHz, FS Error > 16LSB

{

Clock = 75MHz NTSC 40IRE mod. ramp,

}

Fc = 75MSPS

–1.03

150

–150

0.9

2.1

46 40

1.0

0.5

–104

580

–1.62

–9

10

V

V ns ns

MHz

dB dB

TPS

%

deg

mA

mW

∗1

– 7 –