Sonic Alert msm80154s, msm83c154s, msm85c154hvs User Manual
MSM80C154S
MSM83C154S
MSM85C154HVS
USER'S MANUAL
Copyright 1988, OKI ELECTRIC INDUSTRY COMPANY, LTD.
OKI makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained
herein.
OKI retains the right to make changes to these specifications at
any time, without notice.
CONTENTS
1. INTRODUCTION
1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline ..................................3
1.2 MSM80C154S/MSM83C154S Features.............................................................5
1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS...........7
2. SYSTEM CONFIGURATION
2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols ....................11
2.2 MSM80C154S/MSM83C154S Pin Layout ........................................................12
2.2.1 MSM80C154S/MSM83C154S external dimensions..................................15
2.2.2 MSM85C154HVS pin layout and external dimensions..............................17
2.3 MSM80C154S Block Diagram ..........................................................................18
2.4 MSM83C154S Block Diagram ..........................................................................19
2.5 MSM85C154HVS Block Diagram .....................................................................20
2.6 Timing and Control ...........................................................................................21
2.6.1 Outline of MSM80C154S/MSM83C154S timing........................................21
2.6.2 Major synchronizing signals ......................................................................23
(1) ALE ......................................................................................................23
(2) PSEN ...................................................................................................23
(3) WR ...................................................................................................... 23
(4) RD ....................................................................................................... 23
2.6.3 MSM80C154S fundamental operation time charts....................................24
(1) External program memory read cycle timing chart...............................24
(2) MOVX A, @Rr......................................................................................24
(3) MOVX @Rr, A......................................................................................25
(4) MOVX A, @DPTR................................................................................25
(5) MOVX @DPTR, A................................................................................26
(6) MOV direct, PORT[0, 1, 2, 3] execution...............................................26
2.6.4 MSM83C154S fundamental operation time charts....................................27
(1) MOVX A, @Rr......................................................................................27
(2) MOVX @Rr, A..................................................................................... 27
(3) MOVX A, @DPTR................................................................................28
(4) MOVX @DPTR, A................................................................................28
(5) MOV direct, PORT[0, 1, 2, 3] execution...............................................29
2.7 Instruction Register (IR) and Instruction Decoder (PLA) ..................................30
2.8 Arithmetic Operation Section ............................................................................31
(1) Outline..................................................................................................31
(2) Arithmetic operation instruction decoder..............................................31
(3) Arithmetic and logic unit (ALU).............................................................31
2.9 Program Counter ..............................................................................................32
2.10 Program Memory and External Data Memory ..................................................33
2.10.1 MSM80C154S/MSM83C154S program area and
external ROM connections ........................................................................33
2.10.2 Procedures and circuit connections used when external
data memory (RAM) is accessed by data pointer (DPTR) ........................35
2.10.3 Procedures and circuit connections used when external
data memory (RAM) is accessed by registers R0 and R1.........................38
3. CONTROL
3.1 Oscillators [XTAL1 .2] .......................................................................................43
3.2 CPU Resetting ..................................................................................................45
3.2.1 Outline .......................................................................................................45
3.2.2 Reset Schmitt trigger circuit.......................................................................50
3.2.3 CPU internal status by reset......................................................................51
3.3 EA(CPU Memory Separate)..............................................................................52
3.3.1 Outline .......................................................................................................52
(1) Internal ROM mode..............................................................................52
(2) External ROM mode.............................................................................52
4. INTERNAL SPECIFICATIONS
4.1 Internal Data Memory (RAM) and Special Function Registers .........................55
4.1.1 Outline ..........................................................................................................55
4.2 Internal Data Memory (RAM)............................................................................57
4.2.1 Internal data memory (RAM) .....................................................................57
4.2.2 Internal data memory registers R0 thru R7 ...............................................59
4.2.3 Stack..........................................................................................................60
4.3 Internal Data Memory (RAM) Operating Procedures........................................61
4.3.1 Internal data memory indirect addressing .................................................61
4.3.2 Internal data memory register R0 thru R7 designation..............................62
4.3.3 Internal data memory 1-bit data designation .............................................63
4.4 Special Function Registers(TCON, SCON,...ACC, B) ......................................65
4.4.1 Outline .......................................................................................................65
4.4.2 Special function registers ..........................................................................67
4.4.2.1 Timer mode register (TMOD) ................................................................67
4.4.2.2 Power control register (PCON)..............................................................68
4.4.2.3 Timer control register (TCON) ...............................................................69
4.4.2.4 Serial port control register (SCON)........................................................70
4.4.2.5 Interrupt enable register (IE)..................................................................71
4.4.2.6 Interrupt priority register (IP)..................................................................72
4.4.2.7 Program status word register (PSW).....................................................73
4.4.2.8 I/O control register (IOCON)..................................................................74
4.4.2.9 Timer 2 control register (T2CON) ..........................................................75
4.5 Timer/Counters 0, 1, and 2 ...............................................................................76
4.5.1 Outline .......................................................................................................76
4.5.2 Timer/counters 0 and 1..............................................................................76
4.5.2.1 Outline ...................................................................................................76
4.5.2.2 Timer/counter 0 and 1 counting control .................................................76
4.5.2.3 Timer/counter 0 and 1 count clock designation .....................................78
4.5.2.3.1 External clock detector circuit for timer/counters 0 and 1 ...............79
4.5.2.4 Counting control of timer/counters 0 and 1 by INT pin ..........................80
4.5.2.5 Timer/counters 0/1 timer modes............................................................82
4.5.2.5.1 Outline ............................................................................................82
4.5.2.5.2 Mode 0............................................................................................82
4.5.2.5.3 Mode 1............................................................................................84
4.5.2.5.4 Mode 2............................................................................................86
4.5.2.5.5 Mode 3............................................................................................88
4.5.2.5.6 32-bit timer mode............................................................................89
4.5.2.5.7 Caution about use of timer counters 0 and 1..................................90
4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software
power down mode...........................................................................91
4.5.3 Timer/counter 2 .........................................................................................92
4.5.3.1 Outline ...................................................................................................92
4.5.3.2 Timer 2 control register (T2CON) ..........................................................92
4.5.3.3 Timer/counter 2 operation modes..........................................................93
4.5.3.3.1 16-bit auto reload mode..................................................................93
4.5.3.3.2 16-bit capture mode ........................................................................94
4.5.3.3.3 16-bit baud rate generator mode ....................................................95
4.5.3.4 Timer/counter 2 detector circuit .............................................................97
4.5.3.4.1 T2(timer/counter 2 external clock detector) ....................................97
4.5.3.4.2 T2EX(timer/counter 2 external flag input detector) .........................97
4.5.3.5 Timer/counter carry signal detector circuit.............................................98
4.6 Serial Port .........................................................................................................99
4.6.1 Outline .......................................................................................................99
4.6.2 Special function registers for serial port ..................................................101
4.6.2.1 SCON ..................................................................................................101
4.6.2.2 SBUF ...................................................................................................103
4.6.2.3 TCLK ...................................................................................................103
4.6.2.4 RCLK ...................................................................................................103
4.6.2.5 SMOD..................................................................................................104
4.6.2.6 SERR ..................................................................................................105
4.6.3 Operating modes .....................................................................................106
4.6.3.1 Mode 0.................................................................................................106
4.6.3.1.1 Outline...........................................................................................106
4.6.3.1.2 Mode 0 baud rate..........................................................................106
4.6.3.1.3 Mode 0 transmit operation ............................................................106
4.6.3.1.4 Mode 0 receive operation .............................................................106
4.6.3.2 Mode 1..................................................................................................110
4.6.3.2.1 Outline...........................................................................................110
4.6.3.2.2 Mode 1 baud rate..........................................................................110
4.6.3.2.3 Mode 1 transmit operation ............................................................111
4.6.3.2.4 Mode 1 receive operation .............................................................111
4.6.3.2.5 Mode 1 UART error detection.......................................................112
4.6.3.3 Mode 2.................................................................................................115
4.6.3.3.1 Outline...........................................................................................115
4.6.3.3.2 Mode 2 baud rate..........................................................................115
4.6.3.3.3 Mode 2 transmit operation ............................................................115
4.6.3.3.4 Mode 2 receive operation .............................................................115
4.6.3.3.5 Mode 2 UART error detection.......................................................116
4.6.3.4 Mode 3.................................................................................................119
4.6.3.4.1 Outline...........................................................................................119
4.6.3.4.2 Mode 3 baud rate..........................................................................119
4.6.3.4.3 Mode 3 transmit operation ............................................................120
4.6.3.4.4 Mode 3 receive operation. ............................................................120
4.6.3.4.5 Mode 3 UART error detection.......................................................121
4.6.4 Serial port application examples..............................................................124
4.6.4.1 I/O extension .......................................................................................124
4.6.4.2 Multi-processor systems......................................................................128
4.7 Interrupt.............................................................................................................129
4.7.1 Outline .....................................................................................................129
4.7.2 Interrupt enable register (IE)....................................................................131
4.7.3 Interrupt priority register (IP)....................................................................132
4.7.3.1 Priority interrupt routine flow................................................................133
4.7.3.2 Interrupt routine flow when priority circuit is stopped...........................134
4.7.3.3 Interrupt priority when priority register (IP) contents are all “0” ...........135
4.7.4 Detection of external interrupt signals INT0 and INT1 .............................136
4.7.4.1 Outline of INT signal detection.............................................................136
4.7.4.2 External interrupt signal 0 and 1 level detection..................................136
4.7.4.3 External interrupt signal 0 and 1 trigger detection ...............................137
4.7.5 MSM80C154S/MSM83C154S interrupt response time charts ................138
4.7.5.1 Interrupt response time chart when interrupt conditions are satisfied
during execution of ordinary instruction in main routine ......................138
4.7.5.2 Interrupt response time chart when interrupt conditions are satisfied
during execution of IE or IP register operation instruction in main
routine..................................................................................................140
4.7.5.3 Interrupt response time chart when an ordinary instruction is
executed after temporarily returning to the main routine from
continuous interrupt processing...........................................................142
4.7.5.4 Interrupt response time chart when an IE or IP manipulating
instruction is executed after temporarily returning to the main
routine from continuous interrupt processing ......................................144
4.8 CPU “Power Down” ........................................................................................146
4.8.1 Outline .....................................................................................................146
4.8.2 Idle mode (IDLE) setting..........................................................................146
4.8.3 Soft power down mode (PD) setting........................................................151
4.8.3.1 Caution about software power down mode setting .............................151
4.8.4 Hard power down mode (HPD) setting....................................................161
4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation) 169
4.9.1 Outline .....................................................................................................169
4.9.2 Cancellation by CPU resetting (RESET pin) ...........................................169
4.9.3 Cancellation of CPU power down mode(IDLE, PD)by interrupt signal ....176
4.9.3.1 Cancellation of CPU power down mode (IDLE, PD) from interrupt
address................................................................................................176
4.9.3.2 Cancellation of CPU power down mode (IDLE, PD) by interrupt
request signal and restart from next address of stop address.............182
4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode .......187
5. INPUT/OUTPUT PORTS
5.1 Outline ............................................................................................................192
5.2 Port 0 ..............................................................................................................192
5.3 Port 1 ..............................................................................................................195
5.4 Port 2 ..............................................................................................................201
5.5 Port 3 ..............................................................................................................203
5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down
Mode (PD, HPD).............................................................................................205
5.7 High Impedance Input Port Setting of Each Quasi-bidirectional
Port 1, 2, and 3 ...............................................................................................207
5.8 100 kW Pull-Up Resistance Setting for Quasi-bidirectional Input
Ports 1, 2, and 3 .............................................................................................207
5.9 Precautions When Driving External Transistors by Quasi-bidirectional
Port Output Signals.........................................................................................208
5.10 Port Output Timing..........................................................................................210
1) One machine cycle instruction output timing ..............................................210
2) Two machine cycle instruction output timing ..............................................211
5.11 Port Data Manipulating Instructions................................................................212
6. ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings ............................................................................216
6.2 Operational Ranges........................................................................................216
6.3 DC Characteristics..........................................................................................217
6.4 External Program Memory Access AC Characteristics ..................................221
6.5 External Data Memory Access AC Characteristics.........................................223
6.6 Serial Port (I/O Extension Mode) AC Characteristics .....................................225
6.7 AC Characteristics Measuring Conditions ......................................................227
6.8 XTAL1 External Clock Input Waveform Conditions ........................................228
7. DESCRIPTION OF INSTRUCTIONS
7.1 Outline ............................................................................................................231
7.2 Description of Instruction Symbols .................................................................232
7.3 List of Instructions...........................................................................................233
7.4 Simplified Description of Instructions..............................................................234
7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions ...............246
1. INTRODUCTION
MSM80C154S/83C154S/85C154HVS
2
INTRODUCTION
1. INTRODUCTION
1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline
MSM80C154S/MSM83C154S/MSM85C154HVS are single-chip 8-bit fully static microcontrollers featuring high performance and low power consumption. All MSM80C31F /MSM80C51F
instructions and functions have been retained.
Apart from being without the internal program memory (ROM), MSM80C154S is identical to
MSM83C154S. And the difference between MSM85C154HVS and MSM83C154S is that the
internal program memory (ROM) in MSM83C154S is replaced by an external ROM
connected to MSM85C154HVS by using a piggy-back package.
While the MSM83C154S microcontroller integrates a 16384-word × 8-bit program memory
(ROM) in a single chip, MSM80C154S/MSM83C154S/MSM85C154HVS all feature computer functions including a 256-word × 8-bit data memory (RAM), 32 input/ output ports, three
16-bit timer/counters, six interrupts, serial I/O, an 8-bit parallel processing circuit, and a clock
generator.
The internal operation in these CPUs is based on an instruction code address method for
greater efficiency. In this method, operations are specified in the instruction code (OP)
section, and the objective registers are specified by part of that instruction code and the
second or third byte following the code. A feature of this method is the ability to achieve
several operations by simply changing the manipulation register designation in a single
instruction code.
Inclusion of 8-bit multiplication and division instructions further increases the processing
capacity of these CPUs.
In addition to expansion of the bit processing area, a comprehensive range of bit processing
instructions has also been included. Processing operations include logical processing of the
carry flag and specified bit within each register, transfer between the carry flag and specified
bit in certain registers, transfer of specified bits between different registers, setting, resetting,
and complement of the specified bit in each register, and execution of various bit tests within
a wide area.
To make a relative jump after the execution of a bit test instruction, jumps can be made within
a wide address range between –128 and +127 relative to the address of the instruction and
there is no page field restriction.
The contents of specified registers can be saved in stack by using the PUSH instruction, and
the saved contents can be returned from stack to a specified register by the POP instruction.
Absolute interrupt priority can be allocated to any interrupt when in priority circuit operation
mode. And by controlling only the interrupt enable register (IE) when in priority circuit stop
mode, multi-level interrupt processing can be executed to make interrupt processing much
easier than in conventional CPUs.
Employing the low-power consumption feature of C-MOS devices, these CPUs are designed
to operate in a number of “CPU power down” modes. In idle mode the IDL bit in the power
control register (PCON) is set to “1” to halt CPU operations while the oscillator continues to
run. In soft power down mode the PD bit in the power control register is set to “1” to halt CPU
operations as well as the oscillator. And in hard power down mode where the HPD bit in the
power control register is set in advance to “1”, CPU operations and the oscillator are stopped
if the HPDI pin (P3.5) power failure detect signal level is changed from “1” to “0”. CPU power
down modes can be cancelled by resetting the CPU via reset pin and restarting execution
from address 0, by restarting execution from the relevant interrupt address, or by resuming
3
MSM80C154S/83C154S/85C154HVS
execution from the next address after the stop address where CPU power down mode was
activated.
Each of the quasi-bidirectional ports 1, 2, and 3 can be set independently as high impedance
input ports. And the 10 kW pull-up resistance for these input ports can be isolated from the
power supply (VCC), leaving only the 100 kW pull-up resistance and thereby enabling the
quasi-bidirectional ports to be driven by devices with low drive capacity. Furthermore, the
outputs of ports, 0, 1, 2, and 3 can be switched to floating status during CPU power down
modes (PD, HPD).
Three built-in 16-bit timer/counters capable of operating in a wide range of modes enable the
CPUs to be used in many different ways. And since timer/counters 0 and 1 can be operated
by external clock during CPU power down modes (PD, HPD) where the oscillator is stopped,
these two counters can also be used in cancelling CPU power down modes.
UART based serial communication can be executed at any baud rate by carry signal from
timer/counter 1 or timer/counter 2.
If an overrun or framing error is generated during data reception, the SERR bit in the I/O
control register is set. And by testing this SERR bit, the accuracy of the data can be checked
quite easily to ensure correct serial communication.
As can be seen, these CPUs are equipped with a very comprehensive range of functions. Also
note that EASE80C51mkII is available for use as the program development support system
for these CPUs.
Equipped with the MSM85C154E dedicated evachip, EASE80C51mkII is capable of program area mapping, realtime tracing, generating breaks according to accumulator contents,
and various other functions designed for accurate and efficient support of program development of these CPUs.
With this great line-up of functions and with EASE80C51mkII capable of developing
programs in a very short time, MSM80C154S/MSM83C154S/MSM85C154HVS give a highly
integrated high performance solution.
4
INTRODUCTION
1.2 MSM80C154S/MSM83C154S Features
• Full static circuitry
• Internal program memory (ROM)
16384 words × 8 bits (MSM83C154S)
• External program memory (ROM)
Connectable up to 64K bytes
• Internal data memory (RAM)
256 words × 8 bits
• External data memory (RAM)
Connectable up to 64K bytes
• Four sets of working registers (R0 thru R7 × 4)
• Stack
Free use of 256-word × 8-bit internal data memory area
• Four input/output ports (8-bit × 4)
• Serial ports (UART operation)
• Six types of interrupts
(1) Two external interrupts
(2) Three timer interrupts
(3) One serial port interrupt
* Priority allocated interrupt processing
* Multi-level interrupt processing by software management
• CPU power down function
(1) Idle mode: CPU stopped while oscillation continued.
(Software setting)
(2) PD mode: CPU and oscillation all stopped.
(Software setting)
(Setting I/O ports to floating status possible)
(3) HPD mode: CPU and oscillation all stopped.
(Hardware setting)
(Setting I/O ports to floating status possible)
• CPU power down mode cancellation
(1) Execution commenced from address 0 by CPU resetting.
(IDLE, PD, and HPD mode cancellation)
* RESET pin is used
(2) Execution from interrupt address by interrupt request, or execution resumed from next
address after the stop address. (IDLE and PD mode cancellation)
* External, timer, and serial port interrupts
• I/O control registers (0F8H)
b0: Port 0, 1, 2, and 3 floating setting (PD, HPD)
b1: Port 1 high impedance input port setting
b2: Port 2 high impedance input port setting
b3: Port 3 high impedance input port setting
b4: Port 1, 2, and 3 pull-up resistance switching (10 kW pull-up resistance switch off to
leave only 100 kW)
b5: Serial port reception error detector bit
b6: 32-bit timer mode setting (TL0+TH0+TL1+TH1)
5
MSM80C154S/83C154S/85C154HVS
• Timer/counters (three 16-bit timer/counters)
(1) 8-bit timer with 5-bit prescalar
(2) 16-bit timer
(3) 8-bit timer with 8-bit auto-reloader
(4) 8-bit separate timer
(5) 16-bit timer with 16-bit auto-reloader
(6) 16-bit capture timer
(7) 16-bit baud rate generator timer
(8) 32-bit timer
• Wide operating temperature range –40 to +85°C
• Wide operating voltage range
(1) When operating: VCC=+2.2 to 6V (varies according to frequency)
(2) When stopped:
VCC=+2 to +6V (PD or HPD mode)
• Instruction execution cycle
(1) 2-byte 1-machine cycle instructions
(2) Multiplication/division instructions
• Direct initialization of ports 0, 1, 2, and 3 by input of reset signal even if oscillator have been
stopped.
(All ports output “1”.)
• High noise margin (with Schmitt trigger input for each I/O)
• 40-pin plastic DIP/44-pin plastic flat package/44-pin plastic PLCC/44/pin plastic TQFP
• Software compatibility with MSM80C31F and MSM80C51F
6
INTRODUCTION
1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS
In addition to the basic operations of MSM80C31F/MSM80C51F, the MSM80C154S/
MSM83C154S/MSM85C154HVS devices also include the following functions.
• ROM capacity increased from 4K bytes to 16K bytes
• RAM capacity increased from 128 bytes to 256 bytes
• An additional timer counter 2
• An additional timer interrupt 2
• An additional 8-bit timer 2 control register (T2CON 0C8H)
• An additional 8-bit I/O control register (IOCON 0F8H)
• Addition of two bits (bit 5, PT2 and bit 7, PCT) to the priority register (IP 0B8H)
• Addition of one bit (bit 5, ET2) to the interrupt enable register (IE 0A8H)
• Addition of two bits (bit 5, RPD and bit 6, HPD) to the power control register (PCON 87H)
Addition of these extra functions has further increased the performance and widen the range
of application of these CPU devices.
7
MSM80C154S/83C154S/85C154HVS
8
2. SYSTEM
CONFIGURATION
MSM80C154S/83C154S/85C154HVS
10
SYSTEM CONFIGURATION
2. SYSTEM CONFIGURATION
2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols
RESET
ADDRESS LATCH
ENABLE
PROGRAM STORE
ENABLE
CPU MEMORY
SEPARATE
+5(V)
XTAL1
XTAL2
RESET
ALE
PSEN
EA
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
PORT 0
(BUS PORT)
T2
T2EX
PORT 1
PORT 2
P3.0
0(V)
Figure 2-1 MSM80C154S/83C154S/85C154HVS logic symbols
VSS
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD
TXD
INT0
INT1
T0
T1/HPDI
WR
RD
11
PORT 3
MSM80C154S/83C154S/85C154HVS
2.2 MSM80C154S/MSM83C154S pin layouts
MSM80C154SRS/MSM83C154SRS
(Top View) 40 Pin Plastic DIP
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/HPDI
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
MSM80C154SGS/MSM83C154SGS
(Top View) 44 Pin Plastic Package
10
11
12
13
14
15
16
17
18
19
20
1P1.0/T2
2P1.1/T2EX
3P1.2
4P1.3
5P1.4
6P1.5
7P1.6
8P1.7
9RESET
MSM80C154SRS/MSM83C154SRS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2NCVCC
4443424140 39 3837363534
1P1.5
2P1.6
3P1.7
4RESET
5P3.0/RXD
6NC
7P3.1/TXD
8P3.2/INT0
9P3.3/INT1
10P3.4/T0
11P3.5/T1/HPDI
1213141516 17 1819202122
P3.7/RD
P3.6/WR
MSM83C154SGS
VSS
XTAL2
XTAL1
P0.0
O0.1
MSM80C154SGS/
VSS
P2.0
P2.1
P2.2
12
P0.2
33
32
31
30
29
28
27
26
25
24
23
P2.3
P0.3
P0.4
P0.5
P0.6
P0.7
EA
NC
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
MSM80C154SJS/MSM83C154SJS
(Top View) 44 Pin Plastic QFJ
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2NCVCC
654321
7P1.5
8P1.6
9P1.7
10RESET
11P3.0/RXD
12NC
13P3.1/TXD
14P3.2/INT0
15P3.3/INT1
16P3.4/T0
17P3.5/T1/HPDI
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
MSM80C154SJS/MSM83C154SJS
VSS
XTAL2
XTAL1
P3.7/RD
P0.0
44 43 42 41 40
NC
P2.0
P2.1
SYSTEM CONFIGURATION
P0.1
P0.2
P0.3
39 P0.4
38 P0.5
37 P0.6
36 P0.7
35 EA
34 NC
33 ALE
32 PSEN
31 P2.7
30 P2.6
29 P2.5
P2.2
P2.3
P2.4
MSM80C154STS/MSM83C154STS
(Top View) 44 Pin Plastic Package
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2NCVCC
4443424140 39 3837363534
1P1.5
2P1.6
3P1.7
4RESET
5P3.0/RXD
6NC
7P3.1/TXD
8P3.2/INT0
9P3.3/INT1
10P3.4/T0
11P3.5/T1/HPDI
1213141516 17 1819202122
P3.7/RD
P3.6/WR
MSM83C154STS
VSS
XTAL2
XTAL1
P0.0
O0.1
P0.2
P0.3
33
P2.1
P2.2
32
31
30
29
28
27
26
25
24
23
P2.3
P2.4
MSM80C154STS/
VSS
P2.0
P0.4
P0.5
P0.6
P0.7
EA
NC
ALE
PSEN
P2.7
P2.6
P2.5
Figure 2-2 MSM80C154S/MSM83C154S pin layout (top view)
13
MSM80C154S/83C154S/85C154HVS
Applicable Packages
40-Pin Plastic DIP (DIP40-P-600-2.54)
44-Pin Plastic QFJ (QFJ44-P-S650-1.27)
44-Pin Plastic QFP (DFP44-P-910-0.80-2K)
44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K)
40-Pin Ceramic Piggy Back (ADIP40-C-600-2.54)
MSM80C154S RS
MSM83C154S-XXX RS
MSM80C154S JS
MSM83C154S-XXX JS
MSM80C154S GS-2K
MSM83C154S-XXX GS-2K
MSM80C154S TS-K
MSM83C154S-XXX TS-K
MSM85C154HVS
14
SYSTEM CONFIGURATION
2.2.1 MSM80C154S/MSM83C154S external dimensions
MSM80C154SRS/MSM83C154SRS
40-pin Plastic DIP (DIP40-P-600-2.54)
MSM80C154SGS/MSM83C154SGS
44-Pin Plastic QFP (QFP44-P-910-0.80-2K)
MSM80C154SJS/MSM83C154SJS
44-Pin Plastic QFJ (QFJ44-P-S650-1.27)
Figure 2-3 MSM80C154S/MSM83C154S external dimensions
15
MSM80C154S/83C154S/85C154HVS
MSM80C154STS/MSM83C154STS
44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K)
16
SYSTEM CONFIGURATION
2.2.2 MSM85C154HVS pin layout and external dimensions
M85C154H
2764/27128
Pin 1 for 2764, 27128
* The MSM85C154HVS pin layout of bottom side is the same as the pin layout for
MSM83C154SRS.
OKI
JAPAN XXXX
* The 27C64/128 device should be used for EPROM.
40-Pin Ceramic Piggy Back (ADIP40-C-600-2.54)
Figure 2-4 MSM85C154HVS pin layout and external dimensions
17
MSM80C154S/83C154S/85C154HVS
2.3 MSM80C154S Block Diagram
18
P2.0
PORT 2
P2.7
P0.0
PORT 0
Figure 2-5 MSM80C154S block diagram
P0.7
OSC AND TIMING
XTAL1
PCON IOCON
PCHL PCLL
XTAL2
ALE
PSEN
EA
RESET
T2CON TL2
P1.0
PORT 1
P1.7
P3.0
PORT 3
TH1
P3.7
DPH
CONTROL SIGNAL SIGNALR/W
SPECIAL
FUNCTION
DPL
PLA
REGISTER
ADDRESS
DECODER
SP
PCH
PCL
IR AIR
C-ROM
2H
R/W AMP
256WORD
×8bit
ACC TR2 TR1
RAMDP
PSW
INTERRUPT
SBUF
(T)
ALU
SBUF
(R)
SERIAL IO
BR
TH2
TIMER/
COUNTER 2
RCAP
RCAP
2L
TL1 TH0 TL0 TMOD TCON IE IP SCON
TIMER/COUNTER 0&1
2.4 MSM83C154S Block Diagram
19
P2.0
PORT 2 PORT 0 PCON IOCON
P2.7
P0.0
Figure 2-6 MSM83C154S block diagram
P0.7
XTAL1
OSC AND TIMING
PCHL PCLL
XTAL2
ALE
PSEN
EA
RESET
T2CON TL2
P1.0
PORT 1 PORT 3
P1.7
P3.0
TH1
P3.7
DPH
CONTROL SIGNAL SIGNALR/W
SPECIAL
ROM
16KWORD
×8bit
DPL
PLA
FUNCTION
REGISTER
ADDRESS
DECODER
SP
IR AIR
PCH
SENSE AMP
PCL
C-ROM
2H
R/W AMP
256WORD
×8bit
ACC TR2 TR1
RAMDP
PSW
INTERRUPT
SBUF
(T)
ALU
SBUF
(R)
SERIAL IO
BR
TH2
TIMER/
COUNTER 2
RCAP
RCAP
2L
TL1 TH0 TL0 TMOD TCON IE IP SCON
TIMER/COUNTER 0&1
SYSTEM CONFIGURATION
MSM80C154S/83C154S/85C154HVS
2.5 MSM85C154HVS Block Diagram
20
P2.0
PORT 2 PORT 0 PCON IOCON
P2.7
P0.0
Figure 2-7 MSM85C154HVS block diagram
P0.7
XTAL1
OSC AND TIMING
PCHL PCLL
XTAL2
ALE
PSEN
EA
RESET
T2CON TL2
P1.0
PORT 1 PORT 3
P1.7
P3.0
TH1
TL1 TH0 TL0 TMOD TCON IE IP SCON
P3.7
PCH
PCL
TIMER/
COUNTER 2
RCAP
2L
TIMER/COUNTER 0&1
SOCKET
A0
EXTERNAL
A13
16KWORD
×8bit
D0 ... D7
TH2
RCAP
2H
ROM
R/W AMP
256WORD
×8bit
DPH
DPL
SP
RAMDP
INTERRUPT
CONTROL SIGNAL SIGNALR/W
SPECIAL
FUNCTION
PLA
REGISTER
ADDRESS
DECODER
IR AIR
ACC TR2 TR1
PSW
SBUF
(T)
ALU
SBUF
(R)
SERIAL IO
C-ROM
BR
SYSTEM CONFIGURATION
2.6 Timing and Control
2.6.1 Outline of MSM80C154S/MSM83C154S timing
The MSM80C154S/MSM83C154S devices are both equipped with a built-in oscillation
inverter (see Figure 2-8) for use in the generation of clock pulses by external crystal or ceramic
resonator. These clock pulses are passed to the timing counter and control circuits where the
basic timing and control signals required for internal control purposes are generated.
The basic timing consists of state 1 (S1) thru state 6 (S6) (see Figure 2-9) where each state
cycle is based on two XTAL1·2 fundamental clock pulses. The interval from S1 thru S6 forms
a single machine cycle with a total of 12 fundamental clock pulses. 1-byte 1-machine cycle
and 2-byte 1-machine cycle instructions are fetched into the instruction register during
M1·S1, decoded during M1·S2, and executed during M1·S3 thru M1·S6. The second byte is
fetched during M1·S4. 1-byte 2-machine cycle, 2-byte 2-machine cycle, and 3-byte 2machine cycle instructions are also fetched during M1·S1, decoded during M1·S2, and
executed during M1·S3 thru M2·S6. The second and third bytes are fetched during M1·S4,
M2·S1, or M2·S4. The number of clocks used is 24. 1-byte 4-machine cycle instructions are
involved in multiplication and division operations where 48 clocks are used.
S1 S2 S3 S4 S5 S6
XTAL2
XTAL1
RESET
INT
DQ
Figure 2-8 Oscillator, timing counter, and control stage block diagram
DQ DQ DQ DQ DQ
S I/O & TIMER CONTROL
CPU CONTROL
1/2
1/2
POWER DOWN
IDLE
S I/O
TIMER & INTERRUPT
CPU
PLA
PLA OUT
21
MSM80C154S/83C154S/85C154HVS
M1
Instruction excecution
TM+1
M2
M1
M1
S1 S2 S3 S4 S5 S6
S1 S2 S3 S4 S5 S6
S1 S2 S3 S4 S5 S6
DPL & Rr
PCL PCL PCL PCL PCL PCLACC & RAM
PORT NEW DATA
DATA STABLE DATA STABLE
PORT OLD DATA
Instruction decoding
Instruction decoding
PC+1 PC+1
Instruction excecution
PC+1
Instruction excecution
TM+1 TM+1
TM+1
CYCLE
S1 S2 S3 S4 S5 S6
STEP
1
XTAL1
PCH PCH PCH PCH DPH & PORT DATA PCH PCH PCH
0
1
0
1
0
1
0
1
0
1
0
1
0
ALE
PSEN
RD/WR
PORT–0
PORT–2
CPU←PORT
Instruction decoding
1
0
PORT←CPU
Figure 2-9 MSM80C154S/MSM83C154S fundamental timing
22
PC+1 PC+1
SYSTEM CONFIGURATION
2.6.2 Major synchronizing signals
(1) ALE (Address Latch Enable)
The ALE signal is used as a clock signal where the address signals 0 thru 7 output from
CPU port 0 can be latched externally when external program or external data memory
(RAM) is used.
Although two ALE signal outputs are obtained in a single machine cycle during normal
operations, no output is obtained during output of the RD/WR signal when an external
memory instruction (MOVX...... ) is executed.
(2) PSEN (Program Store Enable)
The PSEN output signal is generated during execution of an external program. The
output is obtained when an instruction or data is fetched.
The PSEN signal is valid when at “0” level, and external program data is enabled when
in this valid state.
Although two PSEN signal outputs are obtained in a single machine cycle during
normal operations, no output is obtained during output of the RD/WR signal when an
external data memory instruction (MOVX...... ) is executed.
(3) WR (Write Strobe)
The WR output signal is obtained when an external data memory instruction (MOVX
@Rr, A or MOVX @ DPTR, A) is executed.
CPU port 0 output data is written in the external RAM when the WR signal is at “0” level.
(4) RD (Read Strobe)
The RD output signal is obtained when an external data memory instruction (MOVX
A, @ Rr or MOVX A, @ DPTR) is executed.
The external RAM is enabled and output data is passed to CPU port 0 when the RD
signal is at “0” level.
23
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