SMSC USB97C201 Technical data

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USB97C201

Rev 1.5

USB 2.0 ATA/ AT API Controller

FEATURES

 2.5 Volt, Low Power Core Operation
 3.3 Volt I/O with 5V input tolerance
 Complete USB Specification 2.0 Compatibility

- Includes USB 2.0 Transceiver

- A Bi-directional Control, a Bi-directional
Interrupt, and a Bi-directional Bulk Endpoint
are provided.

 Complete System Solution for interfacing ATA or

ATAPI devices to USB 2.0 bus

- Supports USB Mass Storage Compliant
Bootable BIOS

- Support for ATAPI Devices:

- CD-ROM

- CD-R

- CD-RW

- DVD

- DVD/R/W

 8051 8 bit microprocessor

- Provides low speed control functions

- 30 Mhz execution speed at 4 cycles per
instruction average

- 768 Bytes of internal SRAM for general
purpose scratchpad or program execution
while re-flashing external ROM

 Double Buffered Bulk Endpoint

- Bi-directional 512 Byte Buffer for Bulk
Endpoint

- 64 Byte RX Control Endpoint Buffer

- 64 Byte TX Control Endpoint Buffer

- 64 Byte TX Interrupt Endpoint Buffer

- 64 Byte RX Interrupt Endpoint Buffer

 External Program Memory Interface

- 64K Byte Code Space

- Flash, SRAM, or EPROM Memory

 On Board 12Mhz Crystal Driver Circuit
 Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz

MCU clock, and 60Mhz ATA clock

 Supports firmware upgrade via USB bus if “boot

block” Flash program memory is used

 8 GPIOs for special function use : LED indicators,

button inputs, etc.

- Inputs capable of generating interrupts with
either edge sensitivity

- One GPIO has automatic ½ sec toggle
capability for flashing an LED indicator.

 100 Pin TQFP Package (14.0 x 14.0 mm footprint)

- 25% smaller body size than other 100 pin
TQFP Packages

 100 Pin QFP Package

ORDERING INFORMATION

Order Numbers:

USB97C201-MN

for 100 pin TQFP package

USB97C201-MC

for 100 pin QFP package

SMSC DS – USB97C201 Page 1 Rev. 03/25/2002

PRELIMINARY

© STANDARD MICROSYSTEMS CORPORATION (SMSC) 2002

80 Arkay Drive
Hauppauge, NY 11788
[phone]
FAX [phone]

Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems
Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing S MSC products are incl uded
as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although
the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make
changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest speci fications
before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any
licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most
recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreem ent" ). T he product
may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anom aly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application
where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an
Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well
as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES
ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT
ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.

SMSC DS – USB97C201 Page 2 Rev. 03/25/2002

PRELIMINARY

TABLE OF CONTENTS

1.0 GENERAL DESCRIPTION..................................................................................................................................6

2.0 PIN TABLE..........................................................................................................................................................7

3.0 PIN CONFIGURATION........................................................................................................................................ 8

3.1 QFP/TQFP 100 Pin..........................................................................................................................8

4.0 BLOCK DIAGRAM.............................................................................................................................................. 9

5.0 PIN DESCRIPTIONS......................................................................................................................................... 10

5.1 BUFFER TYPE DESCRIPTIONS...................................................................................................13

6.0 FUNCTIONAL BLOCK DESCRIPTIONS..........................................................................................................14

6.1 MCU ...............................................................................................................................................14

6.1.1 MCU Memory Map: Code Space...........................................................................................14

6.1.2 MCU Memory Map: XData Space..........................................................................................15

6.1.3 MCU Block Register Summary..............................................................................................16

6.1.4 MCU Register Descriptions....................................................................................................19

6.2 SIE Block.......................................................................................................................................42

6.2.1 Autonomous USB Protocol....................................................................................................42

6.2.2 USB Events............................................................................................................................43

6.2.3 Standard Device Requests....................................................................................................44

6.2.4 SIE Configurations.................................................................................................................44

6.3 IDE Controller Description...........................................................................................................44

6.3.1 IDE Configurations.................................................................................................................45

6.3.2 PIO IDE Operations...............................................................................................................45

6.3.3 PIO IDE Data Prefetching and Posting..................................................................................45

6.3.4 DMA Transfers.......................................................................................................................46

6.3.5 Ultra ATA/66 Synchronous DMA Operation...........................................................................46

6.3.6 Ultra ATA/66 Operation..........................................................................................................47

6.4 SRAM Buffers................................................................................................................................48

6.5 8051 Options.................................................................................................................................48

6.6 Address Multiplexing ...................................................................................................................48

6.7 SRAM Time Multiplexer Operation .............................................................................................49

6.7.1 Phase 0 (Ø0)..........................................................................................................................49

6.7.2 Phase 1 (Ø1)..........................................................................................................................49

6.7.3 Phase 2 (Ø2)..........................................................................................................................49

6.7.4 Phase 3 (Ø3)..........................................................................................................................49

6.8 EP2 SRAM Buffer Operation........................................................................................................49

6.9 EP2 Automatic Buffer Operations...............................................................................................50

6.9.1 Receive Auto-Toggle .............................................................................................................50

6.9.2 Transmit Buffer Operation.....................................................................................................51

6.9.3 Automatic Transfer Operation................................................................................................52

7.0 DC PARAMETERS............................................................................................................................................ 54

8.0 AC SPECIFICATIONS....................................................................................................................................... 56

8.1 ATA/ATAPI.....................................................................................................................................56

8.2 USB2.0 Timing ..............................................................................................................................56

9.0 PACKAGING..................................................................................................................................................... 57

10.0 USB97C201 REVISIONS..............................................................................................................................59

SMSC DS – USB97C201 Page 3 Rev. 03/25/2002

PRELIMINARY

TABLES

Table 1 - USB97C201 Buffer Type Descriptions .........................................................................................................13

Table 2 - MCU Code Memory Map.............................................................................................................................. 14

Table 3 - MCU XData Memory Map ............................................................................................................................ 15

Table 4 - MCU Block Register Summary.....................................................................................................................16

Table 5 - 8051 Core SFR Register Summary..............................................................................................................18

Table 6 - Interrupt 0 Source Register..........................................................................................................................19

Table 7 - Interrupt 0 Mask........................................................................................................................................... 20

Table 8 - Interrupt 1 Source Register..........................................................................................................................20

Table 9 - Interrupt 1 Mask........................................................................................................................................... 21

Table 10 - Device Revision Register...........................................................................................................................21

Table 11 - Device Identification Register.....................................................................................................................21

Table 12 - GPIO Direction Register.............................................................................................................................22

Table 13 - GPIO Output Register................................................................................................................................24

Table 14 - GPIO Input Register................................................................................................................................... 24

Table 15 – GPIO Interrupt Status Register (INT4)......................................................................................................24

Table 16 – GPIO Interrupt Mask Register...................................................................................................................25

Table 17 - Utility Configuration Register......................................................................................................................26

Table 18 – SRAM Data Port Register..........................................................................................................................26

Table 19 – SRAM Address Register 1.........................................................................................................................26

Table 20 – SRAM Address Register 2.........................................................................................................................27

Table 21 - MCU Clock Source Select..........................................................................................................................27

Table 22 - Wakeup Source 1 Register (INT2).............................................................................................................28

Table 23 - Wakeup Mask 1 Register...........................................................................................................................28

Table 24 –USB Address Register ............................................................................................................................... 29

Table 25 – SIE Configuration Register........................................................................................................................29

Table 26 - USB Bus Status Register...........................................................................................................................30

Table 27 – USB Bus Status Mask Register.................................................................................................................30

Table 28 – SIE Status Register...................................................................................................................................31

Table 29 – SIE Status Mask Register..........................................................................................................................31

Table 30 – USB Configuration Number Register.........................................................................................................32

Table 31 – Endpoint 0 Receive Control Register........................................................................................................ 32

Table 32 – Endpoint 0 Transmit Control Register....................................................................................................... 32

Table 33 – Endpoint 1 Receive Control Register........................................................................................................ 32

Table 34 – Endpoint 1 Transmit Control Register....................................................................................................... 33

Table 35 – Endpoint 2 Control Register...................................................................................................................... 33

Table 36 – Endpoint 0 Receive Byte Count Register..................................................................................................34

Table 37 – Endpoint 0 Transmit Byte Count Register.................................................................................................35

Table 38 – Endpoint 1 Receive Byte Count Register..................................................................................................35

Table 39 – Endpoint 1 Transmit Byte Count Register.................................................................................................35

Table 40 – RAM Buffer Write Byte Count Register A1................................................................................................35

Table 41 – RAM BUFFER WRITE Byte Count Register A2 Register..........................................................................35

Table 42 – RAM Buffer Write Byte Count Register B1................................................................................................35

Table 43 – RAM Buffer Write Byte Count Register B2 Register..................................................................................36

Table 44 – RAM Buffer Read Byte Count Register A1................................................................................................ 36

Table 45 – RAM Buffer Read Byte Count Register A2 Register..................................................................................36

Table 46 – RAM Buffer Read Byte Count Register B1................................................................................................ 36

Table 47 – RAM Buffer Read Byte Count Register B2 Register..................................................................................36

Table 48 – NAK Register (INT5)..................................................................................................................................36

Table 49 – NAK Mask Register...................................................................................................................................37

Table 50 – USB Error Register.................................................................................................................................... 37

Table 51 – MSB ATA Data Register............................................................................................................................ 38

Table 52 – LSB ATA Data Register............................................................................................................................. 38

Table 53 – ATA Transfer Count Register 0................................................................................................................. 38

Table 54 – ATA Transfer Count Register 1................................................................................................................. 38

Table 55 – ATA Transfer Count Register 2................................................................................................................. 38

Table 56 – ATA Transfer Count Register 3................................................................................................................. 39

Table 57 –ATA Control Register..................................................................................................................................39

Table 58 –ATA Ultra DMA Timing Register................................................................................................................. 40

Table 59 – IDE Timing Register..................................................................................................................................40

Table 60 –ATA Slew Rate Control A Register............................................................................................................. 42

Table 61 –ATA Slew Rate Control B Register............................................................................................................. 42

Table 62 – IDE Transaction Timing............................................................................................................................. 45

Table 63 – ULTRA ATA/66 Control Signal Assignments.............................................................................................46

Table 64 –Buffer SRAM Mapping................................................................................................................................ 48

Table 65 – RAMWR_TOGGLE State Control..............................................................................................................51

SMSC DS – USB97C201 Page 4 Rev. 03/25/2002

PRELIMINARY

FIGURES

Figure 1 - MCU to EXTERNAL CODE SPACE MAP................................................................................................... 14

Figure 2 - GPIO MUXING BLOCK DIAGRAM............................................................................................................. 23

Figure 3 - RECEIVE BUFFER OPERATION...............................................................................................................51

Figure 4 - TRANSMIT BUFFER OPERATION............................................................................................................. 52

Figure 5 - AUTOMATIC DATA TRANSFER OPERATION ......................................................................................... 53

Figure 6 - 100 PIN TQFP PACKAGE.......................................................................................................................... 57

Figure 7 – 100 PIN QFP PACKAGE............................................................................................................................58

SMSC DS – USB97C201 Page 5 Rev. 03/25/2002

PRELIMINARY

1.0 GENERAL DESCRIPTION

The USB97C201 is a USB2.0 Mass Storage Class Peripheral Controller intended for use with standard ATA hard
drives and standard ATAPI-5 devices.

The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad and
768 of program SRAM, and an ATA-66 compatible interface.

Provisions for external Flash Memory up to 64K bytes for program storage is provided.
Internal 768 Bytes of program SRAM are also provided.. This internal SRAM is used for program storage to

implement program upgrade via USB download to “boot block” Flash program memory, if desired.
Eight GPIO pins are provided for controlling external power control elements and sensing specialized drive functions.

Provisions are made to allow dynamic attach and re-attach to the USB bus to allow hot swap of drives to be
implemented.

SMSC DS – USB97C201 Page 6 Rev. 03/25/2002

PRELIMINARY

2.0 PIN TABLE

IDE_D0 IDE_D1 IDE_D2 IDE_D3
IDE_D4 IDE_D5 IDE_D6 IDE_D7
IDE_D8 IDE_D9 IDE_D10 IDE_D11

IDE_D12 IDE_D13 IDE_D14 IDE_D15
IDE_nIOR IDE_nIOW IDE_IRQ IDE_DACK
IDE_DRQ IDE_nCS0 IDE_nCS1 IDE_SA0

IDE_SA1 IDE_SA2 IORDY

USBD+ USBD- LOOPFLTR RBIAS
RTERM FS+ FS-

MD0 MD1 MD2 MD3
MD4 MD5 MD6 MD7
MA0 MA1 MA2 MA3
MA4 MA5 MA6 MA7
MA8 MA9 MA10 MA11

MA12 MA13 MA14 MA15

nMRD nIOR nMWR nIOW

GPIO0 GPIO1 GPIO2 G PIO3

GPIO4/nWE GPIO5 GPIO6 GPIO7

XTAL1/CLKIN XTAL2 nRESET nTEST/nDBGSTR

TST_OUT/DBGOUT nTESTEN CLKOUT

DISK DRIVE INTERFACE (27 Pins)

USB INTERFACE (7 Pins)

MEMORY/IO INTERFACE (28 Pins)

MISC (15 Pins)

POWER, GROUNDS, and NO CONNECTS (23 Pins)

SMSC DS – USB97C201 Page 7 Rev. 03/25/2002

PRELIMINARY

3.0 PIN CONFIGURATION

3.1 QFP/TQFP 100 Pin

GPIO0

GPIO1

GPIO2

GPIO3

GND

GPIO4

GPIO5

GPIO6

GPIO7

nTEST0

nTEST1

nTEST2

VDDIO

IDE_D8

IDE_D7

IDE_D9

VDD

IDE_D6

IDE_D10

GND

IDE_D5

IDE_D11

IDE_D4

VDDIO

IDE_D12

RBIAS

VDDA

FS+

USB+

USB-

FS-

RTERM

VSSA

XTAL1/CLKIN

XTAL2

VSSP

LOOPFLTR

VDDP

N.C.

N.C.
MD7
MD6
MD5
MD4

GND

MD3
MD2
MD1
MD0

nRESET

75

51

IDE_D3
IDE_D13
IDE_D2
GND
IDE_D14
IDE_D1
IDE_D15
IDE_D0
VDDIO
IDE_DRQ
IDE_nIOW
IDE_nIOR

USB97C201

1

nIOR

nIOW

VDDIO

CLKOUT

MA15

MA14

GND

MA13

MA12

VDD

MA11

MA10

MA9

MA8

MA7

VDDIO

MA6

MA5

MA4

N.C.

MA3

MA2

MA1

25

MA0

GND

IORDY
GND
IDE_DACK
IDE_IRQ
IDE_SA1
IDE_SA0
VDD
IDE_SA2
IDE_nCS0
IDE_nCS1
VDDIO
nMWR
nMRD

SMSC DS – USB97C201 Page 8 Rev. 03/25/2002

PRELIMINARY

SMSC DS – USB97C201 Page 9 Rev. 03/25/2002

External PHY

OPTIONAL

( Serial Interface Engine )

( Transceiver )

7 pins

USB 2.0 PHY

SIE

Granted SRAM access

during Phase 0

RAMWR_A/B

RAMRD_A/B

EP1RX_BC

EP1TX_BC

EP0RX_BC

EP0TX_BC

4.0 BLOCK DIAGRAM

Auto address generators

PRELIMINARY

Address

CLOCKOUT

32 bit 15MHz Data Buss

Configuration and Control

12 MHz

XTAL

FAST 8051

CPU CORE

Granted SRAM access during Phase 1

MEM/IO Bus 29pins

Clock Generation

Osc

Interrupt Controller

Program/Scratchpad

768 Byte

SRAM

SIE Control Regs

Address Register

XDATA & SFR

8 bit Data busses

GPIO 8 pins

Interface

ATA-66

Address

Data @ 3 2 b it

15MHz

A
d

d

r

e

s

s

Address MUX

Latch phase 0

Latch phase 1 Latch phase 2

s

Future phase 3

s

u

Address

A
d

d

r

e

s

s

D

t

a

a

B

60MHz32 Bit

Address

Address

512 Bytes EP2 TX/RX Buffer A

512 Bytes EP2 TX/RX Buffer B

64 Bytes EP0RX

64 Bytes EP1RX

64 Bytes EP0TX

64 Bytes EP1TX

1.25KB

SRAM

Bus

Granted SRAM access

during Phase 2

ATA/ATAPI

Drive

Program Memory/ IO

5.0 PIN DESCRIPTIONS

IDE DMA
Request

IDE_DRQ IS This pin is the active high DMA request from

DISK DRIVE INTERFACE

the ATA/ATAPI interface.

IDE IO Read
Strobe

IDE Register
Address 1

IDE Register
Address 0

IDE Register
Address 2

IDE Data IDE_D15 IO20 This pin is the bi-directional data bus bit 15

IDE IO Write
Strobe

IDE DMA
Acknowledge

IDE Interrupt
Request

IDE Data IDE_D13 IO20 This pin is the bi-directional data bus bit 13

IDE_nIOR O20 This pin is the active low read signal for the

interface.

IDE_SA1 O20 This pin is the register select address bit 1

signal for the ATA/ATAPI interface.

IDE_SA0 O20 This pin is the register select address bit 0

signal for the ATA/ATAPI interface.

IDE_SA2 O20 This pin is the register select address bit 2

signal for the ATA/ATAPI interface.

signal for the ATA/ATAPI interface.

IDE_nIOW O20 This pin is active low write signal for the

ATA/ATAPI interface.

IDE_nDACK O20 This pin is the active low DMA acknowledge

signal for the ATA/ATAPI interface.

IDE_IRQ IS This pin is the active high interrupt request

signal for the ATA/ATAPI interface.

signal for the ATA/ATAPI interface.

IDE Data IDE_D14 IO20 This pin is the bi-directional data bus bit 14

signal for the ATA/ATAPI interface.
.

IDE Chip
Select 0

IDE Chip
Select 1 0

IDE Data IDE_D[0:12] IO20 These pins are bits 0-12 of the ATA/ATAPI bi-

IO Ready IORDY I This pin is the active high IORDY signal from

IDE_nCS0 O20 This pin is the active low chip select 0 signal

for the ATA/ATAPI interface.

IDE_nCS1 O20 This pin is the active low select 1 signal for the

ATA/ATAPI interface.

directional data bus.

the IDE drive.

SMSC DS – USB97C201 Page 10 Rev. 03/25/2002

PRELIMINARY

USB Bus
Data

USB
Transceiver
Filter

USB
Transceiver
Bias

Termination
Resistor

Full Speed
USB Data

Memory Data
Bus

Memory
Address Bus

Memory Write
Strobe

Memory Read
Strobe

IO Read
Strobe

IO Write
Strobe

USB INTERFACE

USB­USB+
LOOPFLTR This pin provides the ability to supplement the

RBIAS A 9.09 Kohm precision resistor is attached

RTERM A precision 1.5Kohm precision resistor is

FS­FS+

MD[7:0] IO12 These signals are used to transfer data

MA[15:0] O12 These signals address memory locations

nMWR O12 Program Memory Write; active low

nMRD O12 Program Memory Read; active low

nIOR O12 XDATA space Read; active low

nIOW O12 XDATA space Write; active low

IO-U These pins connect to the USB bus data

signals.

internal filtering of the transceiver with an
external network, if required.

from ground to this pin to set the transceiver’s
internal bias currents.

attached to this pin from a 3.3V supply.

IO-U These pins connect to the USB- and USB+

pins through 31.6 ohm series resistors.

MEMORY/IO INTERFACE

between the internal CPU and the external
program memory.

within the external memory.

SMSC DS – USB97C201 Page 11 Rev. 03/25/2002

PRELIMINARY

MISC

Crystal
Input/External
Clock Input

Crystal
Output

Clock Output CLKOUT O8 This pin produces a 30Mhz clock signal

General
Purpose I/O

RESET input nRESET IS This active low signal is used by the system to

Test input nTest[0:2} IP These signals are used for testing the chip.

XTAL1/
CLKIN

XTAL2 OCLKx 12Mhz Crystal

GPIO[0:7] IO20 These general purpose pins may be used

POWER, GROUNDS, and NO CONNECTS

VDD +2.5V Core power
VDDIO +3.3V I/O power
VDDP +2.5 Analog power
VSSP Analog Ground Reference
VDDA +3.3V Analog power
VSSA Analog Ground Reference
GND Ground Reference
NC No Connect. These pins should not be

ICLKx 12Mhz Crystal or external clock input.

This pin can be connected to one terminal of
the crystal or can be connected to an external
12Mhz clock when a crystal is not used.

This is the other terminal of the crystal, or left
open when an external clock source is used to
drive XTAL1/CLKIN. It may not be used to
drive any external circuitry other than the
crystal circuit.

independent of the processor clock divider. It
is held inactive and low whenever the internal
processor clock is stopped or is being
obtained from the ring oscillator.

either as inputs, edge sensitive interrupt
inputs, or outputs. In addition, GPIO0 has the
capability of auto-toggling at a 1Hz rate when
used as an output.

reset the chip. The active low pulse should be
at least 100ns wide.

User should normally leave them
unconnected. For board testing, all pads
except these test inputs are included in an
XNOR chain, such that by tying nTEST2 low,
nIOR will reflect the toggling of a signal on
each pin. Circuit board continuity of the pin
solder connections after assembly can be
checked in this manner

connected externally.

SMSC DS – USB97C201 Page 12 Rev. 03/25/2002

PRELIMINARY

5.1 BUFFER TYPE DESCRIPTIONS

Table 1 - USB97C201 Buffer Type Descriptions

BUFFER DESCRIPTION

I Input

IS Input with Schmitt trigger

IO8 Input/Output with 8 mA drive

O8 Output with 8mA drive

O12 Output with 12mA drive

IO20 Input/output with 20mA drive

OD12 Open drain….12mA sink

O20 Output with 20mA drive

ICLKx XTAL clock input

OCLKx XTAL clock output

I/O-U Defined in USB specification

SMSC DS – USB97C201 Page 13 Rev. 03/25/2002

PRELIMINARY

6.0 FUNCTIONAL BLOCK DESCRIPTIONS

6.1 MCU

The 64K memory map is as follows from the 8051's viewpoint:

6.1.1 MCU MEMORY MAP: CODE SPACE

The 8051 has a single flat 64K Code space. External memory requires 80ns access times from Address to Data and
less than 80ns output enable access times, assuming the use of the nMEMR signal as OE on the memory.

Table 2 - MCU Code Memory Map

8051 ADDRESS CODE SPACE ACCESS

0x0700-0xFFFF Fixed Memory External Program

Memory

0x0400-0x06FF 768 Bytes of Fixed 16k FLASH Page

OR
768 Bytes of Internal SRAM for program execution
(see bit 7 of the UTIL_CFG register for more

information)

0x0000-0x03FF Fixed Memory External Program

8051 MCU External Code Address

Space

0xFFFF

K

4

6

External Program
Memory

OR
Internal Program

SRAM

Memory

0x0700

0x0400
0x0000

FIGURE 1 - MCU TO EXTERNAL CODE SPACE MAP

SMSC DS – USB97C201 Page 14 Rev. 03/25/2002

Intern al 76 8 Byte

SRAM or External

Memory

PRELIMINARY

6.1.2 MCU MEMORY MAP: XDATA SPACE

Table 3 - MCU XData Memory Map

8051 ADDRESS DATA SPACE ACCESS

0x3F30-0xFFFF

0x3F00-0x3F2F
0x33F7-0X3EFF

033F6 External ATA Interface I/O External

0x31F8-0x33F5 External Memory or I/O Devices External

0x31F0-0x31F7 External ATA Interface I/O External

0x30F4-0x31EF External Memory or I/O Devices External

0X30F0-0X30F3 Internal Test Registers (reserved access) DO NOT ACCESS
0X0700-0X30EF External Memory or I/O Devices External

0x0400-0x06FF 768 Byte SRAM Internal
0x0000-0x03FF (see Note 1) External

External Memory or I/O Devices

Internal Test Registers (reserved access)
External Memory or I/O Devices

External
(IOR or IOW

active)
DO NOT ACCESS
External
(IOR or IOW

active)

(IOR or IOW
active)

(IOR or IOW
active)

(IOR or IOW
active)

(IOR or IOW
active)

(IOR or IOW
active)

(IOR or IOW
active)(see Note 1)

Note 1: This XDATA space is accessed using MOVX instructions. A region of 8051 Special Function Registers

(SFR) is also accessible at 0x0100 to 0x01FF addresses using the MOV instructions. In addition to the
normal 8051 SFRs, there are also numerous Runtime Registers in this SFR space. These Runtime
Registers are external to the 8051, but internal to the USB97C201.

SMSC DS – USB97C201 Page 15 Rev. 03/25/2002

PRELIMINARY

6.1.3 MCU BLOCK REGISTER SUMMARY

Table 4 - MCU Block Register Summary

(These registers are external to the 8051 design core)

ADDRESS NA ME R/W DESCRIPTION PAGE

RUNTIME REGISTERS

80 ISR_0 R/W INT0 Source Register 19
93 IMR_0 R/W INT0 Mask Register 20
90 ISR_1 R/W INT1 Source Register 20
94 IMR_1 R/W INT1 Mask Register 21
95 DEV_REV R Device Revision Register 21
96 DEV_ID R Device ID Register 21

UTILITY REGISTERS

97 GPIO_DIR R/W GPIO Direction Register 22
9A GPIO_OUT R/W GPIO Data Output Register 24
9B GPIO_IN R GPIO Data Input Register 24
C0 GPIO_IRQ R/W GPIO Interrupt Status Register (INT4) 24
9C GPIO_MSK R/W GPIO Interrupt Mask Register (INT4) 25
9D UTIL_CONFIG R/W Miscellaneous Configuration Register 26

9F SRAM_DATA R/W
A1 SRAM_ADD1 R/W SRAM Address 1 Register 26
A2 SRAM_ADD2 R/W SRAM Address 2 Register 27

POWER MANAGEMENT REGISTERS

A5 CLOCK_SEL R/W 8051 Clock Select Register 27
A0 WU_SRC_1 R/W Wakeup Source 1 Register (INT2) 28
A6 WU_MSK_1 R/W Wakeup Mask 1 Register (INT2) 28

SRAM Data Port Register

26

SMSC DS – USB97C201 Page 16 Rev. 03/25/2002

PRELIMINARY

SIE & BUFFER CONTROL REGISTERS

A9 USB_ADD R/W USB Address Register 29
AA SIE_CONF R/W SIE Configuration Register 29
AB USB_STAT R/W USB Bus Status Register 30
AC USB_MSK R/W USB Bus Status Mask Register 30
B0 SIE_STAT R SIE Status Register 31
AD USB_CONF R/W USB Configuration Number Register 32
AE SIE_MSK R/W SIE Status Mask Register 31
AF EP0RX_CTL R/W Endpoint 0 Receive Control Register 32
B1 EP0TX_CTL R/W Endpoint 0 Transmit Control Register 32
B2 EP1RX_CTL R/W Endpoint 1 Receive Control Register 32
B3 EP1TX_CTL R/W Endpoint 1 Transmit Control Register 33
B4 EP2_CTL R/W Endpoint 2 Control Register 33
B5 EP0RX_BC R/W Endpoint 0 Receive Byte Count Register 34
B6 EP0TX_BC R/W Endpoint 0 Transmit Byte Count Register 35
B7 EP1RX_BC R/W Endpoint 1 Receive Byte Count Register 35
C7 EP1TX_BC R/W Endpoint 1 Transmit Byte Count Register 35
CE RAMWRBC_A1 R/W RAM Buffer Write Byte Count Register A1 35
CF RAMWRBC_A2 R/W RAM Buffer Write Byte Count Register A2 35
D1 RAMWRBC_B1 R/W RAM Buffer Write Byte Count Register B1 35
D2 RAMWRBC_B2 R/W RAM Buffer Write Byte Count Register B2 36
D3 RAMRDBC_A1 R/W RAM Buffer Read Byte Count Register A1 36
D4 RAMRDBC_A2 R/W RAM Buffer Read Byte Count Register A2 36
D5 RAMRDBC_B1 R/W RAM Buffer Read Byte Count Register B1 36
D6 RAMRDBC_B2 R/W RAM Buffer Read Byte Count Register B2 36
D7 NAK R/W NAK Status Register 36
D9 NAK_MSK R/W NAK Mask Register 37
DA USB_ERR R USB Error Register 39

ATA CONFIGURATION REGISTERS
DB MSB_ATA R/W MSB ATA Data Register 38
DC LSB_ATA R/W LSB ATA Data Register 38
DD ATA_CTL R/W ATA Control Register 39
DE ATA_DMA R/W ATA Ultra DMA Timing Register 40
DF IDE_TIM R/W IDE Timing Register 40
E1 ATA_CNT0 R/W ATA Transfer Count Register 0 38
E2 ATA_CNT1 R/W ATA Transfer Count Register 1 38
E3 ATA_CNT2 R/W ATA Transfer Count Register 2 38
E4 ATA_CNT3 R/W ATA Transfer Count Register 3 39
E5 ATA_SRCA R/W ATA Slew Rate Control A Register 42
E6 ATA_SRCB R/W ATA Slew Rate Control B Register 42

SMSC DS – USB97C201 Page 17 Rev. 03/25/2002

PRELIMINARY

Table 5 - 8051 Core SFR Register Summary

These registers are part of the 8051 design core itself.

REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDRESS

SP 81h
DPL0 82h
DPH0 83h
DPL1 84h
DPH1 85h
DPS 0 0 00000SEL86h
PCON SMOD0 – 1 1 GF1 GF0 STOP IDLE 87h
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h
TMOD GATE C/T M1 M0 GATE C/T M1 M0 89h
TL0 8Ah
TL1 8Bh
TH0 8Ch
TH1 8Dh
CKCON T2M T1M T0M MD2 MD1 MD0 8Eh
SPC_
FNC
EXIF IE5 IE4 IE3 IE2 1 0 0 0 91h
MPAGE 92h
SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h
SBUF0 99h
IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h
IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h
TL2 CCh
TH2 CDh
PSW CY AC F0 RS1 RS0 OV F1 P D0h
EICON SMOD1 1 EPFI PFI WDTI 0 0 0 D8h
ACC E0h
EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E8h
B F0h
EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 F8h

0 0 00000WRS8Fh

Notes:

 Bit WRS of the SPC_FNC register controls the operation of MOVX writes the program or XDATA bus of the

8051. Setting it to 0 ( the reset state), will direct writes to the XDATA bus, either to internal or external
destinations, while setting it to 1 will allow writes to the program memory bus to occur, either internally( if the
768 SRAM is the target) or externally.

 Bits MD2:0 of the CKCON SFR register (8Eh) control the cycle timing for external accesses using the nIOR and

nIOW signals. This allows slow peripheral devices to be attached. The values and corresponding strobe widths
are shown below:

MD2 MD1 MD0 NIOR/NIOW STOBE

(CLKS)

0 0 0 2 66ns
0 0 1 4 133ns
0 1 0 8 267ns
0 1 1 12 400ns
1 0 0 16 533ns
1 0 1 20 667ns
1 1 0 24 800ns
1 1 1 28 933ns

Note: the strobe width will vary with the actual clock divider used for the processor. For example if, 16 Mhz is used,

an MD[2:0] value of 111 will result in a 28 clock strobe or 1866ns.

SMSC DS – USB97C201 Page 18 Rev. 03/25/2002

NIOR/NIOW STROBE (AT

30MHZ)

PRELIMINARY