SMSC USB97C100 Technical data
查询USB97C100QFP供应商
Multi-Endpoint USB Peripheral Controller
USB97C100
ADVANCE INFORMATION
FEATURES
High Performance USB Peripheral Controller
Engine
- Integrated USB Transceiver
- Serial Interface Engine (SIE)
- 8051 Microcontroller (MCU)
- Patented Memory Management Unit (MMU)
- 4 Channel 8237 DMA Controller
(ISADMA)
- 4K Byte On Board USB Packet Buffer
- Quasi-ISA Peripheral Interface
- USB Bus Snooping Capabilities
-GPIOs
Complete USB Specification 1.1 Compatibility
- Isochronous, Bulk, Interrupt, and Control
Data Independently Configurable per
Endpoint
- Dynamic Hardware Allocation of -Packet
Buffer for Virtual Endpoints
- Multiple Virtual Endpoints (up to 16 TX, 16
RX Simultaneously)
- Multiple Alternate Address Filters
- Dynamic Endpoint Buffer Length
Allocation (0-1280 Byte Packets)
High Speed (12Mbps) Capability
MMU and SRAM Buffer Allow Buffer Optimization
and Maximum Utilization of USB Bandwidth
- 128 Byte Page Size
- 10 Pages Maximum per Packet
- Up to 16 Deep Receive Packet Queue
- Up to 5 Deep Transmit Packet Queue, per
Endpoint
- Hardware Generated Packet Header
Records Each Packet Status Automatically
- Simultaneous Arbitration Between MCU,
SIE, and ISA DMA Accesses
Extended Power Management
- Standard 8051 "Stop Clock" Modes
- Additional USB and ISA Suspend
Resume Events
- Internal 8MHz Ring Oscillator for Immediate
Low Power Code Execution
- 24, 16, 12, 8, 4, and 2 MHz PLL Taps For on
the Fly MCU and DMA Clock Switching
- Independent Clock/Power Management for
SIE, MMU, DMA and MCU
DMA Capability with ISA Memory
- Four Independent Channels
- Transfer Between Internal and External
Memory
- Transfer Between I/O and Buffer Memory
- External Bus Master Capable
External MCU Memory Interface
- 1M Byte Code and Data Storage via 16K
Windows
- Flash, SRAM, or EPROM
- Downloadable via USB, Serial Port, or ISA
Peripheral
Quasi-ISA Interface Allows Interface to New and
"Legacy" Peripheral Devices
- 1M ISA Memory Space via 4K MCU Window
- 64K ISA I/O Space via 256 Byte MCU
Window
- 4 External Interrupt Inputs
- 4 DMA Channels
- Variable Cycle Timing
- 8 Bit Data Path
5V or 3.3v Operation
On Board Crystal Driver Circuit
128 Pin QFP Package
ORDERING INFORMATION
Order Number: USB97C100QFP
128 Pin QFP Package
SMSC DS – USB97C100 Rev. 01/03/2001
GENERAL DESCRIPTION
The USB97C100 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple
endpoint applications. The USB97C100 provides an ISA-like bus interface, which will allow virtually any PC peripheral to
be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput
disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection’s overall
bandwidth. This architecture minimizes the integrated microcontroller’s participation in the USB data flow, allowing backto-back packet transfers to block oriented devices. The efficiency of this architecture allows floppy drives to coexist with
other peripherals such as serial and parallel ports on a single USB link.
The USB97C100 allows external program code to be downloaded over the USB to allow easy implementation of varied
peripheral USB Device Classes and combinations. This also provides a method for convenient field upgrades and
modifications.
© STANDARD MICROSYSTEMS CORPORATION (SMSC) 2001
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems
Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing S MSC products are incl uded
as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although
the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make
changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest speci fications
before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any
licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most
recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreem ent" ). T he product
may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anom aly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application
where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an
Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well
as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES
ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT
ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS – USB97C100 Page 2 Rev. 01/03/2001
TABL E O F CONTENTS
FEATURES................................................................................................................................................................... 1
GENERAL DESCRIPTION............................................................................................................................................ 2
PIN CONFIGURATION................................................................................................................................................. 4
DESCRIPTION OF PIN FUNCTIONS........................................................................................................................... 5
BUFFER TYPE DESCRIPTIONS.................................................................................................................................. 7
FUNCTIONAL DESCRIPTION...................................................................................................................................... 9
Serial Interface Engine (SIE)......................................................................................................................................... 9
Micro Controller Unit (MCU).......................................................................................................................................... 9
SIEDMA......................................................................................................................................................................... 9
Memory Management Unit (MMU) Register Description............................................................................................... 9
ISADMA......................................................................................................................................................................... 9
Applications................................................................................................................................................................. 10
TYPICAL SIGNAL CONNECTIONS............................................................................................................................ 12
MCU MEMORY MAP.................................................................................................................................................. 13
Code Space................................................................................................................................................................. 13
Data Space.................................................................................................................................................................. 13
ISADMA Memory Map................................................................................................................................................. 13
MCU Block Register Summary.................................................................................................................................... 14
MMU Block Register Summary................................................................................................................................... 15
SIE Block Register Summary...................................................................................................................................... 16
MCU REGISTER DESCRIPTION................................................................................................................................ 17
MCU Runtime Registers.............................................................................................................................................. 17
FIFO Status Registers................................................................................................................................................. 20
MCU Power Management Registers...........................................................................................................................24
MCU ISA Interface Registers...................................................................................................................................... 27
8237 (ISADMA) REGISTER DESCRIPTION.............................................................................................................. 30
Memory Map................................................................................................................................................................30
Runtime Registers....................................................................................................................................................... 31
MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION....................................................................... 37
MMU Interface Registers............................................................................................................................................. 37
MMU FREE PAGES REGISTER................................................................................................................................. 40
16 BYTE DEEP TX COMPLETION FIFO REGISTER................................................................................................ 40
TX FIFO POP REGISTER........................................................................................................................................... 41
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION ............................................................................. 45
Packet Header Definition............................................................................................................................................. 45
SIE Interface Registers ............................................................................................................................................... 46
DC PARAMETERS..................................................................................................................................................... 51
USB PARAMETERS................................................................................................................................................... 53
USB DC PARAMETERS............................................................................................................................................. 53
USB AC PARAMETERS.............................................................................................................................................. 54
MECHANICAL OUTLINE............................................................................................................................................ 63
USB97C100 REVISIONS............................................................................................................................................ 64
SMSC DS – USB97C100 Page 3 Rev. 01/03/2001
PIN CONFIGURATION
SA11
SA12
nMEMW
nMEMR
nIOR
nIOW
AEN
VCC
SD0
SD1
SD2
SD3
GND
SD4
SD5
SD6
SD7
nDACK0
DRQ0
nDACK1
DRQ1
nDACK2
DRQ2
nDACK3
DRQ3
TC
SA10
SA9
SA8
SA7
SA6
SA5
SA4
GND
SA3
SA2
SA1
SA0
SA13
SA14
SA15
SA16
SA17
SA18
SA19
GND
IRQ3
IRQ2
IRQ1
IRQ0
VCC
nTEST
PWRGD
RESET_IN
TST_OUT
XTAL1
XTAL2
GND
CLKOUT
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
1
128
127
126
125
124
123
122
121
120
119
118
117
116
115
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657585960616263
USB97C100
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
nMASTER
VCC
READY
EXTCLK
FALE
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
USBD+
VCC3.3
USBDVCC
FA19
FA18
FA11
FA9
FA8
FA13
FA14
FA17
GND
nFWR
FA16
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
FA10
nFCE
nFRD
GPIO5
GPIO6
GPIO7
GND
VCC
FA7
FA12
FA15
FIGURE 1 - PIN CONFIGURATION
SMSC DS – USB97C100 Page 4 Rev. 01/03/2001
DESCRIPTION OF PIN FUNCTIONS
Table 1 - USB97C100 Pin Configuration
QFP PIN
NUMBER SYMBOL PIN DESCRIPTION
ISA INTERFACE
100 READY Channel is ready when high.
ISA memory or slave devices use this signal to lengthen a bus
cycle from the default time. Extending the length of the bus
cycle can only be done when the bus cycles are derived from
the Internal DMA controller core. 8051 MCU generated Memory
or I/O accesses cannot and will not be extended even if
READY is asserted low by an external ISA slave device. The
external slave device negates this signal after decoding a valid
address and sampling the command signals (nIOW, nIOR,
nMEMW, and nMEMR). When the slave’s access has
completed, this signal should be allowed to float high.
104, 106,
108, 110
105, 107,
109, 111
103 TC DMA Terminal Count; active high.
19-13,
127-7,
9-12
112-115,
117-120
122 AEN Address Enable
123 nIOW I/O Write; active low.
124 nIOR I/O Read; active low.
125 nMEMR Memory read; active low
126 nMEMW Memory write; active low
DRQ[3:0] DMA Request channels 3-0; active high.
These signals are used to request DMA service from the DMA
controller. The requesting device must hold the request signal
until the DMA controller drives the appropriate DMA
acknowledge signal (nDACK[3:0]).
nDACK
[3:0]
DMA Acknowledge channels 3-0; active low.
These signals are used to indicate to the DMA requesting
device that it has been granted the ISA bus.
This signal is used to indicate that a DMA transfer has
completed.
SA[19:0] System Address Bus
These signals address memory or I/O devices on the ISA bus.
SD[7:0] System Data Bus
These signals are used to transfer data between system
devices.
This signal indicates address validation to I/O devices. When
low this signal indicates that an I/O slave may respond to
addresses and I/O commands on the bus. This signal is high
during DMA cycles to prevent I/O slaves from interpreting DMA
cycles as valid I/O cycles.
This signal indicates to the addressed ISA I/O slave to latch
data from the ISA bus.
This signal indicates to the addressed ISA I/O slave to drive
data on the ISA bus.
This signal indicates to the addressed ISA memory slave to
drive data on the ISA bus.
This signal indicates to the addressed ISA memory slave to
latch data from the ISA bus.
BUFFER
TYPE
IP
I
O8
O8
O8
I/O8
O8
O8
O8
O8
O8
SMSC DS – USB97C100 Page 5 Rev. 01/03/2001
QFP PIN
NUMBER SYMBOL PIN DESCRIPTION
102 nMASTER External Bus master, active low
This signal forces the USB97C100 to immediately tri-state its
external bus, even if internal transactions are not complete. All
shared ISA signals are tri-stated, except 8237 nDACKs, which
can be used in gang mode to provide external bus-master
handshaking. This pin must be used with some handshake
mechanism to avoid data corruption.
21-24 IRQ[3:0] Interrupt Request 3-0; active high
These signals are driven by ISA devices on the ISA bus to
interrupt the 8051.
30 XTAL1/
Clock In
24MHz Crystal or clock input.
This pin can be connected to one terminal of the crystal or can
be connected to an external clock when a crystal is not used.
31 XTAL2 24MHz Crystal
This is the other terminal of the crystal.
99 EXTCLK Alternate clock to 8237
An external clock can be used for the internal 8237. This clock
can be used to synchronize the 8237 to other devices.
33 CLKOUT Clock output.
This clock frequency is the same as the 8051 running clock.
This clock is stopped when the 8051 is stopped. Peripherals
should not use this clock when they are expected to run when
the 8051 is stopped. This clock can be used to synchronize
other devices to the 8051.
USB INTERFACE
77, 79 USBD-
USDB+
USB Upstream Connection signals
These are two point-to-point signals and driven differentially.
FLASH INTERFACE
45-52 FD[7:0]
Flash ROM Data Bus
These signals are used to transfer data between 8051 and the
external FLASH.
75, 74, 68,
65, 64, 69,
70, 63, 73,
FA[19:0] Flash ROM Address Bus
These signals address memory locations within the FLASH.
43, 72, 71,
62-58,
56-54
42 nFRD Flash ROM Read; active low O8
66 nFWR Flash ROM Write; active low O8
44 nFCE Flash ROM Chip Select; active low O8
98 FALE Flash ROM address latch enable O8
POWER SIGNALS
25,57,76
VCC +3.3V power or 5V
101,121
78 VCC3.3 +3.3V power for USB
8, 20, 32,
GND Ground Reference
53, 67, 80,
97, 116
MISCELLANEOUS
41-34 GPIO[7:0] General Purpose I/O.
These pins can be configured as inputs or outputs under
software control.
BUFFER
TYPE
IP
I
ICLKx
OCLKx
ICLK
O8
IO-U
IO8
O8
I/O16
SMSC DS – USB97C100 Page 6 Rev. 01/03/2001
QFP PIN
NUMBER SYMBOL PIN DESCRIPTION
27 PWRGD Active high input.
This signal is used to indicate to that chip that a good power
level has been reached. When inactive/low, all pins are Tri-
stated except TST_OUT and a POR is generated.
28 RESET_IN Power on reset; active high
This signal is used by the system to reset the chip. It also
generates an internal POR.
29 TST_OUT AND tree output
This signal is used for testing the chip via an internal AND tree.
26 nTEST Test input
This signal is a manufacturing test pin. User can pull it high or
leave it unconnected.
[96:81] NC No connect
BUFFER TYPE DESCRIPTIONS
Table 2 - USB97C100 Buffer Type Description
BUFFER DESCRIPTION
I Input (no pull-up)
IP Input 90µA with internal pull-up
O8 Output with 8mA drive
I/O8 Input/output with 8mA drive
I/O16 Input/output with 16mA drive
O24 Output, 24mA sink, 12mA source.
I/ODP24 Input/Output drain , 24mA sink, 12mA source with 90µA pull-up
ICLKx XTAL clock input
OCLKx XTAL clock output
ICLK Clock input (TTL levels)
I/O-U Defined in USB specification; uses VCC3.3
BUFFER
TYPE
I
I
O8
IP
Note: These DC Characteristics/drive strengths apply to 5V operation only. See the DC Characteristics section for
additional details.
SMSC DS – USB97C100 Page 7 Rev. 01/03/2001
USB97C100 BLOCK DIAGRAM
USB Interface
USBD- USBD+
General
Purpose
IO
GPIO[0:7]
FD[7:0]
FA[19:0]
nFRD
nFWR
nFCE
Flash
Interface
End Point
Control
SIE DMA
Rx/TX
Queue
GPIO
8051
Serial Interfa c e
Engine
Arbiter
8237
Tranceiver
Memory
Management
Unit
4k Data Buffer RAM
Map RAM
IRQ[3:0]
SD[7:0],
SA[19:0]
nIOW,
nIOR,
nMEMW,
nMEMR
DRQ[3:0],
nDACK[3:0],
TC, AEN
Quasi ISA Bus
FIGURE 2 - BLOCK DIAGRAM
SMSC DS – USB97C100 Page 8 Rev. 01/03/2001
FUNCTIONAL DESCRIPTION
The USB97C100 incorporates a USB Serial Interface Engine (SIE), 8051 Microcontroller Unit (MCU), Serial Interface
Engine DMA (SIEDMA), a programmable 8237 ISA bus DMA controller (ISADMA), 4K bytes of SRAM for data
stream buffering, and a patented MMU (Memory Management Unit) to dynamically manage buffer allocation. The
semi-automatic nature of the SIEDMA, ISADMA, and MMU blocks frees the MCU to provide enumeration, protocol
and power management. A bus arbiter integrated into the MMU assures that transparent access between the
SIEDMA, ISADMA, and MCU to the SRAM occurs.
Serial Interface Engine (SIE)
The SIE is a USB low-level protocol interpreter. The SIE controls the USB bus protocol, packet
generation/extraction, parallel-to-serial/serial-to-parallel conversion, CRC coding/decoding, bit stuffing, and NRZI
coding/decoding.
The SIE can be dynamically configured as having any combination of 0-16 transmit, and 0-16 receive endpoints, for
up to 4 independent addresses. There are 3 alternate and one local address. The alternate addresses, for example,
can be used for Hub addresses. The SIE can also "Receive All Addresses" for bus snooping.
Micro Controller Unit (MCU)
The 8051 embedded controller is a static CMOS MCU which is fully software compatible with the industry standard
Intel 80C51 micro-controller. All internal registers of the USB97C100 blocks are mapped into the external memory
space of the MCU.
A detailed description of the microcontroller’s internal registers and instruction set can be found in the “USB97C100
Programmer’s Reference Guide”.
SIEDMA
This is a simplified DMA controller, which automatically transfers data between SIE and SRAM via MMU control. The
SIEDMA appends a status header containing frame number, endpoint, and byte count to each incoming packet
before notifying the MCU of its arrival. This block’s operation is transparent to the firmware.
Memory Management Unit (MMU) Register Description
This patented MMU consists of a 4k buffer RAM which is allocated in 32 pages of 128 bytes. Packets can be
allocated with up to 10 pages each (1280 bytes). The buffer can therefore concurrently hold up to 32 packets with a
64 byte payload. For isochronous pipes, it can hold 3 packets with a 1023 byte payload each, and still have room for
two more 64 byte packets.
This block supports 16 independent transmit FIFO queues (one for each endpoint), and a single receive queue.
Each endpoint can have up to five transmit packets queued. The receive queue can accept 16 packets of any size
combination before forcing the host to back off.
The arbiter makes the single-ported buffer RAM appear to be simultaneously available to the MCU, the four channels
of the ISADMA, and the SIEDMA for receiving and transmitting packets.
ISADMA
This is an industry standard 8237 DMA controller to transfer data between the ISA bus and the SRAM under MMU
control. This DMA contains status and control registers which can be accessed and programmed by the 8051
controller. The 8237 can run at 2, 4, or 8 MHz internally, or via an external clock to synchronize it with another
source.
SMSC DS – USB97C100 Page 9 Rev. 01/03/2001
Applications
The USB97C100 enables entirely new I/O applications, as well as new form factors for existing Legacy I/O
applications. PC98 compliance encourages the elimination ofDMA, IRQ and addressing conflicts via total on-board
ISA elimination. With the USB97C100, the ISA bus can be eliminated from motherboards without sacrificing the
huge infrastructure of Legacy I/O ports. By moving these devices to the flexible USB bus, new form factors such as
monitor peripheral clusters are also possible (mouse, keyboard, serial, parallel ports in a USB connected monitor).
PC system designers are no longer constrained by the physical borders of the motherboard. The USB97C100 is
ideal for USB peripherals which require considerable bandwidth, such as floppy drives, audio, IR, etc. The following
block diagrams illustrate these applications.
TYPICAL PC MOTHERBOARD APPLICATION
USB
South
USB
Bridge
97C100
Commanche
37C67X
SIO
Floppy
PS/2
Serial
Para llel
FIR
ISA AUDIO
SPKR
MIC
SMSC DS – USB97C100 Page 10 Rev. 01/03/2001
USB
TYPICAL MONITOR APPLICATION
USB HUB
(opt.)
USB
EXPANSION
97C100
Commanche
37C67X
SIO
ISA
CODEC
PARALLEL
TYPICAL FLOPPY DRIVE APPLICATION
FLOPPY
PS/2
SERIAL/FIR
USB
97C100
Commanche
37C78
FDC
SMSC DS – USB97C100 Page 11 Rev. 01/03/2001
TYPICAL SIGNAL CONNECTIONS
SRAM
nMEMW
USB UPSTREAM
nMEMR
FDC
LPT
UART
IR
FDC
37C669FR
SD[7..0]
SA[10..0]
IRQ[3..0]
nDACK[3..0]
DRQ[3..0]
TC
nIOR
nIOW
24MHz
nFRD
nFWR
nFCE
USB97C100
FD[7..0]
FA[19..0]
FLASH
SMSC DS – USB97C100 Page 12 Rev. 01/03/2001
MCU Memory Map
The 64K memory map is as follows from the 8051's viewpoint:
Code Space
Table 3 - MCU Code Memory Map
8051 ADDRESS CODE SPACE ACCESS
0xC000-0xFFFF Movable 16k page External FLASH
0x8000-0xBFFF Fixed 16k page External FLASH
0x7000-0x7FFF Movable 16k FLASH page 1 of 64 16k pages in External FLASH
0x6000-0x6FFF External FLASH (0x00000-0xFFFFF) selected by External FLASH
0x5000-0x5FFF MEM_BANK Register Default: 0x04000- External FLASH
0x4000-0x4FFF 0x07FFFFLASH External FLASH
0x3000-0x3FFF Fixed 16k FLASH Page External FLASH
0x2000-0x2FFF 0x00000-0x03FFF FLASH External FLASH
0x1000-0x1FFF External FLASH
0x0000-0x0FFF External FLASH
Data Space
Table 4 - MCU Data Memory Map
8051 ADDRESS DATA SPACE ACCESS
0xC000-0xFFFF Movable 16k page
Default : 0x04000-0x07FFF FLASH
0x8000-0xBFFF Fixed 16k page
0x00000-0x03FFF FLASH
0x7000-0x7FFF 0x7F80-0x7F9F SIE Reg
0x7F70-0x7F7F ISA Reg
0x7F50-0x7F6F MMU Reg
0x7F20-0x7F2F Power Reg
0x7F10-0x7F1F Configuration Reg
0x7F00-0x7F0F Runtime Reg
Note 1.
0x6000-0x6FFF 0x6000
MMU Data Register
0x5000-0x5FFF 0x5000-0x5FFF
ISA MEMORY Window
0x4000-0x4FFF 0x4000-0x40FF
ISA I/O Window
0x3000-0x3FFF Not used
0x2000-0x2FFF Not used
0x1000-0x1FFF Not used
0x0000-0x00FF Registers and SFR’s Internal
External FLASH
External FLASH
Internal
Internal
ISA
ISA
Note 1: The MCU, MMU, and SIE block registers are external to the 8051, but internal to the USB97C100. These
addresses will appear on the FLASH bus, but the read and write strobes will be inhibited.
ISADMA Memory Map
The Internal Memory buffer is virtualized into the 8237's 64K address map as 32 independent 1k blocks. After the
MMU has allocated a given packet size for a specific PNR, the MMU will make that packet appear to the 8237 as a
contiguous block of data in the address ranges depicted in table 5.
Table 5 - ISADMA Memory Map
8237 MEMORY ADDRESS DESCRIPTION
0x8000-0xFFFF 32 blocks of 1k Window to Packet
0x0000-0x7FFF 32K Window to External ISA RAM
SMSC DS – USB97C100 Page 13 Rev. 01/03/2001
MCU Block Register Summary
ADDRESS NAME R/W DESCRIPTION
7F00 ISR_0 R INT0 Source Register
7F01 IMR_0 R/W INT0 Mask Register
7F02 ISR_1 R INT1 Source Register
7F03 IMR_1 R/W INT1 Mask Register
7F06 DEV_REV R Device Revision Register
7F07 DEV_ID R Device ID Register
7F18 GPIOA_DIR R/W GPIO Configuration Register
7F19 GPIOA_OUT R/W GPIO Data Output Register
7F1A GPIOA_IN R GPIO Data Input Register
7F1B UTIL_CONFIG R/W Miscellaneous Configuration Register
7F27 CLOCK_SEL R/W 8051 and 8237 Clock Select Register
7F29 MEM_BANK R/W Flash Bank Select
7F2A WU_SRC_1 R Wakeup Source
7F2B WU_MSK_1 R/W Wakeup Mask
7F2C WU_SRC_2 R Wakeup Source
7F2D WU_MSK_2 R/W Wakeup Mask
7F10 GP1Data R/W GP FIFO Data Port #1
7F11 GP1Status R GP FIFO status Port #1
7F12 GP2Data R/W GP FIFO Data Port #2
7F13 GP2Status R GP FIFO status Port #2
7F14 GP3Data R/W GP FIFO Data Port #3
7F15 GP3Status R GP FIFO status Port #3
7F16 GP4Data R/W GP FIFO Data Port #4
7F17 GP4Status R GP FIFO status Port #4
7F70 BUS_REQ R/W ISA Bus Request Register
7F71 IOBASE R/W 8051 ISA I/O Window Base Register
7F72 MEMBASE R/W 8051 ISA Memory Window Base Register
7F73 BUS_STAT R ISADMA Request Status
7F74 BUS_MASK R/W ISADMA Request Interrupt Mask
7F7E MCU_TEST2 N/A Reserved for Test
7F7F MCU_TEST1 N/A Reserved for Test
Table 6 - MCU Block Register Summary
RUNTIME REGISTERS
UTILITY REGISTERS
POWER MANAGEMENT REGISTERS
ISA BUS CONTROL REGISTERS
SMSC DS – USB97C100 Page 14 Rev. 01/03/2001
MMU Block Register Summary
ADDRESS NAME R/W DESCRIPTION
0x6000 MMU_DATA R/W 8051-MMU Data Window Register FIFO
7F50 PRL R/W 8051-MMU Pointer Register (Low)
7F51 PRH R/W 8051-MMU Pointer Register (High) & R/W
7F52 MMUTX_SEL R/W 8051-MMU TX FIFO Select for Commands
7F53 MMUCR W 8051-MMU Command Register
7F54 ARR R 8051-MMU Allocation Result Register
7F55 PNR R/W 8051-MMU Packet Number Register
7F56 PAGS_FREE R/W Pages Free In the MMU
7F57 TX_MGMT R TX Management Register 2
7F58 RXFIFO R RX Packet FIFO Register (All EPs)
7F59 POP_TX R POP TX FIFO
7F60 TXSTAT_A R TX Packet FIFO Status Register (EP0-3)
7F61 TXSTAT_B R TX Packet FIFO Status Register (EP4-7)
7F62 TXSTAT_C R TX Packet FIFO Status Register (EP8-11)
7F63 TXSTAT_D R TX Packet FIFO Status Register (EP12-15)
7F64 MMU_TESTx N/A Reserved for Test
7F65 MMU_TESTx N/A Reserved for Test
7F66 MMU_TESTx N/A Reserved for Test
7F67 TX_MGMT R/W TX Management Register 1
7F6E MMU_TESTx N/A Reserved for Test
7F6F MMU_TESTx N/A Reserved for Test
Table 7 - MMU Block Register Summary
MMU REGISTERS
SMSC DS – USB97C100 Page 15 Rev. 01/03/2001
SIE Block Register Summary
ADDRESS NAME R/W DESCRIPTION
7F80 EP_CTRL0 R/W Endpoint 0 Control Register
7F81 EP_CTRL1 R/W Endpoint 1 Control Register
7F82 EP_CTRL2 R/W Endpoint 2 Control Register
7F83 EP_CTRL3 R/W Endpoint 3 Control Register
7F84 EP_CTRL4 R/W Endpoint 4 Control Register
7F85 EP_CTRL5 R/W Endpoint 5 Control Register
7F86 EP_CTRL6 R/W Endpoint 6 Control Register
7F87 EP_CTRL7 R/W Endpoint 7 Control Register
7F88 EP_CTRL8 R/W Endpoint 8 Control Register
7F89 EP_CTRL9 R/W Endpoint 9 Control Register
7F8A EP_CTRL10 R/W Endpoint 10 Control Register
7F8B EP_CTRL11 R/W Endpoint 11 Control Register
7F8C EP_CTRL12 R/W Endpoint 12 Control Register
7F8D EP_CTRL13 R/W Endpoint 13 Control Register
7F8E EP_CTRL14 R/W Endpoint 14 Control Register
7F8F EP_CTRL15 R/W Endpoint 15 Control Register
7F90 FRAMEL R USB Frame Count Low
7F91 FRAMEH R USB Frame Count High
7F92 SIE_ADDR R/W USB Local Address Register
7F93 SIE_STAT R SIE Status Register
7F94 SIE_CTRL R/W SIE Control Register
7F95 SIE_TST1 R/W Reserved Test Register
7F96 SIE_TST2 R/W Reserved Test Register
7F97 SIE_EP_TEST R/W Reserved Test Register
7F98 SIE_CONFIG R/W SIE Configuration Register
7F99 ALT_ADDR1 R/W Secondary Local Address Register #1
7F9A SIE_TST3 R/W Reserved Test Register
7F9B SIE_TST4 R/W Reserved Test Register
7F9C SIE_TST5 R/W Reserved Test Register
7F9D SIE_TST6 R/W Reserved Test Register
7F9E ALT_ADDR2 R/W Secondary Local Address Register #2
7F9F ALT_ADDR3 R/W Secondary Local Address Register #3
Table 8 - SIE Block Register Summary
SIE Control Registers
SMSC DS – USB97C100 Page 16 Rev. 01/03/2001
MCU REGISTER DESCRIPTION
MCU Runtime Registers
ISR_0
(0x7F00 - RESET=0x00) INTERRUPT 0 SOURCE REGISTER
BIT NAME R/W DESCRIPTION
7 IRQ3 R External interrupt input.
6 IRQ2 R External interrupt input.
5 IRQ1 R External interrupt input.
4 IRQ0 R External interrupt input.
3 RX_PKT R 1 = A Packet Number (PNR) has been successfully queued
2 TX_EMPTY R 1 = Whenever an enabled TX Endpoint's FIFO becomes
1 TX_PKT R 1 = A Packet was successfully transmitted.
0 ISADMA R 1 = When a selected 8237 channels in
Table 9 - Interrupt 0 Source Register
0 = Inactive
1 = Active
0 = Inactive
1 = Active
0 = Inactive
1 = Active
0 = Inactive
1 = Active
on the RXFIFO.
empty. This will occur when the last queued packet in one of
the 16 TX queues is successfully transferred to the Host.
BUS_STAT/BUS_MASK register pair either reached Terminal
Count or have a new DMA Request Pending.
These bits are automatically cleared each time this register is read. Therefore, each time this register is read all
pending interrupts must be serviced before continuing normal operation.
Notes:
TX_EMPTY is useful for warning of USB performance degradation. This interrupt indicates that the next time the
Host polls the affected endpoint, it will receive a NAK for that endpoint, thus reducing effective overall bandwidth
due to retries. Firmware must use TX_STAT A, B, and C to determine which endpoint queue is empty.
When ISADMA causes an interrupt, the 8237 CH_STAT register should also be read and serviced when the bit
causing the interrupt is to be rearmed. When ISR_0 is read and the ISADMA bit is cleared, any other low-to-high
transitions in the BUS_STAT register bits that are not masked will still cause an interrupt.
SMSC DS – USB97C100 Page 17 Rev. 01/03/2001
Table 10 - Interrupt 0 Mask
IMR_0
(0x7F01- RESET=0xFF) INTERRUPT 0 MASK REGISTER
BIT NAME R/W DESCRIPTION
7 IRQ3 R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
6 IRQ2 R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
5 IRQ1 R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
4 IRQ0 R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
3 RX_PKT R/W Received Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
2 TX_EMPTY R/W Transmit Queue Empty MMU Interrupt
0 = Enable Interrupt
1 = Mask Interrupt
1 TX_PKT R/W Transmit Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
0 ISADMA R/W ISADMA Status Change Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Table 11 - Interrupt 1 Source Register
ISR_1
(0x7F02- RESET=0x00) INTERRUPT 1 SOURCE REGISTER
BIT NAME R/W DESCRIPTION
[7:5] Reserved Reserved
4 EOT R 1 = The SIE returned to Idle State. Marks the end of each
transaction.
3 SOF R 1 = When a Start of Frame token is correctly decoded.
Generated by the write strobe to the Frame Count register.
2 ALLOC R 1 = MCU Software Allocation Request complete interrupt. This
interrupt is not generated for hardware (SIEDMA) allocation
requests.
1 RX_OVRN R 1 = A receive condition has occurred that will stop the current
receive buffer to not be processed The SIE automatically
recovers from this condition after its cause has been
alleviated (e.g. any partially allocated packets will be released.
See Note 2).
0 PWR_MNG R 1 = A wakeup or power management event in the WU_SRC_1
or WU_SRC_2 registers has gone active.
Notes:
These bits are cleared each time this register is read.
The RX_OVRN interrupt should be considered by firmware as a general Receive Overrun of the SIE, meaning
that a packet destined for the RAM buffer could not be received and was not acknowledged back to the Host.
The firmware should check to see if the RX Packet Number FIFO Register (RXFIFO) is full. If it is empty, then
there may be too many transmit packets queued for the device to receive anything, or the last packet may have
been corrupted on the wire. If it is not empty, then one or more receive packets must be dequeued before the
device can continue to receive packets. In the normal course of operation, the MCU should respond to a
RX_PKT interrupt as often as possible and let the buffering logic do its job.
SMSC DS – USB97C100 Page 18 Rev. 01/03/2001
Table 12 - Interrupt 1 Mask
IMR_1
(0x7F03- RESET=0xFF) INTERRUPT 1 MASK REGISTER
BIT NAME R/W DESCRIPTION
[7:5] Reserved Reserved
4 EOT R/W EOT interrupt mask
0 = Enable Interrupt
1 = Mask Interrupt
3 SOF R/W Start of Frame Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
2 ALLOC R/W MCU Software Allocation Complete Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
1 RX_OVRN R/W Receive Overrun Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
0 PWR_MNG R/W Power Management Wakeup Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Table 13 - Device Revision Register
DEV_REV
(0x7F06- RESET=0xXX) DEVICE REVISION REGISTER
BIT R/W DESCRIPTION
[7:0] Rev. R This register defines additional revision information
used internally by SMSC. The value is silicon revision
dependent.
Table 14 - Device Identification Register
DEV_ID
(0x7F07- RESET=0x25) DEVICE IDENTIFICATION REGISTER
BIT R/W DESCRIPTION
[7:0] BCD '25'
HEX 0x25
R This register defines additional revision information
used internally by SMSC
Table 15– 8051 GP FIFO1
GP_FIFO1
(0x7F10- RESET=0xXX) 8051 GP FIFO1
BIT NAME R/W DESCRIPTION
[7:0] GP_FIFO1 R/W 8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
Table 16– 8051 GP FIFO2
GP_FIFO2
(0x7F12 - RESET=0xXX) 8051 GP FIFO2
BIT NAME R/W DESCRIPTION
[7:0] GP_FIFO2 R/W 8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
Table 17– 8051 GP FIFO3
GP_FIFO3
(0x7F14 - RESET=0xXX) 8051 GP FIFO3
BIT NAME R/W DESCRIPTION
[7:0] GP_FIFO3 R/W 8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
SMSC DS – USB97C100 Page 19 Rev. 01/03/2001
GP_FIFO4
(0x7F16 - RESET=0xXX) 8051 GP FIFO4
BIT NAME R/W DESCRIPTION
[7:0] GP_FIFO4 R/W 8 byte deep GP FIFO. This data FIFOs must not be read
FIFO Status Registers
(0x7F11 – RESET=0x01) 8051 GP FIFO status
BIT NAME R/W DESCRIPTION
[7:2] Reserved R Reserved
1 GPFIFO1_FULL R GP FIFO 1 full status
0 GPFIFO1_EMPTY R GP FIFO 1 empty status
(0x7F13 – RESET=0x01) 8051 GP FIFO 2 status
BIT NAME R/W DESCRIPTION
[7:2] Reserved R Reserved
1 GPFIFO2_FULL R GP FIFO 2 full status
0 GPFIFO2_EMPTY R GP FIFO 2 empty status
Table 18 – 8051 GP FIFO4
unless the associated status bit indicates that FIFO is not
empty.
Table 19 – 8051 GP FIFO 1 STATUS
GPFIFO1_STS
0 = Not FULL
1 = FULL
0 = Has one or more TX packet
1 = Empty
Table 20– 8051 GP FIFO 2 STATUS
GPFIFO2_STS
0 = Not FULL
1 = FULL
0 = Has one or more TX packet
1 = Empty
Table 21 – 8051 GP FIFO 3 STATUS
GPFIFO3_STS
(0x7F15 – RESET=0x01) 8051 GP FIFO 3 status
BIT NAME R/W DESCRIPTION
[7:2] Reserved R Reserved
1 GPFIFO3_FULL R GP FIFO 3 full status
0 = Not FULL
1 = FULL
0 GPFIFO3_EMPTY R GP FIFO 3 empty status
0 = Has one or more TX packet
1 = Empty
Table 22 – 8051 GP FIFO 4 STATUS
GPFIFO4_STS
(0x7F17 – RESET=0x01) 8051 GP FIFO status
BIT NAME R/W DESCRIPTION
[7:2] Reserved R Reserved
1 GPFIFO4_FULL R GP FIFO 4 full status
0 = Not FULL
1 = FULL
0 GPFIFO4_EMPTY R GP FIFO 4 empty status
0 = Has one or more TX packet
1 = Empty
SMSC DS – USB97C100 Page 20 Rev. 01/03/2001
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