High Speed (12Mbps) Capability
MMU and SRAM Buffer Allow Buffer Optimization
and Maximum Utilization of USB Bandwidth
-128 Byte Page Size
-10 Pages Maximum per Packet
-Up to 16 Deep Receive Packet Queue
-Up to 5 Deep Transmit Packet Queue, per
Endpoint
-Hardware Generated Packet Header
Records Each Packet Status Automatically
-Simultaneous Arbitration Between MCU,
SIE, and ISA DMA Accesses
Extended Power Management
-Standard 8051 "Stop Clock" Modes
-Additional USB and ISA Suspend
Resume Events
-Internal 8MHz Ring Oscillator for Immediate
Low Power Code Execution
-24, 16, 12, 8, 4, and 2 MHz PLL Taps For on
the Fly MCU and DMA Clock Switching
-Independent Clock/Power Management for
SIE, MMU, DMA and MCU
DMA Capability with ISA Memory
-Four Independent Channels
-Transfer Between Internal and External
Memory
-Transfer Between I/O and Buffer Memory
-External Bus Master Capable
External MCU Memory Interface
-1M Byte Code and Data Storage via 16K
Windows
-Flash, SRAM, or EPROM
-Downloadable via USB, Serial Port, or ISA
Peripheral
Quasi-ISA Interface Allows Interface to New and
"Legacy" Peripheral Devices
-1M ISA Memory Space via 4K MCU Window
-64K ISA I/O Space via 256 Byte MCU
Window
-4 External Interrupt Inputs
-4 DMA Channels
-Variable Cycle Timing
-8 Bit Data Path
5V or 3.3v Operation
On Board Crystal Driver Circuit
128 Pin QFP Package
ORDERING INFORMATION
Order Number: USB97C100QFP
128 Pin QFP Package
SMSC DS – USB97C100Rev. 01/03/2001
GENERAL DESCRIPTION
The USB97C100 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple
endpoint applications. The USB97C100 provides an ISA-like bus interface, which will allow virtually any PC peripheral to
be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput
disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection’s overall
bandwidth. This architecture minimizes the integrated microcontroller’s participation in the USB data flow, allowing backto-back packet transfers to block oriented devices. The efficiency of this architecture allows floppy drives to coexist with
other peripherals such as serial and parallel ports on a single USB link.
The USB97C100 allows external program code to be downloaded over the USB to allow easy implementation of varied
peripheral USB Device Classes and combinations. This also provides a method for convenient field upgrades and
modifications.
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems
Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing S MSC products are incl uded
as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although
the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make
changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest speci fications
before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any
licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most
recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreem ent" ). T he product
may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anom aly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application
where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an
Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well
as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES
ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT
ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
GENERAL DESCRIPTION............................................................................................................................................ 2
DESCRIPTION OF PIN FUNCTIONS........................................................................................................................... 5
BUFFER TYPE DESCRIPTIONS.................................................................................................................................. 7
Serial Interface Engine (SIE)......................................................................................................................................... 9
Micro Controller Unit (MCU).......................................................................................................................................... 9
TYPICAL SIGNAL CONNECTIONS............................................................................................................................ 12
Data Space.................................................................................................................................................................. 13
SIE Block Register Summary...................................................................................................................................... 16
FIFO Status Registers................................................................................................................................................. 20
MCU Power Management Registers...........................................................................................................................24
MCU ISA Interface Registers...................................................................................................................................... 27
16 BYTE DEEP TX COMPLETION FIFO REGISTER................................................................................................ 40
TX FIFO POP REGISTER........................................................................................................................................... 41
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION ............................................................................. 45
SIE Interface Registers ............................................................................................................................................... 46
DC PARAMETERS..................................................................................................................................................... 51
USB PARAMETERS................................................................................................................................................... 53
USB DC PARAMETERS............................................................................................................................................. 53
USB AC PARAMETERS.............................................................................................................................................. 54
ISA memory or slave devices use this signal to lengthen a bus
cycle from the default time. Extending the length of the bus
cycle can only be done when the bus cycles are derived from
the Internal DMA controller core. 8051 MCU generated Memory
or I/O accesses cannot and will not be extended even if
READY is asserted low by an external ISA slave device. The
external slave device negates this signal after decoding a valid
address and sampling the command signals (nIOW, nIOR,
nMEMW, and nMEMR). When the slave’s access has
completed, this signal should be allowed to float high.
104, 106,
108, 110
105, 107,
109, 111
103TCDMA Terminal Count; active high.
19-13,
127-7,
9-12
112-115,
117-120
122AENAddress Enable
123nIOWI/O Write; active low.
124nIORI/O Read; active low.
125nMEMRMemory read; active low
126nMEMWMemory write; active low
DRQ[3:0]DMA Request channels 3-0; active high.
These signals are used to request DMA service from the DMA
controller. The requesting device must hold the request signal
until the DMA controller drives the appropriate DMA
acknowledge signal (nDACK[3:0]).
nDACK
[3:0]
DMA Acknowledge channels 3-0; active low.
These signals are used to indicate to the DMA requesting
device that it has been granted the ISA bus.
This signal is used to indicate that a DMA transfer has
completed.
SA[19:0]System Address Bus
These signals address memory or I/O devices on the ISA bus.
SD[7:0]System Data Bus
These signals are used to transfer data between system
devices.
This signal indicates address validation to I/O devices. When
low this signal indicates that an I/O slave may respond to
addresses and I/O commands on the bus. This signal is high
during DMA cycles to prevent I/O slaves from interpreting DMA
cycles as valid I/O cycles.
This signal indicates to the addressed ISA I/O slave to latch
data from the ISA bus.
This signal indicates to the addressed ISA I/O slave to drive
data on the ISA bus.
This signal indicates to the addressed ISA memory slave to
drive data on the ISA bus.
This signal indicates to the addressed ISA memory slave to
latch data from the ISA bus.
BUFFER
TYPE
IP
I
O8
O8
O8
I/O8
O8
O8
O8
O8
O8
SMSC DS – USB97C100Page 5Rev. 01/03/2001
QFP PIN
NUMBERSYMBOLPIN DESCRIPTION
102nMASTERExternal Bus master, active low
This signal forces the USB97C100 to immediately tri-state its
external bus, even if internal transactions are not complete. All
shared ISA signals are tri-stated, except 8237 nDACKs, which
can be used in gang mode to provide external bus-master
handshaking. This pin must be used with some handshake
mechanism to avoid data corruption.
21-24IRQ[3:0]Interrupt Request 3-0; active high
These signals are driven by ISA devices on the ISA bus to
interrupt the 8051.
30XTAL1/
Clock In
24MHz Crystal or clock input.
This pin can be connected to one terminal of the crystal or can
be connected to an external clock when a crystal is not used.
31XTAL224MHz Crystal
This is the other terminal of the crystal.
99EXTCLKAlternate clock to 8237
An external clock can be used for the internal 8237. This clock
can be used to synchronize the 8237 to other devices.
33CLKOUTClock output.
This clock frequency is the same as the 8051 running clock.
This clock is stopped when the 8051 is stopped. Peripherals
should not use this clock when they are expected to run when
the 8051 is stopped. This clock can be used to synchronize
other devices to the 8051.
USB INTERFACE
77, 79USBD-
USDB+
USB Upstream Connection signals
These are two point-to-point signals and driven differentially.
FLASH INTERFACE
45-52FD[7:0]
Flash ROM Data Bus
These signals are used to transfer data between 8051 and the
external FLASH.
75, 74, 68,
65, 64, 69,
70, 63, 73,
FA[19:0]Flash ROM Address Bus
These signals address memory locations within the FLASH.
43, 72, 71,
62-58,
56-54
42nFRDFlash ROM Read; active lowO8
66nFWRFlash ROM Write; active lowO8
44nFCEFlash ROM Chip Select; active lowO8
98FALEFlash ROM address latch enableO8
POWER SIGNALS
25,57,76
VCC+3.3V power or 5V
101,121
78VCC3.3+3.3V power for USB
8, 20, 32,
GNDGround Reference
53, 67, 80,
97, 116
MISCELLANEOUS
41-34GPIO[7:0]General Purpose I/O.
These pins can be configured as inputs or outputs under
software control.
BUFFER
TYPE
IP
I
ICLKx
OCLKx
ICLK
O8
IO-U
IO8
O8
I/O16
SMSC DS – USB97C100Page 6Rev. 01/03/2001
QFP PIN
NUMBERSYMBOLPIN DESCRIPTION
27PWRGDActive high input.
This signal is used to indicate to that chip that a good power
level has been reached. When inactive/low, all pins are Tri-
stated except TST_OUT and a POR is generated.
28RESET_INPower on reset; active high
This signal is used by the system to reset the chip. It also
generates an internal POR.
29TST_OUTAND tree output
This signal is used for testing the chip via an internal AND tree.
26nTESTTest input
This signal is a manufacturing test pin. User can pull it high or
leave it unconnected.
[96:81]NCNo connect
BUFFER TYPE DESCRIPTIONS
Table 2 - USB97C100 Buffer Type Description
BUFFERDESCRIPTION
IInput (no pull-up)
IPInput 90µA with internal pull-up
O8Output with 8mA drive
I/O8Input/output with 8mA drive
I/O16Input/output with 16mA drive
O24Output, 24mA sink, 12mA source.
I/ODP24Input/Output drain , 24mA sink, 12mA source with 90µA pull-up
ICLKxXTAL clock input
OCLKxXTAL clock output
ICLKClock input (TTL levels)
I/O-UDefined in USB specification; uses VCC3.3
BUFFER
TYPE
I
I
O8
IP
Note: These DC Characteristics/drive strengths apply to 5V operation only. See the DC Characteristics section for
additional details.
SMSC DS – USB97C100Page 7Rev. 01/03/2001
USB97C100 BLOCK DIAGRAM
USB Interface
USBD- USBD+
General
Purpose
IO
GPIO[0:7]
FD[7:0]
FA[19:0]
nFRD
nFWR
nFCE
Flash
Interface
End Point
Control
SIE DMA
Rx/TX
Queue
GPIO
8051
Serial Interfa c e
Engine
Arbiter
8237
Tranceiver
Memory
Management
Unit
4k Data Buffer RAM
Map RAM
IRQ[3:0]
SD[7:0],
SA[19:0]
nIOW,
nIOR,
nMEMW,
nMEMR
DRQ[3:0],
nDACK[3:0],
TC, AEN
Quasi ISA Bus
FIGURE 2 - BLOCK DIAGRAM
SMSC DS – USB97C100Page 8Rev. 01/03/2001
FUNCTIONAL DESCRIPTION
The USB97C100 incorporates a USB Serial Interface Engine (SIE), 8051 Microcontroller Unit (MCU), Serial Interface
Engine DMA (SIEDMA), a programmable 8237 ISA bus DMA controller (ISADMA), 4K bytes of SRAM for data
stream buffering, and a patented MMU (Memory Management Unit) to dynamically manage buffer allocation. The
semi-automatic nature of the SIEDMA, ISADMA, and MMU blocks frees the MCU to provide enumeration, protocol
and power management. A bus arbiter integrated into the MMU assures that transparent access between the
SIEDMA, ISADMA, and MCU to the SRAM occurs.
Serial Interface Engine (SIE)
The SIE is a USB low-level protocol interpreter. The SIE controls the USB bus protocol, packet
generation/extraction, parallel-to-serial/serial-to-parallel conversion, CRC coding/decoding, bit stuffing, and NRZI
coding/decoding.
The SIE can be dynamically configured as having any combination of 0-16 transmit, and 0-16 receive endpoints, for
up to 4 independent addresses. There are 3 alternate and one local address. The alternate addresses, for example,
can be used for Hub addresses. The SIE can also "Receive All Addresses" for bus snooping.
Micro Controller Unit (MCU)
The 8051 embedded controller is a static CMOS MCU which is fully software compatible with the industry standard
Intel 80C51 micro-controller. All internal registers of the USB97C100 blocks are mapped into the external memory
space of the MCU.
A detailed description of the microcontroller’s internal registers and instruction set can be found in the “USB97C100
Programmer’s Reference Guide”.
SIEDMA
This is a simplified DMA controller, which automatically transfers data between SIE and SRAM via MMU control. The
SIEDMA appends a status header containing frame number, endpoint, and byte count to each incoming packet
before notifying the MCU of its arrival. This block’s operation is transparent to the firmware.
Memory Management Unit (MMU) Register Description
This patented MMU consists of a 4k buffer RAM which is allocated in 32 pages of 128 bytes. Packets can be
allocated with up to 10 pages each (1280 bytes). The buffer can therefore concurrently hold up to 32 packets with a
64 byte payload. For isochronous pipes, it can hold 3 packets with a 1023 byte payload each, and still have room for
two more 64 byte packets.
This block supports 16 independent transmit FIFO queues (one for each endpoint), and a single receive queue.
Each endpoint can have up to five transmit packets queued. The receive queue can accept 16 packets of any size
combination before forcing the host to back off.
The arbiter makes the single-ported buffer RAM appear to be simultaneously available to the MCU, the four channels
of the ISADMA, and the SIEDMA for receiving and transmitting packets.
ISADMA
This is an industry standard 8237 DMA controller to transfer data between the ISA bus and the SRAM under MMU
control. This DMA contains status and control registers which can be accessed and programmed by the 8051
controller. The 8237 can run at 2, 4, or 8 MHz internally, or via an external clock to synchronize it with another
source.
SMSC DS – USB97C100Page 9Rev. 01/03/2001
Applications
The USB97C100 enables entirely new I/O applications, as well as new form factors for existing Legacy I/O
applications. PC98 compliance encourages the elimination ofDMA, IRQ and addressing conflicts via total on-board
ISA elimination. With the USB97C100, the ISA bus can be eliminated from motherboards without sacrificing the
huge infrastructure of Legacy I/O ports. By moving these devices to the flexible USB bus, new form factors such as
monitor peripheral clusters are also possible (mouse, keyboard, serial, parallel ports in a USB connected monitor).
PC system designers are no longer constrained by the physical borders of the motherboard. The USB97C100 is
ideal for USB peripherals which require considerable bandwidth, such as floppy drives, audio, IR, etc. The following
block diagrams illustrate these applications.
TYPICAL PC MOTHERBOARD APPLICATION
USB
South
USB
Bridge
97C100
Commanche
37C67X
SIO
Floppy
PS/2
Serial
Para llel
FIR
ISA AUDIO
SPKR
MIC
SMSC DS – USB97C100Page 10Rev. 01/03/2001
USB
TYPICAL MONITOR APPLICATION
USB HUB
(opt.)
USB
EXPANSION
97C100
Commanche
37C67X
SIO
ISA
CODEC
PARALLEL
TYPICAL FLOPPY DRIVE APPLICATION
FLOPPY
PS/2
SERIAL/FIR
USB
97C100
Commanche
37C78
FDC
SMSC DS – USB97C100Page 11Rev. 01/03/2001
TYPICAL SIGNAL CONNECTIONS
SRAM
nMEMW
USB UPSTREAM
nMEMR
FDC
LPT
UART
IR
FDC
37C669FR
SD[7..0]
SA[10..0]
IRQ[3..0]
nDACK[3..0]
DRQ[3..0]
TC
nIOR
nIOW
24MHz
nFRD
nFWR
nFCE
USB97C100
FD[7..0]
FA[19..0]
FLASH
SMSC DS – USB97C100Page 12Rev. 01/03/2001
MCU Memory Map
The 64K memory map is as follows from the 8051's viewpoint:
0x7F70-0x7F7F ISA Reg
0x7F50-0x7F6F MMU Reg
0x7F20-0x7F2F Power Reg
0x7F10-0x7F1F Configuration Reg
0x7F00-0x7F0F Runtime Reg
Note 1.
0x6000-0x6FFF0x6000
MMU Data Register
0x5000-0x5FFF0x5000-0x5FFF
ISA MEMORY Window
0x4000-0x4FFF0x4000-0x40FF
ISA I/O Window
0x3000-0x3FFFNot used
0x2000-0x2FFFNot used
0x1000-0x1FFFNot used
0x0000-0x00FFRegisters and SFR’sInternal
External FLASH
External FLASH
Internal
Internal
ISA
ISA
Note 1: The MCU, MMU, and SIE block registers are external to the 8051, but internal to the USB97C100. These
addresses will appear on the FLASH bus, but the read and write strobes will be inhibited.
ISADMA Memory Map
The Internal Memory buffer is virtualized into the 8237's 64K address map as 32 independent 1k blocks. After the
MMU has allocated a given packet size for a specific PNR, the MMU will make that packet appear to the 8237 as a
contiguous block of data in the address ranges depicted in table 5.
7F18GPIOA_DIRR/WGPIO Configuration Register
7F19GPIOA_OUTR/WGPIO Data Output Register
7F1AGPIOA_INRGPIO Data Input Register
7F1BUTIL_CONFIGR/WMiscellaneous Configuration Register
7F27CLOCK_SELR/W8051 and 8237 Clock Select Register
7F29MEM_BANKR/WFlash Bank Select
7F2AWU_SRC_1RWakeup Source
7F2BWU_MSK_1R/WWakeup Mask
7F2CWU_SRC_2RWakeup Source
7F2DWU_MSK_2R/WWakeup Mask
7F10GP1DataR/WGP FIFO Data Port #1
7F11GP1StatusRGP FIFO status Port #1
7F12GP2DataR/WGP FIFO Data Port #2
7F13GP2StatusRGP FIFO status Port #2
7F14GP3DataR/WGP FIFO Data Port #3
7F15GP3StatusRGP FIFO status Port #3
7F16GP4DataR/WGP FIFO Data Port #4
7F17GP4StatusRGP FIFO status Port #4
7F70BUS_REQR/WISA Bus Request Register
7F71IOBASER/W8051 ISA I/O Window Base Register
7F72MEMBASER/W8051 ISA Memory Window Base Register
7F73BUS_STATRISADMA Request Status
7F74BUS_MASKR/WISADMA Request Interrupt Mask
7F7EMCU_TEST2N/AReserved for Test
7F7FMCU_TEST1N/AReserved for Test
Table 6 - MCU Block Register Summary
RUNTIME REGISTERS
UTILITY REGISTERS
POWER MANAGEMENT REGISTERS
ISA BUS CONTROL REGISTERS
SMSC DS – USB97C100Page 14Rev. 01/03/2001
MMU Block Register Summary
ADDRESSNAMER/WDESCRIPTION
0x6000MMU_DATAR/W8051-MMU Data Window Register FIFO
7F50PRLR/W8051-MMU Pointer Register (Low)
7F51PRHR/W8051-MMU Pointer Register (High) & R/W
7F52MMUTX_SELR/W8051-MMU TX FIFO Select for Commands
7F53MMUCRW8051-MMU Command Register
7F54ARRR8051-MMU Allocation Result Register
7F55PNRR/W8051-MMU Packet Number Register
7F56PAGS_FREER/WPages Free In the MMU
7F57TX_MGMTRTX Management Register 2
7F58RXFIFORRX Packet FIFO Register (All EPs)
7F59POP_TXRPOP TX FIFO
7F60TXSTAT_ARTX Packet FIFO Status Register (EP0-3)
7F61TXSTAT_BRTX Packet FIFO Status Register (EP4-7)
7F62TXSTAT_CRTX Packet FIFO Status Register (EP8-11)
7F63TXSTAT_DRTX Packet FIFO Status Register (EP12-15)
7F64MMU_TESTxN/AReserved for Test
7F65MMU_TESTxN/AReserved for Test
7F66MMU_TESTxN/AReserved for Test
7F67TX_MGMTR/WTX Management Register 1
7F6EMMU_TESTxN/AReserved for Test
7F6FMMU_TESTxN/AReserved for Test
Table 7 - MMU Block Register Summary
MMU REGISTERS
SMSC DS – USB97C100Page 15Rev. 01/03/2001
SIE Block Register Summary
ADDRESSNAMER/WDESCRIPTION
7F80EP_CTRL0R/WEndpoint 0 Control Register
7F81EP_CTRL1R/WEndpoint 1 Control Register
7F82EP_CTRL2R/WEndpoint 2 Control Register
7F83EP_CTRL3R/WEndpoint 3 Control Register
7F84EP_CTRL4R/WEndpoint 4 Control Register
7F85EP_CTRL5R/WEndpoint 5 Control Register
7F86EP_CTRL6R/WEndpoint 6 Control Register
7F87EP_CTRL7R/WEndpoint 7 Control Register
7F88EP_CTRL8R/WEndpoint 8 Control Register
7F89EP_CTRL9R/WEndpoint 9 Control Register
7F8AEP_CTRL10R/WEndpoint 10 Control Register
7F8BEP_CTRL11R/WEndpoint 11 Control Register
7F8CEP_CTRL12R/WEndpoint 12 Control Register
7F8DEP_CTRL13R/WEndpoint 13 Control Register
7F8EEP_CTRL14R/WEndpoint 14 Control Register
7F8FEP_CTRL15R/WEndpoint 15 Control Register
7F90FRAMELRUSB Frame Count Low
7F91FRAMEHRUSB Frame Count High
7F92SIE_ADDRR/WUSB Local Address Register
7F93SIE_STATRSIE Status Register
7F94SIE_CTRLR/WSIE Control Register
7F95SIE_TST1R/WReserved Test Register
7F96SIE_TST2R/WReserved Test Register
7F97SIE_EP_TESTR/WReserved Test Register
7F98SIE_CONFIGR/WSIE Configuration Register
7F99ALT_ADDR1R/WSecondary Local Address Register #1
7F9ASIE_TST3R/WReserved Test Register
7F9BSIE_TST4R/WReserved Test Register
7F9CSIE_TST5R/WReserved Test Register
7F9DSIE_TST6R/WReserved Test Register
7F9EALT_ADDR2R/WSecondary Local Address Register #2
7F9FALT_ADDR3R/WSecondary Local Address Register #3
Table 8 - SIE Block Register Summary
SIE Control Registers
SMSC DS – USB97C100Page 16Rev. 01/03/2001
MCU REGISTER DESCRIPTION
MCU Runtime Registers
ISR_0
(0x7F00 - RESET=0x00)INTERRUPT 0 SOURCE REGISTER
BITNAMER/WDESCRIPTION
7IRQ3RExternal interrupt input.
6IRQ2RExternal interrupt input.
5IRQ1RExternal interrupt input.
4IRQ0RExternal interrupt input.
3RX_PKTR1 = A Packet Number (PNR) has been successfully queued
2TX_EMPTYR1 = Whenever an enabled TX Endpoint's FIFO becomes
1TX_PKTR1 = A Packet was successfully transmitted.
0ISADMAR1 = When a selected 8237 channels in
Table 9 - Interrupt 0 Source Register
0 = Inactive
1 = Active
0 = Inactive
1 = Active
0 = Inactive
1 = Active
0 = Inactive
1 = Active
on the RXFIFO.
empty. This will occur when the last queued packet in one of
the 16 TX queues is successfully transferred to the Host.
BUS_STAT/BUS_MASK register pair either reached Terminal
Count or have a new DMA Request Pending.
These bits are automatically cleared each time this register is read. Therefore, each time this register is read all
pending interrupts must be serviced before continuing normal operation.
Notes:
TX_EMPTY is useful for warning of USB performance degradation. This interrupt indicates that the next time the
Host polls the affected endpoint, it will receive a NAK for that endpoint, thus reducing effective overall bandwidth
due to retries. Firmware must use TX_STAT A, B, and C to determine which endpoint queue is empty.
When ISADMA causes an interrupt, the 8237 CH_STAT register should also be read and serviced when the bit
causing the interrupt is to be rearmed. When ISR_0 is read and the ISADMA bit is cleared, any other low-to-high
transitions in the BUS_STAT register bits that are not masked will still cause an interrupt.
SMSC DS – USB97C100Page 17Rev. 01/03/2001
Table 10 - Interrupt 0 Mask
IMR_0
(0x7F01- RESET=0xFF)INTERRUPT 0 MASK REGISTER
BITNAMER/WDESCRIPTION
7IRQ3R/WExternal interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
6IRQ2R/WExternal interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
5IRQ1R/WExternal interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
4IRQ0R/WExternal interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
3RX_PKTR/WReceived Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
2TX_EMPTYR/WTransmit Queue Empty MMU Interrupt
0 = Enable Interrupt
1 = Mask Interrupt
1TX_PKTR/WTransmit Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
0ISADMAR/WISADMA Status Change Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Table 11 - Interrupt 1 Source Register
ISR_1
(0x7F02- RESET=0x00)INTERRUPT 1 SOURCE REGISTER
BITNAMER/WDESCRIPTION
[7:5]ReservedReserved
4EOTR1 = The SIE returned to Idle State. Marks the end of each
transaction.
3SOFR1 = When a Start of Frame token is correctly decoded.
Generated by the write strobe to the Frame Count register.
2ALLOCR1 = MCU Software Allocation Request complete interrupt. This
interrupt is not generated for hardware (SIEDMA) allocation
requests.
1RX_OVRNR1 = A receive condition has occurred that will stop the current
receive buffer to not be processed The SIE automatically
recovers from this condition after its cause has been
alleviated (e.g. any partially allocated packets will be released.
See Note 2).
0PWR_MNGR1 = A wakeup or power management event in the WU_SRC_1
or WU_SRC_2 registers has gone active.
Notes:
These bits are cleared each time this register is read.
The RX_OVRN interrupt should be considered by firmware as a general Receive Overrun of the SIE, meaning
that a packet destined for the RAM buffer could not be received and was not acknowledged back to the Host.
The firmware should check to see if the RX Packet Number FIFO Register (RXFIFO) is full. If it is empty, then
there may be too many transmit packets queued for the device to receive anything, or the last packet may have
been corrupted on the wire. If it is not empty, then one or more receive packets must be dequeued before the
device can continue to receive packets. In the normal course of operation, the MCU should respond to a
RX_PKT interrupt as often as possible and let the buffering logic do its job.
RThis register defines additional revision information
used internally by SMSC
Table 15– 8051 GP FIFO1
GP_FIFO1
(0x7F10- RESET=0xXX)8051 GP FIFO1
BITNAMER/WDESCRIPTION
[7:0]GP_FIFO1R/W8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
Table 16– 8051 GP FIFO2
GP_FIFO2
(0x7F12 - RESET=0xXX)8051 GP FIFO2
BITNAMER/WDESCRIPTION
[7:0]GP_FIFO2R/W8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
Table 17– 8051 GP FIFO3
GP_FIFO3
(0x7F14 - RESET=0xXX)8051 GP FIFO3
BITNAMER/WDESCRIPTION
[7:0]GP_FIFO3R/W8 byte deep GP FIFO. This data FIFOs must not be read
unless the associated status bit indicates that FIFO is not
empty.
SMSC DS – USB97C100Page 19Rev. 01/03/2001
GP_FIFO4
(0x7F16 - RESET=0xXX)8051 GP FIFO4
BITNAMER/WDESCRIPTION
[7:0]GP_FIFO4R/W8 byte deep GP FIFO. This data FIFOs must not be read
FIFO Status Registers
(0x7F11 – RESET=0x01)8051 GP FIFO status
BITNAMER/WDESCRIPTION
[7:2]ReservedRReserved
1GPFIFO1_FULLRGP FIFO 1 full status
0GPFIFO1_EMPTYRGP FIFO 1 empty status
(0x7F13 – RESET=0x01)8051 GP FIFO 2 status
BITNAMER/WDESCRIPTION
[7:2]ReservedRReserved
1GPFIFO2_FULLRGP FIFO 2 full status
0GPFIFO2_EMPTYRGP FIFO 2 empty status
Table 18 – 8051 GP FIFO4
unless the associated status bit indicates that FIFO is not
empty.
Table 19 – 8051 GP FIFO 1 STATUS
GPFIFO1_STS
0 = Not FULL
1 = FULL
0 = Has one or more TX packet
1 = Empty
Table 20– 8051 GP FIFO 2 STATUS
GPFIFO2_STS
0 = Not FULL
1 = FULL
0 = Has one or more TX packet
1 = Empty
Table 21 – 8051 GP FIFO 3 STATUS
GPFIFO3_STS
(0x7F15 – RESET=0x01)8051 GP FIFO 3 status
BITNAMER/WDESCRIPTION
[7:2]ReservedRReserved
1GPFIFO3_FULLRGP FIFO 3 full status
0 = Not FULL
1 = FULL
0GPFIFO3_EMPTYRGP FIFO 3 empty status
0 = Has one or more TX packet
1 = Empty
Table 22 – 8051 GP FIFO 4 STATUS
GPFIFO4_STS
(0x7F17 – RESET=0x01)8051 GP FIFO status
BITNAMER/WDESCRIPTION
[7:2]ReservedRReserved
1GPFIFO4_FULLRGP FIFO 4 full status
0 = Not FULL
1 = FULL
0GPFIFO4_EMPTYRGP FIFO 4 empty status
0 = Has one or more TX packet
1 = Empty
SMSC DS – USB97C100Page 20Rev. 01/03/2001
Table 23 - GPIO Direction Register
GPIOA_DIR
(0x7F18- RESET=0x00)MCU UTILITY REGISTERS
BITNAMER/WDESCRIPTION
7GPIO7R/WGPIO7 Direction
0 = In
1 = Out
6GPIO6R/WGPIO6 Direction
0 = In
1 = Out
5GPIO5R/WGPIO5 Direction
0 = In
1 = Out
4GPIO4R/WGPIO4 Direction
0 = In
1 = Out
3GPIO3/T1R/WGPIO3 Direction
0 = In
1 = Out
2GPIO2/T0R/WGPIO2 Direction
0 = In
1 = Out
1GPIO1/TXDR/WGPIO1 Direction
0 = In
1 = Out
0GPIO0/RXDR/WGPIO0 Direction
0 = In
1 = Out
Note: The Timer inputs T[1:0] can be configured as outputs and left unconnected so that software can write to the
bits to trigger the timer. Otherwise, the Timer inputs can be used to count external events or internal SOF
receptions.
Table 24 - GPIO Output Register
GPIOA_OUT
(0x7F19- RESET=0x00)
GPIO DATA OUTPUT
REGISTER A
BITNAMER/WDESCRIPTION
7GPIO7R/WGPIO7 Output Buffer Data
6GPIO6R/WGPIO6 Output Buffer Data
5GPIO5R/WGPIO5 Output Buffer Data
4GPIO4R/WGPIO4 Output Buffer Data
3GPIO3/T1R/WGPIO3 Output Buffer Data
2GPIO2/T0R/WGPIO2 Output Buffer Data
1GPIO1/TXDR/WGPIO1 Output Buffer Data
0GPIO0/RXDR/WGPIO0 Output Buffer Data
Table 25 - GPIO Input Register
GPIOA_IN
(0x7F1A- RESET=0xXX)GPIO INPUT REGISTER A
BITNAMER/WDESCRIPTION
7GPIO7RGPIO7 Input Buffer Data
6GPIO6RGPIO6 Input Buffer Data
5GPIO5RGPIO5 Input Buffer Data
4GPIO4RGPIO4 Input Buffer Data
3GPIO3/T1RGPIO3 Input Buffer Data
2GPIO2/T0RGPIO2 Input Buffer Data
1GPIO1/TXDRGPIO1 Input Buffer Data
0GPIO0/RXDRGPIO0 Input Buffer Data
2ISADMACLK_EXTR/WSelects an external clock source for the 8237 ISADMA
controller for synchronizing the DMA with another block.
NOTE: This will initially be an external input, but may
eventually be used within the block to optimize
performance, or as some other internal clock source.
0 = Use ISADMACLK[1..0] select
1 = Use EXT_IN clock source for 8237
The 8051 may program itself to run off of an internal Ring Oscillator having a frequency range between 4 and
12MHz. This is not a precise clock, but is meant to provide the 8051 with a clock source, without running the
24MHz crystal oscillator or the PLL
Switching between fast and slow clocks is recommended to save pow er.
Clock switching can be done on the fly as long as both clocks are running. When switching, it takes a total of six
clocks (3 clocks of the original clock plus 3 clocks of the switching clock) to guarantee the switching.
Time TBD is required from ROSC_EN=1 to MCUCLK_SRC=0.
SMSC DS – USB97C100Page 24Rev. 01/03/2001
Table 28 - FLASH Bank Select Register
MEM_BANK
(0x7F29 - RESET=0x01)FLASH BANK SELECT REGISTER
BITNAMER/WDESCRIPTION
[7:6]ReservedRReserved
[5:0]A[19:14]R/WThis register selects which 16k page resides at 0x4000-0x7FFF in Code
Space and 0xC000-0xFFFF in Data Space. The 0x0000-0x3FFF page
will always reflect the 16K FLASH page 0 (0x00000-0x03FFF).
Table 29 - Wakeup Source 1 Register
WU_SRC_1
(0x7F2A - RESET=0x00)WAKEUP SOURCE 1
BITNAMER/WDESCRIPTION
[7:3]ReservedRReserved
2USB_ResetRThis bit is set when the SIE detects simultaneous logic lows on D+
and D- (Single-Ended 0) for 32 to 64 full speed bit times, or 4 to 8 low
speed bit times (or 2.5<t<5.5us). The USB_Reset signal may be as
long as 10ms. SETUP tokens can be NAK'd for up to 10ms after the
Reset signal is released.
1ResumeRThis bit is set on detection of Global Resume state (when there is a
transition from the "J" state while in Global Suspend).
0Reserved '0'RReserved
Notes:
Only low to high transitions for the associated inputs sets these bits.
These bits are cleared each time this register is read.
Unmasked W akeup Source bits generate an INT1 PWR_MNG interrupt, and restart the 8051 when its clock is
stopped. This restarts the Ring Oscillator and crystal oscillator for the MCU to resume from <500µA operation.
To initiate USB Remote Wakeup, the SIE_Resume bit should be used in the SIE_CONFIG register.
Table 30 - Wakeup Mask 1 Register
WU_MSK_1 (Note 1)
(0x7F2B - RESET=0x07 )WAKEUP MASK 1
BITNAMER/WDESCRIPTION
[7:3]ReservedRReserved
2USB_ResetR/WExternal wakeup event.
0 = Enabled
1 = Masked
1ResumeR/WExternal wakeup event.
0 = Enabled
1 = Masked
0ReservedRReserved
Note: Interrupt events enabled by these bits are routed to the PWR_MNG Bit 0 in the ISR_1 register.
SMSC DS – USB97C100Page 25Rev. 01/03/2001
Table 31 - Wakeup Source 2 Register
WU_SRC_2
(0x7F2C - RESET=0x00)WAKEUP SOURCE 2
BITNAMER/WDESCRIPTION
[7:4]'0'RReserved
3IRQ3RExternal Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
2IRQ2RExternal Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
1IRQ1RExternal Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
0IRQ0RExternal Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
Notes:
Any transition from high to low, or low to high on the associated input sets these bits. These bits are cleared
each time this register is read.
Since this register will report any status change, when devices are to be powered down while monitored, the
appropriate bits must be masked until the device is armed correctly.
Table 32 - Wakeup Mask 2 Register
WU_MSK_2
(0x7F2D - RESET=0x0F)WAKEUP MASK 2
BITNAMER/WDESCRIPTION
[7 :4]'0'RReserved
3IRQ3R/WExternal wakeup event enable.
0 = Enabled
1 = Masked
2IRQ2R/WExternal wakeup event enable.
0 = Enabled
1 = Masked
1IRQ1R/WExternal wakeup event enable.
0 = Enabled
1 = Masked
0IRQ0R/WExternal wakeup event enable.
0 = Enabled
1 = Masked
Note: Interrupt events enabled by these bits are be routed to the PWR_MNG Bit 0 in the ISR_1 register.
SMSC DS – USB97C100Page 26Rev. 01/03/2001
MCU ISA Interface Registers
BUS_REQ
(0x7F70 – RESET=0x00)ISA BUS REQUEST REGISTER
BITNAMER/WDESCRIPTION
7INH_TC3R/WThis bit inhibits DMA channel 3 TC.**See Note Below
6INH_TC2R/WThis bit inhibits DMA channel 2 TC.** See Note Below
5INH_TC1R/WThis bit inhibits DMA channel 1 TC.** See Note Below
4INH_TC0R/WThis bit inhibits DMA channel 0 TC.** See Note Below
3RESET_8237R/WWriting a '1' holds the 8237 hardware reset input active. Writing
2AENRThis bit reflects the status of the 8237's AEN pin. This bit does
1HLDAR/WThe 8051 can grant the bus when it is ready via HLDA. This
0HREQRThis bit reflects the status of the 8237's HREQ bus request pin.
Table 33 – ISA Bus Request Register
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
'0' releases it for normal operation. May be used for clock
switching or power management functions.
not generate an interrupt
should tri-state any common signals between the 8051 and the
8237 on the ISA bus.
This bit does not generate an interrupt.
Note:HLDA Example: When the 8051 is running at 24MHz, and the 8237 is running at 2MHz, the 8237 may take
up to 1.5us to complete a transfer after deasserting HLDA . When running the 8051 at 24MHz, wait states
must be added when the 8237 is running at 2 or 4 MHz. When running the 8051 at 12MHz, wait states must
be added when the 8237 is running at 2 MHz.
Note**: The “Inhibit” function is not valid for Memory-to-Memory DMA cycles
SMSC DS – USB97C100Page 27Rev. 01/03/2001
Table 34 - ISA Bus Status Register
BUS_STAT
(0x7F73 - RESET=0xXX)ISA BUS STATUS REGISTER
BITNAMER/WDESCRIPTION
7CH3RQRChannel 3 DMA Request
0 = No Request Pending
1 = Request Pending
6CH2RQRChannel 2 DMA Request
0 = No Request Pending
1 = Request Pending
5CH1RQRChannel 1 DMA Request
0 = No Request Pending
1 = Request Pending
4CH0RQRChannel 0 DMA Request
0 = No Request Pending
1 = Request Pending
3CH3TCRChannel 3 Terminal Count Reached
0 = No
1 = Yes
2CH2TCRChannel 2 Terminal Count Reached
0 = No
1 = Yes
1CH1TCRChannel 1 Terminal Count Reached
0 = No
1 = Yes
0CH0TCRChannel 0 Terminal Count Reached
0 = No
1 = Yes
Notes:
Each bit in this register reflects the current value of the corresponding bit in the 8237 CH_STAT status register.
The 8237 clears bits 3..0 in the CH_STAT status register when the 8051 reads it through the ISA Bus I/O
Window.
Reading the BUS_STAT register does not clear or otherwise affect the BUS_STAT register.
The ISADMA bit in ISR_0 is latched high whenever any bit in BUS_STAT that is enabled in BUS_MASK
transitions from low to high.
This register is intended (1) to provide a view into the status of the 8237 without having to assume control of the
ISA bus during DMA transfers, and (2) to provide a means for generating the ISADMA interrupt in ISR_0 which
indicates that a DMA transfer has completed and that the 8051 should take control of the bus and setup the
8237 for its next transfer. Bits 7-4 can be used to generate additional interrupt requests from the DREQ pins, or
simply to monitor channel request status by masking them.
[7:0]SA[15:8]R/WWhen the 8051 reads or writes to the ISA I/O Window,
this register is combined with the 8 bit offset in the 256
byte window and presented as the 64k I/O Space address
during an 8051-ISA IOR or IOW cycle
Table 37 - ISA Memory Window Base Register
MEMBASE
(0x7F72 - RESET=0x00)ISA MEMORY WINDOW BASE REGISTER
BITNAMER/WDESCRIPTION
[7:0]SA[19:12]R/WWhen the 8051 reads or writes to the ISA Memory
Window, this register is combined with the 12 bit
offset in the 4k byte window and presented as the
1Mbyte Memory address during an 8051-ISA
MEMR or MEMW cycle.
SMSC DS – USB97C100Page 29Rev. 01/03/2001
8237 (ISADMA) REGISTER DESCRIPTION
Memory Map
Table 38 - ISADMA Memory Map
8237 MEMORY ADDRESSDESCRIPTION
0xFC00-0xFFFF1k Window to Packet with PNR=0x1F
0xF800-0xFBFF1k Window to Packet with PNR=0x1E
0xF400-0xF7FF1k Window to Packet with PNR=0x1D
0xF000-0xF3FF1k Window to Packet with PNR=0x1C
0xEC00-0xEFFF1k Window to Packet with PNR=0x1B
0xE800-0xEBFF1k Window to Packet with PNR=0x1A
0xE400-0xE7FF1k Window to Packet with PNR=0x19
0xE000-0xE3FF1k Window to Packet with PNR=0x18
0xDC00-0xDFFF1k Window to Packet with PNR=0x17
0xD800-0xDBFF1k Window to Packet with PNR=0x16
0xD400-0xD7FF1k Window to Packet with PNR=0x15
0xD000-0xD3FF1k Window to Packet with PNR=0x14
0xCC00-0xCFFF1k Window to Packet with PNR=0x13
0xC800-0xCBFF1k Window to Packet with PNR=0x12
0xC400-0xC7FF1k Window to Packet with PNR=0x11
0xC000-0xC3FF1k Window to Packet with PNR=0x10
0xBC00-0xBFFF1k Window to Packet with PNR=0x0F
0xB800-0xBBFF1k Window to Packet with PNR=0x0E
0xB400-0xB7FF1k Window to Packet with PNR=0x0D
0xB000-0xB3FF1k Window to Packet with PNR=0x0C
0xAC00-0xAFFF1k Window to Packet with PNR=0x0B
0xA800-0xABFF1k Window to Packet with PNR=0x0A
0xA400-0xA7FF1k Window to Packet with PNR=0x09
0xA000-0xA3FF1k Window to Packet with PNR=0x08
0x9C00-0x9FFF1k Window to Packet with PNR=0x07
0x9800-0x9BFF1k Window to Packet with PNR=0x06
0x9400-0x97FF1k Window to Packet with PNR=0x05
0x9000-0x93FF1k Window to Packet with PNR=0x04
0x8C00-0x8FFF1k Window to Packet with PNR=0x03
0x8800-0x8BFF1k Window to Packet with PNR=0x02
0x8400-0x87FF1k Window to Packet with PNR=0x01
0x8000-0x83FF1k Window to Packet with PNR=0x00
0x0000-0x7FFF32K Window to External ISA RAM
The actual packet may be composed of up to 10 different 128 byte non-contiguous packets, but the MMU re-maps
the internal addresses automatically such that the 8237 and 8051 only need to reference the packet number and
offset within the packet. For example, suppose a 312 (0x138) byte packet is received by the SIEDMA from the host.
The patented MMU allocates 384 bytes for the packet (including an 8 byte status header) and returns a PNR tag of
0x0A. The SIEDMA engine will place 0x0A in the receive packet queue and notify the 8051. The 8051 will take that
PNR, examine the packet through its own PNR/Pointer registers, and determine the offset for the payload data it
wants to transfer from the packet, say 0x027. The address it must calculate for the 8237 base address register would
therefore be 0xA827 (0xA800+0x027). Each channel can be programmed with a different (or same) Packet Number
and offset and the data will appear to it as ordinary contiguous RAM (see table 32 for more information).
Software written to this model will work for virtually any Endpoint number and Buffer size combination.
SMSC DS – USB97C100Page 30Rev. 01/03/2001
Runtime Registers
The DMA controller has a block of 16 R/W registers which normally occupy I/O locations 0x00-0x0F on the ISA bus.
When they are located at 0x0000-0x000F on the ISA bus, the 8051 can access them by programming the IOBASE
Register to 0x00, and reading or writing from 0x4000-0x400F.
Register
0x000DMaster Clear
0x000EClear Mask
0x000FWrite All Mask Bits
Note: To write to these registers, HLDA must be logic low.
SMSC DS – USB97C100Page 31Rev. 01/03/2001
Table 40 - 8237 Address Programming Guide
8237 INTERNAL ADDRESS PROGRAMMING GUIDE
BITNAMEDESCRIPTION
15INT_EXTIndicates whether this address refers to Internal Buffer RAM or
External ISA Memory Space
0 = External
1 = Internal
When this bit is set to zero (0), I/O capability is added to External
Memory DMA. This capability can only be used for DMA channels 2
or 3.
[14:10]PN[4:0]/SA[14:10]External Address -or- Internal Packet Number
Note: SA[19..15] are driven low when the 8237 is accessing external ISA memory. PTR10 is driven low when the
8237 is accessing internal buffer RAM. Note that the actual transfer size for the ISADMA is limited to 1024
bytes, which limits the payload data to 1016 bytes per transfer when the 8 byte header is skipped. Also note
that the 8051 still has access to 1Meg of external RAM through the MEMBASE register and it is
independent of the 8237's 32k external limit.
Table 41 - Channel 0 Current Address Register
CH0_ADDR
(ISA 0x0000)CHANNEL 0 CURRENT ADDRESS
BITNAMER/WDESCRIPTION
[7:0]CH0_ADDRLR/WLower 8 bits of Base and Current Address when Byte F/F = 0
[7:0]CH0_ADDRHR/WUpper 8 bits of Base and Current Address when Byte F/F = 1
Note:Byte F/F is an internal Flip Flop which reflects which byte (high or low) is being written. The CLEAR_FF
register should be written to before writing this register to guarantee which byte (high or low) is being
written. See the Address Programming Table for 16 bit Address definitions.
Table 42 - Channel 0 Byte Count Register
CH0_CNT
(ISA 0x0001)CHANNEL 0 BYTE COUNT
BITNAMER/WDESCRIPTION
[7:0]CH0_CNTLR/WLower 8 bits of Byte Count when Byte F/F = 0
[7:0]CH0_CNTHR/WUpper 8 bits of Byte Count when Byte F/F = 1
Note:The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See Address Programming Table for 16 bit Address definitions.
Table 43 - Channel 1 Current Address Register
CH1_ADDR
(ISA 0x0002)CHANNEL 1 CURRENT ADDRESS
BITNAMER/WDESCRIPTION
[7:0]CH1_ADDRLR/WLower 8 bits of Base and Current Address when Byte F/F = 0
[7:0]CH1_ADDRHR/WUpper 8 bits of Base and Current Address when Byte F/F = 1
Note: The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See the Address Programming Table for 16 bit Address definitions.
SMSC DS – USB97C100Page 32Rev. 01/03/2001
Table 44 - Channel 1 Byte Count Register
CH1_CNT
(ISA 0x0003)CHANNEL 1 BYTE COUNT
BITNAMER/WDESCRIPTION
[7:0]CH1_CNTLR/WLower 8 bits of Byte Count when Byte F/F = 0
[7:0]CH1_CNTHR/W Upper 8 bits of Byte Count when Byte F/F = 1
Note:The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See Address Programming Table for 16 bit Address definitions.
Table 45 - Channel 2 Current Address Register
CH2_ADDR
(ISA 0x0004)CHANNEL 2 CURRENT ADDRESS
BITNAMER/WDESCRIPTION
[7:0]CH2_ADDRLR/WLower 8 bits of Base and Current Address when Byte F/F = 0
[7:0]CH2_ADDRHR/WUpper 8 bits of Base and Current Address when Byte F/F = 1
Note:The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See the Address Programming Table for 16 bit Address definitions.
Table 46 - Channel 2 Byte Count Register
CH2_CNT
(ISA 0x0005)CHANNEL 2 BYTE COUNT
BITNAMER/WDESCRIPTION
[7:0]CH2_CNTLR/WLower 8 bits of Byte Count when Byte F/F = 0
[7:0]CH2_CNTHR/WUpper 8 bits of Byte Count when Byte F/F = 1
Note:The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See Address Programming Table for 16 bit Address definitions.
Table 47 - Channel 3 Current Address Register
CH3_ADDR
(ISA 0x0006)CHANNEL 3 CURRENT ADDRESS
BITNAMER/WDESCRIPTION
[7:0]CH3_ADDRLR/WLower 8 bits of Base and Current Address when Byte F/F = 0
[7:0]CH3_ADDRHR/WUpper 8 bits of Base and Current Address when Byte F/F = 1
Note:The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See the Address Programming Table for 16 bit Address definitions.
Table 48 - Channel 3 Byte Count Register
CH3_CNT
(ISA 0x0007)CHANNEL 3 BYTE COUNT
BITNAMER/WDESCRIPTION
[7:0]CH3_CNTLR/WLower 8 bits of Byte Count when Byte F/F = 0
[7:0]CH3_CNTHR/WUpper 8 bits of Byte Count when Byte F/F = 1
Note:The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See Address Programming Table for 16 bit Address definitions.
SMSC DS – USB97C100Page 33Rev. 01/03/2001
Table 49 - Channel Status Register
CH_STAT
(ISA 0x0008)CHANNEL STATUS REGISTER
BITNAMER/WDESCRIPTION
7CH3RQRChannel 3 DMA Request
0 = No Request Pending
1 = Yes Request Pending
6CH2RQRChannel 2 DMA Request
0 = No Request Pending
1 = Yes Request Pending
5CH1RQRChannel 1 DMA Request
0 = No Request Pending
1 = Yes Request Pending
4CH0RQRChannel 0 DMA Request
0 = No Request Pending
1 = Yes Request Pending
3CH3TCRChannel 3 Terminal Count Reached
0 = No
1 = Yes
2CH2TCRChannel 2 Terminal Count Reached
0 = No
1 = Yes
1CH1TCRChannel 1 Terminal Count Reached
0 = No
1 = Yes
0CH0TCRChannel 0 Terminal Count Reached
0 = No
1 = Yes
Notes:
These bits are also visible outside of I/O space in the BUS_STAT register.
These bits are cleared when this register is read through the ISA I/O Window.
Table 50 - 8237 Command Register
CH_CMD
(ISA 0x0008)COMMAND REGISTER
BITNAMER/WDESCRIPTION
7DACK_SENSWDACK Sense
0 = Active High
1 = Active Low
6DREQ_SENSWDREQ Sense (1 = Active Low, 0 = Active High)
5WRITE_TIMEWWrite Timing Select
'XX' if bits 6 and 7 = '11' Or if CH_CMD register bit 0
= 1 (memory-to-memory transfer)
[1:0]SEL[1:0]W'00' = Select Channel 0
'01' = Select Channel 1
'10' = Select Channel 2
'11' = Select Channel 3
Table 54 - Clear Byte Pointer Flip Flop Register
CLEAR_FF
(ISA 0x000C)CLEAR BYTE POINTER FLIP FLOP
BITNAMER/WDESCRIPTION
[7:0]BPFFWThis register must be written to clear the high/low byte
pointer flip flop prior to reading or writing new address or
word count information to the 8237.
SMSC DS – USB97C100Page 35Rev. 01/03/2001
Table 55 - Read Temporary Register
RD_TEMP
(ISA 0x000D)READ TEMPORARY REGISTER
BITNAMER/WDESCRIPTION
[7:0]TEMP_BYTERThis location holds the value of the last byte transferred in a
memory-to-memory operation.
Table 56 - Master Clear Register
MSTR_CLR: (ISA 0x000D)MASTER CLEAR REGISTER
BITNAMER/WDESCRIPTION
[7:0]SW_RESETWWriting to this register has the same effect on the registers
as a hardware reset. The 8237 will enter the idle state.
Table 57 - Clear Mask Register
CLR_MASK: (ISA 0x000E)CLEAR MASK REGISTER
BITNAMER/WDESCRIPTION
[7:0]CLR_ALLWWriting to this register clears the mask bits of all four
channels and allows them to receive DMA requests.
Table 58 - Clear All Mask Bits Register
ALL_MASK
(ISA 0x000F)WRITE ALL MASK BITS REGISTER
BITNAMER/WDESCRIPTION
[7:4]ReservedWReserved
3CH3_MASKWChannel 3 Mask Bit (1 = Set Mask, 0 = Clear Mask)
2CH2_MASKWChannel 2 Mask Bit (1 = Set Mask, 0 = Clear Mask)
1CH1_MASKWChannel 1 Mask Bit (1 = Set Mask, 0 = Clear Mask)
0CH0_MASKWChannel 0 Mask Bit (1 = Set Mask, 0 = Clear Mask)
SMSC DS – USB97C100Page 36Rev. 01/03/2001
MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION
MMU Interface Registers
Table 59 - MMU Data Window Register
MMU_DATA
(0x6000)MMU DATA WINDOW REGISTER
BITNAMER/WDESCRIPTION
[7:0][D7:D0]R/WData Packet Window.
When RCV in the PRH register = '1', this is the byte pointed to by
the packet number on the top of the RXFIFO, and the packet
offset of PRH:PRL.
When RCV in the PRH register = '0', this is the byte pointed to by
the packet number in the PNR register, and the packet offset of
PRH:PRL.
Notes:
The Read FIFO may take at most 1.218µs after the PNH is written to present valid data.
The Write FIFO may take at most 2.520µs after writing the last byte of data to the FIFO to finish writing that data
to the buffer.
The worst case sequential access times to the FIFOs while the 8237 is simultaneously arbitrating for the MMU,
and a USB packet is currently being transferred, is 588ns.
- (READ) Therefore, after changing the PRH register, the 8051 should wait at least 2 instruction cycles (at
12MHz) before reading from this register. After waiting, the 8051, in auto-increment mode (PRH bit 6=1), can
read a byte every cycle (at up to 16MHz).
- (WRITE) The data register mode can be switched to write at any time, and data can be written immediately
on every instruction cycle. After writing data, the 8051 should wait at least 3 instruction cycles (at 12MHz)
before changing the PNR or PRH :PRL registers for a Read . Again, after waiting 1.218µs, the 8051 can read
a byte every instruction cycle.
Table 60 - Pointer Register (Low)
PRL
(0x7F50)POINTER REGISTER (LOW)
BITNAMER/WDESCRIPTION
[7:0]A[7:0]R/WLSB of the (0-1277 Max) offset of the allocated Packet Pointed to
by PNR. The byte(s) pointed to by this register can be read and
written to by the MCU at 0x6000.
Notes:
This register must be written before PRH.
The value read from this register is not necessarily what was last written to it, but actually the last address
used to access the buffer RAM.
SMSC DS – USB97C100Page 37Rev. 01/03/2001
Table 61 - Pointer Register (High)
PRH
(0x7F51)POINTER REGISTER (HIGH)
BITNAMER/WDESCRIPTION
7RCVR/W0 = The packet at 0x6000 is the packet pointed to by the PNR
register.
1 = The packet available at 0x6000 is the packet pointed to by the
packet on the top of the RX Packet Number FIFO.
6AUTO_INCRR/W0 = Auto-increment is disabled
1 = Causes the PRH:PRL register to be automatically
incremented each time the 0x6000 data window is accessed.
5READR/WData register direction. This bit is required for the MMU/Arbiter to
provide a transparent interface to the buffer RAM for the MCU.
When first set, the MMU immediately fills the read FIFO. The
MCU must wait 2.5us (60 Arbiter clocks) after writing to the
MMU_DATA register before changing this bit from '0' to '1'.
0 = WRITE
1 = READ
[4:3]ReservedRReserved
[2:0]A[10:8]R/WMSB of the (0-1277 Max) offset of the allocated Packet Pointed to
by PNR. The byte(s) pointed to by this register can be read and
written to by the MCU at 0x6000.
Note: This register must be written after PRL for its value to take effect.
Table 62 - Transmit FIFO Select Register
MMUTX_SEL
(0x7F52)TRANSMIT FIFO SELECT REGISTER
BITNAMER/WDESCRIPTION
[7:4]ReservedRReserved
[3:0]EP[3:0]R/WThis register selects which Endpoint Commands "110" and "111"
will affect when issued to the MMU
Note:This register must be written before writing the “Enqueue Packet into Endpoint x” or the “Reset TX Endpoint
x” command to the MMUCR .
Table 63 - MMU Command Register
MMUCR
(0x7F53)MMU COMMAND REGISTER
BITNAMER/WDESCRIPTION
[7:5]MMU_CMDWMMUCR COMMAND SET
4ReservedWReserved, writes are ignored and read return “0”
[3:0]N[3:0]WNumber of 128 byte Pages. N[3..0]=0000 indicates 1 page, and
N[3..0]=1001 indicates 10 pages, or 1280 bytes.
MMU COMMAND Bits 7, 6, and 5 Description:
NOOP, No operation
000
Allocate Memory : N3-0 specify how many 128 byte pages to allocate for that packet (up to 10
001
pages allowed (1280 bytes) per packet.) Immediately generates a "FAILED" code at the ARR
and the code is cleared when complete. Can generate an ALLOC interrupt to MCU upon
completion. When an allocation request cannot be completed due to insufficient memory, the
FAILED bit in the ARR will remain set. Any subsequent release of memory pages (by either
the MMUCR or the SIEDMA) will cause the MMUCR to automatically continue the allocate
command until all requested pages have been successfully allocated. Software should never
issue another allocate command until the previous allocate command has been successfully
completed.
RESET MMU : Frees all buffer RAM, clears interrupts, and resets queue pointers.
010
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Remove Packet from top of RX Queue : To be issued after MCU has completed processing the
011
packet number at the RXFIFO.
Remove and Release Top of RXFIFO : Same as (011), but also frees all memory used by the
100
packet. This command is especially useful as a quick way to "ignore" bad packets.
Release specific Packet : Frees all pages allocated to the packet specified in the PNR.
101
Enqueue Packet into Endpoint x : Places the Packet number indicated by the PNR register in
110
the transmit queue of the endpoint pointed to by the MMUTX_SEL register. The MMUTX_SEL
register must be written before this command is issued.
Reset TX Endpoint x : Resets the TX FIFO holding the packet numbers awaiting transmission
111
and the TXFIFO_STAT bits of the endpoint pointed to by the MMUTX_SEL register. The
MMUTX_SEL register must be written before this command is issued. This command does not
release any memory allocated to packets that are dequeued.
Table 64 - Allocation Result Register
ARR
(0x7F54)ALLOCATION RESULT REGISTER
BITNAMER/WDESCRIPTION
7FAILED R
[6:5]ReservedRReserved
[4:0]P[4:0]RReturns Packet Number (0-31, 0x00-0x1F) from an allocation
command. This can be written directly into the PNR register
Table 65 - Packet Number Register
PNR (0x7F55)PACKET NUMBER REGISTER
BITNAMER/WDESCRIPTION
[7:5ReservedRReserved
[4:0]P[4:0]R/WPacket selector to access packet at 0x6000 buffer window
SMSC DS – USB97C100Page 39Rev. 01/03/2001
MMU Free Pages Register
MMU Free Pages bits, and a global NAK_ALLRX (this can only NACK OUT and Bulk packets) control bit for the
firmware to view the real time status of the 32 page allocation bits. This allows the MCU to set NAK_ALLRX which
would inhibit the SIE from asking the SIEDMA to allocate packets, MCU checks how many pages are left, issue an
allocate if enough are free, and then release the SIE/SIEDMA. For the current design, the number of free pages
would range from 0x00 to 0x1F (32) pages left unallocated.
The indication of pages free may be invalid during an allocation or deallocation.
Table 66 - Pages Free In The MMU
PAGS_FREE
(0x7F56 - RESET=0x20)PAGES FREE IN THE MMU
BITNAMER/WDESCRIPTION
7NAK_ALLRXR/WNACK All received packets
0 = Normal Operation (Default)
1 = NACK all RX packets
6Reserved0Reserved
[5:0]PAGS_FREERThese bits indicate the number of free pages in the MMU.
Notes:
Firmware can set a NAK_ALLRX bit to inhibit the SIE from asking the SIEDMA to allocate any pages while the
MCU is observing the page free bits.
This register is used to indicate how many pages are left in many situations, including after an RX_OVRN,
before a multi-packet allocation, etc. This eliminates the possibility of a failed allocation, simplifying software
without adding additional hardware to abort an allocation.
16 BYTE DEEP TX COMPLETION FIFO REGISTER
Table 67 - TX Management Register 2
TX_MGMT
(0x7F57 - RESET=0x80)TX Management Register
BITNAMER/WDESCRIPTION
7CTX_EMTYRCompleted TX FIFO empty status
0 = Has one or more TX packet
1 = Empty
6CTX_FULLRCompleted TX FIFO full status
0 = Not FULL
1 = FULL
5ReservedRReserved
[4:0]CTX_FIFORThis is the data port for the 16 deep TX completion FIFO. This
FIFO is automatically updated by hardware with the last
successfully completed transmit packet. It is the responsibility of
software to ensure that this FIFO never overflows and/or becomes
full.
SMSC DS – USB97C100Page 40Rev. 01/03/2001
Table 68 - Receive Packet Number FIFO Register
RXFIFO
(0x7F58)NEXT RX PACKET NUMBER FIFO REGISTER
BITNAMER/WDESCRIPTION
7RXFIFO_EMPT
R1 = No pending packets from the host to be processed
Y
6RXFIFO_FULLR1 = The SIEDMA will not accept packets from the host (via RX
Overflow)
5ReservedRReserved
[4:0]P[4:0]RPacket Number
When a packet has been received, and the 8-byte header has
been written by the SIEDMA, the associated Packet Number is
placed in this FIFO
A "complete" reception requires that the 8 byte status header is correctly written into the packet buffer, with the
correct data, and moved into the RX Packet Number FIFO. A "successful" reception requires that the CRC and PID
check bits of a "complete" reception are good. The hardware queues only "complete" packets. Firmware must
determine if "complete" packets were "successful". Corrupted token packets causes the complete data payload to
be ignored.
Tx FIFO POP Register
This register is used to help software manage TX Queues. This will provide a method to handle a
CLEAR_FEATURE:ENDPOINT_STALL” condition gracefully. When read, this register will return the Packet
Number of the next packet waiting on the TX queue pointed to by MMUTX_SEL register, AND it will pop that Packet
Number off of the selected TX FIFO.
Table 69 - POP TX FIFO
POP_TX
(0x7F59 – RESET=0x80)POP TX FIFO
BITNAMER/WDESCRIPTION
7POPTX_STATRPOP TX FIFO empty status
0 = Has one or more TX packet
1 = Empty
[6:5]ReservedRReserved
[4:0]POP_TXRThis 5 bit value is the packet number or handle that is at the top of
the TX FIFO pointer to by MMUTX_SEL. The TX FIFO is popped
when this register is read.
Note: It is the software's responsibility to ensure that the appropriate TX EP is disabled during this operation, and to
issue a deallocate command if desired.
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Table 70 - Transmit FIFO Status Register A
TXSTAT_A
(0x7F60 - RESET=0x55)TRANSMIT FIFO STATUS REGISTER A
BITNAMER/WDESCRIPTION
7EP3TX_EMPTYREndpoint 3 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
6EP3TX_FULLR
5EP2TX_EMPTYREndpoint 2 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
4EP2TX_FULLR
3EP1TX_EMPTYREndpoint 1 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
2EP1TX_FULLR
1EP0TX_EMPTYREndpoint 0 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
0EP0TX_FULLR
Table 71 - Transmit FIFO Status Register B
STAT_B
(0x7F61 - RESET=0x55)TRANSMIT FIFO STATUS REGISTER B
BITNAMER/WDESCRIPTION
7EP7TX_EMPTYREndpoint 7 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
6EP7TX_FULLR
5EP6TX_EMPTYREndpoint 6 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
4EP6TX_FULLR
3EP5TX_EMPTYREndpoint 5 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
2EP5TX_FULLR
SMSC DS – USB97C100Page 42Rev. 01/03/2001
STAT_B
(0x7F61 - RESET=0x55)TRANSMIT FIFO STATUS REGISTER B
BITNAMER/WDESCRIPTION
1EP4TX_EMPTYREndpoint 4 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
0EP4TX_FULLR
Table 72 - Transmit FIFO Status Register C
TXSTAT_C
(0x7F62 - RESET=0x55)TRANSMIT FIFO STATUS REGISTER C
BITNAMER/WDESCRIPTION
7EP11TX_EMPTYREndpoint 11 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
6EP11TX_FULLR
5EP10TX_EMPTYREndpoint 10 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
4EP10TX_FULLR
3EP9TX_EMPTYREndpoint 9 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
2EP9TX_FULLR
1EP8TX_EMPTYREndpoint 8 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
0EP8TX_FULLR
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Table 73 - Transmit FIFO Status Register D
TXSTAT_D
(0x7F63 - RESET=0x55)TRANSMIT FIFO STATUS REGISTER D
BITNAMER/WDESCRIPTION
7EP15TX_EMPTYREndpoint 15 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
6EP15TX_FULLR
5EP14TX_EMPTYREndpoint 14 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
4EP14TX_FULLR
3EP13TX_EMPTYREndpoint 13 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
2EP13TX_FULLR
1EP12TX_EMPTYREndpoint 12 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
0EP12TX_FULLR
Table 74 - TX Management Register 1
TX_MGMT
(0x7F67 - RESET=0x00)TX Management Register 1
BITNAMER/WDESCRIPTION
[7:1]ReservedRReserved
0MEM_DALLR/WMemory deallocate Mode
0 = Auto
1 = Manual deallocation, but the TX FIFO Pop is still
automatic.
This control bit selects between Auto and Manual memory
pages deallocation. This bit should be statically set at the
start of operation, and can not be changed during or if
about to transmit. This bit defaults to “0” for normal
operation. When set, the MCU handles freeing up the
memory pages.
SMSC DS – USB97C100Page 44Rev. 01/03/2001
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION
Packet Header Definition
The following header contains information to determine endpoint, status, length of the received packet, and the
payload “received data”.
Table 75 - Packet Header Definition
OFFSETMSB 7654321LSB 0
<n + 7
Payload Data Byte n-1 (n is the payload data size, which is Byte Count -8)
- For 0 Length Packet, Byte Count = 0x008
- For 1 byte Packet, Byte Count = 0x009
- For any Packet, (Byte Count-1) points to last byte of payload data
1. Offset 0 to 7 is the packet header.
a) Offset 0x000 to 0x005 is generated by the SIE.
i)Offset 0x000 bit bit 5 - Bad_TOG- This bit is set when the SIE receives an unexpected
toggle. This is not necessarily an error condition, This bit could indicate a condition when
the return handshake packet is lost .
Last Packet Toggle ValueCurrent Packet Toggle Value“BAD TOG” bit
001
010
100
111
ii) Offset 0x000 bit Last_TOG is the last toggle bit received.
iii)Offset 0x000 bit Bad_CRC, is set when the SIE detects a bad CRC.
b) Offset 0x006 to 0x007 is generated by the SIEDMA.
2.Offset 8 to n+7 is the actual data received from the USB bus and stored in memory.
SMSC DS – USB97C100Page 45Rev. 01/03/2001
SIE Interface Registers
The architecture of the USB97C100 is such that there are no data FIFO's associated with individual endpoints. The
MMU does not differentiate packets by endpoint number. The firmware must read the endpoint number from the
packet header to pass the packet on to the appropriate endpoint handler. This makes the chip dynamic and flexible
in allocating buffers to store any payload size from 0 to 1280 bytes. Each endpoint can be configured separately via
the following register:
Table 76 - Endpoint Control Registers
EP_CTRL[15..0]
(0x7F8F-0x7F80 - RESET=0x00)ENDPOINT CONTROL REGISTERS
BITNAMER/WDESCRIPTION
7TX_ISOR/WBit 7 instructs the SIE how to handle handshakes for transmit
endpoints during "IN" transactions, and how the SIEDMA
engine should handle packet queue status after packet
transmission. When a TX endpoint is configured for
isochronous operation (Bit 7 = '1'), all packet transmissions are
considered successful and the SIEDMA must move the packet
number into the TX Completion FIFO. When the TX endpoint is
non-isochronous (Bit 7 = '0'), then the SIE must receive a valid
ACK handshake from the host before the packet is released.
This guarantees data integrity for non-isochronous
transactions.
Successfully transmitted packets are automatically de-queued
and the packet is released.
0 = Non-Isochronous
1 = Isochronous
6RX_ISOR/WBit 6 instructs the SIE how to handle handshakes for receive
endpoints during "OUT" and "SETUP" transactions. Once a
packet matches the 7-bit Function Address, the SIE must begin
page allocation and generate a new packet in buffer RAM. The
MCU must check PID_Valid and CRC_Valid bits and dequeue
"bad" packets. The SIE will use bit 6 to inhibit handshakes
when enabled.
0 = Non-isochronous
1 = Isochronous
5,3TX_CONT[1:0]R/W
0,0= Endpoint is disabled, and does not send handshakes.
0,1= Send a STALL handshake for an IN transaction directed at
this EP.
1,0= Normal Operation. ACK or NAK is sent depending on
whether data is in the EPXs TX_QUEUE.
1,1= Send a NAK handshake for an IN transaction directed at
this EP, regardless of TX_QUEUE status. (Note 3)
4,2RX_CONT[1:0]R/W0,0= Endpoint is disabled, and does not send handshakes.
0,1= Send a STALL handshake for an OUT transaction directed
at this EP.
1,0= Normal Operation. ACK or NAK is sent depending on
RX_OK status
1,1= Send a NAK handshake for an OUT transaction directed
at this EP (Note 1)
1TX_TOGGLER/WThis bit is toggled after each successful transmiss i on.
TX_TOGGLE can be reset or cleared by the MCU but the MCU
must insure that the endpoint is disabled before modifying
them.
0RX_TOGGLERThis bit reflects the last DATA0/DATA1 toggle.
Notes:
There is one Endpoint Control Register per virtual endpoint. When the SIE decodes a token, the endpoint
number is used to index which EP_CTRL register bits should be used to respond to the SIE and SIEDMA.
This register allows firmware to throttle back RX packets to any specific endpoint(s) until the firmware decides
congestion has subsided.
SMSC DS – USB97C100Page 46Rev. 01/03/2001
If the firmware needs to STALL an endpoint, it should first be taken off-line by setting RX_CONT1=0, and then
RX_CON0=1.
This allows firmware to manage TX endpoint(s) and hold queued data until the firmware is ready, even if the
host is asking. This is not as critical as the RX version, but it may be required for Isochronous synchronization,
as well as STALL recovery.
Table 77 - LSB FRAME Count Register
FRAMEL
0x7F90 Reset 0x00FRAME COUNT REGISTER (LOW)
BITNAMER/WDESCRIPTION
[7:0]FRAME[7:0]RThe 11 bit Frame Number from each SOF packet is loaded with
the RISING edge of EOT when SOF_TOKEN = '1' and ACK = '1'.
Note:This register is always the last correctly received valid SOF Frame number. Garbled and invalid SOF tokens
do not alter this register.
Table 78 - MSB FRAME Count Register
FRAMEH
0x7F91 Reset 0x00FRAME COUNT REGISTER (HIGH)
BITNAMER/WDESCRIPTION
[7:3]EXT_FR[15:11]RExtended Frame Count.
The extended count bits are loaded with the RISING edge of
EOT when SOF_TOKEN = '1' and ACK = '1'. The extended
Frame count bit must also be enabled (EN_EXTFRAME = '1' in
SIE_CONFIG).
[2:0]FRAME[10:8]RFrame Number from each SOF packet is loaded with the
RISING edge of EOT when SOF_TOKEN = '1' and ACK = '1'.
Note:This register is always the last correctly received valid SOF Frame number. Garbled and invalid SOF tokens
do not alter this register.
Table 79 - Local Address Register
SIE_ADDR
(0x7F92 RESET=0x00)LOCAL ADDRESS REGISTER
BITNAMER/WDESCRIPTION
7RX_ALLR/W1 = Overrides the token address decoding of the SIE such
that no compare is done. Token CRC is also ignored when
RX_ALL=1. This bit forces all packets transmitted on the wire
to be received in the RX Packet Queue
[6:0]ADDR[6:0]R/WThis register is only written by the 8051. It is the SIE's local
address assigned during enumeration. This SIE address
allows Endpoints 0 through 3 to be available. This address
can be used for the HUB address.
Note:When RX_ALL is enabled, software should not enable any TX endpoints as they will respond to any
Address with the same endpoint and possibly cause contention on the line. Software should also set each
RX endpoint RX_ISO bit to prevent handshakes from being sent.
SMSC DS – USB97C100Page 47Rev. 01/03/2001
Table 80 - Alternate Address 1 Register
ALT_ADDR1
(0x7F99 - RESET=0x00)ALTERNATE SIE ADDRESS 1
BITNAMER/WDESCRIPTION
7EN_ALTADDR1R/WAlternate address.
1 = Enabled, this bit allows Endpoints 15 through 0 to be
available as Endpoint ALT0 through Endpoint ALT15. In other
words, the SIE can respond to two addresses with up to 32
endpoints distributed between them.
0 = Disabled, this register does not affect EP_OK generation.
6ALT6R/WAlternate address bit 6
5ALT5R/WAlternate address bit 5
4ALT4R/WAlternate address bit 4
3ALT3R/WAlternate address bit 3
2ALT2R/WAlternate address bit 2
1ALT1R/WAlternate address bit 1
0ALT0R/WAlternate address bit 0
Notes:
Endpoint numbers used for ALT_ADDRx are the compliment of the actual Endpoint number received. For
example, any packets sent to Endpoint “0” of the ALT_ADDRx will appear as Endpoint 15.
The Firmware (8051) must make sure that endpoint configurations do not overlap.
Table 81- Alternate Address 2 Register
ALT_ADDR2
(0x7F9E – RESET=0x00)ALTERNATE SIE ADDRESS 2
BITNAMER/WDESCRIPTION
7EN_ALTADDR2R/WAlternate address 2.
1 = Enabled, this bit allows Endpoints 8 through 11 to be
available to this address.
0 = Disabled, this register does not affect EP_OK
generation.
6ALT6R/WAlternate address bit 6
5ALT5R/WAlternate address bit 5
4ALT4R/WAlternate address bit 4
3ALT3R/WAlternate address bit 3
2ALT2R/WAlternate address bit 2
1ALT1R/WAlternate address bit 1
0ALT0R/WAlternate address bit 0
Table 82 - Alternate Address 3 Register
ALT_ADDR3
(0x7F9F – RESET=0x00)ALTERNATE SIE ADDRESS 3
BITNAMER/WDESCRIPTION
7EN_ALTADDR 3R/WAlternate address 3.
1 = Enabled, this bit allows Endpoints 12through 15 to be
available to this address.
0 = Disabled, this register does not affect EP_OK
generation.
6ALT6R/WAlternate address bit 6
5ALT5R/WAlternate address bit 5
4ALT4R/WAlternate address bit 4
3ALT3R/WAlternate address bit 3
2ALT2R/WAlternate address bit 2
1ALT1R/WAlternate address bit 1
0ALT0R/WAlternate address bit 0
SMSC DS – USB97C100Page 48Rev. 01/03/2001
Table 83 - SIE Status Register
SIE_STAT
(0x7F93 - RESET=0xXX)SIE STATUS REGISTER
BITNAMER/WDESCRIPTION
7ERRRIndicates that an error occurred during the last USB
transaction. Considered valid on the rising edge of EOT
6TIMEOUTRIndicate that the last USB transaction ended because of an
inter-packet time out condition (i.e.:>16 bit times).
Considered valid on the rising edge of EOT.
5SETUP_TOKENRIndicates that the token received was a SETUP token.
4SOF_TOKENRIndicates that the SOF PID has been received.
Considered valid when EOT is '0'.
3PRE_TOKENRIndicates that the SIE detected a PRE (preamble) packet
on the USB bus. The signal is asserted when the SIE has
seen a valid SYNC followed by a valid PRE PID.
2ACKRIndicates that the last USB transaction was completed
without error or time-out. Considered valid on the rising
edge of EOT.
1USB_RESETRWhen active '1', it indicates that the USB line is being
reset. This signal is asserted when the SIE detects a
string of single - ended 0's on the bus for a long time.
0EOTREnd - of - Transaction. On transition to a '1', it indicates
the end of transaction. On transition to a '0' it indicates the
beginning of a new transaction.
Note:This read only register reflects the status signals from the SIE state machine. This register can be polled
for test purposes, or by error handling routines for recovery.
Table 84 - SIE Control Register
SIE_CTRL
(0x7F94 - RESET=0x00)SIE CONTROL REGISTER
BITNAMER/WDESCRIPTION
7SIEDMA_DISABLER/W0 = Normal operation
1 = Inhibits SIEDMA operation to facilitate MCU override
6FORCE_RXOKR/WForces SIE to send Acknowledge during receive. Must be
'0' for normal operation.
5FORCE_TTAGR/W0 = Normal operation.
1 = Signals that the next byte written to the SIE TX_FIFO is
the last payload byte.
4FORCE_RXOVFLOR/W0 = Normal operation.
1 = Forces the SIE to generate RXOVFLO and clear the
SIE RX FIFO.
3FORCE_TXABORTR/W0 = Normal operation
1 = Forces a bit-stuff error at the host
2FORCE_EOTR/W0 = Normal operation.
1 = Forces an End-of-Transaction for the SIE
1RTAG_INRStatus of RTAG signal from SIE RX FIFO
0TXOK_INRStatus of TXOK from SIE
Note:Bits 7:2 must be set to “0” for normal operation. Altering these bits will cause an abnormal USB behavior.
SMSC DS – USB97C100Page 49Rev. 01/03/2001
Table 85 - SIE Configuration Register
SIE_CONFIG
(0x7F98 - RESET=0x40)SIE CONFIGURATION REGISTER
BITNAMER/WDESCRIPTION
7FSENR/WThis bit indicates that the USB97C100 supports 12Mbps USB
data rates. This bit must be set to a one ‘1’ for normal
operation.
6RST_SIER/W1 = Resets the SIE
5RST_FRAMER/W1 = Clears FRAMEL and Bit 0 through 2 of FRAMEH
4EN_EXTFRAMER/WExtended Frame Count Enable. Expands the Frame count
from 11 bits to 16 bits for 8051 use.
0 = bits 7-3 of FRAMEH are driven to 0.
1 = Bits 7-3 of FRAMEH count 1-0 transitions of bit 2 in
FRAMEH.
3SIE_SUSPENDR/W1 = Forces the SIE into USB Suspend Mode. The MCU must
determine that Suspend must be entered.
2SIE_RESUMER/W1 = Forces the SIE to transmit Resume signaling on the line.
1USB_RESUMER1 = Indicates Resume signaling has been detected on the line
while in the Suspend State. This signal causes a Resume
Power Management interrupt).
0USB_RESETR1 = Indicates that the USB line is being reset. Asserted when
SE0 is present on the bus for 32 or more 12Mbps bit times.
This causes a USB_RESET Power management interrupt.
SMSC DS – USB97C100Page 50Rev. 01/03/2001
DC PARAMETERS
MAXIMUM GUAR ANTEED RATING S
Operating Temperature Range...........................................................................................................................0
Storage Temperature Range...........................................................................................................................-55
Lead Temperature Range (soldering, 10 seconds).....................................................................................................+325
Positive Voltage on any pin, with respect to Ground.................................................................................................V
Negative Voltage on any pin, with respect to Ground.................................................................................................... -0.3V
*Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only
and functional operation of the device at any other condition above those indicated in the operation sections of this
specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when
the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output.
When this possibility exists, it is suggested that a clamp circuit be used.
o
C to +70oC
o
to +150oC
+0.3V
cc
o
C
DC ELECTRICAL CHARACTERISTICS (T
= 0°C - 70°C, Vcc = +3.3 V ± 10%)
A
PARAMETERSYMBOLMINTYPMAXUNITSCOMMENTS
I Type Input Buffer
Low Input Level
High Input Level
V
ILI
V
IHI
2.0
0.8V
TTL Levels
V
ICLK Input Buffer
Low Input Level
High Input Level
V
ILCK
V
IHCK
2.2
0.4V
V
Input Leakage
(All I and IS buffers)
Low Input Leakage
High Input Leakage
I
IL
I
IH
-10
-10
+10
+10
uAuAVIN = 0
V
O8 Type Buffer
Low Output Level
V
OL
0.4
V
I
5V
I
3.3V
High Output Level
V
OH
2.4
I
V
= 5V
I
= 3.3V
Output Leakage
I
OL
-10
+10
uA
V
(Note 1)
= V
IN
CC
= 8 mA @ VCC =
OL
= 4 mA @ VCC =
OL
= -4 mA @ V
OH
= -2 mA @ V
OH
= 0 to V
IN
CC
CC
CC
SMSC DS – USB97C100Page 51Rev. 01/03/2001
PARAMETERSYMBOLMINTYPMAXUNITSCOMMENTS
I/O8 Type Buffer
Low Output Level
High Output Level
Output Leakage
I/O16 Type Buffer
Low Output Level
High Output Level
Output Leakage
I/O24 Type Buffer
Low Output Level
High Output Level
Output Leakage
IO-U
Note 2
Supply Current Unconfigured
Note: MCU running on Ring
Oscillator
Supply Current Active
Supply Current Standby
V
V
I
OL
V
V
I
OL
V
V
I
OL
I
CCINIT
I
CC
I
CSBY
OL
OH
OL
OH
OL
OH
2.4
-10
2.4
-10
2.4
-10
13
27
21
42
14
130
0.4
+10
0.4
+10
0.4
+10
17
35
32
63
60
350
V
= 8 mA @ VCC =
I
OL
5V
I
= 4 mA @ VCC =
OL
3.3V
V
I
= -4 mA @ V
OH
= 5V
I
= -2 mA @ V
OH
= 3.3V
V
= 0 to V
µA
V
IN
(Note 1)
I
= 16 mA @ V
OL
CC
= 5V
I
= 8 mA @ VCC =
OL
3.3V
V
I
= -8 mA @ V
OH
= 5V
I
= -4 mA @ V
OH
= 3.3V
µA
V
= 0 to V
IN
CC
(Note 1)
V
I
= 24 mA @ V
OL
= 5V
I
= 12 mA @ V
OL
= 3.3V
V
I
= -12 mA @ V
OH
= 5V
I
= -6 mA @ V
OH
= 3.3V
µA
V
= 0 to V
IN
CC
(Note 1)
= 3.3V
mA
mA
@ V
@ V
CC
= 5.0V
CC
mAmA@ VCC = 3.3V
= 5.0V
@ V
CC
@ V
@ V
= 3.3V
CC
= 5.0V
CC
µA
µ
A
CC
CC
CC
CC
CC
CC
CC
CC
CC
Note 1: Output leakage is measured with the current pins in high impedance.
Note 2: See Appendix A for USB DC electrical characteristics.
FIGURE 4 - DIFFERENTIAL INPUT SENSITIVITY OVER ENTIRE COMMON MODE RANGE
Table 86 - DC Electrical Characteristics
CONDITIONS
PARAMETERSYMBOL
(NOTE 1, 2)MINTYPMAXUNIT
Supply Voltage:
Powered (Host or Hub)
VBUS2.973.63V
Port
Supply Current:
FunctionICCNote 4100mA
Un-configured Function
ICCINITNote 5100uA
(in)
Suspend DeviceICCS200uA
Leakage Current:
Hi-Z State Data Line
Leakage
ILO0 V < VIN < 3.3
V
-1010uA
Input Levels:
Differential Input
Sensitivity
Differential Common
Mode Range
Single Ended Receiver
VDI|(D+) - (D-)|, and
0.2V
FIGURE 4
VCMIncludes VDI
0.82.5V
range
VSE0.82.0V
Threshold
Output Levels:
Static Output LowVOL
RL of 1.5 KΩ to
0.3 (3)V
3.6 V
Static Output HighVOH
RL of 15 KΩ to
2.83.6 (3)V
GND
SMSC DS – USB97C100Page 53Rev. 01/03/2001
CONDITIONS
PARAMETERSYMBOL
(NOTE 1, 2)MINTYPMAXUNIT
Capacitance
Transceiver CapacitanceCINPin to GND20pF
Terminals
Bus Pull-up Resistor on
RPU
(1.5 KΩ +/- 5%)
1.4251.575
Root Port
Bus Pull-down Resistor on
RPD
(15 KΩ +/- 5%)
14.2515.75
Downstream Port
Note 1: All voltages are measured from the local ground potential, unless otherwise specified.
Note 2: All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.
Note 3: This is relative to VUSBIN.
Note 4: This is dependent on block configuration set by software.
Note 5: When the internal ring oscillator and waiting for first setup packet.
USB AC PARAMETERS
kΩ
kΩ
C
L
Differential
Data Lines
C
L
Full Speed: 4 to 20ns at CL= 50pF
FIGURE 5 - DATA SIGNAL RISE AND FALL TIME
Driver End
of Cable
VSS
Receiver
End of Cable
VSS
Rise Time
90%
10%
t
R
Round Trip
Cable Delay
80ns (max)
50% Point of
Initial Swing
One Way
Cable
Delay
30ns
(max)
Data Line
Crossover
Point
FIGURE 6 - CABLE DELAY
90%
Fall Time
t
F
10%
T
PERIOD
Crossover
Differential
Points
Data Lines
Consecutive
Transitions
PERIOD
+ T
xJR1
Transitions
N * T
Paired
PERIOD
+ T
xJR2
N * T
FIGURE 7 - DIFFERENTIAL DATA JITTER
SMSC DS – USB97C100Page 54Rev. 01/03/2001
T
PERIOD
Differential
Data Lines
T
Differential
Data Lines
Crossover
Crossover
Point
Diff. Data to
SE0 Skew
N * T
PERIOD
+ T
DEOP
Point Extended
Source EOP Width: T
Receiver EOP Wi dth: T
FIGURE 8 - DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH
PERIOD
EOPT
EOPR1
, T
EOPR2
T
JR
Consecutive
Transitions
N * T
PERIOD
+ T
JR1
Transitions
N * T
Paired
PERIOD
+ T
JR2
T
JR1
T
JR2
FIGURE 9 - RECEIVER JITTER TOLERANCE
Table 87 - Full Speed (12Mbps) Source Electrical Characteristics
CONDITIONS
PARAMETERSYM
(NOTE 1, 2, 3)MINTYPMAXUNIT
DRIVER CHARACTERISTICS:
Transition Time:
Rise Time
Fall Time
TR
TF
Note 4,5 and FIGURE 5
CL = 50 pF
CL = 50 pF
4
4
20
20
ns
ns
Rise/Fall Time MatchingTRFM(TR/TF)90110%
Output Signal Crossover
VCRS1.32.0V
Voltage
Drive Output ResistanceZDRVSteady State Drive2843
DATA SOURCE TIMING:
Full Speed Data RateTDRATEAve. Bit Rate
11.9512.03
Mbs
(12 Mb/s +/- 0.25%) Note
8
Frame IntervalTFRAME1.0 ms +/- 0.05%0.999
1.0005ms
5
Clock PeriodTPERIO
8086ns
D
Source Differential Driver
Jitter
To next Transition
TDJ1
TDJ2
Note 6, 7 and
FIGURE 7
-3.5
-4.0
3.5
4.0
ns
ns
For Paired Transitions
Source EOP WidthTEOPTNote 7 and
160175ns
FIGURE 8
Ω
SMSC DS – USB97C100Page 55Rev. 01/03/2001
PARAMETERSYM
Differential to EOP
transition Skew
Receiver Data Jitter
Tolerance
CONDITIONS
(NOTE 1, 2, 3)MINTYPMAXUNIT
TDEOPNote 7 and
FIGURE 8
Note 7 and FIGURE 9
-25ns
To next Transition
For Paired Transitions
Differential Data Jitter
To next Transition
For Paired Transitions
EOP Width at receiver
TJR1
TJR2
JR1
T
X
T
JR2
X
-18.5
-9
Note 7 and FIGURE 7
-18.5
-9
Note 7 and
FIGURE 8
Must reject as EOP
Must Accept
TEOPR1
TEOPR2
40
82
CABLE IMPEDANCE AND TIMING:
Cable Impedance (Full
ZO
(45 Ω +/- 15%)
38.75
Speed)
Cable Delay (One Way)TCBLFIGURE 630ns
Note 1: All voltages are measured from the local ground potential, unless otherwise specified.
Note 2: All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.
Note 3: Full speed timings have a 1.5KΩ pull-up to 2.8 V on the D+ data line.
Note 4: Measured from 10% to 90% of the data signals.
Note 5: The rising and falling edges should be smoothly transiting (monotonic).
Note 6: Timing differences between the differential data signals.
Note 7: Measured at crossover point of differential data signals.
Note 8: These are relative to the 24 MHz crystal.
t7
AEN
18.5
9.0
18.5
9.0
51.75
ns
ns
ns
ns
ns
ns
Ω
SA[x]
t3
t2
t1
t4t6
nIOW
SD[x]
DATA VALID
t5
t8
FIGURE 10 - 8051 IO WRITE CYCLE
SMSC DS – USB97C100Page 56Rev. 01/03/2001
Table 88 – 8051 IO WRITE Cycle
NAMEDESCRIPTIONMINMAXEQUIATIONUNITS
t1
SA[x] and AEN Valid to nIOW Asserted
1064t-60ns
t2nIOW Asserted to nIOW Deasserted1506t-100ns
t3nIOW Deasserted to SA[x] Invalid22t-20ns
t4SD[x] Valid to nIOW Deasserted1506t-100ns
t5SD[x] Hold from nIOW Deasserted22t-20ns
t6nIOW Deasserted to nIOW Asserted25ns
t7nIOW Deasserted to AEN Deasserted22t-20ns
t8nIOW Deasserted to SD[x] tri-state832tns
Note:Min and Max delays shown for 8051 clk of 24 MHz, to calculate typical timing delays for other clock
frequencies use Oscillator Equations, where t=1/f
CLK
.
AEN
t8t9
t3
SA[x]
t1
t2
t10
nIOR
t4
t5
DATA VALID
SD[x]
nIOW/nIOR
t7
t6
FIGURE 11 – 8051 IO READ CYCLE
Table 89 – 8051 IO Read Timing Parameters
NAMEDESCRIPTIONMINMAXEQUIATIONUNITS
t1SA[x] and AEN Valid to nIOR Asserted1074t-60n s
t2nIOR Asserted to nIOR Deasserted1506t-100ns
t3nIOR Asserted to SA[x] Invalid32t-10ns
t4nIOR Asserted to Data Valid0ns
t5Data Hold/Float from nIOR Deasserted0ns
t6nIOR Asserted after nIOR Deasserted32t-10ns
t7nIOR Asserted after nIOW Deasserted32t-10ns
t8nIOR Asserted to AEN Valid10ns
t9Data Valid to nIOR Deassereted30ns
t10nIOR Deasserted to SD[x] tri-state32t-10ns
Note:Min and Max delays shown for 8051 clk of 24 MHz, to calculate typical timing delays for other clock
frequencies use Oscillator Equations, where t=1/f
SMSC DS – USB97C100Page 57Rev. 01/03/2001
CLK
.
t1
t2
t2
CLOCKI
FIGURE 12 - INPUT CLOCK TIMING
Table 90 - Input Clock Timing Parameters
NAMEDESCRIPTIONMINTYPMAXUNITS
t1Clock Cycle Time for 24 MHz41.67ns
t2Clock High Time/Low Time for 14.318 MHz25/16.716.7/25ns
tr, tfClock Rise Time/Fall Time (not shown)5ns
SA[19:0]
t1
AEN
t3
t15
nDACK
nMEMRD/nIOR
or
nMEMWR/nIOW
DATA
SD[7:0]
TC
t11
t4
t14
t16
t2
t7
t8
DATA VALID
t13
t12
t9
t10
FIGURE 13 - DMA TIMING (SINGLE TRANSFER MODE)
Table 91 - DMA Timing (Single Transfer Mode) Parameters
NAMEDESCRIPTIONMINTYPMAXUNITS
SA[19:0] Address Setup time to nMEMRD/nIOR or
t1
65ns
nMEMWR/nIOW
Asserted
t2nMEMRD/nIOR or nMEMWR/nIOW
100ns
Pulsewidth
t3nMEMRD/nIOR or nMEMWR/nIOW
30ns
deasserted to SA[19:0] Address valid Hold time
t4nDACK Width150ns
t7Data Setup Time to nIOR High50ns
t8Data Set Up Time to nIOW High40ns
t9Data to Float Delay from nIOR High2550ns
t10Data Hold Time from nIOW High10ns
t11nDACK Set Up to nIOW/nIOR Low22.5ns
t12nDACK Hold after nIOW/nIOR High22.5ns
t13TC Pulse Width60ns
t14AEN Set Up to nIOR/nIOW40ns
t15AEN Hold from nDACK10ns
t16nMEMRD/nIOR or nMEMWR/nIOW asserted to Data valid0ns
SMSC DS – USB97C100Page 58Rev. 01/03/2001
SA[19:0]
AEN
t3
t15
t1
t4
t2
t16
t12
t7
t8
t9
t10
DATA VALID
t13
nDACK
nMEMRD /nIOR
or
nMEMWR/ nIOW
DATA
SD[7:0]
t11
t14
DATA VALID
TC
FIGURE 14 - DMA TIMING (BURST TRANSFER MODE)
Table 92 - DMA Timing (Burst Transfer Mode) Parameters
NAMEDESCRIPTIONMINTYPMAXUNITS
t1SA[19:0] Address Setup time to
65ns
nMEMRD/nIOR or nMEMWR/nIOW
Asserted
t2
nMEMRD/nIOR or nMEMWR/nIOW
100ns
Pulsewidth
t3nMEMRD/nIOR or nMEMWR/nIOW
30ns
deasserted to SA[19:0] Address valid Hold
time
t4nDACK Width150ns
t7Data Setup Time to nIOR High50ns
t8Data Set Up Time to nIOW High40ns
t9Data to Float Delay from nIOR High2550ns
t10Data Hold Time from nIOW High25ns
t11nDACK Set Up to nIOW /nIOR Low22.5ns
t12nDACK Hold after nIOW /nIOR High22.5ns
t13TC Pulse Width60ns
t14AEN Set Up to nIOR/nIOW40ns
t15AEN Hold from nDACK10ns
t16nMEMRD/nIOR or nMEMWR/nIOW
0ns
asserted to Data valid
SMSC DS – USB97C100Page 59Rev. 01/03/2001
FALE
t9
t10t11
t3
FA]
t1t2
t10
nRD
t4
t8
t7
FD
FIGURE 15 - 8051 FLASH PROGRAM FETCH TIMING
Table 93 - 8051 Flash Program Fetch Timing Parameters
PARAMETERMINTYPMAX
t1FA Valid to nRD asserted642t-20ns
t2nRD active pulse width1053t-20ns
t3nRD deasserted to FA Invalid32t-10ns
t4nRD asserted to Data Valid0ns
t7FD data Hold from nRD
deasserted
t8nRD deasserted to FD data tri-
state
t9FALE active pulse width532t-30ns
t10FA address Valid to FALE
deasserted
t11FALE deasserted to nRD asserted21.66t-20ns
21.66t-20ns
DATA VALID
OSCILLATOR
EQUATIONUNITS
0ns
32t-10ns
Note:Min and Max delays shown for an 8051 clock of 24MHz, to calculate timing delays for other clock
frequencies use the Oscillator Equations, where T=1/Fclk.