SMSC LAN9500i, LAN9500 User Manual
LAN9500/LAN9500i
Hi-Speed USB 2.0 to 10/100
Ethernet Controller
PRODUCT FEATURES
Highlights
Sin gle Chip Hi-Speed USB 2.0 to 10/100 Ethernet
Controller
Integra ted 10/100 Ethernet MAC with Full-Duplex
Support
Integra ted 10/100 Ethernet PHY with HP Auto-MDIX
support
Integra ted USB 2.0 Hi-Speed Device Controller
Integra ted USB 2.0 Hi-Speed PHY
Impleme nts Reduced Power Operating Modes
Target Applications
Embed ded Systems
Set-Top Boxes
PVR’s
CE Devices
Ne tworked Printers
USB Po rt Replicators
Standalone USB to Ethernet Dongles
Test Instrumentation
Industrial
Key Benefits
USB De vice Controller
— Fully compliant with Hi-Speed Universal Serial Bus
Specification Revision 2.0
— Supports HS (480 Mbps) and FS (12 Mbps) modes
— Four endpoints supported
— Supports vendor specific commands
— Integrated USB 2.0 PHY
— Remote wakeup supported
Hi gh-Performance 10/100 Ethernet Controller
— Fully compliant with IEEE802.3/802.3u
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and half-duplex support
— Full- and half-duplex flow control
Datasheet
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
— TCP/UDP/IP/ICMP checksum offload support
— Flexible address filtering modes
– One 48-bit perfect address
– 64 hash-filtered multicast addresses
– Pass all multicast
– Promiscuous mode
– Inverse filtering
– Pass all incoming with status report
— Wakeup packet support
— Integrated Ethernet PHY
– Auto-negotiation
– Automatic polarity detection and correction
– HP Auto-MDIX support
– Link status change wake-up detection
— Support for 3 status LEDs
— External MII and Turbo MII support HomePNA™ and
HomePlug® PHY
Po wer and I/Os
— Various low power modes
—11 GPIOs
— Supports bus-powered and self-powered operation
— Integrated power-on reset circuit
— External 3.3v I/O supply
– Internal 1.8v core supply regulator
Misce llaneous Features
— EEPROM Controller
— IEEE 1149.1 (JTAG) Boundary Scan
— Requires single 25 MHz crystal
Software
— Windows XP/Vista Driver
— Linux Driver
— Win CE Driver
—MAC OS Driver
— EEPROM Utility
Packaging
— 56-pin QFN (8x8 mm) Lead-Free RoHS Compliant
package
Environmental
— Commercial Temperature Range (0°C to +70°C)
— Industrial Temperature Range (-40°C to +85°C)
SMSC LAN9500/LAN9500i Revision 1.7 (10-02-08)
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
ORDER NUMBER(S):
LAN9500-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO +70°C TEMP RANGE)
LAN9500i-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO +85°C TEMP RANGE)
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a mean s of illustrating typical applications. Conse quently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently da ted
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC LAN9500/LAN9500i 2 Revision 1.7 (10-02-08)
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 FIFO Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.4 Ethernet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.6 EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.7 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 3 EEPROM Controller (EPC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 EEPROM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 EEPROM Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 EEPROM Auto-Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 An Example of EEPROM Format Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 4 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Operating Conditions**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.1 SUSPEND0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.2 SUSPEND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.3 SUSPEND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.4 Operational Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.5 Customer Evaluation Board Operational Power Consumption . . . . . . . . . . . . . . . . . . . . 30
4.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5.1 Equivalent Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5.2 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5.3 Reset and Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5.4 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5.5 Turbo MII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 5 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 6 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SMSC LAN9500/LAN9500i 3 Revision 1.7 (10-02-08)
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
List of Figures
Figure 1.1 LAN9500/LAN9500i System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW). . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4.2 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4.3 nRESET Reset Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4.4 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4.1 Turbo MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 4.2 Turbo MII Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5.1 LAN9500/LAN9500i 56-QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 5.2 LAN9500/LAN9500i 56-QFN Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . 41
Revision 1.7 (10-02-08) 4 SMSC LAN9500/LAN9500i
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
List Of Tables
Table 2.1 MII Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.2 EEPROM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.3 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.4 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.5 USB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.6 Ethernet PHY Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.8 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.9 56-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2.10 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3.1 EEPROM Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3.2 Configuration Flags Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3.3 EEPROM Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3.4 Dump of EEPROM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3.5 EEPROM Example - 256 Byte EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4.1 SUSPEND0 - Supply and Current @3.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4.2 SUSPEND1 - Supply and Current @3.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4.3 SUSPEND2 - Supply and Current @3.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4.4 Operational Power Consumption - Supp ly and Current @3.3V. . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4.5 Customer Evaluation Board Operational Power Consumption - Supply and Current @3.3V . 30
Table 4.6 I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4.7 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4.8 10BASE-T Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4.9 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 4.10 n RESET Reset Pin Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4.11 EEPROM Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 4.12 Turbo MII Output Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4.13 Turbo MII Interface Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4.14 LAN9500/LAN9500i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.1 LAN9500/LAN9500i 56-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6.2 Datasheet Revision History (INTERNAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SMSC LAN9500/LAN9500i 5 Revision 1.7 (10-02-08)
DATASHEET
Chapter 1 Introduction
1.1 Block Diagram
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
USB
USB
PHY
JTAG
TAP
Controller
LAN9500/LAN9500i
1.1.1 Overview
The LAN9500/LAN9500i is a high performance Hi-Speed USB 2.0 to 10/100 Ethernet controller. With
applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators, USB
to Ethernet dongles, and test instrumentation, the LAN9500/LAN9500i is a high performance and co st
competitive USB to Ethernet connectivity solution.
The LAN9500/LAN9500i contains an integrated 10/100 Ethernet PHY, USB PHY, Hi-Speed USB 2.0
device controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with
a total of 30 KB of internal packet buffering.
USB 2.0
Device
Controller
FIFO
Controller
10/100
Ethernet
MAC
SRAM
Figure 1.1 LAN9500/LAN9500i Sy stem Diagram
Ethernet
PHY
EEPROM
Controller
Ethernet
MII: To optional
external PHY
EEPROM
The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed
standard. The LAN9500/LAN9500i implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is
compliant with the IEEE 802.3 and IEEE 802.3u standards. An external MII interface provides support
for an external Fast Ethernet PHY, HomePNA, and HomePlug functionality.
Multiple power management features are provided, including various low power modes and "Magic
Packet", "Wake On LAN", and "Link Status Change" wake events. These wake events can be
programmed to initiate a USB remote wakeup.
An internal EEPROM controller exists to load various USB configuration information and the device
MAC address. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
Revision 1.7 (10-02-08) 6 SMSC LAN9500/LAN9500i
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
1.1.2 USB
The USB portion of the LAN9500/LAN9500i integrates a Hi-Speed USB 2.0 device controller and USB
PHY.
The USB device controller contains a USB low-level protocol interpreter which implements the USB
bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with
autonomous error handling. The USB device controller is capable of operating in USB 2.0 Hi-Speed
and Full-Speed compliant modes and contains autonomous protocol handling functions such as
handling of suspend/resume/reset conditions, remote wakeup, and stall condition clearing on Setup
packets. The USB device controller also autonomously handles error conditions such as retry for CRC
and data toggle errors, and generates NYET, STALL, ACK and NACK handshake responses,
depending on the endpoint buffer status.
The LAN9500/LAN9500i implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The
Bulk-in and Bulk-out Endpoints allow for Ethernet reception and transmission respectively.
Implementation of vendor-specific commands allows for efficient statistics gathering and access to the
LAN9500/LAN9500i system control and status registers.
1.1.3 FIFO Controller
The FIFO controller uses an internal SRAM to buffer RX and TX traffic. Bulk-out packets from the USB
controller are directly stored into the TX buffer. Ethernet Frames are directly stored into the RX buffer
and become the basis for bulk-in packets.
1.1.4 Ethernet
The LAN9500/LAN9500i integrates an IEEE 802.3 PHY for twisted pair Ethernet applications and a
10/100 Ethernet Media Access Controller (MAC).
The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet
operation in either full- or half-duplex configurations and includes auto-negotiation, auto-polarity
correction, and Auto-MDIX. Minimal external components are required for the utilization of the
Integrated PHY.
Optionally, an external PHY may be used via the MII (Media Independent Interface) port, effectively
bypassing the internal PHY. This option allo ws support for HomePNA and HomePlug applications.
The Ethernet MAC/PHY supports numerous power management wakeup features, including “Magic
Packet”, “Wake on LAN”, and “Link Status Change”.
1.1.5 Power Management
The LAN9500/LAN9500i features three variations of USB suspend: SUSPEND0, SUSPEND1, and
SUSPEND2. These modes allow the application to select the ideal balance of remote wakeup
functionality and power consumption.
SUSPEND0: Supports GPIO, “Wake On LAN”, and “Magic Packet” remote wakeup events. This
suspend state reduces power by stopping the clocks of the MAC and other internal modules.
SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend
state consumes less power than SUSPEND0.
SUSPEND2: Supports only GPIO assertion for a remote wake up event. This suspend state
consumes less than 1 mA. This is the default suspend mode for the LAN9500/L AN9500i.
SMSC LAN9500/LAN9500i 7 Revision 1.7 (10-02-08)
DATASHEET
1.1.6 EEPROM Controller
The LAN9500/LAN9500i contains an EEPROM controller for connection to an external EEPROM. This
allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software
reset. The EEPROM can be configured to load USB descriptors, USB device configuration, and MAC
address.
1.1.7 General Purpose I/O
When configured for internal PHY mode, up to ele ven GPIOs are supported. All GPIOs can serve as
remote wakeup events when the LAN9500/LAN9500i is in a suspended state.
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Revision 1.7 (10-02-08) 8 SMSC LAN9500/LAN9500i
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Chapter 2 Pin Description and Configuration
RXCLK
TDI/RXD3
TMS/RXD2
TCK/RXD1
TDO/nPHY_RST
nTRST/RXD0
VDD33IO
PHY_SEL
TEST3
EEDI
EEDO/AUTOMDIX_EN
EECS
RXDV
42
41
40
39
38
37
36
35
34
33
32
31
EECLK/PWR_SEL
30
29
TXEN
RXER
CRS/GPIO3
COL/GPIO0
TXCLK
VDD33IO
TEST1
VDD18CORE
VDD33IO
VDD33IO
TXD3/GPIO7/EEP_SIZE
TXD2/GPIO6/PORT_SWAP
TXD1/GPIO5/RMT_WKP
TXD0/GPIO4/EEP_DISABLE
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
TXN
nPHY_INT
LAN9500/LAN9500i
3
4
TXP
VDD33A
SMSC
56 PIN QFN
(TOP VIEW)
VSS
5
6
7
RXP
RXN
VDD33A
8
9
10
11
12
13
EXRES
VDD33A
USBDM
VDD18PLL
TEST2
USBDP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
NC
nSPD_LED/GPIO10
nLNKA_LED/GPIO9
nFDX_LED/GPIO8
VDD33IO
nRESET
MDIO/GPIO1
MDC/GPIO2
VDD18CORE
VBUS_DET
XO
XI
VDD18USBPLL
USBRBIAS
VDD33A
NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa
NOTE: Exposed pad (VSS) on bottom of package must be connected to gr ound
Figure 2.1 LAN9500/LAN9500i 56-QF N Pin Assignments (TOP VIEW)
SMSC LAN9500/LAN9500i 9 Revision 1.7 (10-02-08)
DATASHEET
NUM PINS NAME SYMBOL
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Ta b le 2.1 MII Interface Pins
BUFFER
TYPE DESCRIPTION
Receive Error
1
1
1
1
1
1
(External
PHY Mode)
Transmit
Enable
(External
PHY Mode)
Receive Data
Valid
(External
PHY Mode)
Receive
Clock
(External
PHY Mode)
Carrier Sense
(External
PHY Mode)
General
Purpose I/O 3
(Internal PHY
Mode Only)
MII Collision
Detect
(External
PHY Mode)
General
Purpose I/O 0
(Internal PHY
Mode Only)
RXER IS
(PD)
TXEN O8
(PD)
RXDV IS
(PD)
RXCLK IS
(PD)
CRS IS
(PD)
GPIO3 IS/O8/
OD8
(PU)
COL IS
(PD)
GPIO0 IS/O8/
OD8
(PU)
Receive Error: In external PHY mode, the signal
on this pin is input from the external PHY and
indicates a receive error in the packet. In internal
PHY mode, this pin is not used.
Transmit Enable: In external PHY mode, this pin
output to the external PHY and indicates valid
data on TXD[3:0]. In internal PHY mode, this pin
is not used.
Receive Data Valid: In external PHY mode, the
signal on this pin is input from the external PHY
and indicates valid data on RXD[3:0]. In internal
PHY mode, this pin is not used.
Receive Clock: In external PHY mode, this pin
is the receiver clock input from the external PHY.
In internal PHY mode, this pin is not used.
Carrier Sense: In external PHY mode, the signal
on this pin is input from the external PHY and
indicates a network carrier.
General Purpose I/O 3
MII Collision Detect: In external PHY mode, the
signal on this pin is input from the external PHY
and indicates a collision event.
General Purpose I/O 0
Management
Data
(External
PHY Mode)
1
General
Purpose I/O 1
(Internal PHY
Mode Only)
Management
Clock
(External
PHY Mode)
1
General
Purpose I/O 2
(Internal PHY
Mode Only)
Revision 1.7 (10-02-08) 10 SMSC LAN9500/LAN9500i
MDIO IS/O8
(PD)
GPIO1 IS/O8/
OD8
(PU)
MDC O8
(PD)
GPIO2 IS/O8/
OD8
(PU)
Management Data: In external PHY mode, this
pin provides the management data to/from the
external PHY.
General Purpose I/O 1
Management Clock: In external PHY mode, this
pin outputs the management clock to the external
PHY.
General Purpose I/O 2
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
T able 2.1 MII Interface Pins (continued)
NUM PINS NAME SYMBOL
BUFFER
TYPE DESCRIPTION
Transmit Data
3
(External
PHY Mode)
General
Purpose I/O 7
(Internal PHY
Mode Only)
EEPROM
Size
1
Configuration
Strap
Transmit Data
2
(External
PHY Mode)
TXD3 O8
(PU)
GPIO7 IS/O8/
OD8
(PU)
EEP_SIZE IS
(PU)
TXD2 O8
(PD)
Transmit Data 3: In external PHY mode, this pin
functions as the transmit data 3 output to the
external PHY.
General Purpose I/O 7
EEPROM SIZE: The EEP_SIZE strap selects the
size of the EEPROM attached to the
LAN9500/LAN9500i.
0 = 128 byte EEPROM is attached and a total of
seven address bits are used.
1 = 256/512 byte EEPROM is attached and a
total of nine address bits are used.
Note: A 3-wire style 1K/2K/4K EEPROM that
is organized for 128 x 8-bit or 256/512 x
8-bit operation must be used.
See Note 2.1 for more information on
configuration straps.
Transmit Data 2: In external PHY mode, this pin
functions as the transmit data 2 output to the
external PHY.
General
Purpose I/O 6
(Internal PHY
Mode Only)
1
USB Port
Swap
Configuration
Strap
GPIO6 IS/O8/
PORT_SWAP
OD8
(PU)
IS
(PD)
General Purpose I/O 6
USB Port Swap Configuration Strap: Swaps
the mapping of USBDP and USBDM.
0 = USBDP maps to the USB D+ line and
USBDM maps to the USB D- line.
1 = USBDP maps to the USB D- line. USBDM
maps to the USB D+ line.
See Note 2.1 for more information on
configuration straps.
SMSC LAN9500/LAN9500i 11 Revision 1.7 (10-02-08)
DATASHEET
T able 2.1 MII Interface Pins (continued)
NUM PINS NAME SYMBOL
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
BUFFER
TYPE DESCRIPTION
Transmit Data
1
(External
PHY Mode)
General
Purpose I/O 5
(Internal PHY
1
1
Mode Only)
Remote
Wakeup
Configuration
Strap
Transmit Data
0
(External
PHY Mode)
General
Purpose I/O 4
(Internal PHY
Mode Only)
EEPROM
Disable
Configuration
Strap
TXD1 O8
(PD)
GPIO5 IS/O8/
OD8
(PU)
RMT_WKP
TXD0 O8
GPIO4 IS/O8/
EEP_DISABLE IS
IS
(PD)
(PD)
OD8
(PU)
(PD)
Transmit Data 1: In external PHY mode, this pin
functions as the transmit data 1 output to the
external PHY.
General Purpose I/O 5
Remote Wakeup Configuration Strap: This
strap configures the default descriptor values to
support remote wakeup.
0 = Remote wakeup is not supported.
1 = Remote wakeup is supported.
See Note 2.1 for more information on
configuration straps.
Transmit Data 0: In external PHY mode, this pin
functions as the transmit data 0 output to the
external PHY.
General Purpose I/O 4
EEPROM Disable Configuration Strap: This
strap disables the autoloading of the EEPROM
contents. The assertion of this strap does not
prevent register access to the EEPROM.
0 = EEPROM is recognized if present.
1 = EEPROM is not recognized even if it is
present.
See Note 2.1 for more information on
configuration straps.
Transmit
1
Revision 1.7 (10-02-08) 12 SMSC LAN9500/LAN9500i
Clock
(External
PHY Mode)
Note 2.1 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that func tion as configuration
straps must be augmented with an external resistor when connected to a load.
TXCLK IS
(PU)
Transmit Clock: In external PHY mode, this pin
is the transmitter clock input from the external
PHY. In internal PHY mode, th is pin is not used.
DATASHEET
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Table 2.2 EEPROM Pins
NUM PINS NAME SYMBOL
1
1
1
1
EEPROM
Data In
EEPROM
Data Out
Auto-MDIX
Enable
Configuration
Strap
EEPROM
Chip Select
EEPROM
Clock
Power Select
Configuration
Strap
EEDI IS
EEDO O8
AUTOMDIX_EN
EECS O8 EEPROM chip select: This pin drives the chip
EECLK O8
PWR_SEL
BUFFER
TYPE DESCRIPTION
EEPROM Data In: This pin is driven by the
(PD)
(PU)
IS
(PU)
(PD)
IS
(PD)
EEDO output of the external EEPROM.
EEPROM Data Out: This pin drives the EEDI
input of the external EEPROM.
Auto-MDIX Enable Configuration Strap:
Determines the default Auto-MDIX setting.
0 = Auto-MDIX is disabled.
1 = Auto-MDIX is enabled.
See Note 2.2 for more information on
configuration straps.
select output of the external EEPROM.
EEPROM Clock: This pin drives the EEPROM
clock of the external EEPROM.
Power Select Configuration Strap: Determines
the default power setting when no EEPROM is
present.
0 = The LAN9500/LAN9500i is bus powered.
1 = The LAN9500/LAN9500i is self powered.
Note 2.2 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that func tion as configuration
straps must be augmented with an external resistor when connected to a load.
NUM PINS NAME SYMBOL
JTAG Test
Port Reset
(Internal PHY
1
1
Mode)
Receive Data
0
(External
PHY Mode)
JTAG Test
Data Out
(Internal PHY
Mode)
PHY Reset
(External
PHY Mode)
nTRST IS
RXD0 IS
TDO O8 JTAG Data Output: In internal PHY mode, this
nPHY_RST O8 PHY Reset (Active-Low): In external PHY
See Note 2.2 for more information on
configuration straps.
Table 2.3 JTAG Pins
BUFFER
TYPE DESCRIPTION
JTAG Test Port Reset (Active-Low): In internal
(PU)
(PD)
PHY mode, this pin functions as the JTAG test
port reset input.
Receive Data 0: In external PHY mode, this pin
functions as the receive data 0 input from the
external PHY.
pin functions as the JTAG data output.
mode, this pin functions as the PHY reset output.
SMSC LAN9500/LAN9500i 13 Revision 1.7 (10-02-08)
DATASHEET
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