Skyworth 8M48A Schematic

SERVICE MANUAL

8M48A CHASSIS

Design and specifications are subject to change without prior notice.

(Only Referrence)

SIZE:A5

Description:

MODEL.

JOB NO.

Engineering Dept:

Artwork By:

Checked By:

Approved By:

SERVICE MANUAL 8M48A

Brand Name:

SKYWORTH

Date:

2012-02-28

Content--------------------------------------------------------------2

11-17

18

19-20

21-29

30-47

48-51

52-59

LED 8M26A

TOSHIBA CODE

Component

PAL SECAM / BG DK PAL / I NTSC / M

VHF LOW K1~S6 VHF HIGH S7~S36 VHF S37~DS57

44.25MHz ~ 140.25MHz

147.25MHz ~ 423.25MHz

431.25MHz ~ 863.25MHz

Asia\Europe

40

55

80

For 22” LED

For 24” LED

For 32” LED

(24 inches is 4 ohm)

(24 inches is 3W)

80

(26inches is 8 ohm)

40

3

2

1

4.2 50

0.5 12000

40

3

Standard

20

40

NO

YES

8 6

46

NO

Spanish

4 2

4

0 40 7 0

0 40

40 85

-Y 0 5 0

30000

D

C

B

P12

SPEAKER

1

EARPHONE

TU2

TUNER

1

U29

U42

FLASH

2

M13S2561616A-5TG2K ESMT

U7 U1

TPA1517NE

SDA

SCL

P7

S/PDIP

2

3

4

LVDS OUT

U10

MST6E181VS

BH3544F-E2 TPA3113D2/

U19

PS331TQFP64G

P13

2P3P1P

P6

AV OUT

YPbPr AV2 INHDMI 1 VGA

PC

AUDIO

HDMI 2

3

4

MEDIA 2

5

AV1 IN

CON11

C

B

A A

D

CON10

CON6 MEDIA 1

5

ʳ

Typical Application Circuit ʳ

AP1117

1A LOW DROPOUT POSITIVE ADJUSTABLE OR

FIXED-MODE REGULATOR

5V

C1 10uF

V

in

V

out

GND

Tab is V

out

( 5V/3.3V fixed output ) ʳ

ʳ

Connection Diagramʳ

ʳ ʳ

3 PIN SOT223 3 PIN TO252 / TO263

C2

22uF

3.3V/1A

5V

Tab is V

V

out

V

out

Adj

C1

10uF

in

( 5V/2.5V ADJ output ) ʳ

Note:

(1VV 

REFo

R1

121

R2

121

R R

V

o

2.5V/1A

C2

ȍ

22uF

ȍ

2

)

1

(

Top View )

3

2

1

Tab is V

out

3 PIN SOT89

3

2

1

Tab is V

out

V

in

V

out

Adj ( GND)

V

in

V

out

Adj ( GND)

(

Top View )

3

2

1

Tab is V

out

3 PIN TO220

3

2

1

Tab is V

out

V

out

Adj ( GND)

in

V

in

V

out

Adj ( GND)

ʳ

AP1117 Rev. 3 2 of 11 SEPTEMBER 2006

www.diodes.com © Diodes Incorporated

ʳ

Block Diagramʳ

AP1117

1A LOW DROPOUT POSITIVE ADJUSTABLE OR

FIXED-MODE REGULATOR

3

V

in

Thermal

Shutdown

Pin Descriptionsʳ

2

V

out

+

-

1.25V

CURRENT

LIMIT

+

-

+

1

GND

(FIXED)

1

Adj

NAME I/O PIN # FUNCTION

Adj (GND) I 1

V

out

V

in

O 2

I 3

A resistor divider from this pin to the V

(Ground only for Fixed-Mode).

The output of the regulator. A minimum of 10uF capacitor (0.15ȍ ESR  20ȍ)

must be connected from this pin to ground to insure stability.

The input pin of regulator. Typically a large storage capacitor (0.15ȍ ESR  20ȍ)

is connected from this pin to ground to insure that the input voltage does not sag below the minimum dropout voltage during the load transient response. This pin

must always be 1.3V higher than V

pin and ground sets the output voltage

out

in order for the device to regulate properly.

out

ʳ

AP1117 Rev. 3 3 of 11 SEPTEMBER 2006

www.diodes.com © Diodes Incorporated

A1semi 1A Fixed and Adjustable Low

A1

Electronics Ltd Dropout Linear Regulator(LDO)

Pin Configurations

L Package

(SOT-223)

V

OUT

T Package

(TO-220) (TO-252)

AS1117

U Package

(SOT-89)

3

INPUT

2

OUTPUT

1

ADJ/GND

V

OUT

3

2

1

R Package

3

INPUT

OUTPUT

ADJ/GND

INPUT

V

OUT

S Package

(TO-263)

V

OUT

3

2

1

3

2

1

INPUT

OUTPUT

ADJ/GND

INPUT

OUTPUT

ADJ/GND

Figure 2. Pin Configurations of AS111 7

V

OUT

2

1

OUTPUT

ADJ/GND

AI SEMI ELECTRONICS LTD. 2

http://www.a1semi.com

A1semi 1A Fixed and Adjustable Low

A1

Functional Block Diagram

Electronics Ltd Dropout Linear Regulator(LDO)

Thermal

Shutdown

AS1117

INPUT

Out

+

-

OUTPUT

GND (Fixed Output)

Figure 3. Functional Block Diagram of AS1117

ADJ (Adjustable Output)

A1 SEMI ELECTRONICS LTD. 3

http://www.a1semi.com

AOZ1051PI

EZBuck™ 3 A Synchronous Buck Regulator

General Description

The AOZ1051PI is a high efficiency, easy to use, 3 A synchronous buck regulator. The AOZ1051PI works from

4.5 V to 18 V input voltage range, and provides up to 3 A of continuous output current with an output voltage adjustable down to 0.8 V.

The AOZ1051PI comes in an exposed pad SO-8 package and is rated over a -40 °C to +85 °C operating ambient temperature range.

Features

z 4.5 V to 18 V operating input voltage range

z Synchronous Buck: 70 m internal high-side switch

and 40 m internal low-side switch (at 12 V)

z Up to 95 % efficiency

z External soft start

z Output voltage adjustable to 0.8 V

z 3 A continuous output current

z 500 kHz PWM operation

z Cycle-by-cycle current limit

z Pre-bias start-up

z Short-circuit protection

z Thermal shutdown

z Exposed pad SO-8 package

Applications

z Point of load DC/DC converters

z LCD TV

z Set top boxes

z DVD and Blu-ray players/recorders

z Cable modems

Typical Application

VIN

C1 10μF

VIN

EN

AOZ1051PI

COMP

R

C

Figure 1. 3.3 V 3 A Synchronous Buck Regulator, Fs = 500 kHz

Rev. 1.0 June 2011 www.aosmd.com Page 1 of 14

AGND

SS

PGND

C

SS

L1 4.7μH

LX

R1

FB

R2

VOUT

C2, C3 22μF

AOZ1051PI

A

Ordering Information

Part Number Ambient Temperature Range Package Environmental

AOZ1051PI -40 °C to +85 °C EPAD SO-8 Green Product

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration

PGND

VIN

GND

FB

1

2

3

4

PAD (LX)

8

NC

7

SS

6

EN

5

COMP

Exposed Pad SO-8

(Top View)

Pin Description

Pin Number Pin Name Pin Function

1 PGND Power ground. PGND needs to be electrically connected to AGND.

2 VIN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,

the device starts up.

3 AGND Analog ground. AGND is the reference point for controller section. AGND needs to be

electrically connected to PGND.

4 FB Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider

between the output and AGND.

5 COMP External loop compensation pin. Connect a RC network between COMP and AGND to

compensate the control loop.

6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the

device. If on/off control in not needed, connect EN to VIN and do not leave it open.

7 SS Soft-start pin. 5 μA current charging current.

8 NC No Connect Pin. Pin 8 is not internally connected. Connect this pin externally to LX and

use it for better thermal performance.

Exposed pad LX Switching node. LX is the drain of the internal PFET. LX is used as the thermal pad of the

power stage.

Rev. 1.0 June 2011 www.aosmd.com Page 2 of 14

Block Diagram

AOZ1051PI

VIN

EN

SS

FB

COMP

Reference

& Bias

0.8V

UVLO

& POR

+

EAmp

–

Softstart

5μA

SS

5V LDO

Regulator

Internal

+5V

+

PWM

–

Comp

+

500kHz

Oscillator

OTP

ILimit

PWM

Control

Logic

Level

Shifter

FET

Driver

AGND

+

ISen

–

Q1

+

LX

Q2

PGND

Absolute Maximum Ratings

Exceeding the Absolute Maximum Ratings may damage the device.

Parameter Rating

Supply Voltage (VIN) 20 V

LX to AGND -0.7 V to V

LX to AGND (20 ns) -5 V to 22 V

EN to AGND -0.3 V to V

FB, SS, COMP to AGND -0.3 V to 6.0 V

PGND to AGND -0.3 V to +0.3 V

Junction Temperature (T

Storage Temperature (T

ESD Rating

Note:

1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5 k

Rev. 1.0 June 2011 www.aosmd.com Page 3 of 14

(1)

) +150 °C

J

) -65 °C to +150 °C

S

 in series with 100 pF.

+0.3 V

IN

+0.3 V

IN

2.0 kV

Recommended Operating Conditions

The device is not guaranteed to operate beyond the Maximum Recommended Operating Conditions.

Parameter Rating

Supply Voltage (VIN) 4.5 V to 18 V

Output Voltage Range 0.8 V to 0.85 • V

Ambient Temperature (TA) -40 °C to +85 °C

Package Thermal Resistance Exposed Pad SO-8 (4

Note:

2. The value of FR-4 board with 2 oz. Copper, in a still air environment with T

= 25 °C. The value in any given application depends on the

A

user’s specific board design.

4

is measured with the device mounted on a 1-in

JA

(2)

)

50 °C/W

IN

2

SY8086

Package Code

High Efficiency 1.4MHz, 1A

Synchronous Step Down Regulator

Preliminary Specification

General Description

The SY8086 is a high-efficiency 1.4MHz synchronous step-down DC-DC regulator ICs capable of delivering up to 1A output current. The SY8086 operates over a wide input voltage range from 2.5V to 5.5V and integrate main switch and synchronous switch with very low R

Low output voltage ripple and s mall external indu ctor and capacitor sizes are achieved with 1.4MHz switching frequency. This along with small SOT-23 footprint prov ides small PCB area a pplication.

to minimize the conduction loss.

DS(ON)

Ordering Information

SY8086

Temperature Range: -40

ƶƶƶƶ(ƶƶ

ƶƶ)ƶƶƶƶ

ƶƶƶƶ(ƶƶ

ƶƶ)ƶƶƶƶ

ƶƶƶƶ

Temperature Code

Optional Spec Code

e

C to 85eC

Ordering Number Package type Note

SY8086AAC SOT23-5 1A

Featur es

•

Low R 250m

2.5-5.5V input voltage range

•

1.4MHz switching frequency minimizes the external components

•

Internal softstart limits the inrush current

•

RoHS Compliant and Halogen Free

•

Compact package: SOT23 5 pin

for inter n al switche s (t op/ bottom):

DS(ON)

Ω

/200m

Ω

Applications

•

Portable Navigation Device

•

Smart phone

•

USB Dongle

•

Set Top Box

•

Media Player

Typical Applications

V

IN

C

IN

EN

IN

LX

FB

GND

Figure 1. Schematic Diagram Figure2 Efficiency vs Load Current

SY8086 Rev. 0.11 Silergy Corp. Confidential- Prepared for Customer Use Only 1

L

R

C1(opt.)

1

2

V

OUT

C

OUT

Pinout (top view)

SY8086

EN

GND

LX

Top mark:

Pin Name Pin Number Pin Description

EN 1 Enable control. Pull high to turn on. Do not float.

GND 2 Ground pin

LX 3 Inductor pin. Connect this pin to the switching node of inductor

IN 4 Input pin. Decouple this pin to GND pin with at least 1uF ceramic cap

FB 5 Output Feedback Pin. Connect this pin to the center p oint of the output

BE

xyz

(Device code: BE, x=year code, y=wee k code , z = lot number code )

resistor divider (as shown in Figure 1) to progra m th e output voltage: Vout=0.6*(1+R

Absolute Maximu m Ratings

Supply Input Voltage --------------------------------------------------------------------------------------------- 6.0V Enable, FB Voltage------------------------------------------------------------------------------------------------ V Power Dissipation, P Package Thermal Resistance (Note 2)

SOT23-5,

SOT23-5, Junction Temperature Range ------------------------------------------------------------------------------------ 150°C Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C

Storage Temperature Range ------------------------------------------------------------------------------------ESD Susceptibility (Note 2)

HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ----------------------------------------------------------------------------------------------200V

D

@ TA = 25°C SOT-23-5 -------------------------------------------------------------- 0.4W

θ

JA

------------------------------------------------------------------------------------------ 250°C/W

θ

JC

-------------------------------------------------------------------------------------------130°C/W

1

2

3

SOT23-5

1/R2

(Note 1)

5

FB

4

IN

)

IN

+ 0.6V

-

65°C to 150°C

Recommended Operating Conditions

Supply Input Voltage -------------------------------------------------------------------------------------------- 2.5V to 5.5V Junction Temperature Range ---------------------------------------------------------------------------------- -40°C to 125°C

Ambient Temperature Range ----------------------------------------------------------------------------------

(Note 3)

-

40°C to 85°C

SY8086 Rev. 0.11 Silergy Corp. Confidential- Prepared for Customer Use Only 2

IC Block Diagram

U10(LCDTV CONTROLLER WITH VIDEO ECODE)MST6E181VS

PIN DIAGRAM (MST6E181VS)

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

NC

LDQS0

LDQM0

A_DDR1_BA0

DVDD_DDR_1.2V

A_DDR1_DQ8 A_DDR1_DQ9

AVDDIO_2.5V

A_DDR1_DQ10 A_DDR1_DQ11 A_DDR1_DQ12 A_DDR1_DQ13

A_DDR1_DQ14

AVDDIO_2.5V

A_DDR1_DQ15

A_DDR1_MCLKZ

AVDDIO_2.5V

A_DDR1_MCLK

A_DDR1_CKE A_DDR1_A12 A_DDR1_A11

A_DDR1_A9

AVDDIO_2.5V A_DDR1_A8 A_DDR1_A7 A_DDR1_A6 A_DDR1_A5 A_DDR1_A4

AVDD_NODIE DVDD_NODIE

GND_EFUSE

GPIO11/SAR0

GPIO12/SAR1

GPIO13/SAR2

GPIO10/PMGPIO

GPIO6/PM1/TX

GPIO8/PM5/RX

GPIO9/PM6/CS1

AVDDIO_2.5V

GPIO7/PM4/POWER_ON

163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217

AVDD_PLL

UDQM0

UDQS0

A_MVREF

NC

VDDC

DDCR_DA

VDDP_3

DDCR_CK

TESTPIN

DM_P0

DP_P0

DM_P1

DP_P1

SPI_CK

SPI_DI

SPI_DO SPI_CZ

DDCA_CK DDCA_DA

E-pad

AVDDIO_2.5V

A_DDR1_DQ4

A_DDR1_DQ7

A_DDR1_DQ6

A_DDR1_DQ5

AVDDIO_2.5V

A_DDR1_DQ3

A_DDR1_DQ2

A_DDR1_DQ1

A_DDR1_DQ0

AVDDIO_2.5V

A_DDR1_CAS

A_DDR1_RAS

A_DDR1_WEZ

A_DDR1_BA1

A_DDR1_A0

A_DDR1_A1

A_DDR1_A2

A_DDR1_A3

A_DDR1_A10

NC

VDDC

VDDP_2

GPIO21/PWM1

GPIO20/PWM0

GPIO77/I2S_OUT_MUTE/PWM3/LVSYNC

MST6E181VS

128

127

126

125

124

123

122

121

120

119

118

117

116

115

VDDC

AVDD_LPLL

R_ODD7/RXO0-

R_ODD5/RXO1-

AVDD2P5_MOD

GPIO75/I2S_IN_SD/PWM5/TX3/LDE

GPIO74/I2S_IN_WS/PWM4/RX3/LCK

GPIO76/I2S_IN_BCK/PWM2/LHSYNC

R_ODD3/RXO2-

R_ODD1/RXOC-

R_ODD6/RXO0+

R_ODD4/RXO1+

R_ODD2/RXO2+

114

113

112

111

110

G_ODD3/RXE0-

G_ODD7/RXO3-

G_ODD5/RXO4-

G_ODD6/RXO3+

G_ODD4/RXO4+

R_ODD0/RXOC+

109

G_ODD2/RXE0+

AVDD2P5_MOD

108

G_ODD1/RXE1-

107

G_ODD0/RXE1+

106

B_ODD7/RXE2-

105

B_ODD6/RXE2+

104

B_ODD5/RXEC-

103

B_ODD4/RXEC+

102

B_ODD3/RXE3-

101

B_ODD2/RXE3+

100

B_ODD1/RXE4-

99

B_ODD0/RXE4+

98

NC

97

GPIO49

96

GPIO47

95

GPIO45

94

GPIO38

93

GPIO37

92

GPIO36

91

GPIO32/I2S_OUT_BCK

90

GPIO30/I2S_OUT_MCK

89

GPIO28

88

VDDP_1

87

VDDC

86

GPIO27/SPDIF_OUT

85

GPIO26/SPDIF_IN/RX1/PWM3

84

GPIO25/TUNER_SDA

83

GPIO24/TUNER_SCL

82

GPIO23/I2S_OUT_SD/TX2

81

GPIO22/I2S_OUT_WS/RX2

80

TAGC

79

SIFM

78

SIFP

77

AVDD25_PGA

76

VIFP

75

VIFM

74

AVSS_PGA

73

AVDD25_REF

72

AVDD_DMPLL

71

XTAL_OUT

70

XTAL_IN

69

NC

68

NC

67

NC

66

LINEOUT_R0

65

LINEOUT_L0

64

LINEOUT_R3

63

LINEOUT_L3

62

AVDD_AU33

61

LINEIN_R5

60

LINEIN_L5

59

LINEIN_R4

58

LINEIN_L4

57

LINEIN_R3

56

LINEIN_L3

55

U?

IRIN

2

1

9876543

10

RX1N

AVDD_DVI_3.3V

RX0P

RX0N

RXCP

RXCN

HOTPLUGA

RESET

CEC

HSYNC0

VDDC

NC

SOGIN0

BIN0P

2726252423222120191817161514131211

GIN0M

GIN0P

VSYNC0

RIN0P

SOGIN1

BIN1P

AVDD2P5_ADC

AVDD1P2

GIN1P

GIN1M

CVBS2

CVBS3

CVBS4

AVDD3P3_ADC

RIN1P

CVBS0

CVBS1

4443424140393837363534333231302928

CVBS_OUT1

VCOM

45

LINEIN_L1

LINEIN_R0

LINEIN_L0

VRP

VRM

LINEIN_R1

AVDD_AU25

VAG

545352515049484746

NCNCNCNCNC

ARC

DDCDA_CK

RX2P

RX2N

DDCDA_DA

RX1P

-13-

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MST6M181VG/MST6M182VG

2012010018

LCD Television System-on-Chip

Preliminary Pin Diagram/Description and Mechanical Dimensions Version 0.2

Doc. No.:

PIN DIAGRAM (MST6M181VG/MST6M182VG)

1 2 3 4 5 6 7 8 9 10111213141516

A RXCKP RXCKN NC NC HWRESET GPIO7 GPIO6 GND USB1_DM USB0_DP USB0_DM A

B RX1N RX 0P RX0 N NC NC NC NC IRIN GPIO8 SAR0 PWM0 USB1_DP DDCR_CK SCZ SDO B

C RX2N RX2P RX1P NC NC NC NC GPIO9 SAR2 SA R1 PW M1 GND DDCR_DA SCK SDI C

D DDCD_CK ARC

ESOGIN0BIN0PHSYNC0

DDCD_DAHOTPLUG

A

NC CEC B YPASS

MStar Confidential

F RIN0P GIN0M GIN0P VSYNC0 GND

G GND GN D GND

for Skyworth

H SOGIN1 BIN1P

J RIN1P GIN1M GIN1P AVDD_33

K CV BS2 CVBS1 N C

Internal Use Only

L CVBS0 VCOM AUVAG AUVRP

M CVBSOU T AUL0 AUL3 GND

AVDD_AL

IVE

AVDD_D

MPLL

AVDD_ME

MPLL

AVDD_MODAVDD_ RE

AVDD_M

OD

AVDD_AU

33

AVDD_126DVDD_D

AVDD_25

AVDD_AU

VDDC VDDC GND GND GND

25

VDDC VDDC GND GND GND MVREF

F

VDDP VD DC VDDC FLK2 GCLK6 RLV2P L

VDDP

AVDD_D

DR

AVDD_D

DDCA_CK DDC A_DA GPIO10 GND LEDON HCON DPM D

DR

GND GND GND

AVDD_ DDRAVDD_D

DR

AVDD_DDRSCAN_BL

GND SAR3 OPT_N GCLK4 G

K

SCAN_BL

K1

GSP/

VST

GSP_R/

GCLK1

VGH_OD

D

RLVCKM RLVCKP RLV2M M

GOE/

POL

GCLK2

WPWM OPT_P F

SOE FLK3 H

GSC/

GCLK 3

GCLK 5

FLK J

VGH_EVE

N

E

K

N AUR0 AUL1 AUR3 AUOUTL1

PAUR1 AUL2AUOUTR1 GND PGA_COM GND GND

RAUR2AUOUTL0 XOUT GND GND VIFM GND

T AUOUTR0 XIN TAGC GND VIFP GND

1 2 3 4 5 6 7 8 9 10111213141516

Doc. No.:

AVDD_PG

Copyright

GND NC NC RLV1M RLV1P RLV0M RLV0P RLV3M RLV3 P N

A

I2S_OUT

SPDIFI LLV5M LLV4M LLV3P LLV2M LLV1M RLV4M RLV4 P P

_SD

I2S_OUT

_MCK

_BCK

SPDIFO LLV3M LLVCKM LLV0M LLV0P T

_WS

- 1 - 8/29/2011

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LLV5P LLV4P LLV CKP LLV2P LLV1P RLV5 M RLV5 P R

MST6M181VG/MST6M182VG

2012010018

LCD Television System-on-Chip

Preliminary Pin Diagram/Description and Mechanical Dimensions Version 0.2

Doc. No.:

PIN DESCRIPTION

Analog Interface

Pin Name Pin Type Function Pin

HSYNC0 Schmitt Trigger Input

w/ 5V-tolerant

VSYNC0 Schmitt Trigger Input

w/ 5V-tolerant

BIN0P Analog Input Analog Blue Input from Channel 0 E3

SOGIN0 Analog Input Sync On Green Input from Channel 0 E2

GIN0P Analog Input Analog Green Input from Channel 0 F3

GIN0M Analog Input Reference Ground for Analog Green Input from Channel 0 F2

RIN0P Analog Input Analog Red Input from Channel 0 F1

MStar Confidential

BIN1P Analog Input Analog Blue Input from Channel 1 H3

SOGIN1 Analog Input Sync On Green Input from Channel 1 H2

GIN1P Analog Input Analog Green Input from Channel 1 J3

GIN1M Analog Input Reference Ground for Analog Green Input from Channel 1 J2

RIN1P Analog Input Analog Red Input from Channel 1 J1

HSYNC / Composite Sync for VGA Input from channel 0 E4

VSYNC for VGA Input from channel 0 F4

for Skyworth

Analog Video Input/Output Interface

Pin Name Pin Type Function Pin

CVBS2 Analog Input CVBS (Composite) Video Input Channel 2 K1

CVBS1 Analog Input CVBS (Composite) Video Input Channel 1 K2

Internal Use Only

CVBS0 Analog Input CVBS (Composite) Video Input Channel 0 L1

VCOM Analog Input CVBS Input Reference Ground L2

CVBSOUT Analog Output CVBS (Composite) Video Output Channel M1

Analog Audio Input/Output Interface

Pin Name Pin Type Function Pin

I2S_OUT_WS I/O w/ 5V-tolerant Word Select Output; 4mA driving strength /

Universal Asynchronous Receiver 2 (UART2_RX)

I2S_OUT_SD I/O w/ 5V-tolerant Audio Serial Data Output; 4mA driving strength /

Universal Asynchronous Transmitter 2 (UART2_TX)

SPDIFI Input w/ 5V-tolerant S/PDIF Audio Input /

Pulse Width Modulation Output; 4mA driving strength (PWM3)

SPDIFO Output S/PDIF Audio Output; 4mA driving strength T9

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T8

P8

P9

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MST6M181VG/MST6M182VG

2012010018

LCD Television System-on-Chip

Preliminary Pin Diagram/Description and Mechanical Dimensions Version 0.2

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Pin Name Pin Type Function Pin

I2S_OUT_MCK Output w/ 5V-tolerant Audio Master Clock Output R8

I2S_OUT_BCK Output w/ 5V-tolerant Audio Bit Clock Output R9

AUL0 Analog Input Audio Line Input Left Channel 0 M2

AUR0 Analog Input Audio Line Input Right Channel 0 N1

AUL1 Analog Input Audio Line Input Left Channel 1 N2

AUR1 Analog Input Audio Line Input Right Channel 1 P1

AUL2 Analog Input Audio Line Input Left Channel 2 P2

AUR2 Analog Input Audio Line Input Right Channel 2 R1

AUL3 Analog Input Audio Line Input Left Channel 3 M3

AUR3 Analog Input Audio Line Input Right Channel 3 N3

AUVRP Analog Output Positive Reference Voltage for Audio ADC L4

MStar Confidential

AUVAG Analog Output Reference Voltage for Audio Common Mode L3

AUOUTL1 Analog Output Main Audio Output Left Channel 1 N4

AUOUTR1 Analog Output Main Audio Output Right Channel 1 P3

AUOUTL0 Analog Output Main Audio Output Left Channel 0 R2

AUOUTR0 Analog Output Main Audio Output Right Channel 0 T2

for Skyworth

Mini-LVDS Interface

Pin Name Pin Type Function Pin

LLV5M Output Mini-LVDS L-Link Channel 5 Negative Data Output P10

LLV5P Output Mini-LVDS L-Link Channel 5 Positive Data Output R10

Internal Use Only

LLV4M Output Mini-LVDS L-Link Channel 4 Negative Data Output P11

LLV4P Output Mini-LVDS L-Link Channel 4 Positive Data Output R11

LLV3M Output Mini-LVDS L-Link Channel 3 Negative Data Output T11

LLV3P Output Mini-LVDS L-Link Channel 3 Positive Data Output P12

LLV2M Output Mini-LVDS L-Link Channel 2 Negative Data Output P13

LLV2P Output Mini-LVDS L-Link Channel 2 Positive Data Output R13

LLV1M Output Mini-LVDS L-Link Channel 1 Negative Data Output P14

LLV1P Output Mini-LVDS L-Link Channel 1 Positive Data Output R14

LLV0M Output Mini-LVDS L-Link Channel 0 Negative Data Output T14

LLV0P Output Mini-LVDS L-Link Channel 0 Positive Data Output T15

LLVCKM Output Mini-LVDS L-Link Negative Clock Output T12

LLVCKP Output Mini-LVDS L-Link Positive Clock Output R12

RLV5M Output Mini-LVDS R-Link Channel 5 Negative Data Output R15

RLV5P Output Mini-LVDS R-Link Channel 5 Positive Data Output R16

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