Silicon Labs Proven 8051 User Manual

Proven 8051 Microcontroller

Technology, Brilliantly Updated

By: Tom David, Principal Design Engineer, Silicon Labs

Introduction

The proven 8051 core received a welcome second wind when its architecture lost patent protection

in 1998. A plethora of new 8051 MCUs entered the market at that time, some subscribing to the

original architecture and others modifying it to varying degrees.

The Silicon Labs 8051 architecture is of the second variety. It maintains code compatibility with the

original core while modernizing and “RISC-ifying” the architecture, resulting in a massive

performance boost. This is a tradition that’s never been more obvious than in the Silicon Labs

EFM8™ 8-bit MCU family.

Speeding Execution with a Pipelined Architecture and

MAC

The original Intel 8051 core took 12 cycles to execute 1 instruction; thus, at 12 MHz, it ran at 1million

instructions per second (1 MIP). In contrast, a 100 MHz Silicon Labs 8051 core will run at 100 MIPS or

100 times faster than the classic 8051 at a frequency that is only about 8x the classic 8051’s

frequency.

Silicon Labs implemented its version of the 8051 core as a 3-stage pipe Von-Neuman machine. The

simplicity of this 3-stage pipe combined with the straightforward instruction decode logic of an 8-bit

machine enables this device to run at 100 MHz in a 0.35-micron process. The 32 Byte register file

with four regions for ease of context switching was preserved since code compatibility with the

classic 8051 was of utmost importance. Figure 1 shows a classical three-stage pipeline structure as

implemented on the Silicon Labs 8051 core.

Figure 1. Example of a Typical Pipeline

An 8051 MCU may never be the right device if your design calls for high-speed, higher-order

arithmetic. However, some of Silicon Labs’ high-speed 8051 MCUs also implement a 16-bit MAC with

a 40-bit accumulator. This technique enables single-cycle 16-bit MAC operations or multiplications

to be performed. Certainly, it still takes a few cycles to load and unload the data.

Since the MAC is pipelined, the data can be moved into the input registers while the MAC is

operating on the previous data. Figure 2 shows a diagram of the MAC as implemented on the

C8051F120 MCU.

Figure 2. MAC Implementation

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