Silicon Labs EFM32PG22 User manual

EFM32PG22 Gecko MCU Family Data
Sheet

The EFM32PG22 Gecko family of microcontrollers is part of the
Series 2 Gecko portfolio. EFM32PG22 Gecko MCUs are ideal for
enabling energy-friendly embedded applications.

The highly efficient solution contains a 76.8 MHz Cortex-M33 with rich analog and com­munication peripherals to provide an industry-leading, energy efficient MCU for consum­er and industrial applications.

Gecko applications include:

• Personal Hygiene devices

• Appliances and whitegoods

• Industrial Automation

• Consumer electronics

Core / Memory

ARM Cortex
with DSP, FPU and TrustZone

TM

M33 processor

ETM Debug Interface RAM Memory

Flash Program

Memory

LDMA

Controller

Clock Management

HF Crystal

Oscillator

Fast Startup

RC Oscillator

LF Crystal

Oscillator

RC Oscillator

RC Oscillator

Precision LF

Ultra LF RC

Oscillator

KEY FEATURES

• 32-bit ARM® Cortex®-M33 core with 76.8
MHz maximum operating frequency

• Up to 512 kB of flash and 32 kB of RAM

• Low energy operation

• 26 uA/MHz (EM0)

• 1.10 uA sleep (EM2)

• Secure Boot with Root of Trust and
Secure Loader (RTSL)

• 16-bit ADC with 16-channel scan

Energy Management

HF

Voltage

Regulator

Power-On

Reset

DC-DC

Converter

Brown-Out

Detector

32-bit bus

Peripheral Reflex System

Security

AES-128, AES-256,

SHA-1, SHA-2,

ECC

Secure Boot RTSL

Secure Debug

True Random Number

Generator

Lowest power mode with peripheral operational:

Serial Interfaces I/O Ports

USART

PDM

EUART

2

I

External

Interrupts

General

Purpose I/O

Pin Reset

C

Pin Wakeup

Timers and Triggers

Timer/Counter

Low Energy Timer Watchdog Timer

Real Time

Capture Counter

EM3—StopEM2—Deep SleepEM1—SleepEM0—Active

Protocol Timer

Back-Up Real
Time Counter

Analog I/F

ADC

Temperature

Sensor

EM4—Shutoff

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1. Feature List

The EFM32PG22 highlighted features are listed below.

• Low Power MCU

•

High Performance 32-bit 76.8 MHz ARM Cortex®-M33 with
DSP instruction and floating-point unit for efficient signal
processing

• Up to 512 kB flash program memory

• Up to 32 kB RAM data memory

• Low System Energy Consumption

• 26 μA/MHz in Active Mode (EM0) at 38.4 MHz

• 1.10 μA EM2 DeepSleep current (8 kB RAM retention and
RTC running from LFRCO)

• 0.95 μA EM3 DeepSleep current (8 kB RAM retention and
RTC running from ULFRCO)

• 0.17 μA EM4 current

• Security Features

• Secure Boot with Root of Trust and Secure Loader (RTSL)

• Hardware Cryptographic Acceleration for AES128/256,
SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA,
and ECDH

• True Random Number Generator (TRNG) compliant with
NIST SP800-90 and AIS-31

•

ARM® TrustZone

• Secure Debug with lock/unlock

• Packages

• QFN40 5 mm × 5 mm × 0.85 mm

• QFN32 4 mm × 4 mm × 0.85 mm

®

EFM32PG22 Gecko MCU Family Data Sheet

Feature List

• Wide selection of MCU peripherals

• Analog to Digital Converter (ADC)

• 12-bit @ 1 Msps

• 16-bit @ 76.9 ksps

• Up to 26 General Purpose I/O pins with output state reten­tion and asynchronous interrupts

• 8 Channel DMA Controller

• 12 Channel Peripheral Reflex System (PRS)

• 4 × 16-bit Timer/Counter with 3 Compare/Capture/PWM
channels

• 1 × 32-bit Timer/Counter with 3 Compare/Capture/PWM
channels

• 32-bit Real Time Counter

• 24-bit Low Energy Timer for waveform generation

• 1 × Watchdog Timer

• 2 × Universal Synchronous/Asynchronous Receiver/Trans­mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)

• 1 × Enhanced Universal Asynchronous Receiver/Transmit­ter (EUART)

•

2 × I2C interface with SMBus support

• Digital microphone interface (PDM)

• Die temperature sensor with +/-1.5 °C accuracy after single­point calibration

• Wide Operating Range

• 1.71 V to 3.8 V single power supply

• -40 °C to 125 °C

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2. Ordering Information

EFM32PG22 Gecko MCU Family Data Sheet

Ordering Information

Table 2.1. Ordering Information

Flash

Ordering Code Max CPU Speed

EFM32PG22C200F128IM32-C 76.8 MHz 128 32 18 QFN32 -40 to 125 °C

EFM32PG22C200F128IM40-C 76.8 MHz 128 32 26 QFN40 -40 to 125 °C

EFM32PG22C200F256IM32-C 76.8 MHz 256 32 18 QFN32 -40 to 125 °C

EFM32PG22C200F256IM40-C 76.8 MHz 256 32 26 QFN40 -40 to 125 °C

EFM32PG22C200F512IM32-C 76.8 MHz 512 32 18 QFN32 -40 to 125 °C

EFM32PG22C200F512IM40-C 76.8 MHz 512 32 26 QFN40 -40 to 125 °C

EFM32PG22C200F64IM32-C 76.8 MHz 64 32 18 QFN32 -40 to 125 °C

EFM32PG22C200F64IM40-C 76.8 MHz 64 32 26 QFN40 -40 to 125 °C

(kB)

RAM

(kB) GPIO Package Temp Range

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Table of Contents

1. Feature List ................................2

2. Ordering Information ............................3

3. System Overview ..............................7

3.1 Introduction ...............................7

3.2 General Purpose Input/Output (GPIO) ......................7

3.3 Clocking ................................8

3.3.1 Clock Management Unit (CMU) .......................8

3.3.2 Internal and External Oscillators.......................8

3.4 Counters/Timers and PWM ..........................8

3.4.1 Timer/Counter (TIMER) .........................8

3.4.2 Low Energy Timer (LETIMER) .......................8

3.4.3 Real Time Clock with Capture (RTCC) ....................8

3.4.4 Back-Up Real Time Counter (BURTC) ....................8

3.4.5 Watchdog Timer (WDOG) .........................8

3.5 Communications and Other Digital Peripherals ...................9

3.5.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ..........9

3.5.2 Enhanced Universal Asynchronous Receiver/Transmitter (EUART) ...........9

3.5.3 Inter-Integrated Circuit Interface (I2C) .....................9

3.5.4 Peripheral Reflex System (PRS) ......................9

3.5.5 Pulse Density Modulation (PDM) Interface ...................9

3.6 Security Features .............................9

3.6.1 Secure Boot with Root of Trust and Secure Loader (RTSL) .............9

3.6.2 Cryptographic Accelerator.........................10

3.6.3 True Random Number Generator ......................10

3.6.4 Secure Debug with Lock/Unlock.......................10

3.7 Analog.................................10

3.7.1 Analog to Digital Converter (IADC) ......................10

3.8 Power .................................11

3.8.1 Energy Management Unit (EMU) ......................11

3.8.2 Voltage Scaling ............................11

3.8.3 DC-DC Converter ...........................11

3.8.4 Power Domains ............................11

3.9 Reset Management Unit (RMU) ........................12

3.10 Core and Memory ............................12

3.10.1 Processor Core ............................12

3.10.2 Memory System Controller (MSC) .....................12

3.10.3 Linked Direct Memory Access Controller (LDMA) ................12

3.11 Memory Map ..............................13

3.12 Configuration Summary ..........................14

4. Electrical Specifications ..........................15

4.1 Electrical Characteristics ..........................15

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4.2 Absolute Maximum Ratings..........................16

4.3 General Operating Conditions .........................17

4.4 DC-DC Converter .............................18

4.4.1 DC-DC Operating Limits .........................20

4.5 Thermal Characteristics ...........................21

4.6 Current Consumption ............................22

4.6.1 MCU current consumption using DC-DC at 3.0 V input ...............22

4.6.2 MCU current consumption at 3.0 V ......................24

4.6.3 MCU current consumption at 1.8 V ......................26

4.7 Flash Characteristics ............................28

4.8 Wake Up, Entry, and Exit times ........................29

4.9 Oscillators ...............................30

4.9.1 High Frequency Crystal Oscillator ......................30

4.9.2 Low Frequency Crystal Oscillator ......................31

4.9.3 High Frequency RC Oscillator (HFRCO) ....................32

4.9.4 Fast Start_Up RC Oscillator (FSRCO).....................33

4.9.5 Low Frequency RC Oscillator (LFRCO) ....................34

4.9.6 Ultra Low Frequency RC Oscillator ......................34

4.10 GPIO Pins (3V GPIO pins) .........................35

4.11 Analog to Digital Converter (IADC) .......................37

4.12 Temperature Sense ............................39

4.13 Brown Out Detectors ...........................40

4.13.1 DVDD BOD .............................40

4.13.2 LE DVDD BOD ............................40

4.13.3 AVDD and IOVDD BODs ........................41

4.14 PDM Timing Specifications .........................42

4.14.1 Pulse Density Modulator (PDM), Common DBUS ................42

4.15 USART SPI Master Timing .........................43

4.15.1 SPI Master Timing, Voltage Scaling = VSCALE2.................44

4.15.2 SPI Master Timing, Voltage Scaling = VSCALE1.................44

4.16 USART SPI Slave Timing ..........................45

4.16.1 SPI Slave Timing, Voltage Scaling = VSCALE2 .................45

4.16.2 SPI Slave Timing, Voltage Scaling = VSCALE1 .................46

4.17 I2C Electrical Specifications .........................47

4.17.1 I2C Standard-mode (Sm) ........................47

4.17.2 I2C Fast-mode (Fm) ..........................48

4.17.3 I2C Fast-mode Plus (Fm+) ........................49

4.18 Typical Performance Curves .........................49

4.18.1 Supply Current ............................50

4.18.2 DC-DC Converter ...........................51

4.18.3 IADC ...............................52

5. Typical Connections ...........................53

5.1 Power .................................53

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5.2 Other Connections.............................54

6. Pin Definitions ..............................55

6.1 QFN32 Device Pinout ...........................55

6.2 QFN40 Device Pinout ...........................57

6.3 Alternate Function Table...........................59

6.4 Analog Peripheral Connectivity ........................59

6.5 Digital Peripheral Connectivity .........................60

7. QFN32 Package Specifications........................ 63

7.1 QFN32 Package Dimensions .........................63

7.2 QFN32 PCB Land Pattern ..........................65

7.3 QFN32 Package Marking ..........................67

8. QFN40 Package Specifications........................ 68

8.1 QFN40 Package Dimensions .........................68

8.2 QFN40 PCB Land Pattern ..........................70

8.3 QFN40 Package Marking ..........................71

9. Revision History .............................72

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3. System Overview

3.1 Introduction

The EFM32PG22 Gecko product family is well suited for any battery operated application as well as other systems requiring high per­formance and low energy consumption. This section gives a short introduction to the MCU system. The detailed functional description
can be found in the EFM32PG22 Reference Manual.

A block diagram of the EFM32PG22 family is shown in Figure 3.1 Detailed EFM32PG22 Block Diagram on page 7. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult

Ordering Information.

RESETn

Debug Signals

(shared w/GPIO)

IOVDD

AVDD

DVDD

VREGVDD

VREGSW

DECOUPLE

LFXTAL_I

LFXTAL_O

HFXTAL_I

HFXTAL_O

Reset Management Unit,

Brown Out and POR

Serial Wire and ETM

Debug / Programming

with Debug Challenge I/F

Energy Management

Voltage
Monitor

bypass

DC-DC

Converter

Voltage

Regulator

Core and Memory

ARM Cortex-M33 Core

with Floating Point Unit

Up to 512 KB ISP Flash

Program Memory

32 KB RAM

Trust Zone

LDMA Controller

Watchdog

Timer

Clock Management

ULFRCO

FSRCO

LFRCO

LFXO

HFRCO

HFXO

Port I/O Configuration

IOVDD

Digital Peripherals

USART

EUART

I2C

LETIMER

TIMER

RTCC

A

A

H

P

B

B

PDM

TRNG

CRYPTOACC

CRC

DBUS

Port

Mappers

Port A

Drivers

Port B

Drivers

Port C

Drivers

Port D

Drivers

PAn

PBn

PCn

PDn

Analog Peripherals

Internal

Reference

12-16-bit

ADC

Temperature

Sensor

VDD

Input Mux

ABUS Multiplexers

Figure 3.1. Detailed EFM32PG22 Block Diagram

3.2 General Purpose Input/Output (GPIO)

EFM32PG22 has up to 26 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or
input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher­als. The GPIO subsystem supports asynchronous external pin interrupts.

All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be
used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon
which internal peripherals could once again drive those pads.

A few GPIOs also have EM4 wake functionality. These pins are listed in the Alternate Function Table.

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3.3 Clocking

3.3.1 Clock Management Unit (CMU)

The Clock Management Unit controls oscillators and clocks in the EFM32PG22. Individual enabling and disabling of clocks to all periph­eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.

3.3.2 Internal and External Oscillators

The EFM32PG22 supports two crystal oscillators and fully integrates four RC oscillators, listed below.

• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer­ence for the MCU. The HFXO can also support an external clock source such as a TCXO for applications that require an extremely
accurate clock frequency over temperature.

• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.

• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 76.8 MHz.

• An integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz

• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation without an external crystal. Precision mode
enables periodic recalibration against the 38.4 MHz HFXO crystal to improve accuracy to +/- 500 ppm.

• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con­sumption in low energy modes.

3.4 Counters/Timers and PWM

3.4.1 Timer/Counter (TIMER)

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each
channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In
compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER
supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the
compare registers. In addition some timers offer dead-time insertion.

See 3.12 Configuration Summary for information on the feature set of each timer.

3.4.2 Low Energy Timer (LETIMER)

The unique LETIMER is a 24-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave­forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to
start counting on compare matches from other peripherals such as the Real Time Clock.

3.4.3 Real Time Clock with Capture (RTCC)

The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of
the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.

3.4.4 Back-Up Real Time Counter (BURTC)

The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC
can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined inver­vals.

3.4.5 Watchdog Timer (WDOG)

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by the Peripheral Reflex System (PRS).

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3.5 Communications and Other Digital Peripherals

3.5.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup­porting:

• ISO7816 SmartCards

• IrDA

•

I2S

3.5.2 Enhanced Universal Asynchronous Receiver/Transmitter (EUART)

The Enhanced Universal Asynchronous Receiver/Transmitter supports full duplex asynchronous UART communication with hardware
flow control, RS-485 and IrDA support. In EM0 and EM1 the EUART provides a high-speed, buffered communication interface.

When routed to GPIO ports A or B, the EUART may also be used in a low-energy mode and operate in EM2. A 32.768 kHz clock
source allows full duplex UART communication up to 9600 baud.

3.5.3 Inter-Integrated Circuit Interface (I2C)

The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The

interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans­fers. Automatic recognition of slave addresses is provided in active and low energy modes. Note that not all instances of I2C are avalia-

ble in all energy modes.

3.5.4 Peripheral Reflex System (PRS)

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph­erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)
can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving pow­er.

3.5.5 Pulse Density Modulation (PDM) Interface

The PDM module provides a serial interface and decimation filter for Pulse Density Modulation (PDM) microphones, isolated Sigma­delta ADCs, digital sensors and other PDM or sigma delta bit stream peripherals. A programmable Cascaded Integrator Comb (CIC)
filter is used to decimate the incoming bit streams. PDM supports stereo or mono input data and DMA transfer.

3.6 Security Features

The following security features are available on the EFM32PG22:

• Secure Boot with Root of Trust and Secure Loader (RTSL)

• Cryptographic Accelerator

• True Random Number Generator (TRNG)

• Secure Debug with Lock/Unlock

3.6.1 Secure Boot with Root of Trust and Secure Loader (RTSL)

The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).

It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed.

More information on this feature can be found in the Application Note AN1218: Series 2 Secure Boot with RTSL.

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3.6.2 Cryptographic Accelerator

The Cryptographic Accelerator is an autonomous hardware accelerator which supports AES encryption and decryption with
128/192/256-bit keys, Elliptic Curve Cryptography (ECC) to support public key operations and hashes.

Supported block cipher modes of operation for AES include:

• ECB (Electronic Code Book)

• CTR (Counter Mode)

• CBC (Cipher Block Chaining)

• CFB (Cipher Feedback)

• GCM (Galois Counter Mode)

• CBC-MAC (Cipher Block Chaining Message Authentication Code)

• GMAC (Galois Message Authentication Code)

• CCM (Counter with CBC-MAC)

The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and
Technology) recommended curves including P-192 and P-256 for ECDH(Elliptic Curve Diffie-Hellman) key derivation and ECDSA (El­liptic Curve Digital Signature Algorithm) sign and verify operations.

Supported hashes include SHA-1, SHA2/224, and SHA-2/256.

This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.

3.6.3 True Random Number Generator

The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal
energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online
health tests required for NIST SP800-90C.

The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.

3.6.4 Secure Debug with Lock/Unlock

For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.

In addition, the EFM32PG22 also provides a secure debug unlock function that allows authenticated access based on public key cryp­tography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive end­user data.

More information on this feature can be found in the Application Note AN1190.

3.7 Analog

3.7.1 Analog to Digital Converter (IADC)

The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. It has a resolution of 12 bits
at 1 Msps and 16 bits at up to 76.9 ksps. Hardware oversampling reduces system-level noise over multiple front-end samples. The
IADC includes integrated voltage reference options. Inputs are selectable from a wide range of sources, including pins configurable as
either single-ended or differential.

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3.8 Power

The EFM32PG22 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci­tor.

The EFM32PG22 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.

3.8.1 Energy Management Unit (EMU)

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to implement system-wide voltage
scaling and turn off the power to unused RAM blocks to optimize the energy consumption in the target application. The DC-DC regula­tor operation is tightly integrated with the EMU.

3.8.2 Voltage Scaling

The EFM32PG22 supports supply voltage scaling for the LDO powering DECOUPLE, with independent selections for EM0 / EM1 and
EM2 / EM3. Voltage scaling helps to optimize the energy efficiency of the system by operating at lower voltages when possible. The
default EM0 / EM1 voltage scaling level is VSCALE2, which allows the core to operate in active mode at full speed. The intermediate
level, VSCALE1, allows operation in EM0 and EM1 at up to 40 MHz. The lowest level, VSCALE0, can be used to conserve power in
EM2 and EM3. The EMU will automatically switch the target voltage scaling level when transitioning between energy modes.

3.8.3 DC-DC Converter

The DC-DC buck converter covers a wide range of load currents, provides high efficiency in energy modes EM0, EM1, EM2 and EM3,
and can supply up to 60 mA for device operation. An on-chip supply-monitor signals when the supply voltage is low to allow bypass of
the regulator via programmable software interrupt. It employs soft switching at boot and DCDC regulating-to-bypass transitions to limit
the max supply slew-rate and mitigate inrush current.

3.8.4 Power Domains

The EFM32PG22 has three peripheral power domains for operation in EM2 and EM3, as well as the ability to selectively retain configu­rations for EM0/EM1 peripherals. A small set of peripherals always remain powered on in EM2 and EM3, including all peripherals which
are available in EM4. If all of the peripherals in PD0B or PD0C are configured as unused, that power domain will be powered off in EM2
or EM3, reducing the overall current consumption of the device. Likewise, if the application can tolerate the setup time to re-configure
used EM0/EM1 peripherals on wake, register retention for these peripherals can be disabled to further reduce the EM2 or EM3 current.

Table 3.1. Peripheral Power Subdomains

Always available in EM2/EM3 Power Domain PD0B Power Domain PD0C

RTCC LETIMER0 LFRCO (Precision Mode)

LFRCO (Non-precision mode)

1

LFXO

BURTC

ULFRCO

1

1

1

IADC0

I2C0

WDOG0

EUART0

FSRCO PRS

DEBUG

Note:

1. Peripheral also available in EM4.

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3.9 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the EFM32PG22. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

3.10 Core and Memory

3.10.1 Processor Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz

• ARM TrustZone security technology

• Embedded Trace Macrocell (ETM) for real-time trace and debug

• Up to 512 kB flash program memory

• Up to 32 kB RAM data memory

• Configuration and event handling of all modules

• 2-pin Serial-Wire debug interface

3.10.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. In addition to the main flash array where Program code is normally written the MSC also provides an
Information block where additional information such as special user information or flash-lock bits are stored. There is also a read-only
page in the information block containing system and device calibration data. Read and write operations are supported in energy modes
EM0 Active and EM1 Sleep.

3.10.3 Linked Direct Memory Access Controller (LDMA)

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so­phisticated operations to be implemented.

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3.11 Memory Map

The EFM32PG22 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

Figure 3.2. EFM32PG22 Memory Map — Core Peripherals and Code Space

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EFM32PG22 Gecko MCU Family Data Sheet

System Overview

3.12 Configuration Summary

The features of the EFM32PG22 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.

Table 3.2. Configuration Summary

Module Lowest Energy Mode Configuration

I2C0

I2C1 EM1

IADC0 EM2

LETIMER0

PDM EM1 2-channel

TIMER0 EM1 32-bit, 3-channels, +DTI

TIMER1 EM1 16-bit, 3-channels, +DTI

TIMER2 EM1 16-bit, 3-channels, +DTI

TIMER3 EM1 16-bit, 3-channels, +DTI

EM2

EM2

1

1

TIMER4 EM1 16-bit, 3-channels, +DTI

EUART0 EM1 - Full high-speed operation

EM21 - Low-energy operation, 9600 Baud

USART0 EM1 +IrDA, +I2S, +SmartCard

USART1 EM1 +IrDA, +I2S, +SmartCard

Note:

1. EM2 and EM3 operation is only supported for digital peripheral I/O on Port A and Port B. All GPIO ports support digital peripheral

operation in EM0 and EM1.

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EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

4. Electrical Specifications

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on TA=25 °C and all supplies at 3.0 V, by production test and/or technology characterization.

• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.

Power Supply Pin Dependencies

Due to on-chip circuitry (e.g., diodes), some EFM32 power supply pins have a dependent relationship with one or more other power
supply pins. These internal relationships between the external voltages applied to the various EFM32 supply pins are defined below.
Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD & DVDD

• In systems using the DCDC converter, DVDD (the buck converter output) should be connected to the recommended L
C

, and should not be driven by an off-chip regulator.

DCDC

• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD=DVDD)

• DVDD ≥ DECOUPLE

• AVDD, IOVDD: No dependency with each other or any other supply pin

DCDC

and

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EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

4.2 Absolute Maximum Ratings

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia­bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter Symbol Test Condition Min Typ Max Unit

Storage temperature range T

Voltage on any supply pin

1

Junction temperature T

Voltage ramp rate on any
supply pin

Voltage on HFXO pins V

DC voltage on any GPIO pin V

DC voltage on RESETn pin

2

Total current into VDD power
lines

Total current into VSS
ground lines

Current per I/O pin I

Current for all I/O pins I

STG

V

DDMAX

JMAX

V

DDRAMPMAX

HFXOPIN

DIGPIN

V

RESETn

I

VDDMAX

I

VSSMAX

IOMAX

IOALLMAX

-50 — +150 °C

-0.3 — 3.8 V

-I grade — — +125 °C

— — 1.0 V / µs

-0.3 — 1.4 V

-0.3 — V

IOVDD

+

V

0.3

-0.3 — 3.8 V

Source — — 200 mA

Sink — — 200 mA

Sink — — 50 mA

Source — — 50 mA

Sink — — 200 mA

Source — — 200 mA

Note:

1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica­tions for more details.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at
DVDD.

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EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

4.3 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Operating ambient tempera­ture range

T

A

-I temperature grade

1

-40 — +125 ° C

DVDD supply voltage V

AVDD supply voltage V

IOVDDx operating supply
voltage (All IOVDD pins)

VREGVDD operating supply
voltage

DECOUPLE output capaci-

4

tor

HCLK and SYSCLK frequen-cyf

PCLK frequency f

EM01 Group A clock fre­quency

DVDD

AVDD

V

IOVDDx

V

VREGVDD

C

DECOUPLE

HCLK

PCLK

f

EM01GRPACLK

EM0/1 1.71 3.0 3.8 V

EM2/3/4

2

1.71 3.0 3.8 V

1.71 3.0 3.8 V

1.71 3.0 3.8 V

DC-DC in regulation

3

2.2 3.0 3.8 V

DC-DC in bypass 60 mA load 1.8 3.0 3.8 V

DC-DC not in use. DVDD exter-

1.71 3.0 3.8 V

nally shorted to VREGVDD

1.0 µF ± 10% X8L capacitor used

1.0 — 2.75 µF

for performance characterization.

VSCALE2, MODE = WS1 — — 76.8 MHz

VSCALE2, MODE = WS0 — — 40 MHz

VSCALE2 — — 50 MHz

VSCALE1 — — 40 MHz

VSCALE2 — — 76.8 MHz

VSCALE1 — — 40 MHz

EM01 Group B clock fre­quency

f

EM01GRPBCLK

VSCALE2 — — 76.8 MHz

VSCALE1 — — 40 MHz

Note:

1. The device may operate continuously at the maximum allowable ambient TA rating as long as the absolute maximum T

JMAX

exceeded. For an application with significant power dissipation, the allowable TA may be lower than the maximum TA rating. TA =
T

- (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for

JMAX

T

and THETAJA.

JMAX

2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.

3. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica­tions for more details.

4. Murata GCM21BL81C105KA58L used for performance characterization. Actual capacitor values can be significantly de-rated
from their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The
minimum capacitance counting all error sources should be no less than 0.6 µF.

is not

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4.4 DC-DC Converter

EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

Test conditions: L
V

= 1.8 V, IPKVAL in EM0/1 modes is set to 150 mA, and in EM2/3 modes is set to 90 mA, unless otherwise indicated.

OUT

= 2.2 µH (Samsung CIG22H2R2MNE), C

DCDC

= 4.7 µF (Samsung CL10B475KQ8NQNC), V

DCDC

VREGVDD

= 3.0 V,

Table 4.3. DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range at
VREGVDD pin

1

V

VREGVDD

DCDC in regulation, I
mA, EM0/EM1 mode

DCDC in regulation, I

LOAD

LOAD

= 60

= 5

2.2 3.0 3.8* V

1.8 3.0 3.8* V

mA, EM0/EM1 or EM2/EM3 mode

Bypass mode 1.8 3.0 3.8 V

Regulated output voltage V

OUT

Regulation DC accuracy ACC

DC

V

VREGVDD

≥ 2.2 V, Steady state in

— 1.8 — V

-2.5 — 3.3 %

EM0/EM1 mode or EM2/EM3
mode

Regulation total accuracy ACC

TOT

With mode transitions between

-5 — 7 %

EM0/EM1 and EM2/EM3 modes

Steady-state output ripple V

DC line regulation V

R

REG

I

= 20 mA in EM0/EM1 mode — 14.3 — mVpp

LOAD

I

= 60 mA in EM0/EM1

LOAD

mode, V

VREGVDD

≥ 2.2 V

— 5.5 — mV/V

DC load regulation I

REG

Load current between 100 µA and
60 mA in EM0/EM1 mode

Efficiency EFF Load current between 100 µA and

60 mA in EM0/EM1 mode, or be­tween 10 µA and 5 mA in
EM2/EM3 mode

Output load current I

LOAD

EM0/EM1 mode, DCDC in regula­tion

EM2/EM3 mode, DCDC in regula­tion

Bypass mode — — 60 mA

Nominal output capacitor C

DCDC

4.7 µF ± 10% X7R capacitor used
for performance characterization

Nominal inductor L

Nominal input capacitor C

Resistance in bypass mode R

DCDC

IN

BYP

± 20% tolerance — 2.2 — µH

Bypass switch from VREGVDD to
DVDD, V

VREGVDD

= 1.8 V

Powertrain PFET switch from
VREGVDD to VREGSW,
V

VREGVDD

= 1.8 V

— 0.27 — mV/mA

— 91 — %

— — 60 mA

— — 5 mA

4.7 — 10 µF

2

C

DCDC

— — µF

— 1.75 3 Ω

— 0.86 1.5 Ω

Supply monitor threshold

V

CMP_RNG

Programmable in 0.1 V steps 2.0 — 2.3 V

programming range

Supply monitor threshold ac-

V

CMP_ACC

Supply falling edge trip point -5 — 5 %

curacy

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EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Supply monitor threshold
hysteresis

V

CMP_HYST

Positive hysteresis on the supply
rising edge referred to the falling

— 4 — %

edge trip point

Supply monitor response
time

t

CMP_DELAY

Supply falling edge at -100 mV /
µs

— 0.6 — µs

Note:

1. The supported maximum V

VREGVDD

in regulation mode is a function of temperature and 10-year lifetime average load current.

See more details in 4.4.1 DC-DC Operating Limits.

2. Samsung CL10B475KQ8NQNC used for performance characterization. Actual capacitor values can be significantly de-rated from
their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The mini­mum capacitance counting all error sources should be no less than 2.4 µF.

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EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

4.4.1 DC-DC Operating Limits

The maximum supported voltage on the VREGVDD supply pin is limited under certain conditions. Maximum input voltage is a function
of temperature and the average load current over a 10-year lifetime. Figure 4.1 Lifetime average load current limit vs. Maximum input

voltage on page 20 shows the safe operating region under specific conditions. Exceeding this safe operating range may impact the

reliability and performance of the DC-DC converter.

The average load current for an application can typically be determined by examining the current profile during the time the device is
powered. For example, an application that is continuously powered which spends 99% of the time asleep consuming 2 µA and 1% of
the time active and consuming 10 mA has an average lifetime load current of about 102 µA.

60

(mA)

LOAD

Tj ≤ 125 °C

5

Average Lifetime I

3.3 3.8

Maximum V

Figure 4.1. Lifetime average load current limit vs. Maximum input voltage

The minimum input voltage for the DC-DC in EM0/EM1 mode is a function of the maximum load current, and the peak current setting.

Figure 4.2 Transient maximum load current vs. Minimum input voltage on page 20 shows the max load current vs. input voltage for

different DC-DC peak inductor current settings.

VREGVDD

(V)

60

(mA)

36

LOAD

= 150 mA

I

PEAK

= 90 mA

I

VREGVDD

PEAK

(V)

5

Maximum I

1.8

2.2

Minimum V

Figure 4.2. Transient maximum load current vs. Minimum input voltage

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EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

4.5 Thermal Characteristics

Table 4.4. Thermal Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Thermal Resistance Junction
to Ambient QFN32 (4x4mm)

THE­TA

JA_QFN32_4X4

4-Layer PCB, Natural Convection

Package

Thermal Resistance, Junc­tion to Ambient, QFN40

THE­TA

JA_QFN40_5X5

4-Layer PCB, Natural Convection

(5x5mm) Package

Note:

1. Measured according to JEDEC standard JESD51-2A. Integrated Circuit Thermal Test Method Environmental Conditions - Natural
Convection (Still Air).

1

— 35.4 — °C/W

1

— 32.6 — °C/W

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EFM32PG22 Gecko MCU Family Data Sheet

Electrical Specifications

4.6 Current Consumption

4.6.1 MCU current consumption using DC-DC at 3.0 V input

Unless otherwise indicated, typical conditions are: VREGVDD = 3.0 V. AVDD = DVDD = IOVDD = 1.8 V from DC-DC. Voltage scaling
level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T

= 25 °C.

Table 4.5. MCU current consumption using DC-DC at 3.0 V input

Parameter Symbol Test Condition Min Typ Max Unit

A

Current consumption in EM0
mode with all peripherals dis­abled

I

ACTIVE

76.8 MHz HFRCO w/ DPLL refer­enced to 38.4 MHz crystal, CPU
running Prime from flash,
VSCALE2

76.8 MHz HFRCO w/ DPLL refer­enced to 38.4 MHz crystal, CPU
running while loop from flash,
VSCALE2

76.8 MHz HFRCO w/ DPLL refer­enced to 38.4 MHz crystal, CPU
running CoreMark loop from flash,
VSCALE2

38.4 MHz crystal, CPU running
Prime from flash

38.4 MHz crystal, CPU running
while loop from flash

38.4 MHz crystal, CPU running
CoreMark loop from flash

38 MHz HFRCO, CPU running
while loop from flash

26 MHz HFRCO, CPU running
while loop from flash

— 28 — µA/MHz

— 27 — µA/MHz

— 37 — µA/MHz

— 28 — µA/MHz

— 26 — µA/MHz

— 38 — µA/MHz

— 22 — µA/MHz

— 24 — µA/MHz

16 MHz HFRCO, CPU running

— 27 — µA/MHz

while loop from flash

1 MHz HFRCO, CPU running

— 159 — µA/MHz

while loop from flash

Current consumption in EM1
mode with all peripherals dis­abled

I

EM1

76.8 MHz HFRCO w/ DPLL refer­enced to 38.4 MHz crystal,
VSCALE2

— 17 — µA/MHz

38.4 MHz crystal — 17 — µA/MHz

38 MHz HFRCO — 13 — µA/MHz

26 MHz HFRCO — 15 — µA/MHz

16 MHz HFRCO — 18 — µA/MHz

1 MHz HFRCO — 150 — µA/MHz

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