Silicon Labs AN895 User Manual

AN895

IEC 61000-4-2 ESD SYSTEM LEVEL PROTECTION

1. Introduction

This application note provides a brief overview about the possible ESD protecting realizations for any Silicon
Labs RF designs. However, experimental measurements have only been taken with, and thus the efficiency of
the ESD protection realizations has been demonstrated on, Si4x6x-based reference designs.

RF radio chips are designed for and tested against the different chip-level ESD standards such as Human Body
Model (HBM), Machine Model (MM) and Charged Device Model (CDM). These chip-level test results are
summarized in the RF IC’s Qualification Report.

However, in a real-world application the final module has to resist and stand against an ESD shock. For this
purpose, the final electronic product has to be tested against a different, more stringent standard that simulates
and replicates the real world ESD stress conditions. This system-level standard is the IEC 61000-4-2.

System/module designers should take care to comply with the IEC 61000-4-2 system-level ESD standard. This
application note shows Silicon Labs’ customers how to achieve the best possible system-level protections on
board level using Silicon Labs radio chips.

2. Si4x6x Qualification Report

The Si4x6x radios’ ESD robustness against the different chip level ESD standards are summarized in “Electrical
Verification” of the “Qualification Report”.

The following is a brief summary from those results:

ESD-HBM: pass up to 2 kV
ESD-MM: pass up to 50 V for all pins, excluding RF pins if it is 200 V
ESD-CDM: pass up to 500 V

3. Overview of IEC 61000-4-2 Standard

The IEC standard is a system level test that replicates a charged person discharging to a system in a system end
user environment. The purpose of the system level test is to ensure that finished products can survive normal
operation and it is generally assumed that the user of the product will not take any ESD precautions to lower ESD
stress to the product.

The IEC 61000-4-2 standard defines four standard levels of ESD protection, using two different testing
methodologies. Contact discharge involves discharging an ESD pulse directly from the ESD test gun that is
touching the device under test. This is the preferred method of testing. However, the standard provides for an
alternate test methodology known as air discharge for cases where contact discharge testing is not possible. In
the air discharge test, the ESD test gun is brought close to the device under test until a discharge occurs. The
standards are defined so that each level is considered equivalent – a Level 4 contact discharge of 8 kV is
considered equivalent to a 15 kV air discharge.

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3.1. Recommended ESD Test Bench

Figure 1. IEC 61000-4-2 Test Bench

3.2. Simulation Circuit

The IEC standard replicates a charged person discharging into a system in an uncontrolled environment. This test
is performed to ensure the system will remain operational in an end user environment where no ESD stress
precautions are taken.

Figure 2. Simulation Circuit of IEC 61000-4-2

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3.3. IEC 61000-4-2 Test Levels

Contact Discharge Air Discharge

Level Test Voltage (kV) Level Test Voltage (kV)

1212

2424

3638

48415

3.4. Pulse Waveform

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Figure 3. IEC 61000-4-2 ESD Pulse Waveform

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3.5. Peak Current of IEC 61000-4-2 ESD Standard

Applied Voltage (kV) Peak Current (A)

2 7.5

4 15.0

6 22.5

8 30.0

10 37.5

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4. ESD Protection Circuit Example

This section contains an example of an ESD protection circuit that can effectively suppress an IEC 61000-4-2 ESD
shock.

The following passive components can be included in an effective external ESD protection circuit: series resistors,
ferrites, filtering capacitors and inductors, transient voltage suppressors (e.g., TVS diodes), thyristors, varistors,
polymer, etc.

The ESD protection circuit composed from these above components can block ESD currents and clamp ESD­induced high voltages. The exceeded ESD currents can be suppressed and shunted to minimize the effects of the
ESD pulses in the system. It is highly recommended to place the protection circuit as close as possible to the
connection point on the board where the ESD shock event can occur. This placing approach can minimize the
possibility of causing further couplings of the ESD currents and voltages to the other blocks on the module.

A general I/O connector of a piece of electrical equipment can be protected with the example circuit composed with
external passive components shown in Figure 4.

Figure 4. Example for ESD Protection Circuit

J1: connection point where the ESD shock occurs (high-voltage IEC 61000-4-2 Test Pulse)

J2: ESD-protected connection point (suppressed test signal)

L1: series filtering inductor

C1, C2: parallel filtering capacitors

D1: TVS diode

R: series resistor

The ESD shock is supposed to occur at the “J1” point. The “L-C” low-pass filtering section suppresses the fast ESD
shock signal; the “L1” inductor can block the large currents, while the “C1” and “C2” capacitors can limit the high
voltage induced by the transient fast current spike.

The “D1” TVS diode can be effectively used for suppressing the fast ramped-up ESD signals and plenty of these
kinds of diodes are available on the market from different manufacturers (specified for assisting equipment to pass
IEC 61000-4-2, even level 4 testing).

The optimum values for the components and even the optimum structure (i.e., it might not be necessary to use all
of the shown components in Figure 4) depend on the level of the ESD signal, board layout, and on the termination
at the “J2” point.

It is possible to select the filtering element values in a way where the largest suppression can be achieved at the
GHz region, since the ramp-up time of the fast ESD signal is around 1 ns, as shown in Figure 3.

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5. Waveform Measurements as IEC 61000-4-2 Standard

Silicon Labs performed waveform measurements with the following setup:

IEC 61000-4-2 ESD standard test bench setup
IEC 61000-4-2 ESD standard test signals
Direct contact waveform measurements from the IEC 61000-4-2 test signal
Contact waveform measurements with applying an example ESD protection circuit

This section illustrates how the waveforms look before (direct measurement of IEC 61000-4-2 test signal) and after
an example ESD protection circuit. In addition, this section demonstrates the effectiveness of the protection circuit.

The TVS diode used in the example protection circuit (“D1”) is: SESD0402X1UN.

The ESD protection circuit was realized on a small PCB that only included the elements shown in Figure 4.

The following figures show the measured waveforms with different conditions such as voltage of the test signal,
different elements mounted on the ESD protection board, different element values, and etc. The conditions are
identified in each figure caption.

Figure 5. IEC 61000-4-2 Test Signal, +2 kV, without Protection

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