Silicon Laboratories Si5397 Series, Si5396 Series, Si5397L/M, Si5397A/B, Si5396A/B Reference Manual

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Si5397/96 Reference Manual

Quad/Dual DSPLL Any-frequency, Any-output Jitter Attenuators Si5397/96 Family Reference Manual

1. Work Flow Using ClockBuilder Pro and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to the applications notes and Knowledge Base articles within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes.

The primary purpose of the software is to enable use of the device without an in-depth understanding of its complexities. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the settings in the register map described in this document.

1.1 Field Programming

To simplify design and software development of systems using the Si5397/96, a field programmer is available in addition to the evaluation board. The ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a PCB), as well as “in-socket” programming of Si5397/96 sample devices. Refer to www.silabs.com/CBProgrammer for information about this kit.

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Si5397/96 Reference Manual

Family Product Comparison

2. Family Product Comparison

The following table is a comparison of the different parts in the product family showing the differences in the inputs, MultiSynths, outputs and package type.

Table 2.1. Family Feature Comparison

Part Number

Si5397A/B External 4 4 8 64-QFN

Si5397J/K Internal 4 4 8 64-LGA

Si5397C/D External 4 4 4 64-QFN

Si5397L/M Internal 4 4 4 64-LGA

Si5396A/B External 4 2 4 44-QFN

Si5396J/K Internal 4 2 4 44-LGA

Internal/External

Number of Inputs

Reference

Number of Multi-

Synths

Number of Outputs Package Type

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Si5397/96 Reference Manual

Functional Description

3. Functional Description

The Si5397 takes advantage of Silicon Labs fourth-generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) after having been divided down by the P dividers, which are either fractional or integer. Clock selection can be either manual or automatic. Any of the output clocks can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5396 is a smaller form factor dual DSPLL version with four inputs and four outputs.

The Si5397J/K is the internal refernce version of the Si5397A/B. Si5397L/M is the internal reference version of Si5397C/D. Si5396J/K is the internal reference version of Si5396A/B. All the features and functions are the same. The only difference is that the reference is integrated into the package. The registers and features of the external reference parts match that of the internal reference parts. Throughout this document the register descriptions for labels of the external reference grades can be assumed to be the same for the internal reference grades.

3.1 DSPLL and MultiSynth

The DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input dividers (Pxn/Pxd) allow for integer or fractional division of the input frequency, but the input frequencies must be integer related to allow the DSPLL to perform hitless switching between input clocks (INx). Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. Note that a XTAL (or suitable XO reference on XA/XB) is always required and is the jitter reference for the device. The high-performance MultiSynth dividers (Nxn/Nxd) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the generated frequencies to any of the outputs. A single MultiSynth output can connect to one or more output drivers. Additional integer division (R) determines the final output frequency. The internal reference grade devices have a XTAL integrated in the package, so no external XTAL is needed. The specs for the integrated reference can be found in the data sheet.

IN0

IN1

IN2

IN3

Si5397

÷FRAC

NVM

C/SPI

Control/

Status

XTAL/

REFCLK

OSC

DSPLL

XTAL/

REFCLK

OSC

DSPLL

XBXA

÷INT

OUT0

OUT1

OUT2

OUT3

XBXA

÷INT

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

Si5347C/D

Si5347A/B

÷INT

OUT6

OUT7

IN0

IN1

IN2

IN3

Si5396

÷FRAC

NVM

C/SPI

Control/

Status

Figure 3.1. DSPLL and Multisynth System Flow Diagram

The frequency configuration of the DSPLL is programmable through the SPI or I2C

interface and can also be stored in non-vola-

serial tile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software.

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3.1.1 Dividers

Si5397/96 Reference Manual

Functional Description

There are

five main divider classes within the Si5397/96. Additionally, FSTEPW can be used to adjust the nominal output frequency in

DCO mode. See Section 7. Digitally-Controlled Oscillator (DCO) Mode for more information and block diagrams on DCO mode.

• 1. PXAXB: Reference input divider (0x0206)

• Divide reference clock by 1, 2, 4, or 8 to obtain an internal reference < 125 MHz

• 2. P0-P3: Input clock wide range dividers (0x0208-0x022F)

• Integer or Fractional divide values

•

Min. value is 1, Max. value is 224 (Fractional-P divisors must be > 5)

• 48-bit numerator, 32-bit denominator

• Practical P divider range of (Fin / 2 MHz) < P < (Fin / 8 kHz)

• Each P divider has a separate update bit for the new divider value to take effect

• 3. MA-MD: DSPLL feedback dividers (0x0415-0x041F, 0x0515-0x051F, 0x0615-0x061F, 0x0716-0x0720)

• Integer or Fractional divide values

•

Min. value is 1, Max. value is 224 (Fractional-M divisors must be > 10)

• 56-bit numerator, 32-bit denominator

• Practical M divider range of (Fdco / 2 MHz) < M < (Fdco / 8 kHz)

• Each M divider has a separate update bit for the new divider value to take effect

• Soft reset will also update M divider values

• 4. Output N dividers N0-N3(0x0302-0x032D)

• MultiSynth divider

• Integer or fractional divide values

• 44 bit numerator, 32 bit denominator

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

• 5. R0-R7: Output dividers (0x024A-0x026A)

• 24-bit field

•

Min. value is 2, Max. value is 225-2

• Only even integer divide values: 2, 4, 6, etc.

• R Divisor = 2 x (Field + 1). For example, Field = 3 gives an R divisor of 8

• FSTEPW: DSPLL DCO step words (0x0423-0x0429, 0x0523-0x0529, 0x0623-0x0629, 0x0724-0x072A)

• Positive Integers, where FINC/FDEC select direction

•

Min. value is 0, Max. value is 2

• 56-bit step size, relative to 32-bit M denominator

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3.1.2 DSPLL Loop Bandwidth

Si5397/96 Reference Manual

Functional Description

The DSPLL

loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. The loop bandwidth is controlled digitally and remains stable with less than 0.1 dB of peaking for the loop bandwidth selected. The DSPLL loop bandwidth is set in registers 0x0508-0x050D and are determined using ClockBuilder Pro.

The higher the PLL bandwidth is set relative to the phase detector frequency (f

), the more chance that f

pfd

will cause a spur in the

pfd

Phase Noise plot of the output clock and increase the output jitter. To guarantee the best phase noise/jitter it is recommended that the normal PLL bandwidth be kept less than f

/160 although ratios of f

pfd

/100 will typically work fine.

pfd

Note: After changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x414, 0x514, 0x614, 0x714) must be set high to latch the new values into operation. The update bits will latch both nominal and fastlock bandwidths.

Table 3.1. PLL Bandwidth Registers

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

BW_PLLA 0408[7:0] -

040D[7:0]

BW_PLLB 0508[7:0] -

050D[7:0]

BW_PLLC 0608[7:0] -

0408[7:0] -

040D[7:0]

0508[7:0] -

050D[7:0]

—

This group of registers determine the loop bandwidth for DSPLL A, B, C, D. They are all independently selectable in the range from 0.1 Hz up to 4 kHz. Register values determined by ClockBuilderPro.

060D[7:0]

BW_PLLD 0709[7:0] -

070E[7:0]

—

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3.1.2.1 Fastlock Feature

Si5397/96 Reference Manual

Functional Description

Selecting a

low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the nominal DSPLL Loop Bandwidth setting. The Fastlock feature can be enabled or disabled independently by register control. If enabled, when LOL is asserted Fastlock will be automatically enabled. When LOL is no longer asserted, Fastlock will be automatically disabled. The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in the fault monitoring section.

Note: After changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x414, 0x514, 0x614, 0x714) must be set hight to latch the new values into operation. This update bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3.2. PLL Fastlock Registers

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

FASTLOCK_AUTO_EN_PLLA 042B[0] 042B[0] Fastlock enable/disable. Fastlock is enabled by default

FASTLOCK_AUTO_EN_PLLB 052B[0] 052B[0]

with a bandwidth of 4 kHz.

FASTLOCK_AUTO_EN_PLLC 062B[0] —

FASTLOCK_AUTO_EN_PLLD 072C[0] —

FAST_BW_PLLA 040E[7:0] -

0413[7:0]

FAST_BW_PLLB 050E[7:0] -

0513[7:0]

040E[7:0] -

0413[7:0]

050E[7:0] -

0513[7:0]

Fastlock bandwidth is selectable in the range of 100 Hz up to 4 kHz. Register values determined using ClockBuilderPro.

FAST_BW_PLLC 060E[7:0] -

—

0613[7:0]

FAST_BW_PLLD 070F[7:0] -

—

0714[7:0]

3.1.2.2 Holdover Exit Bandwidth

In addition

to the operating loop and fastlock bandwidths, there is also a user-selectable bandwidth when exiting holdover and locking or relocking to an input clock, available when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the loop bandwidth by default.

Note: The BW_UPDATE bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3.3. DSPLL Holdover Exit Bandwidth Registers

0x049D-0x04A2 (PLLA)

HOLDEXIT_BW_PLLx

0x059D–0x05A2 (PLLB)

0x069D-0x06A2 (PLLC)

Determines the Holdover Exit BW for the DSPLL. Parameters are generated by ClockBuilder Pro. See CBPro for the generated values and corresponding bandwidths.

0x079D-0x07A2 (PLLD)

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Si5397/96 Reference Manual

Modes of Operation

4. Modes of Operation

Once initialization is complete, the DSPLL operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of these modes in greater detail.

Power-Up

Reset and

Initialization

No valid input

clocks available

for selection

No valid

input clocks

selected

An input is

qualified and

available for

selection

Holdover

Mode

Free-run

Lock Acquisition

(Fast Lock)

Input Clock

Yes

Holdover

History

Valid?

Figure 4.1. Modes of Operation

Valid input clock

selected

Switch

Yes

Phase lock on selected

is achieved

clock

Locked

Mode

Other Valid

Clock Inputs

Available?

input

Selected input

clock

fails

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4.1 Reset and Initialization

Si5397/96 Reference Manual

Modes of Operation

Once power

is applied, the device begins an initialization period where it downloads default register values and configuration data from internal non-volatile memory (NVM) and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete.

There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.

NVM

OTP

RAM

Figure 4.2. Si5397/96 Memory Configuration

Table 4.1. Reset Control Registers

Setting Name Hex Address

Function

[Bit Field]

Si5397 Si5396

HARD_RST 001E[1] 001E[1] Performs the same function as power cycling the de-

vice. All registers will be restored to their default values.

SOFT_RST_ALL 001C[0] 001C[0] Resets the device without re-downloading the regis-

ter configuration from NVM.

SOFT_RST_PLLA 001C[1] 001C[1] Performs a soft reset on DSPLL A only.

SOFT_RST_PLLB 001C[2] 001C[2] Performs a soft reset on DSPLL B only.

SOFT_RST_PLLC 001C[3] — Performs a soft reset on DSPLL C only.

SOFT_RST_PLLD 001C[4] — Performs a soft reset on DSPLL D only.

Power-Up

NVM download

Initialization

Serial interface

ready

Hard Reset bit asserted

Soft Reset

bit asserted

RST

pin asserted

Figure 4.3. Initialization from Hard Reset and Soft Reset

The Si5397/96

fully configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values

is from NVM. Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8 V) and VDDA (3.3 V) pins. Neither VDDOx or VDDS supplies are required to write the NVM.

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4.2 Dynamic PLL Changes

Si5397/96 Reference Manual

Modes of Operation

ClockBuilder Pro

generates all necessary control register writes to update settings for the entire device, including the ones described below. This is the case for both “Export” generated files as well as when using the GUI. This is sufficient to cover most applications. However, in some applications it is desirable to modify only certain sections of the device while maintaining unaffected clocks on the remaining outputs. If this is the case CBPro provides some frequency changes on the fly examples.

If certain registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock indefinitely). Additionally, making single frequency step changes greater than ±350 ppm, either by using the DCO or by directly updating the M dividers, may also cause the PLL to become unresponsive. Changes to the following registers require this special sequence of writes:

Control Register(s)

PXAXB 0x0206[1:0]

MXAXB_NUM 0x0235 – 0x023A

MXAXB_DEN 0x023B – 0x023E

PLL lockup can easily be avoided by using the following the preamble and postamble write sequence below when one of these regis-

modified or large frequency steps are made. Clockbuilder Pro software adds these writes to the output file by default when Ex-

ters is porting Register Files.

To start, write the preamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0B24 0xC0

0x0B25 0x00

0x0B4E 0x1A

Wait 300 ms for the device state to stabilize.

Then, modify all desired control registers.

Write 0x01 to Register 0x001C (SOFT_RST_ALL) to perform a Soft Reset once modifications are complete.

Write the postamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0B24 0xC3

0x0B25 0x02

Note, however, that this procedure affects all DSPLLs and outputs on the device.

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4.3 NVM Programming

Si5397/96 Reference Manual

Modes of Operation

Devices have

two categories of non-volatile memory: user NVM and Factory (Silabs) NVM. Each type is segmented into NVM banks. There are three user NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). User NVM can be therefore be burned in the field up to two times. Factory NVM cannot be modified, and contains fixed configuration information for the device.

The ACTIVE_NVM_BANK device setting can be used to determine which user NVM bank is currently being used and therefore how many banks, if any, are available to burn. The following table describes possible values:

Table 4.2. NVM Bank Burning Values

Active NVM BANK Value (Deci-

Number of User Banks Burned Number of User Banks Available to Burn

mal)

3 (factory state) 1 2

15 2 1

63 3 0

Note: While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct values are written into the NVM:

• VDD and VDDA power must both be stable throughout the process.

No additional registers may be written or read during DEVICE_READY polling. This includes the PAGE register at address 0x01.

• DEVICE_READY is available on every register page, so no page change is needed to read it.

• Only the DEVICE_READY register (0xFE) should be read during this time.

The procedure for writing registers into NVM is as follows:

1. Write all registers as needed. Verify device operation before writing registers to NVM.

2. You may write to the user scratch space (Registers 0x026B to 0x0272 DESIGN_ID0-DESIGN_ID7) to identify the contents of the NVM bank.

3. Write 0xC7 to NVM_WRITE register.

4. Poll DEVICE_READY until DEVICE_READY=0x0F.

5. Set NVM_READ_BANK 0x00E4[0]=1. This will load the NVM contents into non-volatile memory.

6. Poll DEVICE_READY until DEVICE_READY=0x0F.

7. Read ACTIVE_NVM_BANK and verify that the value is the next highest value in the table above. For example, from the factory it will be a 3. After NVM_WRITE, the value will be 15.

Alternatively, steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device to generate a POR. All of these actions will load the new NVM contents back into the device registers.

The ClockBuilder Pro Field Programmer kit is a USB attached device to program supported devices either in-system (wired to your PCB) or in-socket (by purchasing the appropriate field programmer socket). ClockBuilder Pro software is then used to burn a device configuration (project file). Learn more at https://www.silabs.com/products/development-tools/timing/cbprogrammer.

Table 4.3. NVM Programming Registers

Function

[Bit Field]

ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.

NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.

NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.

DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept commands when

value = 0x0F.

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Si5397/96 Reference Manual

Modes of Operation

Warning: Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt

NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the

the PAGE register.

4.4 Free Run Mode

Once power is applied to the Si5397/96 and initialization is complete, if valid input is not present, the DSPLL will automatically enter freerun mode, generating the frequencies determined by the NVM. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes. Because there is little or no jitter attenuation from the XAXB pins to the clock outputs, a low-jitter XAXB source will be needed for low-jitter clock outputs.

4.5 Lock Acquisition Mode

Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

4.6 Locked Mode

Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point any XTAL frequency drift will not affect the output frequency. DSPLL has its LOL pin and status bit to indicate when lock is achieved. See Section 5.3.3 Loss of Lock (LOL) Fault Monitoring for more details on the operation of the loss of lock circuit.

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4.7 Holdover Mode

Si5397/96 Reference Manual

Modes of Operation

The DSPLL

programmed for holdover mode automatically enters holdover when the selected input clock becomes invalid (i.e. when either OOF or LOS are asserted) and no other valid input clocks are available for selection. The DSPLL calculates a historical average of the input frequency while in locked mode to minimize the initial frequency offset when entering the holdover mode.

The averaging circuit for the DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window with the stored historical frequency data. The window size determines the amount of holdover frequency averaging. The delay value is used to ignore frequency data that may be corrupt just before the input clock failure. Both the window size and the delay are programmable as shown in the figure below.

Clock Failure

and Entry into

Holdover

Historical Frequency Data Collected

time

120s

Programmable historical data window

used to

determine the final holdover value

1s,10s, 30s, 60s

Programmable delay

30ms, 60ms, 1s,10s, 30s, 60s

Figure 4.4. Programmable Holdover Window

When entering Holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Holdover, the

output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XAXB pins. If the clock input becomes valid, the DSPLL will automatically exit the Holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. These options are register programmable.

The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency difference between the output frequency while in holdover and the desired, new output frequency is measured. It is likely that the new output clock frequency will not be the same as the holdover output frequency because the new input clock frequency might have changed and the XTAL drift might have changed the output frequency. The ramp logic calculates the difference in frequency between the holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp time is calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends, the output frequency will be the desired new frequency. Using the ramp, the transition between the two frequencies is smooth and linear. The ramp rate can be selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or any of approximately 40 values that are in between. The loop bandwidth values do not limit or affect the ramp rate selections and vice versa. CBPro defaults to ramped exit from holdover. Ramped exit from holdover is also used for ramped input clock switching. See Section 5.2.3 Ramped Input Switching for more information.

As shown in Figure 4.1 Modes of Operation on page 12, the Holdover and Freerun modes are closely related. The device will only enter Holdover if a valid clock has been selected long enough for the holdover history to become valid. If the clock fails before the combined holdover history length and holdover history delay time has been met, then holdover history won't be valid and the device will enter Freerun mode instead. Reducing the holdover history length and holdover history delay times will allow Holdover in less time, limited by the source clock failure and wander characteristics. Note that the Holdover history accumulation is suspended when the input clock is removed and resumes accumulating when a valid input clock is again presented to the DSPLL.

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Si5397/96 Reference Manual

Modes of Operation

Table 4.4. Holdover Mode Control Registers

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

Holdover Status

HOLD_PLL(D,C,B,A) 000E[7:4] 000E[5:4] Holdover status indicator. Indicates when a DSPLL is in

holdover or free-run mode and is not synchronized to the input reference. The DSPLL goes into holdover only when the historical frequency data is valid, otherwise the DSPLL will be in free-run mode.

HOLD_FLG_PLL(D,C,B,A) 0013[7:4] 0013[5:4] Holdover status monitor sticky bits. Sticky bits will re-

main asserted when an holdover event occurs until cleared. Writing a zero to a sticky bit will clear it.

HOLD_HIST_VALID_PLLA 043F[1] 043F[1] Holdover historical frequency data valid. Indicates if

HOLD_HIST_VALID_PLLB 053F[1] 053F[1]

HOLD_HIST_VALID_PLLC 063F[1] —

there is enough historical frequency data collected for valid holdover value.

HOLD_HIST_VALID_PLLD 0740[1] —

Holdover Control and Settings

HOLD_HIST_LEN_PLLA 042E[4:0] 042E[4:0] Window Length time for historical average frequency

HOLD_HIST_LEN_PLLB 052E[4:0] 052E[4:0]

used in Holdover mode. Window Length in seconds (s): Window Length = ((2

LEN

) – 1)*268nsec

HOLD_HIST_LEN_PLLC 062E[4:0] —

HOLD_HIST_LEN_PLLD 072F[4:0] —

HOLD_HIST_DELAY_PLLA 042F[4:0] 042F[4:0] Delay Time to ignore data for historical average frequen-

HOLD_HIST_DELAY_PLLB 052F[4:0] 052F[4:0]

cy in Holdover mode. Delay Time in seconds (s): Delay Time = (2

DELAY

) x268nsec

HOLD_HIST_DELAY_PLLC 062F[4:0] —

HOLD_HIST_DELAY_PLLD 0730[4:0] —

FORCE_HOLD_PLLA 0435[0] 0435[0] These bits allow forcing any of the DSPLLs into hold-

FORCE_HOLD_PLLB 0535[0] 0535[0]

over

FORCE_HOLD_PLLC 0635[0] —

FORCE_HOLD_PLLD 0736[0] —

HOLD_EXIT_BW_SEL1_PLLA 042C[4] 042C[4] Selects the exit from holdover bandwidth. Options are:

HOLD_EXIT_BW_SEL1_PLLB 052C[4] 052C[4]

0: Exit of holdover using the fastlock bandwidth

HOLD_EXIT_BW_SEL1_PLLC 062C[4] —

1: Exit of holdover using the DSPLL loop bandwidth

HOLD_EXIT_BW_SEL1_PLLD 072D[4] —

HOLD_EXIT_BW_SEL0_PLLA 049B[6] 049B[6]

HOLD_EXIT_BW_SEL0_PLLB 059B[6] 059B[6]

HOLD_EXIT_BW_SEL0_PLLC 069B[6] —

HOLD_EXIT_BW_SEL0_PLLD 079B[6] —

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Si5397/96 Reference Manual

Modes of Operation

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

HOLD_RAMP_EN_PLLA 042C[3] 042C[3] Must be set to 1 for normal operation.

HOLD_RAMP_EN_PLLB 052C[3] 052C[3]

HOLD_RAMP_EN_PLLC 062C[3] —

HOLD_RAMP_EN_PLLD 072D[3] —

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Si5397/96 Reference Manual

Clock Inputs

5. Clock Inputs

There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both standard format inputs and low duty cycle pulsed CMOS clocks. The input P dividers can be either fractional or integer. A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs as shown in the figure below.

Si5397

Input

Crosspoint

IN0

0 1 2 3

DSPLL

IN1

IN2

IN3

0 1 2 3

DSPLL

Figure 5.1. Clock Inputs Example

5.1 Input Source Selection

inputs

The

accept AC coupled clocks that are differential or singled ended such as LVCMOS. In addition, the inputs also accept DC coupled CMOS type inputs with 50% or very low input duty cycle. Input selection can be manual (pin or register controlled) or automatic with user definable priorities. There is a register to select pin or register control, and to configure the input as shown below.

Table 5.1. Manual or Automatic Input Clock Selection Control Registers

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

CLK_SWITCH_MODE_PLLA 0436[1:0] 0436[1:0] Selects manual or automatic switching mode for DSPLL

CLK_SWITCH_MODE_PLLB 0536[1:0] 0536[1:0]

CLK_SWITCH_MODE_PLLC 0636[1:0] —

CLK_SWITCH_MODE_PLLD 0737[1:0] —

A, B, C, D.

0: For manual

1: For automatic, non-revertive

2: For automatic, revertive

3: Reserved

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5.1.1 Manual Input Switching

Si5397/96 Reference Manual

Clock Inputs

In manual

mode the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will

automatically enter holdover mode if the holdover history is valid or Freerun if it is not.

Table 5.2. Manual Input Select Control Registers

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

IN_SEL_PLLA 042A[2:0] 042A[2:0] Selects the clock input used to synchronize DSPLL A, B,

IN_SEL_PLLB 052A[3:1] 052A[3:1]

IN_SEL_PLLC 062A[2:0] —

C, or D. Selections are: IN0, IN1, IN2, IN3, corresponding to the values 0, 1, 2, and 3. Selections 4–7 are reserved.

IN_SEL_PLLD 072B[2:0] —

5.1.2 Automatic Input Switching

Automatic input

switching is available in addition to the manual selection described previously. In automatic mode, the switching criteria is based on input clock qualification, input priority and the revertive option. The IN_SEL_PLLx register bits are not used in automatic input switching. Also, only input clocks that are valid (i.e., with no active fault indicators) can be selected by the automatic clock switching. If there are no valid input clocks available, the DSPLL will enter Holdover or Freerun mode. With Revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input will be initiated. With Non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid, an automatic switchover to the highest priority valid input will be initiated.

Table 5.3. Automatic Input Select Control Registers

Setting Name Hex Address Function

Si5397 Si5396

IN(3,2,1,0)_PRIORITY_PLLA 0x0438–0x0439 0x0438–0x0439 Selects the automatic selection priority for [IN3, IN2,

IN(3,2,1,0)_PRIORITY_PLLB 0x0538–0x0539 0x0538–0x0539

IN(3,2,1,0)_PRIORITY_PLLC 0x0638–0x0639 —

IN1, IN0] for each DSPLL A, B, C, D. Selections are: 1st, 2nd, 3rd, 4th, or never select. Default is IN0=1st, IN1=2nd, IN2=3rd, IN3=4th.

IN(3,2,1,0)_PRIORITY_PLLD 0x0739–0x073A —

IN(3,2,1,0)_LOS_MSK_PLLA 0x0437 0x0437 Determines if the LOS status for [IN3, IN2, IN1, IN0] is

IN(3,2,1,0)_LOS_MSK_PLLB 0x0537 0x0537

IN(3,2,1,0)_LOS_MSK_PLLC 0x0637 —

used in determining a valid clock for the automatic input selection state machine for DSPLL A, B, C, D. Default is LOS is enabled (un-masked).

IN(3,2,1,0)_LOS_MSK_PLLD 0x0738 —

IN(3,2,1,0)_OOF_MSK_PLLA 0x0437 0x0437 Determines if the OOF status for [IN3, IN2, IN1, IN0] is

IN(3,2,1,0)_OOF_MSK_PLLB 0x0537 0x0537

IN(3,2,1,0)_OOF_MSK_PLLC 0x0637 —

used in determining a valid clock for the automatic input selection state machine for DSPLL A, B, C, D. Default is OOF enabled (un-masked).

IN(3,2,1,0)_OOF_MSK_PLLD 0x0738 —

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5.2 Types of Inputs

Si5397/96 Reference Manual

Clock Inputs

Each of ac-coupled single-ended CMOS formats. The standard format inputs have a nominal 50% duty cycle, must be ac-coupled and use the “Standard” input buffer selection as these pins are internally dc-biased to approximately 0.83 V.

Floating clock inputs are noise sensitive. Add a cap to ground for all non-CMOS unused clock inputs. To place the input into Standard Mode make sure IN_PULSED_CMOS_EN 0x949 [7:4] = 0. Bit 7 = IN3, Bit 6 = IN2, Bit 5 = IN1 and Bit 4 = IN0. Make sure the corresponding input bit is set to 0 for Standard Mode. If this bit is 1 this will turn on dc coupled CMOS Mode. Although the name is PULSED_CMOS_EN this setting actually corresponds to enable all dc coupled CMOS modes described further below for the Standard CMOS and Non-Standard/Pulsed CMOS inputs, which are all dc coupled inputs.

the four different inputs IN0-IN3 can be configured as ac coupled differential formats such as LVDS, LVPECL, HCSL, CML, and

Standard AC-Coupled Differential

0.1uF *

INx

100

Standard

INxb

LVDS, LVPECL, CML

0.1uF *

* These caps should have < ~5 ohms capacitive reactance at the clock input frequency.

Clock IC

Standard AC-Coupled Single-Ended

3.3V, 2.5V, 1.8V LVCMOS

RS matches the CMOS driver to a 50 ohm transmission

line (if used)

0.1uF

INx

INxb

Standard

0.1uF *

*This cap should have less than ~20 ohms of capacitive reactance at the clock input frequency. ** Only when 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the output jitter due to faster input slew rate at INx. If attenuation is not needed for Inx<3.6Vppse, make R1 = 0 ohm and omit C1, R2 and the capacitor below R2. C1, R1, and R2 should be physically placed as close as practicle to the device input pins.

Figure 5.2. AC Coupled Standard Input Termination Diagrams

Clock IC

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Si5397/96 Reference Manual

Clock Inputs

Each of the four different inputs IN0-IN3 can be configured as single ended DC-coupled standard pulsed CMOS inputs. In all cases, the inputs should be terminated near the device input pins. In these configurations CMOS mode is enabled via register setting "IN_PULSED_CMOS_EN" = 1 for each input. Note from the datasheet that the Standard CMOS selection has higher VIL and VIH settings than the non-standard/ pulsed CMOS Input buffer selection. Please see the datasheet for the max VIL and min VIH values for both Standard CMOS vs Non-standard CMOS & Pulsed CMOS selection. In general, following the “Standard AC Coupled Single Ended” arrangement shown above will give superior jitter performance than the DC-coupled arrangements below.

CMOS, non-standard CMOS or

Standard CMOS

3.3V, 2.5V, 1.8V LVCMOS

RS matches the CMOS driver to a 50

ohm transmission line (if used)

* Attenuation circuit

not required for 1.8V input or if all input specifications in datasheet are met.

*R1

*R2

INx

Standard CMOS

INxb

Clock IC

Non-Standard or Pulsed CMOS

3.3V, 2.5V, 1.8V LVCMOS

*R1

INx

INxb

Non-Standard

Pulsed CMOS

*R2

RS matches the CMOS driver to a 50

ohm transmission

* Attenuation circuit recommended but not required if input specifications in datasheet are met.

Figure 5.3. Input Terminations for DC Coupled Standard CMOS and Non-Standard/Pulsed CMOS Inputs

Standard CMOS refers to a signal with a swing of (1.8V, 2.5V or 3.3V) +/- 5% that complies with the specified maximum VIL and minimum VIH specifications in the datasheet. Please refer to the datasheet for the VIL and VIH specifications. For non-compliant inputs, a resistive attenuator is required as shown. It is not recommended to add the attenuation circuit for compliant inputs as it adversely affects the signal integrity at the input pins. Note that maximum input frequency cannot be guaranteed with the attenuator circuit. If an input exceeds 3.3V +5% then the input must be attenuated before going into the chip.

line (if used)

Clock IC

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Si5397/96 Reference Manual

Clock Inputs

Non-standard CMOS refers to to a signal with a swing of (1.8V, 2.5V or 3.3 V) +/-5% that has been attenuated/level-shifted in order to comply with VIH specifications. For non-compliant inputs, a resistive attenuator is required as shown. It is not recommended to add the attenuation circuit for compliant inputs as it adversely affects the signal integrity at the input pins. Note that maximum input frequency cannot be guaranteed with the attenuator circuit. If an input exceeds 3.3V +5% then the input must be attenuated before going into the chip.

The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals having a duty cycle much less than 50%. These pulsed CMOS signals are DC-coupled and use the “Pulsed CMOS” Input Buffer selection. The resistor divider values given in the diagram will work with up to 1 MHz pulsed inputs. Pulsed CMOS refers to a low-frequency (up to 1 MHz), low/high duty cycle signal with a swing of (1.8 V, 2.5 V or 3.3 V) +/-5% that has been attenuated/level-shifted in order to comply with the specified non-standard maximum VIL and minimum VIH specifications. Please refer to the datasheet for the VIL and VIH specifications. Make sure to not violate the max and min specifications or use the attenuator circuit to ensure the specifications.

Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected, as shown in the above figure, including the “Standard AC Coupled Single Ended” case. In any of the CMOS modes, it is not necessary to connect the inverting INx input pin. To place the input buffer into any one of the CMOS modes, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4]. Make sure the corresponding input bit is set to 1 for DC Coupled CMOS Mode. Although the name is PULSED_CMOS_EN this setting actually corresponds to enable all DC coupled CMOS modes. IN_CMOS_USE1P8 0x094F[7:4] determines Standard CMOS mode when the input bit is high and Non-Standard or Pulsed CMOS Mode when the input bit is low. The difference between Standard CMOS and Non-Standard/ Pulsed CMOS is the VIL/VIH settings, which should be reviewed carefully from the datasheet.

the specified non-standard maximum VIL and minimum VIH specifications. Please refer to the datasheet for the VIL and

Table 5.4. Input Clock Control and Configuration Registers

Setting Name Hex Address [Bit Field] Function

Si5397/96

IN_EN 0x0949[3:0] Enable each of the input clock buffers for IN3

through IN0.

IN_PULSED_CMOS_EN 0x0949[7:4] Enable CMOS mode for each input

1 = DC Coupled CMOS Mode either Standard or Non-Standard/Pulsed CMOS

0 = Standard AC Coupled Mode

7: IN3

6: IN2

5: IN1

4: IN0

IN_CMOS_USE1P8 0x094F[7:4] 1 = Standard DC-Coupled CMOS mode

0 = Non-Standard or Pulsed DC-Coupled CMOS Mode

7: IN3

6: IN2

5: IN1

4: IN0

Review datasheet for max and min VIL/VIH thresholds

5.2.1 Unused Inputs

Unused inputs

can be disabled and left unconnected. Register 0x0949[3:0] defaults the input clocks to being enabled. Clearing the unused input bits will disable them. Enabled inputs not actively being driven by a clock may benefit from pull up or pull down resistors to avoid them responding to system noise.

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5.2.2 Hitless Input Switching with Phase Buildout

Si5397/96 Reference Manual

Clock Inputs

Phase buildout,

also referred to as hitless switching, prevents a phase change from propagating to the output when switching between two clock inputs with an integer related frequency and a fixed phase relationship (i.e., they are phase/frequency locked, but with a nonzero phase difference). When phase buildout is enabled, the DSPLL absorbs the phase difference between the two input clocks during a clock switch. When phase buildout is disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL loop bandwidth. Lower PLL loop bandwidth provides more filtering.

Hitless Switching with Phase Buildout should be used for applications where the input clocks are all locked to a common upstream clock, as in most synchronization systems. Hitless switching is supported for input frequencies down to 8 kHz. Gapped clocks are not recommended for use with Hitless Switching, as this may increase the phase transient on the outputs.

Table 5.5. Hitless Switching Enable Bit

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

HSW_EN_PLLA 0436[2] 0436[2] Phase Buildout Switching Enable/Disable for DSPLL A,

HSW_EN_PLLB 0536[2] 0536[2]

B, C, D. Phase Buildout Switching is enabled by default.

HSW_EN_PLLC 0636[2] —

HSW_EN_PLLD 0737[2] —

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5.2.3 Ramped Input Switching

Si5397/96 Reference Manual

Clock Inputs

When switching

between input clocks that are not synchronized to the same upstream clock source (i.e. are plesiochronous) there will be differences in frequency between clocks. Ramped switching should be enabled in these cases to ensure a smooth frequency transition on the outputs. In this situation, it is also advisable to enable phase buildout, as discussed in the previous section to minimize the input-to-output clock skew after the frequency ramp has completed.

When ramped clock switching is enabled, the Si5397/96 will enter into holdover and then exit from holdover when the exit ramp has been calculated. This means that ramped switching behaves like an exit from holdover. This is particularly important when switching between two input clocks that are not the same frequency so that the transition between the two frequencies will be smooth and linear. Ramped switching is not needed for cases where the input clocks are locked to the same upstream clock source. The CBPro 'DSPLL Configure' page defaults to enable 'Ramped Exit from Holdover', but the user needs to select the 'Ramped Input Switching & Exit from Holdover' option when switching between non-synchronized input clocks.The same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped exit from holdover including the ramp rate, see Section 4.7 Holdover Mode.

Table 5.6. Ramped Switching Decision Matrix

Frequency Difference be-

tween Input Frequencies

> 500 kHz f

Pfd

< 500 kHz

Pfd

Zero PPM Select "Ramped Exit from Holdover"

If difference is:

Less than 10 ppm, select "Ramped Exit from Hold-

Non-Zero PPM

• over".

•

More than 10 ppm, select "Ramped input switching

Select "Ramped input switching and Ramped

Exit from Holdover".

and Ramped Exit from Holdover".

Table 5.7. Ramped Input Switching Control Registers

Setting Name Hex Address [Bit Field] Function

RAMP_SWITCH_EN_PLLA 0x04A6[3] Enable frequency ramping on an input switch

RAMP_SWITCH_EN_PLLB 0x05A6[3]

RAMP_SWITCH_EN_PLLC 0x06A6[3]

RAMP_SWITCH_EN_PLLD 0x07A6[3]

HSW_MODE_PLLA 0x043A[1:0] Input switching mode select

HSW_MODE_PLLB 0x053A[1:0]

HSW_MODE_PLLC 0x063A[1:0]

HSW_MODE_PLLD 0x073A[1:0]

5.2.4 Hitless Switching, LOL (Loss of Lock) and Fastlock

When doing

a clock switch between clock inputs that are frequency locked, LOL may be momentarily asserted. In such cases, the assertion of LOL will invoke Fastlock. Because Fastlock temporarily increases the loop BW by asynchronously inserting new filter parameters into the DSPLL’s closed loop, there may be transients at the clock outputs when Fastlock is entered or exited. For this reason, it is suggested that automatic entry into Fastlock be disabled by writing a zero to FASTLOCK_AUTO_EN_PLLx whenever a clock switch might occur.

5.2.5 External Clock Switching

When applications require an external switch, it is difficult for the the PLL to predict when that switch will occur. The Si5397/96 will temporarily go into holdover and then exit in a controlled manner to have a minimum phase/frequency transient. If expansion beyond the maximum number of inputs is required, please see AN1111: DSPLL Input Clock Expander which describes how an external FPGA can be used for this purpose.

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5.2.6 Synchronizing to Gapped Input Clocks

Si5397/96 Reference Manual

Clock Inputs

The DSPLL

supports locking to an input clock with missing clock edges. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its edges. Gapping a clock significantly increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter, periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of 2 missing cycles out of every 8. Gapped input clocks are not recommended for use with Hitless Switching, as the output phase transients may be significantly higher.

When properly configured, locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification for a maximum phase transient, when the switch occurs during a gap in either input clocks. The following figure shows a 100 MHz clock with one cycle removed every 10 cycles, which results in a 90 MHz periodic non-gapped output clock.

Gapped Input Clock Periodic Output Clock

100 MHz clock

1 missing period

100 ns 100 ns

every

90 MHz non-gapped clock

DSPLL

1 2 3 4 5 6 7 8 9 10

10 ns

Period Removed

1 2 3 4 5 6 7 8 9

11.11111... ns

Figure 5.4. Gapped Input Clock Use

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Si5397/96 Reference Manual

Clock Inputs

5.2.7 Rise Time Considerations

well known that slow rise time signals with low slew rates are a cause of increased jitter. In spite of the fact that the low loop BW of

It is the Si5397/96 will attenuate a good portion of the jitter that is associated with a slow rise time clock input, if the slew rate is low enough, the output jitter will increase. The following figure shows the effect of a low slew rate on RMS jitter for a differential clock input. It shows the relative increase in the amount of RMS jitter due to slow rise time and is not intended to show absolute jitter values.

IN_X Slew Rate in Differential Mode

4.5

3.5

2.5

Relateive Jitter

1.5

TYP

0.5

0 100 200 300 400 500 600

Input Slew (V/us)

Figure 5.5. Effect of Low Slew Rate on RMS Jitter

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5.3 Fault Monitoring

Si5397/96 Reference Manual

Clock Inputs

All four

input clocks (IN0, IN1, IN2, IN3) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. There is a Loss Of Lock (LOL) indicator asserted when the DSPLL loses synchronization with its reference input.

Si5397

OSC

LOS

DSPLL A

LOL

LPF

LOL

÷M

DSPLL B

LPF

÷M

DSPLL C

LPF

÷M

DSPLL D

LPF

÷M

IN0

IN1

IN2

IN3

LOS

OOF

Precision

Fast

Precision

Fast

Precision

Fast

Precision

Fast

Figure 5.6. Fault Monitors

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5.3.1 Input Loss of Signal (LOS) Fault Detection

Si5397/96 Reference Manual

Clock Inputs

The loss

of signal monitor qualifies the input signal with the following criteria to determine if a valid signal is present. The loss of signal monitor measures the period of each phase detector input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits compares the measured phase detector input period to a maximum (set) and minimum (clear) period thresholds. LOS asserts if the maximum input period threshold is exceeded or if the input period is less than the minimum input period threshold. The thresholds for assert and de-assert of LOS are specified in a number of corresponding clock cycles at the input to the phase detector which is the input clock divided by it's corresponding P divider. This is translated to a time based on the frequency of the corresponding phase detetor input clock. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility.

Figure 5.7. LOS Clock Maximum (Trigger) and Minimum (Clear) Period Thresholds

The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register when set, always stays asserted until cleared by the user.

Monitor

LOS

Live

LOS

Sticky

Figure 5.8. LOS Status Indicators

A LOS monitor is also available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when LOSXAXB is detected. This feature can be disabled such that the device will continue to produce output clocks even when LOSXAXB is detected. Single-ended inputs must be connected to the XA input pin with the XB pin terminated properly for LOSXAXB to function correctly. The table below lists the loss of signal status indicators and fault monitoring control registers.

Table 5.8. Loss of Signal Status Monitoring and Control Registers

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

LOS Status Indicators

LOS(3,2,1,0) 000D[3:0] 000D[3:0] LOS status monitor for IN3, IN2, IN1, IN0. Indicates if a

valid clock is detected or if a LOS condition is present.

LOSXAXB 000C[1] 000C[1] LOS status monitor for the XTAL or REFCLK at the

XA/XB pins.

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+ 287 hidden pages

Silicon Laboratories Si5397 Series, Si5396 Series, Si5397L/M, Si5397A/B, Si5396A/B Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Work Flow Using ClockBuilder Pro and the Register Map

1.1 Field Programming

2. Family Product Comparison

3. Functional Description

3.1 DSPLL and MultiSynth

3.1.1 Dividers

3.1.2 DSPLL Loop Bandwidth

3.1.2.1 Fastlock Feature

3.1.2.2 Holdover Exit Bandwidth

4. Modes of Operation

4.1 Reset and Initialization

4.2 Dynamic PLL Changes

4.3 NVM Programming

4.4 Free Run Mode

4.5 Lock Acquisition Mode

4.6 Locked Mode

4.7 Holdover Mode

5. Clock Inputs

5.1 Input Source Selection

5.1.1 Manual Input Switching

5.1.2 Automatic Input Switching

5.2 Types of Inputs

5.2.1 Unused Inputs

5.2.2 Hitless Input Switching with Phase Buildout

5.2.3 Ramped Input Switching

5.2.4 Hitless Switching, LOL (Loss of Lock) and Fastlock

5.2.5 External Clock Switching

5.2.6 Synchronizing to Gapped Input Clocks

5.2.7 Rise Time Considerations

5.3 Fault Monitoring

5.3.1 Input Loss of Signal (LOS) Fault Detection