Silicon Laboratories Si5372 User Manual

UG372: Si5372 Evaluation Board User’s
Guide

The Si5372-EVB is used for evaluating the Si5372 Any-Frequency, Any-Output, Jitter
Attenuating
synth™ technologies to enable any-frequency clock generation for applications that re-

quire the highest level of jitter performance. There are two different EVBs for the
Si5372. There is an A grade which uses an external XTAL reference and there is a J
grade which has an internal XTAL reference. This user guide is intended for all ver­sions of the Si5372 EVB. The device grade and revision is distinguished by a white 1
inch x 0.187 inch label installed in the lower left hand corner of the board. In the exam­ple below, the label "SI5372J-A-EB" indicates the evaluation board has been assem­bled with an Si5372 device, Grade J, Revision A, installed. (For ordering purposes on­ly, the terms “EB” and “EVB” refer to the board and the kit respectively. For the purpose
of this document, the terms are synonymous in context.)The device The Si5372-EVB
has two independent input clocks and four independent output clocks. The Si5372-EVB

can be controlled and configured using the ClockBuilderPro™ (CBPro) software tool.

Clock Multiplier. The Si5372 combines 4th generation DSPLL and Multi-

EVB FEATURES:

• Si5372A-A-EB for evaluating external
XTAL version Si5372A

•

Onboard 48 MHz XTAL or Reference
SMA Inputs allow holdover mode of
operation on the Si5372.

• Si5372J-A-EB for evaluating internal XTAL
version Si5372J

• Powered from USB port or external power
supply.

•

CBPro™ GUI-programmable VDD supply
allows the device to operate from 3.3, 2.5,
or 1.8 V.

• CBPro GUI-programmable VDDO supplies
allow each of the ten outputs to have its
own supply voltage, selectable from 3.3,

2.5, or 1.8 V.

• CBPro GUI-controlled voltage, current,
and power measurements of VDD and all
VDDO supplies.

• Status LEDs for power supplies and
control/status signals of Si5372.

• SMA connectors for input clocks, output
clocks, and optional external timing
reference clock.

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UG372: Si5372 Evaluation Board User’s Guide

Functional Block Diagram

1. Functional Block Diagram

A functional block diagram of the Si5372-EVB is shown below. Keep in mind the J grade does not use an external XTAL or reference
and does not use the XA/XB pins. This EVB can be connected to a PC via the main USB connector for programming, control, and
monitoring. See or Section 2. Quick Start for more information.

Main USB

Connector

Ext +5V

Connector

Input Clock 0

Input Clock 1

C8051F380

MCU

+

Peripherals

{
{

Power only

48 MHz

XTAL

Input

Termination

Input

Termination

+5V_USB

Power Supply

+5V_Ext

VDDMCU
I2C/SPI Bus

I2C/SPI Bus

Control/

Status

INTR
Alarm_Status

XA
XB

IN_0

IN_0B

IN_1

IN_1B

Si5372

VDD_Core

VDD_Core

VDDO_0

VDD_3.3

VDDO_0

VDD_3.3

VDDO_1

VDDO_2

VDDO_3

VDDO_1

VDDO_2

VDDO_3

OUT_0

OUT_0B

OUT_1

OUT_1B

OUT_2

OUT_2B

OUT_3

OUT_3B

Output

Termination

Output

Termination

Output

Termination

Output

Termination

Output Clock 0

}

Output Clock 1

}

Output Clock 2

}

Output Clock 3

}

Figure 1.1. Si5372-EVB Functional Block Diagram

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UG372: Si5372 Evaluation Board User’s Guide

2. Quick Start

1. Install ClockBuilderPro™ desktop software: http://www.silabs.com/CBPro.

• Installation instructions and the user’s guide for ClockBuilderPro can also be found at the download link shown above.

2. Connect a USB cable from the Si5372-EVB to the PC where the software is installed.

3. Leave the jumpers as installed from the factory, and launch the ClockBuilderPro™ software.

4. You can use ClockBuilderPro™ to create, download, and run a frequency plan on the Si5372-EVB.

5. Contact Silicon Labs for the Si5372 data sheet.

Quick Start

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3. Jumper Defaults

UG372: Si5372 Evaluation Board User’s Guide

Jumper Defaults

Table 3.1. Si5372 EVB Jumper Defaults

Location Type I = Installed

0 = Open

JP1 2 pin I JP14 2 pin O

JP2 2 pin I JP15 2 pin O

JP3 2 pin O JP16 3 pin all open

JP4 2 pin O JP17 3 pin all open

JP5 3 pin 1 to 2 JP18 2 pin O

JP6 2 pin O JP19 2 pin O

JP7 2 pin O JP20 3 pin all open

JP8 2 pin O JP21 3 pin all open

JP9 2 pin O JP22 2 pin O

JP10 2 pin O JP23 2 pin O

JP11 2 pin O JP24 3 pin all open

JP12 2 pin O

JP13 2 pin O JP17 5x2 Hdr All 5 installed

Note:

1.

Refer to the Si5372 EVB Schematics for the functionality associated with each jumper.

Location Type I = Installed

0 = Open

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UG372: Si5372 Evaluation Board User’s Guide

Status LEDs

4. Status LEDs

Table 4.1. Si5372 EVB Status LEDs

Location Silkscreen Color Status Function Indication

D5 INTRB Blue DUT Interrupt

D7 LOLB Blue DUT Loss of Lock

D8 LOSXAXBB Blue DUT Loss of Reference

D11 +5V MAIN Green Main USB +5 V present

D12 READY Green MCU Ready

D13 BUSY Green MCU Busy

D11 is illuminated when USB +5 V supply voltage is present. D12 and D13 are status LEDs showing on-board MCU activity.

Figure 4.1. Status LEDs

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UG372: Si5372 Evaluation Board User’s Guide

External Reference Input (XA/XB)

5. External Reference Input (XA/XB)

An external reference (XTAL) is required for Grade A in combination with the internal oscillator to produce an ultra-low jitter reference
clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. The Si5372-EVB for these versions can
also accommodate an external reference clock instead of a crystal. To evaluate the device with a REFCLK, C93 and C94 must be
populated and the XTAL removed (see the figure below). The REFCLK can then be applied to J25 and J26. In the case of the

Si5372J-A which is the grade with the internal XTAL, there will be no external XTAL supplied on the board and no input from
Ref_XA and Ref_XB. In this case it is advised to remove any resistor connections to XTAL1 and XTAL2 on component Y1.

Figure 5.1. External Reference Input Circuit

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UG372: Si5372 Evaluation Board User’s Guide

Clock Input Circuits (INx/INxB and FB-IN/FB-INB)

6. Clock Input Circuits (INx/INxB and FB-IN/FB-INB)

The Si5372-EVB has four SMA connectors (IN0/IN0B and IN1/IN1B) for receiving external clock signals. All input clocks are terminated,
as shown in the figure below.

Input clocks are ac-coupled and 50 Ω terminated. This represents four differential input clock pairs. Single-ended clocks can be used by
appropriately driving one side of the differential pair with a single-ended clock. See the Si5372 data sheet for details on how to config­ure inputs as single-ended.

Figure 6.1. Input Clock Termination Circuit

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UG372: Si5372 Evaluation Board User’s Guide

Clock Output Circuits (OUTx/OUTxB)

7. Clock Output Circuits (OUTx/OUTxB)

Each of the eight outputs (four differential pairs) is ac-coupled to its respective SMA connector. The output clock termination circuit is
shown in the figure below. The output signal has no dc bias. If dc coupling is required, the ac coupling capacitors can be replaced with
a resistor of appropriate value. The Si5372-EVB provides pads for optional output termination resistors and/or low frequency capacitors.

Note: Components with schematic “NI” designation are not normally populated on the Si5372-EVB and provide locations on the PCB
for optional dc/ac terminations by the end user.

Figure 7.1. Output Clock Termination Circuit

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UG372: Si5372 Evaluation Board User’s Guide

Installing ClockBuilder Pro Desktop Software

8. Installing ClockBuilder Pro Desktop Software

To install the CBOPro software on any Windows 7 (or above) PC, go to http://www.silabs.com/CBPro and download the ClockBuilder
Pro software.

Installation instructions and User’s Guide for ClockBuilder Pro can be found at the download link shown above.

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UG372: Si5372 Evaluation Board User’s Guide

Using Si5372 EVB

9. Using Si5372 EVB

9.1 Connecting the EVB to Your Host PC

Once ClockBuilderPro™ software is installed, connect the software to the EVB with a USB cable, as shown in the figure below.

Figure 9.1. EVB Connection Diagram

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