Silicon Laboratories Si5365-EVB, Si5366-EVB, Si5369-EVB, Si5368-EVB, Si5367-EVB User Manual

Si5365/66-EVB

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Si5367/68-EVB

Si5369-EVB

Si5365/66/67/68/69 E

VALUATION B OARD U SER ’S G UIDE

1. Introduction

The Si5365/66-EVB,Si5367/68-EVB, and Si5369-EVB provide platforms for evaluating Silicon Laboratories'
Si5365/Si5366, Si5367/Si5368, and Si5369 Any-Frequency Precision Clocks. The Si5365 and Si5366 are
controlled directly using configuration pins on the devices, while the Si5367, Si5368, and Si5369 are controlled by
a microprocessor or MCU (microcontroller unit) via an I
clock multipliers with a loop bandwidth ranging from 30 kHz to 1.3 MHz. The Si5366 and Si5368 are jitter­attenuating clock multipliers, with a loop bandwidth ranging from 60 Hz to 8.4 kHz. The Si5369 is similar to the
Si5368, with a much lower loop BW of from 4 to 525 Hz. The Si5366 device can optionally be configured to operate
as a Si5365, so a single evaluation board is available to evaluate both devices. Likewise, the Si5368 can be
configured to operate as a Si5367, so the two devices share a single evaluation board.

The Si5365/66/67/68/69 Any-Frequency Precision Clocks are based on Silicon Laboratories' 3rd-generation
DSPLL
need for external VCXO and loop filter components. The devices have excellent phase noise and jitter
performance. The Si5366, Si5368, and Si5369 jitter attenuating clock multipliers support jitter generation of 0.3 ps
RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. The Si5365 and SI5367 support
jitter generation of 0.6 ps RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. For all
devices, the DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the
application level. These devices are ideal for providing clock multiplication/clock division, jitter attenuation, and
clock distribution in mid-range and high performance timing applications.

®

technology , which pr ovides any-frequen cy synthesis in a highly inte grated PLL solutio n that eliminates the

2

C or SPI interface. The Si5365 and Si5367 are low jitter

Rev. 0.6 1/12 Copyright © 2012 by Silicon Laboratories Si536x-EVB

Figure 1. Si536x TQFP EVB

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

Table 1. Features by Part Number

Device PN

Si5365 4 5 Pin 15 to

Si5367 4 5 I

Si5366 4 5 Pin .008 to

Si5368 4 5 I

Si5369 4 5 I

# Clock Inputs

# Clock Outputs

Control

2

C or

SPI

Any-Frequency Precision Clock Multipliers with Jitter Attenuation

2

C or

SPI

2

C or

SPI

Input Freq

(MHz)

707

10 to

710

707

.002 to

710

.002 to

710

Output Freq

(MHz)

Precision Clock Multipliers

19 to
1050

10 to
1400

.008 to

1050

.002 to

1400

.002 to

1400

Jitter Generation

0.6 ps

rms typ

0.6 ps

rms typ

0.3 ps

rms typ

0.3 ps

rms typ

0.3 ps

rms typ

(12 kHz–20 MHz)

30 kHz–1.3 MHz Y N LOS, FOS 14 x 14

30 kHz–1.3 MHz Y N LOS, FOS 14 x 14

60 Hz–8.4 kHz Y Y LOL, LOS,

60 Hz–8.4 kHz Y Y LOL, LOS,

4 Hz–525 Hz Y Y LOL, LOS,

Prog. Loop BW

Clock Mult.

Hitless Switching

Alarms

FOS

FOS

FOS

Package

100-TQFP

100-TQFP

14 x 14

100-TQFP

14 x 14

100-TQFP

14 x 14

100-TQFP

2. Applications

The Si536x Any-Frequency Precision Clocks have a comprehensive feature set, including any-frequency
synthesis, multiple clock inputs, multiple clock outputs, alarm and status outputs, hitless switching between input
clocks, programmable output clock signal format (LVPECL, LVDS, CML, CMOS), output phase adjustment
between output clocks, and output phase adjustment between all output clocks and the selected reference input
clock (phase increment/decrement). For more details, consult the Silicon Laboratories timing products website at

www.silabs.com/timing.

Both evaluation boards (EVBs) have a Silicon Laboratories MCU (C8051F340) that supports USB communications
with a PC host. For the pin controlled parts (Si5365 and Si5366), the pin settings of the devices are determined by
the MCU and the PC resident software that is provided with the EVB. For the MCU controlled parts (Si5367,
Si5368, and Si5369), the devices are controlled and monitored through the serial port (either SPI or I
sits between the MCU and the Precision Clock device that performs voltage level translation and stores the pin
configuration data for the pin controlled devices. Jumper plugs are provided so that the user can bypass the MCU/
CPLD to manually control the pin controlled devices. Ribbon headers and SMA connectors are included so that
external clock in, clock out and status pins can be easily accessed by the user. For the MCU controlled devices
(Si5367, Si5368, and Si5369)), the user also has the option of bypassing the MCU and controlling the parts from an
external serial device. On-board termination is included so that the user can evaluate either single-ended or
differential as well as ac or dc coupled clock inputs and outputs. A separate DUT (device under test) power supply
connector is included so that the Precision Clocks can be run at either 1.8, 2.5, or 3.3 V, while the USB MCU
remains at 3.3 V. LEDs are provided for convenient monitoring of key status signals.

For more detailed information about these devices, refer to the Any-Frequency Precision Clock Family Reference
Manual.

2

C). A CPLD

2 Rev. 0.6

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

3. Features

The Si5365/66-EVB, Si5367/68-EVB, and Si5369-EVBs each include the following:

 CD with documentation and EVB software including the DSPLLsim configuration software utility
 USB cable
 EVB circuit board including a Si5366 (Si5365/66-EVB), a Si5368 (Si5367/68-EVB), or a Si5369 (Si5369-EVB)
 User's Guide (this document)

4. Si5365/66-EVB, Si5367/68-EVB, and Si5369-EVB Quick Start

1. Install the Precision Clock EVB Driver. (This must be installed before the EVB is connected to the PC via the
USB cable.) For details, see Section "7.EVB Software Installation" on page 12.

2. Install the Precision Clock EVB Software. (Assumes that Microsoft .NET Framework 3.1 is already installed.)

3. Connect the two power supplies to the EVB. One is 3.3 V and the other is either 1.8, 2.5, or 3.3 V. The DUT is
powered by the 1.8/2.5/3.3 V supply.

4. Turn on the power supplies.

5. Connect a USB cable from the EVB to the PC where the software was installed.

6. Install USB driver.

7. Launch software by clicking on Start
and selecting one of the programs.

ProgramsSilicon LaboratoriesPrecision Clock EVB Software

Rev. 0.6 3

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

USB

MCU

SPI bus

CPLD

ss

+3.3 V

DUT PWR

+1.8 V

Vreg

Reset
switch

LEDs

SPI bus

1.8 to 3.3 V

reg addr

Si536x

Output
SMAs

Input
SMAs

Ext RefClk

Jumper
Headers

Terminate

status signals

SPI, I2C signals

Control signals

CKOUT1
CKOUT2

CKOUT3
CKOUT4

FSOUT

5. Functional Description

The Si5365/66-EVB, Si5367/68-EVB, Si5369-EVB, and DSPLLsim software allow for a complete and simple
evaluation of the functions, features, and performance of the Si536x Any-Frequency Precision Clo cks.

5.1. Narrowband versus Wideband Operation

This document describes three evaluation boards: one for the Si5365 and Si5366, another for the Si5367 and
Si5368, and a third for the Si5369. The fi rst evaluation board is for pin controlled clock part s, the second is for clock
parts that are to be controlled by an MCU over a serial port, and the third is for a very low loop bandwidth device
that is also controlled by an MCU. Two of the boards supports two parts: one that is wideband (the Si5365 and the
Si5367) and the one that is narrowband (the Si5366 and the Si5368). The third board only supports the low loop
bandwidth narrowband Si5369. The narrowband parts other than the Si5369 are both capable of op erating in the
wideband mode, so evaluation of the wideband parts can be done by using a narrowband part in wideband mode.
As such, these evaluation boards are only populated with narrowband parts.

To evaluate Si5365 device operation using the Si5365/66-EVB, the RATE[1:0] pins must be set to HH using the
jumper provided. To evaluate Si5367 device operation using the Si5367/68-EVB, the Precision Clock EVB
Software should be configured for wideband mode. For details, see the Precision Clock EVB Software
documentation that can be found on the enclosed distribution CD.

5.2. Block Diagram

Figure 2 is a block diagram of the evaluation board. The MCU communicates to the host PC over a USB
connection. The MCU controls and monitors the Si536x through the CPLD. The CPLD, among other tasks,
translates the signals at the MCU voltage level of 3.3 V to the Si536x's voltage level, which is nominally 3.3, 2.5, or

1.8 V. The user has access to all of the Si536x's pins using the various jumper settings as well as through the host

PC via the MCU and CPLD.

4 Rev. 0.6

Figure 2. Si536x TQFP Block Diagram

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

5.3. Si536x Input and Output Clocks

The Si536x has four differential inputs that are ac terminated to 50  and then ac coupled to the part. Single ended
operation can be implemented by simply not connecting to one of the two of the differential pairs. When operating
with clock inputs of 1 MHz or less in frequency, the appropriate dc blocking capacitors (C58, C61, C47, C50, C53,
C55, C42 and C45) located on the bottom of the board should be replaced with zero ohm resistors. The reason for
this is that the capacitive reactance of the ac coupling capacitors becomes significant at low frequencies. It is also
important that the CKIN signal meet the minumum rise time of 11 ns (CKNtrf) even though the input frequency is
low.

The four clock outputs are all differential, ac coupled and configured for driving 50  transmission lines. When
using single ended outputs, it is important that the unused half of the output be terminated. Given that the
Frame Sync signal can have a duty cycle that is far from 50%, the Frame Sync outputs are dc coupled. If the
Frame Sync or other clock ouputs signals are configured for CMOS, then the two outputs are not complements of
one another and should be wired in parallel so that the output drive current is doubled. To evaluate CMOS level
Frame Sync outputs, a 0  resistor should be installed at R19. Note that for the MCU controlled parts that support
Frame Sync mode (Si5367 and Si5368), the Frame Sync output signal format can be configured independently of
the other four outputs.

Two jumpers are provided to assist in monitoring the Si536x power. When R36 is removed, J25 can be used to
measure the device current. J18 can be used at any time to monitor the supply voltage at the device.

The Si5366, Si5368, and Si5369 require that an external reference clock be provided to enable the devices to
operate as narrowband jitter attenuato rs with loop bandwid ths as low as 60 Hz (as low as 4 Hz for the Si5369). The
external reference clock can be either a crystal, a stand-alone oscillator or some other clock source. The range of
acceptable reference frequencies is described in the Any-Frequency Precision Clocks Family Reference Manual
(Si53xx-RM). The EVB's are shipped with a 3rd overtone 114.285 MHz crystal that is used in the majority of
applications. J1 and J2 are used when the Si536x is to be configured in narrowband mode with an external
reference oscillator (i.e., without using the 114.285 MHz crystal).

The RATE pins should also be configured for the desired mode, either through DSPLLsim or using the jumper
plugs at J17 (see Table 7 on page 11).

Table 2 shows how the various components should be configured for the three modes of operation:

Table 2. Reference Input Mode

Mode

Xtal

Input 1 NC

1

3

38.88 MHz Ext

2

Ref

J1 NC

Wideband

Input 2 NC J2 NC

C39 NOPOP

4

install install

C22 NOPOP install NOPOP
R50 NOPOP NOPOP install

R28 install NOPOP NOPOP
RATE0 M—H
RATE1 M—H

Notes:

1. Xtal is 1 14.285 MHz 3rd overtone.

2. For external reference frequencies and RATE pin settings, see the

Any-Frequency Precision Clock Family Reference Manual.

3. NC—no connect.

4. NOPOP—do not install this component.

For a differential external reference, connect the balanced input signals to J1 and J2. For single-ended operation,
connect the input signal to J1 and disconnect J2.

R51 is provided so that a different termination scheme can be used. If R51 is populated, then remove R52 and R24.

Rev. 0.6 5

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

MCU CPLD Si5367, Si5368

SS_CPLD_B

SCLK

MOSI

MISO

SS_B

SCLK

SDI

SDO

DUT_PWR

+3.3 V

5.4. CPLD

This CPLD is required for the MCU to control an Si536x operating at either 1.8, 2.5, or 3.3 V. The CPLD provides
two main functions: it translates the voltage level from 3.3 V (the MCU voltage) to the Si536x voltage (either 1.8,

2.5, or 3.3 V). The MCU communicates to the CPLD with the SPI signals SS_CPLD_B (slave select), MISO
(master in, slave out), MOSI (master out, slave in) and SCLK. The MCU can talk to CPLD-resident registers that
are connected to pins that control the Si536x's pins, mainly for pin control mode. When the MCU wishes to ac ce ss
a Si536x register, the SPI signals are passed through the CPLD, while being level translated, to the Si536x. The
CPLD is an EE device that is retains its code that is loaded through the JTAG port (J32). The core of the CPLD
runs at 1.8 V , which is p rovided by volt age regulator U4. Th e CPLD also log ically co nnect s many of the LEDs to the
appropriate Si536x pins.

Figure 3. SPI Mode Serial Data Flow

5.5. MCU

The MCU communicates with the PC over USB so that PC resident software can be used to control and monitor
the Si536x. The USB connector is J6 and the debug port, by which the MCU is flashed, is J31. The reset switch,
SW1, resets the MCU, but not the CPLD. The MCU is a self-contained USB master and runs all of the code
required to control and monitor the Si536x, both in the MCU mode and in the pin-controlled modes.

U3 contains a unique serial number for each board and U5 is an EEPROM that is used to store configuration
information for the board. The board powe rs up in free ru n mode with a con figuration that is outlin ed in "Appendix—
Powerup and Factory Default Settings" on page 25. For the pin controlled parts (Si5365/66-EVB), the contents of
U5 configure the board on power up so that jumper plugs may be used. If DSPLLsim is subsequently run, the
jumper plugs should be removed before DSPLLsim downloads the configuration to the EVB so that the jumpers do
not conflict with the CPLD outputs. Fo r microproce ssor parts, U5 configures the EVB for a specific frequency plan
as described in "Appendix—Powerup and Factory Default Settings" on page 25.

The Evaluation board has a serial port connector (J22) that supports the following:

 Control by the MCU/CPLD of an Any-Frequency part on an external target board.
 Control of the Any-Frequency part that is on the Evaluation board through an external SPI or I

For details, see J22 (Table 6).
Though they are not needed on this Evaluation Board because the CPLD has low output leakage current, some

applications will require the use of external pullup and pulldown resistors when three level pins are being driven by
external logic drivers. This is particularly true for the pin-controlled parts: the Si5365 and Si5367. Consult the
Si53xx-RM Any-Frequency Precision Clock Family Reference Manual for details.

LVPECL outputs will not function at 1.8 V. If the Si536x part is to be operated at 1.8 V, the output format
needs to be changed by altering either the SFOUT pins (Si5365/66) or the SFOUT register bits (Si5367/68/

69).

6 Rev. 0.6

2

C port.

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

5.6. Power and 2L Signals

This evaluation board requires t wo power inputs +3.3 V for the MCU and either 1.8, 2.5, or 3.3 V for the Any­Frequency Precision Clock part. The power connector is J40. The grounds for the two supplies ar e tied together on
the EVB. There are sixteen LEDs, as described in Table 3. J14 is a three by 10 pin male header by which the user
can manually set the values of the two-level inputs using jumper plugs connected to either ground (silkscreen
labeled L) or the power supply (labeled H). J8 is a twenty pin ribbon header that brings out all of the status outputs
from the Si536x. Note that some pins are shared and serve as both inputs and outputs, depending on how the
device is configured. For users that wish to remotely access the input and output pins settings with external
hardware, J14 and J8 can be connected to ribbo n ca ble s.

5.7. 3L Pins

The three-level inputs can all be manually configured by installing jumper plugs at J17, either H or L. The M level is
achieved by not installing a jumper plug at a given location. J17 can also be used as a connection to an external
circuit that controls these pins. J22 is a ten pin ribbon header that is provided so that an external processor can
control the Si536x over either the SPI or I

2

C bus.

Rev. 0.6 7

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

6. Connectors and LEDs

6.1. LEDs

There are sixteen LEDs on the board which provide a quick and convenient means of determining board status.

Table 3. LED Status and Description

LED Color Label LED Color Label

D1 green 3.3 V D2 red LOL
D3 green DUT_PWR D4 red C1B
D5 red ALRMOUT D6 red C2B
D7 yellow CPLD_2 D8 red C3B

D9 yellow CPLD_1 D10 green C1A
D11 red MCU_3 D12 green C2A
D13 red MCU_2 D14 green C3A
D15 red MCU_1 D16 green C4A

8 Rev. 0.6

Si5365/66-EVB Si5367/68-EVB Si5369-EVB

R24, R28, C22 on top;
R50, R51, R52, C39 on bot

J18

Ext Ref, J1, J2

J17

J14

J8

J22

J25, R36

C22

R24, R28, C22 on top;
R50, R51, R52, C39 on bot

J18

Ext Ref, J1, J2

J17

J14

J8

J22

J25, R36

C22

6.2. User Jumpers and Headers.

Use Figure 4 to locate the jumpers described in Tables 4, 5, 6, and 7:

Figure 4. Connectors, Jumper Header Locations

J25 assists in measuring the Any-Frequency Precision Clock current draw. If J25 is to be used, R36 should be
removed.

Rev. 0.6 9