Silicon Laboratories SI5351A-B-C User Manual
Si5351A/B/C
Si5351A
Multi
Synth
N
N = 2 or 7
I
2
C
SSEN
OEB
Multi
Synth
0
Multi
Synth
1
Si5351B
PLL
VC
VCXO
I2C
SSEN
OEB
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
Si5351C
PLLA
CLKIN
PLLB
I2C
INTR
OEB
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
XA
XB
OSC
XA
XB
OSC
PLLB
PLLA
XA
XB
OSC
10-MSOP
24-QSOP
20-QFN
I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK
GENERATOR + VCXO
Features
Generates up to 8 non-integer-rel ated
I
Exact frequency synthesis at each output
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: 100 ps pp
Configurable spread spec trum selectable
Operates from a low-cost, fixed frequency
Supports static phase offset
Programmable rise/fall time contro l
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equip me nt, gaming
Printers, scanners, projectors
Description
The Si5351 is an I2C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. The Si5351B eliminates the need for high er cost, custom pullable
crystals while providing reliable operation over a wide tuning range. The Si5351C offers
the same flexibility but synchronizes to an external reference clock (CLKIN).
frequencies from 8 kHz to 160 MHz
2
C user definable configuration
(0 ppm error)
at each output
crystal: 25 or 27 MHz
Glitchless frequency changes
Separate voltage supply pins:
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates extern al
power supply filtering
Very low power consumption
Adjustable output-output delay
Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
Residential gatew ays
Networking/communication
Servers, storage
XO replacement
Ordering Information:
See page 66
Functional Block Diagram
Preliminary Rev. 0.95 8/11 Copyright © 2011 by Silicon Laboratories Si5351A/B/C
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5351A/B/C
2 Preliminary Rev. 0.95
Si5351A/B/C
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .19
5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.6. Replacing a Crystal with a Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . .62
10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . .63
11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . .64
12. Si5351A Pin Descriptions (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
14. Package Outline (24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
15. Package Outline (20-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
16. Package Outline (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
21
Preliminary Rev. 0.95 3
Si5351A/B/C
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature T
A
–402585°C
3.0 3.3 3.60 V
Core Supply Voltage V
DD
2.25 2.5 2.75 V
1.71 1.8 1.89 V
Output Buffer Voltage V
DDOx
2.25 2.5 2.75 V
3.0 3.3 3.60 V
Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
VDD and VDDOx can be operated at independent voltages.
Power supply sequencing for VDD and VDDOx requires that both voltage rails are powered at the same time.
Table 2. DC Characteristics
(VDD= 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Enabled 3 outputs — 22 35 mA
Core Supply Current I
Output Buffer Supply Current
(Per Output)*
DD
I
DDOx
Enabled 8 outputs — 27 45 mA
Power Down (PDN = V
)— — 20 µA
DD
CL=5pF — 2.2 5 mA
CLKIN, SDA, SCL
Vin < 3.6 V
VC — — 30 µA
Input Current
I
CLKIN
I
VC
8 mA output drive current.
Output Impedance Z
O
See "6. Design Consider-
ations" on page 21.
*Note: Output clocks less than or equal to 10 0 MHz.
4 Preliminary Rev. 0.95
——10 µA
—85—
Si5351A/B/C
Table 3. AC Characteristics
(VDD= 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
From VDD=V
Power-up Time T
RDY
output clock, C
f
>1MHz
CLKn
From OEB pulled low to valid
Output Enable Time T
Output Phase Offset P
Spread Spectrum Frequency
Deviation
Spread Spectrum Modulation
Rate
SS
SS
OE
STEP
DEV
MOD
clock output, C
f
>1MHz
CLKn
Down spread –0.1 — –2.5 %
Center spread ±0.1 — ±1.5 %
VCXO Specifications (Si5351B onl y)
VCXO Control Voltage Range Vc 0 V
VCXO Gain (configurable) Kv Vc = 10–90% of V
VCXO Control Voltage Linearity KVL Vc = 10–90% of V
VCXO Pull Range
(configurable)
PR V
= 3.3 V* ±30 0 ±240 ppm
DD
VCXO Modulation Bandwidth — 10 — kHz
*Note: Contact Silicon Labs for 2.5 V VCXO operation.
to valid
DDmin
=5pF,
L
=5pF,
L
—110ms
——10 µs
— 333 — ps/step
30 31.5 33 kHz
/2 V
DD
, VDD = 3.3 V 18 — 150 ppm/V
DD
DD
–5 — +5 %
DD
V
Table 4. Input Clock Characteristics
(VDD= 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
CLKIN Input Low Voltage V
CLKIN Input High Voltage V
CLKIN Frequency Range f
CLKIN
IL
IH
–0.1 — 0.3 x V
0.7 x V
DD
—3.60V
DD
10 — 100 MHz
V
Preliminary Rev. 0.95 5
Si5351A/B/C
Table 5. Output Clock Characteristics
(VDD= 2.5 V ±10%, or 3.3 V ±10%, TA=–40 to 85°C)
Parameter Symbol Test Condition Min Typ Max Units
Frequency Range F
CLK
Load Capacitance C
Duty Cycle DC
t
Rise/Fall Time
t
Output High Voltage V
Output Low Voltage V
Period Jitter J
Period Jitter VCXO J
Cycle-to-Cycle Jitter J
Cycle-to-Cycle Jitter
VCXO
RMS Phase Jitter J
RMS Phase Jitter VCXO J
OH
OL
PER
PER_VCXO
CC
J
CC_VCXO
RMS
RMS_VCXO
0.008 — 160 MHz
L
Measured at V
f
=50MHz
CLK
r
f
20%–80%, CL=5pF,
Drive Strength = 8 mA
DD
/2,
—515pF
45 50 55 %
0.5 1 1.5 ns
0.5 1 1.5 ns
– 0.6 — — V
V
DD
CL=5pF
——0.6V
— 35 100 ps pk-pk
Measured over 10k cycles
— 60 110 ps pk-pk
—3090ps pk
Measured over 10k cycles
—5095ps pk
— 3.5 11 ps rms
12 kHz–20 MHz
— 8.5 18.5 ps rms
Table 6. Crystal Requirements
Parameter
Crystal Frequency f
Load Capacitance C
Equivalent Series Resistance r
Crystal Max Drive Level d
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors.
2. Refer to “AN551: Crystal Selection Guide” for more details.
1,2
Symbol Min Typ Max Unit
XTAL
L
ESR
L
25 — 27 M Hz
6—12pF
——150
——100µW
6 Preliminary Rev. 0.95
Si5351A/B/C
Table 7. I2C Specifications (SCL,SDA)
Parameter
LOW Level
Input Voltage
HIGH Level
Input Voltage
Hysteresis of
Schmitt Trigger
Inputs
LOW Level
Output Voltage
(open drain or
open collector)
at 3 mA Sink
Current
Input Current I
Capacitance for
Each I/O Pin
2
I
C Bus
Timeout
Symbol Test Condition Standard Mode
V
–0.5
ILI2C
V
IHI2C
V
HYS
2
= 2.5/3.3 V 0 0.4 0 0.4 V
2
V
DDI2C
= 1.8 V — — 0 0.2 x V
2
V
OLI2C
II2C
C
VIN= –0.1 to V
II2C
T
TO
V
DDI2C
Timeout Enabled 25 35 25 35 ms
1
DDI2C
Fast Mode
100 kbps
Min Max Min Max
0.7 x V
C
0.3 x V
DDI2
DDI2
C
3.63 0.7 x V
400 kbps
–0.5 0.3 x V
2
DDI2C
DDI2C
3.63 V
Unit
2
V
——0.1 —V
DDI2C
V
–10 10 –10 10 µA
—4 — 4pF
Notes:
1. Refer to NXP’s UM10204 I
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
2
C-bus specification and user manual, revision 03, for further details, go to:
Table 8. Thermal Characteristics
Parameter Symbol Test Condition Package Value Unit
10-MSOP 131 °C/W
Thermal Resistance
Junction to Ambient
Thermal Resistance
Junction to Case
JA
JC
Still Air
Still Air
24-QSOP 80 °C/W
20-QFN 51 °C/W
10-MSOP 43 °C/W
24-QSOP 31 °C/W
20-QFN 16 °C/W
Preliminary Rev. 0.95 7
Si5351A/B/C
Table 9. Absolute Maximum Ratings
1
Parameter Symbol Test Condition Value Unit
DC Supply Voltage V
Input Voltage
Junction Temperature T
Soldering Temperature (Pb-free
profile)
Soldering Temperature Time at
TPEAK (Pb-free profile)
Notes:
2
2
1. Permanent de vice damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
DD_max
V
IN_CLKIN
V
IN_VC
V
IN_XA/B
T
PEAK
T
CLKIN, SCL, SDA –0.5 to 3.8 V
VC –0.5 to (VDD+0.3) V
Pins XA, XB –0.5 to 1.3 V V
J
P
–0.5 to 3.8 V
–55 to 150 °C
260 °C
20–40 Sec
8 Preliminary Rev. 0.95
2. Detailed Block Diagrams
PLL
B
PLL
A
SDA
SCL
OSC
XA
XB
VDDO
R0
R1
CLK0
CLK1
R2
CLK2
Mu lt iSynth
0
Mu lt iSynth
1
Mu lt iSynth
2
VDD
GND
10-MSOP
Si5351A 3-Output
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSynth
0
MultiSynth
1
MultiSynth
2
MultiSynth
3
Mu lt iSynth
4
Mu lt iSynth
5
Mu lt iSynth
6
Mu lt iSynth
7
VDD
GND
20-QFN, 24-QSOP
SCL
A0
SDA
Control
Logic
OEB
SSEN
I2C
Interface
Si5351A 8-Output
I2C
Interfa ce
PLL
B
PLL
A
OSC
XA
XB
Si5351A/B/C
Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices
Preliminary Rev. 0.95 9
Si5351A/B/C
OSC
XA
XB
PLL
VCXO
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSynth
0
MultiSynth
1
MultiSynth
2
MultiSynth
3
MultiSynth
4
MultiSynth
5
MultiSynth
6
MultiSynth
7
VC
VDD
GND
Si5351B
SCL
SDA
Control
Logic
OEB
SSEN
I2C
Interface
20-QFN, 24-QSOP
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSynth
0
MultiSynth
1
MultiSynth
2
MultiSynth
3
MultiSynth
4
MultiSynth
5
MultiSynth
6
MultiSynth
7
VDD
GND
Si5351C
PLL
A
PLL
B
XA
XB
OSC
CLKIN
SCL
SDA
Control
Logic
INTR
OEB
I2C
Interface
20-QFN, 24-QSOP
Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices
10 Preliminary Rev. 0.95
Si5351A/B/C
Input
Stage
Synthesis
Stage 1
PLL B
(VCXO)
PLL A
(SSC)
VC
VCXO
XA
XB
OSC
XTAL
CLKIN
Div
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
Synthesis
Stage 2
R0
R1
R2
R3
R4
R5
R6
R7
Output
Stage
CLK0
CLK1
VDDOA
CLK2
CLK3
VDDOB
CLK4
CLK5
VDDOC
CLK6
CLK7
VDDOD
XA
XB
Selectable internal
load capacitors
6 pF, 8 pF, 10 pF
C
L
C
L
C
L
Optional
Additional external
load capacitors
(<
2 pF)
C
L
3. Functional Description
The Si5351 is a versatile I2C programmable clock generator that is ideally suited for replacing crystals, crystal
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a clock input (CLKIN), or a control voltage input (VC)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 8 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
Figure 3. Si5351 Block Diagram
3.1. Input Stage
3.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors (C
to the Si5351. Options for internal load capacitors are 6, 8, or 10 pF. Crystals with alternate load capacitance
requirements are supported using additional external load capacitors as shown in Figure 4. Refer to application
note AN551 for crystal recommendations.
) are provided to eliminate the need for external components when connecting a crystal
L
Figure 4. External XTAL with Optional Load Capacitors
Preliminary Rev. 0.95 11
Si5351A/B/C
CLK0
VC
Multi
Synth
2
CLK1
CLK2
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
frequencies
XA XB
OSC
VCXO
Multi
Synth
1
Multi
Synth
0
Control
Voltage
Fixed Frequency
Crystal (non-pullable)
The clock frequency
generated from CLK0 is
controlled by the VC input
R2
R1
R0
3.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL inp ut freq uen cy to
30 MHz.
3.1.3. Voltage Control Input (VC)
The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, lowcost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 3 on page 5 for VCXO specification details.
A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 9 on page 15.
3.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock. The second stage uses highresolution MultiSynth fractional dividers to generate frequencies in the range of 1 MHz to 100 MHz. It is also
possible to generate two unique frequencies up to 160 MHz on two or more of the outputs.
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of the PLLs to lock to a diff erent source for g enerating in dependent fr ee-running and synchronous
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronou s or non-synchronous clocks, with spre ad spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
Since the VCXO already generates a high-frequency intermediate clock, it is fed directly into the second stage of
synthesis. The MultiSynth high-resolution dividers synthesize the VCXO center frequency to any frequency in the
range of ~391 kHz to 160 MHz. The center frequency is then controlled (or pulled) by the VC input. An interesting
feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This creates a
VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.
Frequencies down to 8 kHz can be generated by applying the R divider at the output of the Multisynth (see
Figure 5 below).
Figure 5. Using the Si5351 as a Multi-Output VCXO
3.3. Output Stage
An additional level of division (R) is available at the output stage for generating clocks as low as 8 kHz. All output
drivers generate CMOS level outputs with sep arate output volt age supply pins (VDDOx) allowing a dif ferent vo ltage
signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.
12 Preliminary Rev. 0.95
Si5351A/B/C
f
c
Reduced
Amplitude
and EMI
Down Spread
f
c
Reduced
Amplitude
and EMI
Center Spread
f
c
No Spread
Spectrum
Center
Frequency
Amplitude
3.4. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). E nab ling spre ad spectrum on a n output clock modu lates its
frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB
Layout Guide” for details. Note that spread spectrum is not available on clocks synchronized to PLLB or to the
VCXO.
The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise
between system performance and EMI comp lia nce .
Figure 6. Available Spread Spectrum Profiles
3.5. Control Pins (OEB, SSEN)
The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.
3.5.1. Output Enable (OEB)
The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is
held low, an d disabled when pulle d high. When disabled, the output state is configur able as disa bled high , disa bled
low, or disabled in high-impedance.
The output enable control circuitry ensures glitchless op eration by st arting th e output clock cycle on the first lea ding
edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before
going into a disabled state.
3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only
This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread
spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of
evaluating the effect of using spread spectrum clocks during EMI compliance testing.
Preliminary Rev. 0.95 13
Si5351A/B/C
SCL
VDD
SDA
I2C Bus
INTR
A0
I
2
C Address Select:
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Si5351
>1k
>
1k
4.7 k
Slave Address
1 1 0 0 0 0 0/1
A0
0123456
4. I2C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
2
I
C interface. The following is a list of the common features that are controllable through the I2C interface. A
summary of register functions is shown in Section 7.
Read Status Indicators
Loss of signal (LOS) for the CLKIN input
Loss of lock (LOL) for PLLA and PLLB
Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectru m profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Enable/disable for each clock output
Invert/non-invert for each clock output
Output divider values (2
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
The I2C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
2
The I
C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
2
I
C specification.
n
, n=1.. 7)
Figure 7. I2C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
require more than one Si5351 on a single I
2
C bus.
Figure 8. Si5351 I2C Slave Address
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7bit device (slave) address + a write b it, an 8-bit register ad dress, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
14 Preliminary Rev. 0.95
Si5351A/B/C
1 – Read
0 – Write
A – Acknowledge (SDA LOW )
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP c o n d it io n
From slave to master
From master to slave
Write Operation – Single Byte
S 0 A Re g A ddr [7:0 ]Slv Addr [6:0] A Da ta [7:0] PA
Write Operation - Burst (Auto Address Increment)
Reg Addr +1
S 0 A Re g A ddr [7:0 ]Slv A d d r [6 :0 ] A Data [7 :0] A Da ta [ 7 :0 ] PA
1 – Read
0 – Write
A – Acknowledge (SDA LOW )
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP c o n d it io n
From slave to master
From master to slave
Re a d O pera tio n – Sin gle B y te
S 0 A Re g A ddr [7:0 ]Slv Addr [6:0] A P
Re ad Ope ra tion - Burs t (Auto Add res s In c re ment)
Reg Addr +1
S 1 ASlv A d d r [6 :0 ] Data [7 :0 ] PN
S 0 A R e g A ddr [7:0 ]Slv A d d r [6 :0 ] A P
S 1 ASlv A d d r [6 :0 ] Data [7 :0 ] A PNData [7 :0 ]
Figure 9. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10.
Figure 10. I2C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 7. The timing specifications and
timing diagram for the I
with SMBus interfaces.
2
C bus is compatible with the I2C-Bus Standard. SDA timeout is supported for compatibility
Preliminary Rev. 0.95 15
Si5351A/B/C
Power-Up
I
2
C
RAM
NVM
(OTP)
Default
Config
5. Configuring the Si5351
The Si5351 is a highly flexible clock generator which is entirely configurable through its I2C interface. The device’s
default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time
programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for
applications that need a clock present at power-up (e.g., for providing a clock to a processor).
Figure 11. Si5351 Memory Configuration
During a power cycle the contents of the NVM are copied into random access memory (RAM), which sets the
device configuration that will be used during normal operation. Any changes to the device configuration after
power-up are made by reading and writing to registers in the RAM space through the I
register map is shown in Section "8. Register Descriptions" on page 25.
2
C interface. A detailed
5.1. Writing a Custom Configuration to RAM
To simplify device configuration, Silicon Labs has released the ClockBuilder Desktop. The software serves two
purposes: to configure the Si5351 with optimal configuration based on the desired frequencies and to control the
EVB when connected to a host PC.
The optimal configuration can be saved from the software in text files that can be used in any system, which
configures the device over I
runs on Windows XP, Windows Vista, and Windows 7.
Once the configuration file has been saved, the device can be progr am med via I
Figure 12.
2
C. ClockBuilder Desktop can be downloaded from www.silabs.com/ClockBuilder and
2
C by following the steps shown in
16 Preliminary Rev. 0.95
Disable Outputs
Set CLKx_DIS high; Reg. 3 = 0xFF
Powerdown all output drivers
Reg. 16, 17, 18, 19, 20, 21, 22, 23 =
0x80
Set interrup t masks
(see register 2 description)
Write new configuration to device using
the contents of the register map
generated by ClockBuilder Desktop. This
step also powers up the output drivers.
(Registers 15-92 and 149-170)
Apply PLLA and PLLB soft reset
Reg. 177 = 0xAC
Enable desired outputs
(see Register 3)
Use ClockBuilder
Desktop v3.1 or later
Register
Map
Si5351A/B/C
Figure 12. I2C Programming Procedure
Preliminary Rev. 0.95 17
Si5351A/B/C
48 MHz
USB
Controller
28.322 MHz
125 MHz
Video/Audio
Processor
74.25/1.001 MHz
24.576 MHz
OSC
XA
XB
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
PLL
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
74.25 MHz
27 MHz
Si5351A
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
7
HDMI
Port
Ethernet
PHY
Multi
Synth
6
22.5792 MHz
CLK6
33.3333 MHz
CLK7
CPU
Note: Si5351A replaces crystals, XOs, and PLLs.
5.2. Si5351 Application Examples
The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show
how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.
5.3. Replacing Crystals and Crystal Oscillators
Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies
for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is also available for
applications that require fewer clocks. An example is shown in Figure 13.
Figure 13. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs
18 Preliminary Rev. 0.95
Si5351A/B/C
Ethernet
PHY
USB
Controller
HDMI
Port
28.322 MHz
48 MHz
125 MHz
Video/Audio
Processor
74.25/1.001 MHz
24.576 MHz
OSC
XA
XB
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
PLL
VCXO
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
74.25 MHz
VC
27 MHz
Si5351B
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Free-running
Clocks
Synchronous
Clocks
Note: FBW = 10 kHz
Ethernet
PHY
USB
Controller
HDMI
Port
28.322 MHz
48 MHz
125 MHz
Video/Audio
Processor
74.25/1.001 MHz
24.576 MHz
OSC
XA
XB
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
PLL
PLL
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
74.25 MHz
CLKIN
25 MHz
Si5351C
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
54 MHz
Free-running
Clocks
Synchronous
Clocks
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs
The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video
applications. An example is shown in Figure 14.
Figure 14. Using the Si5351B to Replace Crystals, Crystal Oscillators, VCXOs, and PLLs
5.5. Replacing Crystals, Crystal Oscillators, and PLLs
The Si5350C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO.
Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running
clocks. An example is shown in Figure 15.
Figure 15. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs
Preliminary Rev. 0.95 19
Si5351A/B/C
Multi
Synth
N
Multi
Synth
0
Multi
Synth
1
PLLB
PLLA
XA
XB
OSC
VIN = 1 V
PP
25/27 MHz
Note: Float the XB input while driving
the XA input with a clock
0.1 µF
Multi
Synth
N
Multi
Synth
0
Multi
Synth
1
PLLB
PLLA
OSC
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
R
1
511
240
R
2
ZO = 70
0
HCSL
CLKIN
R
1
511
240
R
2
ZO = 70
0
5.6. Replacing a Crystal with a Clock
The Si5351 can be driven with a clock signal through the XA input pin.
Figure 16. Si5351 Driven by a Clock Signal
5.7. HCSL Compatible Outputs
The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair. See register setting CLKx_INV.
Figure 17. Si5350C Output is HCSL Compatible
20 Preliminary Rev. 0.95
Si5351A/B/C
6. Design Considerations
The Si5351 is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for
additional layout recommendations.
6.1. Power Supply Decoupling/Filtering
The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage
regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 µF
decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and VDDOx
pins as possible without using vias.
6.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. If a minimum output-to-output skew is important, then all VDDOx must be applied
before VDD. Unused VDDOx pins should be tied to VDD.
6.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
6.4. External Crystal Load Capacitors
The Si5351 provides the option of using internal and external crystal load capacitors. If internal load capacitance is
insufficient, capacitors of value <
capacitors are used, they should be placed as close to the XA/XB pads as possible. See AN554 for more details.
2 pF may be used to increased equivalent load capacitance. If external load
6.5. Unused Pins
Unused voltage control pin should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "5.6. Replacing a Crystal with a Clock" on page 20 when using
XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left floating.
Unused VDDOx pins should be tied to VDD.
Preliminary Rev. 0.95 21
Si5351A/B/C
ZO = 85 ohms
Length = No Restrictions
CLK
(Op tio n a l re s ist o r fo r
EMI management)
R = 0 ohms
6.6. Trace Characteristics
The Si5351A/B/C features various output current drives ranging from 2 to 8 mA (default). It is recommended to
configure the trace characteristics as shown in Figure 18 when an output drive setting of 8 mA is used.
Figure 18. Recommended Trace Characteristics with 8 mA Drive Strength Setting
Note: Jitter is only specified at 6 and 8 mA drive strength.
22 Preliminary Rev. 0.95
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