Silicon Laboratories Si5347-EVB User Manual

Si5347-EVB

Si5347 EVALUATION BOARD USER’S GUIDE

Description

The Si5347-EVB is used for evaluating the Si5347
Quad Any-Frequency Jitter Attenuating Clock Multiplier.
The Si5347 contains 4 independent DSPLLs in a single
IC with programmable jitter attenuation bandwidth on a
per DSPLL basis. The Si5347-EVB supports 4
independent input clocks and 8 independent output
clocks via on-board SMA connectors. The Si5347-EVB
can be controlled and configured via a USB connection
to a host PC running Silicon Labs’ next generation
Clock Builder Pro
are provided on-board for external monitoring of supply
voltages.

 (CBPro) software tool. Test points

EVB Features

 Powered from USB port or external +5 V power

supply via screw terminals.

 Onboard 48 MHz XTAL allows standalone or

holdover mode of operation on the Si5347.

 CBPro GUI programmable V

device supply voltages of 3.3, 2.5, or 1.8 V.

 CBPro GUI programmable V

of the 8 outputs to have its own supply voltage
selectable from 3.3, 2.5, or 1.8 V.

 CBPro GUI allows control and measurement of

voltage, current, and power of V
supplies.

 Status LEDs for power supplies and control/status

signals of Si5347.

 SMA connectors for input clocks, output clocks and

optional external timing reference clock.

supply allows

DD

supplies allow each

DDO

and all 8 V

DD

DDO

Rev. 1.1 5/15 Copyright © 2015 by Silicon Labs Si5347-EVB

Figure 1. Si5347 Evaluation Board

Si5347-EVB

Si5347

CLKOUT_0

CLKOUT_0B

Output

Termination

CLKOUT_1

CLKOUT_1B

Output

Termination

CLKOUT_2

CLKOUT_2B

Output

Termination

CLKOUT_3

CLKOUT_3B

Output

Termination

CLKOUT_4

CLKOUT_4B

Output

Termination

CLKOUT_5

CLKOUT_5B

Output

Termination

CLKOUT_6

CLKOUT_6B

Output

Termination

CLKOUT_7

CLKOUT_7B

Output

Termination

Input

Termination

Input

Termination

Input

Termination

Input

Termination

CLKIN_0
CLKIN_0B

CLKIN_1

CLKIN_1B

CLKIN_2

CLKIN_2B

CLKIN_3

CLKIN_3B

Power Supply

C8051F380

MCU

+

Peripherals

I2C/SPI Bus

VDDO_0

VDD_Core

VDD_3.3

VDDO_1

VDDO_2

VDDO_3

VDDO_4

VDDO_5

VDDO_6

VDDO_7

VDDO_0

VDD_Core

VDD_3.3

VDDO_1

VDDO_2

VDDO_3

VDDO_4

VDDO_5

VDDO_6

VDDO_7

Main USB

Connector

Aux USB

Connector

Ext +5V

Connector

FINC

OE_0

OE_0

DSPLL_SEL0

DSPLL_SEL1

FDEC

I2C/SPI Bus

Alarm_Status

INTR

+5V_USB

+5V_Aux

+5V_Ext

VDDMCU

Input Clock 0

{

Input Clock 1

{

Input Clock 2

{

Input Clock 3

{

}

Output Clock 0

}

Output Clock 1

}

Output Clock 2

}

Output Clock 3

}

Output Clock 4

}

Output Clock 5

}

Output Clock 6

}

Output Clock 7

Power only

Power only

XAXB

Crystal / Term

XA

XB

Optional External

XAXB Ref Input {

1. Si5347-EVB Functional Block Diagram

Below is a functional block diagram of the Si5347-EVB. This EVB can be connected to a PC via the main USB
connector for programming, control, and monitoring. See section “3. Quick Start” for more information.

Figure 2. Si5347-EVB Functional Block Diagram

2 Rev. 1.1

Si5347-EVB

2. Si5347-EVB Support Documentation and ClockBuilderPro Software

All Si5347 schematics, BOMs, User’s Guides, and software can be found online at the following link:

http:www.silabs.com/products/clocksoscillators/pages/si538x-4x-evb.aspx

3. Quick Start

1. Install ClockBuilderPro desktop software from EVB support web page given in Section 2.

2. Connect USB cable from Si5347-EVB to PC with ClockBuilderPro software installed.

3. Leave the jumpers as installed from the factory, and launch the ClockBuilderPro software.

4. You can use ClockBuilderPro

5. For the Si5347 data sheet, go to http://www.silabs.com/timing.

4. Jumper Defaults

to create, download, and run a frequency plan on the Si5347-EVB.

Table 1. Si5347 EVB Jumper Defaults

Location Type I = Installed

0 = Open

JP1 2 pin I JP23 2 pin O

JP2 2 pin O JP24 2 pin O

JP3 2 pin I JP25 2 pin O

JP4 2 pin I JP26 2 pin O

JP5 2 pin O JP27 2 pin O

JP6 2 pin O JP28 2 pin O

JP7 2 pin I JP29 2 pin O

JP8 2 pin O JP30 2 pin O

JP9 2 pin O JP31 2 pin O

JP10 2 pin I JP32 2 pin O

JP13 2 pin O JP33 2 pin O

JP14 2 pin I JP34 2 pin O

JP15 3 pin all open JP35 2 pin O

JP16 3 pin 1 to 2 JP36 2 pin O

Location Type I = Installed

0 = Open

JP17 2 pin O JP38 3 pin all open

JP18 2 pin O JP39 2 pin O

JP19 2 pin O JP40 2 pin I

JP20 2 pin O JP41 2 pin I

JP21 2 pin O

JP22 2 pin O J36 5x2 Hdr All 5 installed

Refer to the Si5347-EVB schematics for the functionality associated with each jumper.

Rev. 1.1 3

Si5347-EVB

5. Status LEDs

Location Silkscreen Color Status Function Indication

Table 2. Si5347-EVB Status LEDs

D27 5VUSBMAIN

D22 3P3V

D26 VDD DUT

D25 INTR

D21 READY

D24 BUSY

D2 LOS_XAX-

B_B

D5 LOL_AB

D6 LOL_BB

D8 LOL_CB

D11 INTRB

D12 LOL_DB

D27, D22, and D26 are illuminated when USB +5 V, Si5347 +3.3 V, and Si5347 Vcore supply voltages,
respectively, are present. D25, D21, and D24 are status LEDs showing on-board MCU activity. D2 indicates loss of
signal at XAXB input (either crystal osc or external reference). D5, D6, D8, D12 indicate loss of lock for one of 4
internal DSPLLs (A–D). D11 indicates Si5347 interrupt output is active (as configured by Si5347 register
programming). LED locations are highlighted below with LED function name indicated on board silkscreen.

Blue Main USB +5 V present

Blue DUT +3.3 V is present

Blue DUT VDD Core voltage present

Red MCU INTR (Interrupt) active

Green MCU Ready

Green MCU Busy

Blue Loss of Signal at XAXB input

Blue Loss of Lock - DSPLL A

Blue Loss of Lock - DSPLL B

Blue Loss of Lock _ DSPLL C

Blue Si5347 Interrupt Active

Blue Loss of Lock _ DSPLL D

4 Rev. 1.1

Si5347-EVB

Figure 3. Si5347-EVB LED Locations

Rev. 1.1 5

Si5347-EVB

6. External Reference Input (XA/XB)

An external timing reference (48 MHz XTAL) is used in combination with the internal oscillator to produce an
ultra-low jitter reference clock for the DSPLL and for providing a stable reference for the free-run and holdover
modes. The Si5347-EVB can also accommodate an external reference clock instead of a crystal. To evaluate the
device with an external REFCLK, C111 and C113 must be populated and XTAL Y1 removed (see Figure 4 below).
The REFCLK can then be applied to SMA connectors J39 and J40.

Figure 4. External Reference Input Circuit

6 Rev. 1.1

Si5347-EVB

7. Clock Input Circuits (INx/INxB)

The Si5347-EVB has eight SMA connectors (IN0-IN0B—IN3./IN3B) for receiving external clock signals. All input
clocks are terminated as show in Figure 5 below. Note input clocks are AC coupled and 50  terminated. This
represents 4 differential input clock pairs. Single-ended clocks can be used by appropriately driving one side of the
differential pair with a single-ended clock. For details on how to configure inputs as single-ended, please refer to
the Si5347 data sheet.

Figure 5. Input Clock Termination Circuit

8. Clock Output Circuits (OUTx/OUTxB)

Each of the sixteen output drivers (8 differential pairs, OUT0/OUT0B—OUT7/OUT7B) is ac coupled to its
respective SMA connector. The output clock termination circuit is shown in Figure 6 below. The output signal will
have no dc bias. If dc coupling is required, the ac coupling capacitors can be replaced with a resistor of appropriate
value. The Si5347-EVB provides pads for optional output termination resistors and/or low frequency capacitors.
Note that components with schematic “NI” designation are not normally populated on the Si5347-EVB and provide
locations on the PCB for optional dc/ac terminations by the end user.

Figure 6. Output Clock Termination Circuit

Rev. 1.1 7