The Si5345-EVB is used for evaluating the Si5345
Any-Frequency, Any-Output, Jitter-Attenuating Clock
Multiplier. The Si5345 combines 4th generation DSPLL
and Multisynth
clock generation for applications that required the
highest level of jitter performance. The Si5345-EVB has
4 independent input clocks and 10 independent output
clocks. The Si5345-EVB can be controlled and
configured using the Clock Builder Pro
software tool.
technologies to enable any-frequency
(CB Pro)
EVB Features
Powered from USB port or external power supply.
Onboard 48 MHz XTAL or Reference SMA Inputs
allow holdover mode of operation on the Si5345.
CBPro GUI programmable V
device to operate from 3.3, 2.5, or 1.8 V.
CBPro GUI programmable V
of the 10 outputs to have its own power supply
voltage selectable from 3.3, 2.5, or 1.8 V.
CBPro GUI-controlled voltage, current, and power
measurements of V
Status LEDs for power supplies and control/status
signals of Si5345.
SMA connectors for input clocks, output clocks, and
Below is a functional block diagram of the Si5345-EVB. This EVB can be connected to a PC via the main USB
connector for programming, control, and monitoring. See section “3. Quick Start” or section “10.3. Overview of
ClockBuilderPro Applications” for more information.
Figure 2. Si5345-EVB Functional Block Diagram
2Rev. 1.1
Si5345-EVB
2. Si5345-EVB Support Documentation and ClockBuilderPro Software
All Si5345 schematics, BOMs, User’s Guides, and software can be found online at the following link:
1. Install ClockBuilderPro desktop software from http://www.silabs.com/CBPro.
2. Connect a USB cable from Si5345-EVB to the PC where the software was installed.
3. Leave the jumpers as installed from the factory, and launch the ClockBuilderPro software.
4. You can use ClockBuilderPro
5. For the Si5345 data sheet, go to http://www.silabs.com/timing.
to create, download, and run a frequency plan on the Si5345-EVB.
4. Jumper Defaults
Si5345 EVB Jumper Defaults
LocationType
JP12 pinOJP232 pinO
JP22 pinI
JP32 pinO
JP42 pinI
JP52 pinI
JP62 pinI
JP72 pinI
JP82 pinO
JP92 pinO
JP102 pinI
JP132 pinO
JP142 pinI
JP153 pin1 to 2
JP163 pin1 to 2
JP172 pinO
JP182 pinO
JP192 pinO
JP202 pinO
JP212 pinO
JP222 pinOJ365x2 HdrAll 5 installed
I = Installed
0 = Open
LocationType
JP242 pinO
JP252 pinO
JP262 pinO
JP272 pinO
JP282 pinO
JP292 pinO
JP302 pinO
JP312 pinO
JP322 pinO
JP332 pinO
JP342 pinO
JP352 pinO
JP362 pinO
JP383 pinall open
JP392 pinO
JP402 pinO
JP412 pinO
I = Installed
0 = Open
Refer to the Si5345 EVB schematics for the functionality associated with each jumper.
Rev. 1.13
Si5345-EVB
5. Status LEDs
Si5345 EVB Status LEDs
LocationSilkscreenColorStatus Function Indication
D275VUSBMAIN BlueMain USB +5 V present
D223P3VBlueDUT +3.3 V is present
D26VDD DUTBlueDUT VDD voltage present
D25INTRRedMCU INTR (Interrupt) active
D21READYGreenMCU Ready
D24BUSYGreenMCU Busy
D27, D22, and D26 are illuminated when USB +5 V, Si5345 +3.3 V, and Si5345 VDD supply voltages, respectively,
are present. D25, D21, and D24 are status LEDs showing on-board MCU activity.
4Rev. 1.1
Figure 3. Status LEDs
Si5345-EVB
6. External Reference Input (XA/XB)
An external reference (XTAL) is used in combination with the internal oscillator to produce an ultra-low jitter
reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. The
Si5345-EVB can also accommodate an external reference clock instead of a crystal. To evaluate the device with a
REFCLK, C111 and C113 must be populated and the XTAL removed (see Figure 4 below). The REFCLK can then
be supplied to J39 and J40.
Figure 4. External Reference Input Circuit
Rev. 1.15
Si5345-EVB
7. Clock Input Circuits (INx/INxB)
The Si5345-EVB has eight SMA connectors (IN0, IN0B–IN3, IN3B) for receiving external clock signals. All input
clocks are terminated as shown in Figure 5 below. Note input clocks are AC coupled and 50 ohm terminated. This
represents 4 differential input clock pairs. Single-ended clocks can be used by appropriately driving one side of the
differential pair with a single-ended clock. For details on how to configure inputs as single-ended, please refer to
the Si5345 data sheet.
Figure 5. Input Clock Termination Circuit
8. Clock Output Circuits (OUTx/OUTxB)
Each of the twenty output drivers (10 differential pairs) is AC coupled to its respective SMA connector. The output
clock termination circuit is shown in Figure 6 below. The output signal will have no dc bias. If DC coupling is
required, the AC coupling capacitors can be replaced with a resistor of appropriate value. The Si5345-EVB
provides pads for optional output termination resistors and/or low frequency capacitors. Note that components with
schematic “NI” designation are not normally populated on the Si5345-EVB and provide locations on the PCB for
optional DC/AC terminations by the end user.
Figure 6. Output Clock Termination Circuit
6Rev. 1.1
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