Silicon Laboratories Si5342, Si5345, Si5344 Family Reference Manual

ANY-FREQUENCY, ANY-OUTPUT

JITTER-ATTENUATORS/CLOCK MULTIPLIERS

Si5345, Si5344, Si5342 REV. D

F

AMILY REFERENCE MANUAL

Rev. 1.0 7/16 Copyright © 2016 by Silicon Laboratories Si5345-44-42-D-RM

Si5345-44-42-D-RM

TABLE OF CONTENTS

Section Page

1. Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.1. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.1. Work Flow Expectations with ClockBuilder Pro™ and the Register Map . . . . . . . . . . . . .9

2.2. Family Product Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.3. Available Software Tools and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3. DSPLL and MultiSynth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1. Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.2.1. Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.2. Holdover Exit Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.1. Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.2. Dynamic PLL Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.2.1. Revision B and A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.2. Revision D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3. NVM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.4. Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.5. Acquisition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.6. Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.7. Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5. Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.1. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.1.1. Manual Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.2. Automatic Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2. Types of Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.2.1. Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.2. Hitless Input Switching with Phase Buildout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.3. Ramped Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.4. Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.5. Synchronizing to Gapped Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5.3.1. Input Loss of Signal (LOS) Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.2. Out of Frequency (OOF) Fault Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3.3. Loss of Lock Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.1. Output Crosspoint Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.2. Performance Guidelines for Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

6.3. Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

6.3.1. Differential Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3.2. Differential Output Swing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3.3. Programmable Common Mode Voltage for Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3.4. LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.3.5. LVCMOS Output Impedance and Drive Strength Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Si5345-44-42-D-RM

6.3.6. LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.7. LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.3.8. Output Driver Settings for LVPECL, LVDS, HCSL, and CML . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.4. Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

6.4.1. Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.4.2. Synchronous Output Disable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5. Output Skew Control (t0–t4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

6.6. Output Buffer Supply Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

7. Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8. Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

8.1. DCO with Frequency Increment/Decrement Pins/Bits . . . . . . . . . . . . . . . . . . . . . . . . . .49

8.2. DCO with Direct Register Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

9. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

9.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

9.2. SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

10. Field Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

11. XAXB External References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

11.1. Performance of External References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

11.2. Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

11.3. Recommended Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

11.4. Register Settings to Control External XTAL Reference . . . . . . . . . . . . . . . . . . . . . . . .66

11.4.1. XAXB_FREQ_OFFSET Frequency Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.4.2. XAXB_EXTCLK_EN Reference Clock Selection Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.4.3. PXAXB Pre-scale Divide Ratio for Reference Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 67

12. Crystal and Device Circuit Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . .68

12.1. 64-Pin QFN Si5345 Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

12.1.1. Si5345 Applications without a Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12.1.2. Si5345 Crystal Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12.1.3. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

12.2. 44-Pin QFN Si5344/42 Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . .73

12.2.1. Si5342/44 Applications without a Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.2.2. Si5342/44 Crystal Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

13. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

13.1. Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

13.2. Power Supply Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

13.3. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

13.4. Grounding Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

14. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

14.1. Base vs. Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

14.1.1. “Base” Devices (a.k.a. “Blank” Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

14.1.2. “Factory Preprogrammed” (Custom OPN) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

14.2. Register Map Overview and Default Settings Values . . . . . . . . . . . . . . . . . . . . . . . . . .80

14.3. Si5345 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

14.3.1. Page 0 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

14.3.2. Page 1 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.3.3. Page 2 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

14.3.4. Page 3 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.3.5. Page 4 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

14.3.6. Page 5 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

14.3.7. Page 9 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

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14.3.8. Page A Registers Si5345. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

14.3.9. Page B Registers Si5345. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.4. Si5344 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

14.4.1. Page 0 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

14.4.2. Page 1 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.4.3. Page 2 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

14.4.4. Page 3 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14.4.5. Page 4 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

14.4.6. Page 5 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

14.4.7. Page 9 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

14.4.8. Page A Registers Si5344. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

14.4.9. Page B Registers Si5344. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

14.5. Si5342 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

14.5.1. Page 0 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.5.2. Page 1 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

14.5.3. Page 2 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

14.5.4. Page 3 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

14.5.5. Page 4 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

14.5.6. Page 5 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

14.5.7. Page 9 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

14.5.8. Page A Registers Si5342. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

14.5.9. Page B Registers Si5342. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Appendix A—Setting the Differential Output Driver to

Non-Standard Amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

4 Rev. 1.0

Si5345-44-42-D-RM

LIST OF FIGURES

Figure Page

Figure 1. Block Diagram Si5345/44/42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Si5342 DSPLL and Multisynth System Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. Si5345/44/42 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. Initialization from Hard Reset and Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Programmable Holdover Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Input Termination for Standard and Pulsed CMOS Inputs. . . . . . . . . . . . . . . . . . . . 23

Figure 8. Generating an Averaged Non Gapped Output Frequency from a Gapped Input. . . 26

Figure 9. Si5342/44/45 Fault Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. LOS Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. OOF Status Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12. Example of Precise OOF Monitor Assertion and De-assertion Triggers . . . . . . . . 28

Figure 13. LOL Status Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14. LOL Set and Clear Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15. Interrupt Pin Source Masking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 16. MultiSynth to Output Driver Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17. Supported Differential Output Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18. Vpp_se and Vpp_diff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 19. LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20. Example of Independently-Configurable Path Delays . . . . . . . . . . . . . . . . . . . . . . 45

Figure 21. Si5345 Zero Delay Mode Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 22. DCO with FINC/FDEC Pins or Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 23. I2C/SPI Device Connectivity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 24. I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 25. 7-bit I2C Slave Address Bit-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 26. I2C Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 27. I2C Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. SPI Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29. Example Writing Three Data Bytes Using the Write Commands . . . . . . . . . . . . . . 56

Figure 30. Example of Reading Three Data Bytes Using the Read Commands. . . . . . . . . . . 57

Figure 31. SPI “Set Address” Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 32. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing . . . . . . 58

Figure 33. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing . . . . . 59

Figure 34. SPI “Burst Data Write” Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 35. Crystal Resonator and External Reference Clock Connection Options . . . . . . . . . 61

Figure 36. Clipped Sine Wave TCXO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 37. CMOS TCXO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 38. Maximum ESR vs. C0 for 25 MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 39. Maximum ESR vs. C0 for 48–54 MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 40. 64-pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1) . . . . . . . . . 69

Figure 41. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) . . . . . . . . . . . . . 69

53

Rev. 1.0 5

Si5345-44-42-D-RM

Figure 42. Crystal Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 43. Power Plane (Layer 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 44. Layer 5 Power Routing on Power Plane (Layer 5). . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 45. Ground Plane (Layer 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 46. Output Clock Layer (Layer 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 47. Bottom Layer Ground Flooded (Layer 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 48. Device Layer (Layer 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 49. Crystal Shield Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 50. Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 51. Power Plane and Clock Output Power Supply Traces (Layer 4) . . . . . . . . . . . . . . 75

Figure 52. Clock Input Traces (Layer 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 53. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer) . . . . . . . . . 76

Figure 54. FINC, FDEC Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 55. Logic Diagram of the FINC/FDEC Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 56. Logic Diagram of the FINC/FDEC Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 57. FINC, FDEC Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

6 Rev. 1.0

Si5345-44-42-D-RM

LIST OF TABLES

Table Page

Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. PLL_BW Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Fastlock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. DSPLL Holdover Exit Bandwidth Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Reset Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. NVM Programming Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Holdover Mode Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Input Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Manual Input Selection using IN_SEL[1:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Registers for Automatic Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Register 0x0949 Clock Input Control and Configuration . . . . . . . . . . . . . . . . . . . . . 24

Table 12. Hitless Switching Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. Ramped Input Switching Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. Loss of Signal Status Monitoring and Control Registers . . . . . . . . . . . . . . . . . . . . . 27

Table 15. Out-of-Frequency Status Monitoring and Control Registers . . . . . . . . . . . . . . . . . . 29

Table 16. Loss of Lock Status Monitor and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 17. Output Driver Crosspoint Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 18. Example of Output Clock Frequency Sequencing Choice . . . . . . . . . . . . . . . . . . . 35

Table 19. Output Signal Format Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 20. Differential Output Voltage Swing Control Registers. . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. Differential Output Common Mode Voltage Control Registers . . . . . . . . . . . . . . . . 38

Table 22. Output Impedance and Drive Strength Selections . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23. LVCMOS Drive Strength Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 24. LVCMOS Output Polarity Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 25. Output Polarity of OUTx and OUTx Pins in LVCMOS Mode. . . . . . . . . . . . . . . . . . 41

Table 26. Settings for LVDS, LVPECL, and HCSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 27. Output Enable/Disable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 28. Output Driver State Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 29. Synchronous Disable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 30. Output Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 31. OUTx VDD Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 32. Zero Delay Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 33. Input Clock Selection in Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 34. Frequency Increment/Decrement Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 35. I2C/SPI Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 36. SMBus Timeout Error Bit Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 37. SPI Command Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 38. Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 39. Recommended Oscillator Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 40. XAXB Frequency Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 41. XAXB External Clock Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Rev. 1.0 7

Si5345-44-42-D-RM

Table 42. Pre-Scale Divide Ratio Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 43. Pre-Scale Divide Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 44. Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 45. Register Map Paging Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 46. Registers that Follow the Same Definitions Above . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 47. Registers that Follow the P0_NUM and P0_DEN Above . . . . . . . . . . . . . . . . . . . 104

Table 48. Registers that Follow the R0_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 49. Registers that Follow the N0_NUM and N0_DEN Definitions . . . . . . . . . . . . . . . . 112

Table 50. Registers that Follow the N0_FSTEPW Definitions . . . . . . . . . . . . . . . . . . . . . . . 113

Table 51. Registers that Follow the Same Definitions Above . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 52. Registers that Follow the P0_NUM and P0_DEN . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 53. Registers that Follow the R0_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 54. Registers that Follow the N0_NUM and N0_DEN Definitions . . . . . . . . . . . . . . . . 157

Table 55. Registers that Follow the N0_FSTEPW Definition . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 56. Registers that Follow the Same Definition as Above . . . . . . . . . . . . . . . . . . . . . . 193

Table 57. Registers that Follow the P0_NUM and P0_DEN Definitions . . . . . . . . . . . . . . . . 196

Table 58. Registers that Follow the R0_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 59. Register that Follows the N0_NUM and N0_DEN Definitions . . . . . . . . . . . . . . . . 202

Table 60. Registers that Follow the N0_FSTEPW Definition . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 61. Registers that Follow the N0_DELAY Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 62. Output Differential Common Mode Voltage Settings. . . . . . . . . . . . . . . . . . . . . . . 219

Table 63. Typical Differential Amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

8 Rev. 1.0

Si5345-44-42-D-RM

1. Scope

This Family Reference Manual is intended to provide system, PCB design, signal integrity, and software engineers
the necessary technical information to successfully use the Si5345/44/42 devices in end applications. The official
device specifications can be found in the Si5345/44/42 data sheets.

1.1. Related Documents

Si5345/44/42 Data Sheet
Si5345/44/42 Device Errata
Si5345/44/42-EVB User Guide

2. Overview

The Si5345/44/42 jitter attenuating clock multipliers combine 4th generation DSPLL and MultiSynth™ technologies
to enable any-frequency clock generation for applications that require the highest level of jitter performance. These
devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM) ensuring
power up with a known frequency configuration. Free-run, synchronous, and holdover modes of operation are
supported offering both automatic and manual input clock switching. The loop filter is fully integrated on-chip
eliminating the risk of potential noise coupling associated with discrete solutions. Further, the jitter attenuation
bandwidth is digitally programmable providing jitter performance optimization at the application level.

These devices are capable of generating any combination of output frequency from any input frequency within the
specified input and output range.

2.1. Work Flow Expectations with ClockBuilder Pro™ and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with
register map details on how to implement them. It is important to understand that the intent is for customers to use
the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is
documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond
the scope of this document. Real-time changes to the frequency plan and other operating settings are supported
by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to
Applications Notes and Knowledge Base
implement the most common, real-time frequency plan changes.

The primary purpose of the software is that it saves having to understand all the complexities of the device. The
software abstracts the details from the user to allow focus on the high level input and output configuration, making
it intuitive to understand and configure for the end application. The software walks the user through each step, with
explanations about each configuration step in the process to explain the different options available. The software
will restrict the user from entering an invalid combination of selections. The final configuration settings can be
saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory
preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by
viewing the settings in the register map described in this document.

article links within the ClockBuilder Pro GUI for information on how to

2.2. Family Product Comparison

Table 1 lists a comparison of the different family members.

Table 1. Product Selection Guide

Part Number Number of Inputs Number of MultiSynths Number of Outputs Package Type

Si5342 4 2 2 44-QFN

Si5344 4 4 4 44-QFN

Si5345 4 5 10 64-QFN

Rev. 1.0 9

Si5345-44-42-D-RM

Si5345/44/42

IN_SEL[1:0]

DSPLL

LPFPD

Optional
External

Feedback

VDD

VDDA

3

OUT2

VDDO2
OUT2

VDDO3

VDDO0

OUT0

OUT0

÷R

2

OUT3

OUT3

÷R

3

OUT1

VDDO1

OUT1

÷R

1

OUT5

VDDO5

OUT5

VDDO6

÷R

5

OUT6

OUT6

÷R

6

OUT4

VDDO4

OUT4

÷R

4

OUT7

VDDO7

OUT7

VDDO8

÷R

7

OUT8

OUT8

÷R

8

÷R

0

INTR

Multi

Synth

÷

N

0n

N

0d

Multi

Synth

Multi

Synth

Multi

Synth

÷

N

2n

N

2d

÷

N

3n

N

3d

÷

N

4n

N

4d

Multi

Synth

÷

N

1n

N

1d

t

0

t

1

t

2

t

3

t

4

IN0

IN0

IN1

IN1

÷

P

0n

P

0d

÷

P

1n

P

1d

IN2

IN2

IN3/FB_IN

IN3/FB_IN

÷

P

3n

P

3d

÷

P

2n

P

2d

OUT9

OUT9

÷R

9

VDDO9

RST

OE

FDEC

FINC

÷

M

n

M

d

SDA/SDIO

A1/SDO

SCLK

A0/CS

I2C_SEL

NVM

LOL

48-54MHz XTAL

or REFCLK

OSC

XBXA

÷

PXAXB

Si5342

Si5344

Si5345

SPI/

I

2

C

Status

Monitors

2.3. Available Software Tools and Support

ClockBuilder Pro is a software tool that is used for the Si5345/44/42 family and other product families, capable of

configuring the timing chip in an intuitive, easy-to-use, step-by-step process. The software abstracts the details
from the user to allow focus on the high level input and output configuration, making it intuitive to understand and
configure for the end application. The software walks the user through each step, with explanations about each
configuration step in the process to explain the different options available. The software will restrict the user from
entering an invalid combination of selections. The final configuration settings can be saved, written to a device or
written to the EVB and a custom part number can be created. This is all done with one software tool. ClockBuilder
Pro integrates all the data sheets, application notes and information that might be helpful in one environment. It is
intended that customers will use the software tool for the proper configuration of the device. Register map
descriptions given in the document should not be the only source of information for programming the device. The
complexity of the algorithms is embedded in the software tool.

10 Rev. 1.0

Figure 1. Block Diagram Si5345/44/42

Si5345-44-42-D-RM

IN_SEL[1:0]

DSPLL

LPFPD

Optional
External

Feedback

VDDO0

OUT0

OUT0

OUT1

VDDO1

OUT1

÷R

1

÷R

0

Multi

Synth

÷

N

0n

N

0d

Multi

Synth

÷

N

1n

N

1d

t

0

t

1

IN0

IN0

IN1

IN1

÷

P

0n

P

0d

÷

P

1n

P

1d

IN2

IN2

IN3/FB_IN

IN3/FB_IN

÷

P

3n

P

3d

÷

P

2n

P

2d

÷

M

n

M

d

48-54MHz XTAL

or REFCLK

OSC

XBXA

÷

PXAXB

3. DSPLL and MultiSynth

The DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input
dividers (Pxn/Pxd) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally
related. Input switching is controlled manually or automatically using an internal state machine. The oscillator
circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the
device is in free-run or holdover mode. Note that a XTAL (or suitable XO reference on XA/XB) is always required
and is the jitter reference for the device. The high-performance MultiSynth dividers (Nxn/Nxd) generate integer or
fractionally related output frequencies for the output stage. A crosspoint switch connects any of the MultiSynth
generated frequencies to any of the outputs. A single MultiSynth output can connect to two or more output drivers.
Additional integer division (R) determines the final output frequency as shown in Figure 2.

The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be
stored in non-volatile memory or RAM. The combination of fractional input dividers (Pn/Pd), fractional frequency
multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the
generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan

are easily determined using the ClockBuilder Pro software.

Figure 2. Si5342 DSPLL and Multisynth System Flow Diagram

Rev. 1.0 11

Si5345-44-42-D-RM

3.1. Dividers

There are five divider classes within the Si5345/4/2. See Figure 1 for a block diagram that shows all of these
dividers.

Wide range input dividers P3, P2, P1, P0

MultiSynth divider
48 bit numerator, 32 bit denominator
Min value is 1
Practical range limited by phase detector and VCO range
Each divider has an update bit that must be written to cause a newly written divider value to take effect.

Narrow range input divider Pxaxb

Only divides by 1, 2, 4, 8

Feedback M divider

MultiSynth divider
Integer or fractional divide values
56 bit numerator, 32-bit denominator
Practical range limited by phase detector and VCO range
Each divider has an update bit that must be written to cause a newly written divider value to take effect.

Output N divider

MultiSynth divider
Integer or fractional divide values
44 bit numerator, 32 bit denominator
Each divider has an update bit that must be written to cause a newly written divider value to take effect.

Output R divider

Only even integer divide values
Min value is 2

Maximum value is 2

25

– 2

3.2. DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register
configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. Since the
loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking
regardless of the loop bandwidth selection. The DSPLL loop bandwidth is set in registers 0x0508-0x050D and are
determined using ClockBuilder Pro.

The higher the PLL bandwidth is set relative to the phase detector frequency (F

), the more chance that F

pfd

cause a spur in the Phase Noise plot of the output clock and increase the output jitter. To guarantee the best phase
noise/jitter it is recommended that the normal PLL bandwidth be kept less than F

/160 although ratios of F

pfd

will typically work fine.

Table 2. PLL_BW Registers

Register Name Hex Address [Bit

Field]

BW_PLL 0x0508[7:0]-

0x050D[7:0]

Determines the loop BW for the DSPLL.

Function

pfd

pfd

will

/100

12 Rev. 1.0

Si5345-44-42-D-RM

3.2.1. Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock
feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to
reduce lock time. Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock
Bandwidth settings in the range from 100 Hz up to 4 kHz are available for selection. Once lock acquisition has
completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The
Fastlock feature can be enabled or disabled independently by register control. If enabled, when LOL is asserted
Fastlock will be automatically enabled. When LOL is no longer asserted, Fastlock will be automatically disabled.

Note: This update bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3. Fastlock Registers

Register Name Hex Address [Bit

Field]

FASTLOCK_AUTO_EN 0x052B[0] Auto Fastlock Enable/Disable

FASTLOCK_MAN 0x052B[1] 0 for normal operation,

1 to force fast lock

FASTLOCK_BW_PLL 0x050E[7:0]-

0x0513[7:0]

The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in "5.3.3.
Loss of Lock Fault Monitoring" on page 29.

3.2.2. Holdover Exit Bandwidth

In addition to the operating loop and fastlock bandwidths, there is also a user-selectable bandwidth when exiting
holdover and locking or relocking to an input clock, available when ramping is disabled (HOLD_RAMP_BYP = 1).
CBPro sets this value equal to the loop bandwidth by default.

Note: The BW_UPDATE bit will latch new values for Loop, Fastlock, and Holodver bandwidths simultaneously.

Fastlock BW selection.

Function

Table 4. DSPLL Holdover Exit Bandwidth Registers

Register Name Hex Address Function

HOLDEXIT_BW 0x059D-0x05A2 Determines the Holdover Exit BW for the DSPLL. Parameters are

generated by ClockBuilder Pro.

Rev. 1.0 13

Si5345-44-42-D-RM

No valid

input clocks

selected

Lock Acquisition

(Fast Lock)

Locked

Mode

Holdover

Mode

Phase lock on
selected input

clock is achieved

Selected input

clock fails

An input is qualified

and available for

selection

Y

e

s

Free-run

Valid input clock

selected

Reset and

Initialization

Power-Up

Is holdover

history valid?

No

4. Modes of Operation

After initialization the DSPLL will operate in one of the following modes: Free-run, lock-acquisition, locked, or
holdover. See Figure 3 below for the state diagram showing the modes of operation. The following sections
describe each of these modes in greater detail.

Figure 3. Modes of Operation

4.1. Reset and Initialization

Once power is applied, the device begins an initialization period where it downloads default register values and
configuration data from NVM and performs other initialization tasks. Communicating with the device through the
serial interface is possible once this initialization period is complete. No clocks will be generated until initialization is
complete.

There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers are
restored to the values stored in NVM, and all circuits, including the serial interface, are restored to their initial state.
A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM
download. It is simply used to initiate register configuration changes. Table 5 lists the reset and control registers.

14 Rev. 1.0

Si5345-44-42-D-RM

NVM

2x

OTP

RAM

Power-Up

Serial interface

ready

RST

pin asserted

Hard Reset
bit asserted

Initialization

NVM download

Soft Reset

bit asserted

Figure 4. Si5345/44/42 Memory Configuration

Table 5. Reset Registers

Register Name Hex

Address

[Bit Field]

HARD_RST 0x001E[1] Performs the same function as power cycling the device. All registers will be

restored to their default values.

SOFT_RST 0x001C[0] Performs a soft reset. Initiates register configuration changes.

Function

Figure 5. Initialization from Hard Reset and Soft Reset

The Si5345/44/42 is fully configurable using the serial interface (I2C or SPI). At power up the device downloads its
default register values from internal non-volatile memory (NVM). Application specific default configurations can be
written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to
NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8V) and VDDA
(3.3 V) pins.

Rev. 1.0 15

Si5345-44-42-D-RM

4.2. Dynamic PLL Changes

4.2.1. Revision B and A

It is possible for a PLL to become unresponsive (i.e., lose lock indefinitely) when it is dynamically reprogrammed or
changed via the serial port. Reprogramming/changing the N divider does not affect the PLL. Any change that
causes the VCO frequency to change by more than 250 ppm since Power-up, NVM download, or SOFT_RST
requires the following special sequence of writes. Changes to the following registers require the following special
sequence of writes:

XAXB_FREQ_OFFSET
PXAXB
MXAXB_NUM
MXAXB_DEN
M_NUM
M_DEN

1. |First, the preamble
Write 0x0B24 = 0xD8
Write 0x0B25 = 0x00

2. Wait 300 ms.

3. Then perform the desired register modifications

4. Write SOFT_RST - x001C[0] = 1

5. Write the post-amble
Write 0x0B24 = 0xDB
Write 0x0B25 = 0x02

4.2.2. Revision D

The revision D preamble and postamble values for updating certain registers during device operation have
changed after revision B. Either the new or old values below may be written to revision D or later devices without
issue. No system software changes are necessary for legacy systems. When writing old values, note that reading
back these registers will not give the written old values, but will reflect the new values. Silicon Labs recommends
using the new values for all revision D and later designs, since the write and read values will match.

The device revision can be determined in the setting DEVICE_REV, register 0x0005.

DEVICE_REV = 0x02 or higher: New Values

Revision D Preamble:0x0B24 = 0xC0, 0x0B25 = 0x00

Revision D Postamble:0x0B24 = 0xC3, 0x0B25 = 0x02

Note that revision B and earlier devices must continue to use the original values for these registers:

DEVICE_REV = 0x00 or 0x01: Old Values

Revision B Preamble:0x0B24 = 0xD8, 0x0B25 = 0x00

Revision B Postamble:0x0B24 = 0xDB, 0x0B25 = 0x02

16 Rev. 1.0

Si5345-44-42-D-RM

4.3. NVM Programming

The NVM is two time writable. Because it can only be written two times, it is important to configure the registers
correctly before beginning the NVM programming process. Once a new configuration has been written to NVM, the
old configuration is no longer accessible. Note: In-circuit programming is only supported over a temperature range
of 0° to 80°C.

The procedure for writing registers into NVM is as follows:

1. Write all registers as needed.

2. You may write to the user scratch space (registers 0x026B to 0x0272) to identify the content of NVM bank.

3. Write 0xC7 to NVM_WRITE register.

4. Wait until DEVICE_READY = 0x0F

WARNING! Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads
as 0x0F may corrupt the register contents or NVM programming. Note that this includes writes to the PAGE
register.

5. Set NVM_READ_BANK 0x00E4[0] = “1”.

6. Wait until DEVICE_READY = 0x0F.

7. Steps 5 and 6 can be replaced by simply powering down and then powering up the device.

Table 6. NVM Programming Registers

Register Name Hex Address

[Bit Field]

ACTIVE_NVM_BANK 0x00E2[7:0] Indicates number of user bank writes carried out so far.A

NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with 0xC7

NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM

DEVICE_READY 0x00FE[7:0] Indicates that the device serial interface is ready to accept commands.

Function

4.4. Free Run Mode

The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete.
The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency
accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is
±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode.
Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is
recommended for applications that need better frequency accuracy and stability while in freerun or holdover
modes. Because there is little or no jitter attenuation from the XAXB pins to the clock outputs, a low-jitter XAXB
source will be needed for low-jitter clock outputs.

4.5. Acquisition Mode

The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the
DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will
acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting
when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO
frequency change as it pulls-in to the input clock frequency.

4.6. Locked Mode

Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input
clock. At this point any XTAL frequency drift will typically not affect the output frequency. A loss of lock pin (LOL)
and status bit indicate when lock is achieved. See “5.3.3. Loss of Lock Fault Monitoring” for more details on the
operation of the loss of lock circuit.

Rev. 1.0 17

Si5345-44-42-D-RM

Programmable delay

Clock Failure

and Entry into

Holdover

time

0s

Historical Frequency Data Collected

Programmable historical data window

used to determine the final holdover value

120s

1s,10s, 30s, 60s

30ms, 60ms, 1s,10s, 30s, 60s

4.7. Holdover Mode

The DSPLL will automatically enter Holdover mode when the selected input clock becomes invalid and no other
valid input clocks are available for selection. It uses an averaged input clock frequency as its final holdover
frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails.
The holdover circuit stores up to 120 seconds of historical frequency data while locked to a valid clock input. The
final averaged holdover frequency value is calculated from a programmable window within the stored historical
frequency data. Both the window size and the delay are programmable as shown in the figure below. The window
size determines the amount of holdover frequency averaging. This delay value allows recent frequency information
to be ignored for Holdover in cases where the input clock source frequency changes as it is removed.

Figure 6. Programmable Holdover Window

When entering Holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover
frequency. While in Holdover, the output frequency drift is entirely dependent on the external crystal or external
reference clock connected to the XAXB pins. If the clock input becomes valid, the DSPLL will automatically exit the
Holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency
to achieve frequency and phase lock with the input clock. This pull-in process is Glitchless and its rate is controlled
by the DSPLL bandwidth or the Fastlock bandwidth, if Fastlock is enabled. These options are register
programmable.

The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency
difference between the output frequency while in holdover and the desired, new output frequency is measured. It is
quite possible (even likely) that the new output clock frequency will not be the same as the holdover output
frequency because the new input clock frequency might have changed and the holdover history circuit may have
changed the holdover output frequency. The ramp logic calculates the difference in frequency between the
holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp
time is calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends,
the output frequency will be the desired new frequency. Using the ramp, the transition between the two frequencies
is smooth and linear. The ramp rate can be selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or
any of approximately 40 values that are in between. The loop BW values do not limit or affect the ramp rate
selections and vice versa. CBPro defaults to ramped exit from holdover. Ramped exit from holdover is also used
for ramped input clock switching. See “5.2.3. Ramped Input Switching” for more information.

As shown in Figure 3, the Holdover and Freerun modes are closely related. The device will only enter Holdover if a
valid clock has been selected long enough for the holdover history to become valid, i.e., HOLD_HIST_VALID = 1. If
the clock fails before the combined HOLD_HIST_LEN + HOLD_HIST_DELAY time has been met,
HOLD_HIST_VALID = 0 and the device will enter Freerun mode instead. Reducing the HOLD_HIST_LEN and
HOLD_HIST_DELAY times will allow Holdover in less time, limited by the source clock failure and wander
characteristics. Note that the Holdover history accumulation is suspended when the input clock is removed and
resumes accumulating when a valid input clock is again presented to the DSPLL.

18 Rev. 1.0

Si5345-44-42-D-RM

Table 7. Holdover Mode Control Registers

Register Name Hex

Function

Address

[Bit Field]

Holdover Status

HOLD 0x000E[5] DSPLL Holdover status indicator.

0: Normal Operation
1: In Holdover/Freerun Mode:
HOLD_HIST_VALID = 0 ≥ Freerun Mode
HOLD_HIST_VALID = 1 ≥ Holdover Mode

HOLD_FLG 0x0013[5] Holdover indicator sticky flag bit. Remains asserted after the indicator

bit shows a fault until cleared by the user. Writing a 0 to the flag bit will
clear it if the indicator bit is no longer asserted.

HOLD_INTR_MSK 0x0019[5] Masks Holdover/Freerun from generating INTR

interrupt.
0: Allow Holdover/Freerun interrupt (default)
1: Mask (ignore) Holdover/Freerun for interrupt

HOLD_HIST_VALID 0x053F[1] Holdover historical frequency data valid.

0: Incomplete Holdover history, Freerun mode available
1: Valid Holdover history, Holdover mode available

Holdover Control and Settings

HOLD_HIST_LEN 0x052E[4:0] Window Length time for historical average frequency used in Holdover

mode. Window Length in seconds (s):
Window Length = (2

HOLD_HIST_LEN

- 1) x 8 / 3 x 10

-7

HOLD_HIST_DELAY 0x052F[4:0] Delay Time to ignore data for historical average frequency in Holdover

mode. Delay Time in seconds (s):
Delay Time = 2

HOLD_HIST_DELAY

x 2 / 3 x 10

-7

FORCE_HOLD 0x0535[0] Force the device into Holdover mode. Used to hold the device output

clocks while retraining an upstream input clock.
0: Normal Operation
1: Force Holdover/Freerun Mode:
HOLD_HIST_VALID = 0 ≥ Freerun Mode
HOLD_HIST_VALID = 1 ≥ Holdover Mode

Rev. 1.0 19

Si5345-44-42-D-RM

Table 7. Holdover Mode Control Registers (Continued)

Register Name Hex

Address

[Bit Field]

Holdover Exit Control

HOLD_RAMP_BYP 0x052C[3] Holdover Exit Ramp Bypass

0: Use Ramp when exiting from Holdover (default)
1: Use Holdover/Fastlock/Loop bandwidth when exiting from Holdover

HOLDEXIT_BW_SEL0 0x059B[6] Select the exit bandwidth from Holdover when ramped exit is not

selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
01: Use Holdover Exit bandwidth on Holdover exit (default)
10, 11: Use Normal Loop bandwidth on Holdover exit

HOLDEXIT_BW_SEL1 0x052C[4] Select the exit bandwidth from Holdover when ramped exit is not

selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
01: Use Holdover Exit bandwidth on Holdover exit (default)
10, 11: Use Normal Loop bandwidth on Holdover exit

RAMP_STEP_INTERVAL 0x052C[7:5] Time Interval of the frequency ramp steps when ramping between

inputs or exiting holdover.

RAMP_STEP_SIZE 0x05A6[2:0] Size of the frequency ramp steps when ramping between inputs or

exiting holdover.

Function

20 Rev. 1.0

Si5345-44-42-D-RM

5. Clock Inputs

The Si5342/44/45 support 4 inputs that can be used to synchronize to the internal DSPLL.

5.1. Inputs (IN0, IN1, IN2, IN3)

The inputs accept both standard format inputs and low-duty-cycle pulsed CMOS clocks. Input selection from
CLK_SWITCH_MODE can be manual (pin or register controlled) or automatic with user definable priorities.
Register 0x052A is used to select pin or register control, and to configure the input as shown below in Table 8.

Table 8. Input Selection Configuration

Register Name Hex Address

[Bit Field]

CLK_SWITCH_MODE 0x0536[1:0] Selects manual or automatic switching modes. Automatic mode can be

revertive or non-revertive. Selections are the following:
00 Manual,01 Automatic non-revertive
02 Automatic revertive, 03 Reserved

IN_SEL_REGCTRL 0x052A [0] 0 for pin controlled clock selection

1 for register controlled clock selection

IN_SEL 0x052A [2:1] 0 for IN0, 1 for IN1,

2 for IN2, 3 for IN3 (or FB_IN)

5.1.1. Manual Input Switching

In manual mode, CLK_SWITCH_MODE=0x00.

Input switching can be done manually using the IN_SEL[1:0] device pins from the package or through register
0x052A IN_SEL[2:1]. Bit 0 of register 0x052A determines if the input selection is pin selectable or register
selectable. The default is pin selectable. The following table describes the input selection on the pins. Note that
when Zero Delay Mode is enabled, the FB_IN pins will become the feedback input and IN3 therefore is not
available as a clock input. Also, in Zero Delay Mode, ZDM_EN must be set and register based input clock selection
must be done with ZDM_IN_SEL. If there is no clock signal on the selected input, the device will automatically
enter free-run or holdover mode.

Function

Table 9. Manual Input Selection using IN_SEL[1:0] Pins

IN_SEL[1:0] DEVICE PINS Zero Delay Mode Disabled Zero Delay Mode Enabled

00 IN0 IN0

01 IN1 IN1

10 IN2 IN2

11 IN3 Reserved

Rev. 1.0 21

Si5345-44-42-D-RM

5.1.2. Automatic Input Selection

In automatic mode CLK_SWITCH_MODE = 0x01 (non-revertive) or 0x02 (revertive)

An automatic input selection is available in addition to the above mentioned manual switching option described in
“5.1.1. Manual Input Switching”. In automatic mode, the selection criteria is based on input clock qualification, input
priority and the revertive option. The IN_SEL[1:0] pins or IN_SEL[2:1] register bits are not used in automatic input
selection. Also, only input clocks that are valid (i.e., with no active alarms) can be selected by the automatic clock
selection. If there are no valid input clocks available the DSPLL will enter the holdover mode. With revertive
switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher
priority becomes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the
active input will always remain selected while it is valid. If it becomes invalid an automatic switchover to a valid
input with the highest priority will be initiated.

Table 10. Registers for Automatic Input Selection

Register Name Hex

Address

[Bit Field]

CLK_SWITCH_MODE 0x0536[1:0] Selects manual or automatic switching modes. Automatic mode can be

revertive or non-revertive. Selections are the following: 00 Manual,01
Automatic non-revertive 02 Automatic revertive, 03 Reserved

ZDM_EN 0x0487[0] 0: disable zero delay mode

1: enable zero delay mode

ZDM_IN_SEL 0x0487[2:1] Selects the input when in manual register controlled mode when zero

delay mode is enabled. Selections are IN0,IN1,IN2. A register value of 3
is not allowed.

ZDM_AUTOSW_EN 0x0487[4] 0: automatic switching disabled for zero-delay mode

1: automatic input switching enabled and input clock selection governed
by automatic input switching engine

IN0_PRIORITY 0x0538[2:0] IN0, IN1, IN2, IN3 priority select for the automatic selection state machine.

IN1_PRIORITY 0x0538[6:4]

IN2_PRIORITY 0x0539[2:0]

IN3_PRIORITY 0x0539[6:4]

IN_LOS_MSK 0x0537[3:0] Determines the LOS status for IN3,2,1,0 and is used in determining a

IN_OOF_MSK 0x0537[7:4] Determines the OOF status for IN3,2,1,0 and is used in determining a

Priority selections are 1,2,3,4, or zero for never selected.

valid clock for automatic input selection
0 to use LOS in clock selection logic, 1 to mask LOS from the clock selec-

tion logic

valid clock for the automatic input selection
0 to use OOF in the clock selection logic, 1 to mask the OOF from the

clock selection logic

Function

When in zero delay mode (ZDM_EN (0x0487[0]) the phase difference between the output, which is connected to
the selected input, will be nulled to zero. However the IO delay variation will substantially increase in ZDM mode if
the Fpfd is much below 64 kHz. When in zero delay mode, the DSPLL must have the phase buildout turned off for
input switching or else the IO delay can change on each input switch. Manual control of the input clock selection is
by either pin or register and also depends upon the device being in zero delay mode or not. See Table 11.

22 Rev. 1.0

PulsedCMOSDCCoupledSingleEnded

StandardACCoupledSingleEnded

100

3.3V,2.5V,1.8V
LVCMOS

StandardACCoupledDifferentialLVPECL

INx

INx

50

100

StandardACCoupledDifferentialLVDS

INx

INx

3.3V,2.5V
LVPECL

3.3V,2.5V

LVDSorCML

INx

INx

INx

INx

50

50

50

50

PulsedCMOS

Standard

Si5347/46

Si5347/46

Si5347/46

Si5347/46

3.3V,2.5V,1.8V
LVCMOS

50

R2

R1

PulsedCMOS

Standard

PulsedCMOS

Standard

PulsedCMOS

Standard

VDD R1()R2()

1.8V 324 665

2.5V 511 475

3.3V 634 365

Si5345-44-42-D-RM

5.2. Types of Inputs

Each of the four different inputs IN0-IN3 can be configured as standard LVDS, LVPECL, HCL, CML, and single­ended LVCMOS formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal
50% duty cycle, must be AC-coupled and use the “Standard” Input Buffer selection as these pins are internally dc­biased to approximately 0.83 V. The pulsed CMOS input format allows pulse-based inputs, such as frame-sync
and other synchronization signals, having a duty cycle much less than 50%. These pulsed CMOS signals are DC­coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be terminated near the
device input pins as shown in Figure 7. The resistor divider values given below will work with up to 1 MHz pulsed
inputs.

Figure 7. Input Termination for Standard and Pulsed CMOS Inputs

Rev. 1.0 23

Si5345-44-42-D-RM

Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused
clock inputs may be powered down and left unconnected at the system level. For standard mode inputs, both input
pins must be properly connected as shown in Figure 7 above, including the “Standard AC Coupled Single Ended”
case. In Pulsed CMOS mode, it is not necessary to connect the inverting INx
Pulsed CMOS mode, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through
IN0.

Table 11. Register 0x0949 Clock Input Control and Configuration

input pin. To place the input buffer into

Register Name Hex Address

[Bit Field]

IN_EN 0x0949[3:0] Enables for the four inputs clocks, IN0 through IN3.

1 to enable.

IN_PULSED_CMOS_EN 0x0949[7:4] Selects CMOS or differential receiver for IN3, IN2, IN1, IN0.

Defaults to differential input.
Differential=0, CMOS=1

5.2.1. Unused Inputs

Unused inputs can be disabled and left unconnected when not in use. Register 0x0949[3:0] defaults the input
clocks to being enabled. Clearing the unused input bits will disable them.

5.2.2. Hitless Input Switching with Phase Buildout

Phase buildout, also referred to as hitless switching, prevents a phase change from propagating to the output when
switching between two clock inputs with the exact same frequency and a fixed phase relationship (i.e., they are
phase/frequency locked, but with a non-zero phase difference). When phase buildout is enabled, the DSPLL
absorbs the phase difference between the two input clocks during a clock switch. When phase buildout is disabled,
the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL loop
bandwidth. It supports a minimum input frequency of 8 kHz, but if a fractional P input divider is used, the input
frequency must be 300 MHz or higher in order to ensure proper performance. Note that hitless switching is not
available in zero delay mode.

Function

Table 12. Hitless Switching Enable Bit

Register Name Hex

Address

[Bit Field]

HSW_EN 0x0536[2] Hitless switching is enabled = 1, or disabled = 0.

24 Rev. 1.0

Function

Si5345-44-42-D-RM

5.2.3. Ramped Input Switching

If switching between input clocks that are not exactly the same frequency (i.e. are plesiochronous), ramped
switching should be enabled to ensure a smooth transition between the two inputs. In this situation, it is also
advisable to enable phase buildout to minimize the input-to-output clock skew after the clock switch ramp has
completed.

When ramped clock switching is enabled, the Si5345/44/42 will very briefly go into holdover and then immediately
exit from holdover. This means that ramped switching will behave the same as an exit from holdover. This is
particularly important when switching between two input clocks that are not the same frequency because the
transition between the two frequencies will be smooth and linear. Ramped switching should be turned off when
switching between input clocks that are always frequency locked (i.e. are the same exact frequency). Because
ramped switching avoids frequency transients and overshoot when switching between clocks that are not the same
frequency, CBPro defaults to ramped clock switching. The same ramp rate settings are used for both exit from
holdover and clock switching. For more information on ramped exit from holdover including the ramp rate, see “4.7.
Holdover Mode”.

Table 13. Ramped Input Switching Control Registers

Setting Name Hex Address [Bit Field] Function

RAMP_SWITCH_EN 0x05A6[3] Enable frequency ramping on an input switch.

HSW_MODE 0x053A[1:0] Input switching mode select.

5.2.4. Glitchless Input Switching

The DSPLL has the ability to switch between two input clock frequencies that are up to ±500 ppm apart. The
DSPLL will pull-in to the new frequency at a rate determined by the DSPLL loop bandwidth. The DSPLL loop
bandwidth is set using registers 0x0508–0x050D. Note that if “Fastlock” is enabled then the DSPLL will pull-in to
the new frequency using the Fastlock Loop Bandwidth. Depending on the LOL configuration settings, the loss of
lock (LOL) indicator may assert while the DSPLL is pulling-in to the new clock frequency. There will never be output
runt pulses generated at the output during the transition.

Rev. 1.0 25

Si5345-44-42-D-RM

DSPLL

100 ns 100 ns

12345678910

123456789

100 MHz clock

1 missing period every 10

90 MHz non-gapped clock

10 ns

11.11111... ns

Gapped Input Clock Periodic Output Clock

Period Removed

DSPLL

LPFPD

÷M

IN0

IN0

Precision

Fast

OOF

LOS

÷P

0

IN1

IN1

Precision

Fast

OOF

LOS

÷P

1

IN3/FB_IN

IN3/FB_IN

Precision

Fast

OOF

LOS

÷P

3

IN2

IN2

Precision

Fast

OOF

LOS

÷P

2

LOL

XB

XA

OSC

LOS

Si5345/44/42

5.2.5. Synchronizing to Gapped Input Clocks

The DSPLL supports locking to an input clock that has missing clock periods. This is also referred to as a gapped
clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing
some of its cycles. Gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and
low loop bandwidth is required to produce a low-jitter, truly periodic clock. The resulting output will be a periodic
non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of
100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. A valid
gapped clock input must have a minimum frequency of 10 MHz with a maximum of 2 missing cycles out of every 8.

When properly configured, locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock
switching between gapped clocks may violate the hitless switching specification of up to 1.5 ns for a maximum
phase transient, when the switch occurs during a gap in either input clocks. Figure 8 shows a 100 MHz clock with
one cycle removed every 10 cycles, which results in a 90 MHz periodic non-gapped output clock.

Figure 8. Generating an Averaged Non Gapped Output Frequency from a Gapped Input

5.3. Fault Monitoring

The four clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF).
Note that the reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for
the DSPLL. There is also a Loss of Lock (LOL) indicator asserted when the DSPLL loses synchronization within
the feedback loop. Figure 9 shows the fault monitors for each input path going into the DSPLL, which includes the
crystal input as well as IN0-3.

26 Rev. 1.0

Figure 9. Si5342/44/45 Fault Monitors

Si5345-44-42-D-RM

LOS

en

Monitor

LOS

LOS

Sticky

Live

5.3.1. Input Loss of Signal (LOS) Fault Detection

The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing
clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing
edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS
status for each of the monitors is accessible by reading a status register. The live LOS register always displays the
current LOS state and a sticky register when set, always stays asserted until cleared by the user.

Figure 10. LOS Status Indicators

A LOS monitor is also available to ensure that the external crystal or reference clock is valid. By default the output
clocks are disabled when LOSXAXB is detected. This feature can be disabled such that the device will continue to
produce output clocks even when LOSXAXB is detected. Single-ended inputs must be connected to the XA input
pin with the XB pin terminated properly for LOSXAXB to function correctly. The table below lists the loss of signal
status indicators and fault monitoring control registers.

Table 14. Loss of Signal Status Monitoring and Control Registers

Register Name Hex

Address

[Bit Field]

LOS 0x000D[3:0] LOS status monitor for IN3 (bit3), IN2 (bit2), IN1(bit1), IN0 (bit0) indicates if a

valid clock is detected. A set bit indicates the input is LOS.

SYSINCAL 0x000C[0] Asserted when in calibration

LOSXAXB 0x000C[1] LOS status monitor for the STAL or REFCLK at the XA/XB pins

LOS_FLG 0x0012[3:0] LOS status monitor sticky bits for IN3, IN2, IN1, IN0. Sticky bits will remain

asserted when a LOS event occurs until manually cleared. Writing zero to the
bit will clear it.

SYSINCAL_FLG 0x0011[0] SYSINCAL sticky bit. Sticky bits will remain asserted until written with a zero to

clear.

LOSXAXB_FLG 0x0011[1] LOS status monitor sticky bits for XAXB. Sticky bits will remain asserted when

a LOS event occurs until cleared. Writing zero to the bit will clear it.

LOS_EN 0x002C[3:0] LOS monitor enable for IN3, IN2, IN1, IN0. Allows disabling the monitor if

unused.
0: Disable LOS Detection
1: Enable LOS Detection (default)

LOSXAXB_DIS 0x002C[4] Enable LOS detection on the XAXB inputs.

0: Enable LOS Detection (default)
1: Disable LOS Detection

Function

Rev. 1.0 27

Si5345-44-42-D-RM

en

en

Precision

Fast

OOF

Monitor

LOS

OOF

Sticky

Live

OOF

Reference

Hysteresis Hysteresis

OOF Declared

OOF Cleared

-6 ppm

(Set)

-4 ppm

(Clear)

0 ppm

+4 ppm

(Clear)

+6 ppm

(Set)

f

IN

Table 14. Loss of Signal Status Monitoring and Control Registers (Continued)

Register Name Hex

Function

Address

[Bit Field]

LOS_TRIG_THR 0x002E[7:0]-

0x0035[7:0]

Sets the LOS trigger threshold and clear sensitivity for IN3, IN2, IN1, IN0.
These 16- bit values are determined by ClockBuilder Pro

LOS_CLR_THR 0x0036[7:0]-

0x003D[7:0]

LOS_VAL_TIME 0x002D[7:0] LOS clear validation time for IN3, IN2, IN1, IN0. This sets the time that an input

must have a valid clock before the LOS condition is cleared. Settings of 2ms,
100ms, 200ms, and 1 s are available.

LOS_INTR_MSK 0x0018[3:0] This is the LOS interrupt mask, which can be cleared to trigger an interrupt on

the INTR pin if an LOS occurs for IN0-3.

5.3.2. Out of Frequency (OOF) Fault Detection

Each input clock is monitored for frequency accuracy with respect to an OOF reference which it considers as its
0 ppm reference. This OOF reference can be selected as either:

XA/XB pins
Any input clock (IN0, IN1, IN2, IN3)

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as
shown in Figure 9. An option to disable either monitor is also available. The live OOF register always displays the
current OOF state and its sticky register bit stays asserted until cleared.

The Precision OOF monitor circuit measures the frequency of all input clocks to within up to ±1 ppm accuracy with
respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the
register-programmable OOF frequency range of from ±2 ppm to ±500 ppm in steps of 1/16 ppm. A configurable
amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example
is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm
and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead
of the XAXB pins is available. These options are all register configurable.

Figure 12. Example of Precise OOF Monitor Assertion and De-assertion Triggers

28 Rev. 1.0

Figure 11. OOF Status Indicator

Si5345-44-42-D-RM

Table 15 lists the OOF monitoring and control registers. Because the precision OOF monitor needs to provide
1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a
relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An
additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to
quickly detect a ramping input frequency. The Fast OOF responds more quickly and has larger thresholds.

Table 15. Out-of-Frequency Status Monitoring and Control Registers

Register Name Hex Address

[Bit Field]

OOF 0x000D[7:4] OOF status monitor for IN3, IN2, IN1, IN0. Indicates if a valid clock is

detected or if a OOF condition is detected.

OOF_FLG 0x0012[7:4] OOF status monitor sticky bits for IN3, IN2, IN1, IN0. Stick bits will

remain asserted when an OOF event occurs until cleared. Writing zero
to the bit will clear it.

OOF_INTR_MSK 0x0018[7:4] Masks OOF from generating INTR

0: Allow OOF interrupt (default)
1: Mask (ignore) OOF for interrupt

OOF_REF_SEL 0x0040[2:0] This selects the clock that the OOF monitors use as the 0 ppm refer-

ence. Selections are XA/XB, IN0, IN1, IN2, IN3. Default is XAXB.

OOF_EN 0x003F[3:0] This allows to enable/disable the precision OOF monitor for IN3, IN2,

IN1, IN0

FAST_OOF_EN 0x003F[7:4] This allows to enable/disable the fast OOF monitor for IN3, IN2, IN1,

IN0

OOF_SET_THR 0x0046[7:0]-

0x0049[7:0]

OOF_CLR_THR 0x004A[7:0]-

0x004D[7:0]

OOF Set threshold. Range is up to

OOF Clear threshold. Range is up to

Function

interrupt for IN3 – IN0.

500 ppm in steps of 1/16 ppm

500 ppm in steps of 1/16 ppm

FAST_OOF_SET_THR 0x0051[7:0]-

0x0054[7:0]

FAST_OOF_CLR_THR 0x0055[7:0]-

0x0058[7:0]

5.3.3. Loss of Lock Fault Monitoring

The Loss of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its
selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL
monitor functions by measuring the frequency difference between the input and feedback clocks at the phase
detector. There are four parameters to the LOL monitor,

1. Assert to set the LOL,

a. User sets the threshold in ppm in CBPro

2. Fast assert to set the LOL

a. CBPro sets this to ~100 times the assert threshold

b. A very large ppm error in a short time will assert the LOL

3. De-assert to clear the LOL

a. User sets the threshold in ppm in CBPro

Determines the fast OOF alarm set threshold for IN3, IN2, IN1, IN0.

Determines the fast OOF alarm clear threshold for IN3, IN2, IN1, IN0.

Rev. 1.0 29

Si5345-44-42-D-RM

DSPLL

LPFPD

÷M

Si5345/44/42

LOL

Clear

LOL

Set

Timer

LOL

LOS

LOL

Sticky

Live

LOL Monitor

f

IN

Feedback

Clock

Phase Detector Frequency Difference (ppm)

Hysteresis

LOL

LOCKED

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

0

Lost Lock

0.1 1

10,000

4. Clear delay

a. CBPro sets this based upon the project plan

A block diagram of the LOL monitor is shown in Figure 13. The live LOL register always displays the current LOL
state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL
monitor.

The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to
10000 ppm. CBPro provides a wide range of set and clear thresholds for the LOL function. Having two separate
frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration of the
LOL set and clear thresholds is shown in Figure 14.

Figure 14. LOL Set and Clear Thresholds

Table 16. Loss of Lock Status Monitor and Control Registers

Register Name Hex Address

30 Rev. 1.0

LOL 0x000E[1] Status bit that indicates if the DSPLL is locked to an input clock

LOL_FLG 0x0013[1] Sticky bits for LOL register. Writing 0 to a sticky bit will clear it.

LOL_SET_THR 0x009E[7:4] Configures the loss of lock set threshold in ppm.

LOL_CLR_THR 0x00A0[7:4] Configures the loss of lock clear threshold in ppm.

Figure 13. LOL Status Indicators

[Bit Field]

Function