Silicon Laboratories Si5341, Si5340 User Manual
Si5341/40
GND
Pad
IN1
IN1
IN_SEL0
IN_SEL1
SYNC
RST
X1
XA
XB
X2
OE
INTR
VDDA
IN2
IN2
SCLK
A0/CS
SDA/SDIO
A1/SDO
VDD
RSVD
RSVD
VDDO0
OUT0
OUT0
FDEC
OUT1
OUT1
VDDO2
OUT2
OUT2
FINC
LOL
VDD
OUT6
OUT6
VDDO6
OUT5
OUT5
VDDO5
I2C_SEL
OUT4
OUT4
VDDO4
OUT3
OUT3
VDDO3
VDDO7
OUT7
OUT7
VDDO8
OUT8
OUT8
OUT9
OUT9
VDDO9
VDD
FB_IN
FB_IN
IN0
IN0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
171819202122232425262728293031
32
646362616059585756555453525150
49
VDDO1
Si5341 64QFN
Top View
RSVD
RSVD
GND
Pad
IN1
IN1
IN_SEL0
INTR
X1
XA
XB
X2
OE
RST
VDDA
VDDA
IN2
A0/CS
SDA/SDIO
A1/SDO
OUT0
OUT0
VDDO0
SCLK
I2C_SEL
OUT1
OUT1
VDDO1
VDDO3
OUT3
OUT3
FB_IN
FB_IN
IN0
IN0
Si5340 44QFN
Top View
1
2
3
4
5
6
7
8
9
10
33
32
31
30
29
28
27
26
25
24
121314151617181920
21
444342414039383736
35
VDD
OUT2
OUT2
VDDO2
VDDS
LOL
LOS_XAXB
VDD
IN_SEL1
IN2
11
23
NC
22
VDD
VDD
34
LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT
CLOCK GENERATOR
Features
Generates free-running or
synchronous output clocks
MultiSynth™ technology enables
any-frequency synthesis on anyoutput with 0 ppm frequency
accuracy with respect to the input
Highly configurable outputs
compatible with LVDS, LVPECL,
L VCMOS, HCSL, or programmable
voltage swing and common mode
Excellent jitter: <100 fs RMS typ
Input frequency rang e:
External crystal: 25, 48-54 MHz
Differential clock: 10 to 750 MHz
LVCMOS clock: 10 to 250 MHz
Output frequency ra nge:
Differential: 100 Hz to 800 MHz
LVCMOS: 100Hz to 250 MHz
Output-output skew: <100 ps
Adjustable output-output delay
Optional zero delay mode
Independent glitchless on-the-fly
output frequency changes
Applications
DCO mode with frequency
increment and decrement as low as
0.001 ppb/step
Core voltage:
V
: 1.8 V ±5%
DD
V
: 3.3 V ±5%
DDA
Independent output supply pins:
3.3V, 2.5V, or 1.8V
Built-in power supply filtering
Status monitoring: LOS, LOL
Serial Interface: I
2
C or SPI (3-wire
or 4-wire)
In-circuit programmable with non-
volatile OTP memory (2x
programmable)
ClockBuilder Pro
TM
software utility
simplifies device configuration and
assigns customer part numbers
Si5341: 4 input, 10 output, 64 QFN
Si5340: 4 input, 4 outpu t, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Ordering Information:
See section 7
Pin Assignments
Clock tree generation replacing
XOs, buffers, signal format
translators
Any-frequency synchronous clock
translation
Clocking for FPGAs, processors,
memory
Description
The any-frequency, any-output Si5341/40 clock generators combine a wide-band
PLL with proprietary MultiSynth fractional synthesizer technology to offer a
versatile and high performance clock generator platform. This highly flexible
architecture is capable of synthesizing a wide range of integer and non-integer
related frequencies up to 800 MHz on 10 differential clock outputs while
delivering sub-100 fs rms phase jitter performance and 0 ppm error. Each of the
clock outputs can be assigned its own format and output voltage enabling the
Si5341/40 to replace multiple clock ICs and oscillators with a single device
making it a true “clock tree in a chip”.
The Si5341/40 can be quickly and easily configured using ClockBuilder Pro
software. Custom part numbers are automatically assigned using a
ClockBuilderPro for fast, free, and easy factory programming, or the Si53 41/40
can be programmed in-circuit via I
Preliminary Rev. 0.9 7/14 Copyright © 2014 by Silicon Laboratories Si5341/40
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Ethernet switches/routers
OTN framers/mappers/processors
Test equipment & instrumentation
Broadcast video
2
C and SPI serial interface.
Si5341/40
Si5341/40
FB_IN
IN0
IN_SEL
IN1
IN2
XB
XA
XTAL
÷INT
÷INT
÷INT
OSC
Multi
Synth
OUT0
÷INT
OUT1
÷INT
OUT2
÷INT
OUT3
÷INT
OUT4
÷INT
OUT5
÷INT
OUT6
÷INT
OUT7
÷INT
OUT8
÷INT
OUT9
÷INT
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Si5340
Si5341
PLL
÷INT
NVM
I2C/SPI
Control/
Status
Functional Block Diagram
2 Preliminary Rev. 0.9
Si5341/40
TABLE OF CONTENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3. Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.4. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.5. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.6. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.7. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.8. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.9. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.1. Si5341 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.2. Si5340 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
11. D
evice Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Appendix—Advance Product Information Revision History . . . . . . . . . . . . . . . . . . . . . . .46
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Preliminary Rev. 0.9 3
Si5341/40
PCB Clock Tree
Level
Translator
Clock
Generator
161.1328125
MHz
Buffe r
133.33 MHz
Buffer
One Si5341 replaces:
3x crystal oscillators (XO)
4x b u ffe rs
1x clock generator
2x le v e l tra n sla tors
1x delay line
“Clock Tree
O n -a -C h ip ”
XA
XB
25 MHz
4x 200 MHz
2.5V LVCMO S
2x 161.1328125 MHz
LVDS
2x 133.33 MHz
1.8V LVCMO S
Buffer
125 MHz
Level
Translator
Buffe r
Delay Line
4x 125 MHz
3.3V LVCMOS
3x 125 MH z
LVPECL
Si5341
N
n0
N
d0
LPF
PD
PLL
÷
M
n
M
d
Free Run
Mode
OSC
N
n1
N
d1
t
2
N
2n
N
2d
N
3n
N
3d
N
4n
N
4d
161.1328125MHz
133.33MH z
125MHz
XA
XB
125MHz
200MHz
1x 161.1328125 MHz
LVDS
1x 161.1328125 MHz
LVDS
2x 133.33 MHz
1.8V LVCMOS
2x 125 MHz
3.3V LVCMOS
2x 125 MHz
3.3V LVCMOS
2x 200 MHz
2.5V LVCMOS
2x 200 MHz
2.5V LVCMOS
1x 125 MHz
LVPECL
1x 125 MHz
LVPECL
1x 125 MHz
LVPECL
25 MHz
1. Typical Application Schematic
4 Preliminary Rev. 0.9
Figure 1. Using The Si5341 to Replace a Discrete Clock Tree
Si5341/40
50
50
100
OUT
OUT
I
DDO
Differential Output Test Configuration
50
OUTa
I
DDO
5 pF
LVCMOS Output Test Configuration
6 inch
OUTb
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD=1.8V ±5%, V
Parameter Symbol Min Typ Max Units
Ambient Temperature T
Junction Temperature TJ
Core Supply Voltage V
Output Driver Supply Voltage V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD=1.8V ±5%, V
=3.3V ±5%,TA= –40 to 85 °C)
DDA
A
MAX
DD
V
DDA
DDO
=3.3V ±5%, V
DDA
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)
DDO
–402585°C
——125°C
1.71 1.80 1.89 V
3.14 3.30 3.47 V
3.14 3.30 3.47 V
2.38 2.50 2.62 V
1.71 1.80 1.89 V
Parameter Symbol Test Condition Min Typ Max Units
Core Supply Current I
Output Buffer Supply Current I
DD
I
DDA
DDOx
Si5341 or
Si5340
LVPECL Output
Notes 1,
2
—98140mA
—115125mA
3
—2325mA
@ 156.25 MHz
LVDS Output
3
—1618mA
@ 156.25 MHz
3.3V LVCMOS
4
output
—1926mA
@ 156.25 MHz
2.5 V LVCMOS
output
—1519mA
4
@ 156.25 MHz
1.8 V LVCMOS
output
—1113mA
4
@ 156.25 MHz
2,5
5
— 836 945 mW
— 645 — mW
Total Power Dissipation P
d
Si5341 Notes 1,
Si5340 Notes
Notes:
1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Differential outputs terminated into an AC coupled 100 load.
4. LVCMOS outputs measured into a 6 inch 50 PCB trace with 5 pF load.
5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Preliminary Rev. 0.9 5
Si5341/40
Table 3. Input Specifications
(VDD=1.8V ±5%, V
Parameter Symbol Test Condition Min Typ Max Units
=3.3V ±5%, TA=–40 to 85°C)
DDA
Differential or Single-Ended - AC Coupled (IN0/IN0
Input Frequency Range f
Voltage Swing V
IN_DIFF
IN
, IN1/IN1, IN2/IN2, FB_IN/FB_IN)
10 — 750 MHz
fin < 400 MHz 100 — 1000 mVpp_se
600 MHz < f
<
in
225 — 1000 mVpp_se
800 MHz
> 800 MHz 375 — 1000 mVpp_se
f
in
Slew Rate
1, 2
SR 400 — — V/µs
Duty Cycle DC 40 — 60 %
Capacitance C
IN
—2 — pF
LVCMOS - DC Coupled (IN0, IN1, IN2)
Input Frequency f
IN_CMOS
Input Voltage V
Slew Rate
1, 2
IL
V
IH
SR 400 — — V/µs
10 — 250 MHz
-0.1 — 0.33 V
0.80 — — V
Duty Cycle DC Clock Input 40 — 60 %
Minimum Pulse Width PW Pulse Input 1.6 — — ns
Input Resistance R
IN
—8 — kΩ
REFCLK (Applied to XA/XB)
REFCLK Frequency f
IN_REF
Frequency range
48 — 54 MHz
for best output
jitter performance
10 — 120 MHz
Input Voltage Swing V
Slew rate
1, 2
IN
SR Imposed for best
350 — 1600 mVpp_se
400 — — V/µs
jitter performance
Input Duty Cycle DC 40 — 60 %
Notes:
1. Imposed for jitter performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf
3. V
is determined by the IO_VDD_SEL bit. It is selectable as V
DDIO
DDA
or VDD.
= ((0.8 - 0.2) * V
80-20
IN_Vpp_se
) / SR.
6 Preliminary Rev. 0.9
Table 4. Control Input Pin Specifications
OUTx
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
Vcm
Vcm
(VDD=1.8V ±5%, V
Parameter Symbol Test Condition Min Typ Max Units
=3.3V ±5%, V
DDA
= 3.3 V ±5%, 1.8 V ±5%, TA= –40 to 85 °C)
DDS
Si5341/40
Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST
Input Voltage V
Input Capacitance C
Input Resistance I
IL
V
IH
IN
L
, OE, SYNC, A1, SCLK, A0/CS, FINC, FDEC)
-0.1 — 0.3xV
DDIO
1
—3.6 V
0.7xV
DDIO
*
—2— pF
—20— k
Minimum Pulse Width PW RST 50 — — ns
Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST
Input Voltage V
Input Capacitance C
Input Resistance I
IL
V
IH
IN
L
, OE, A1, SDA, SDI, SCLK, A0/CS)
–0.1 — 0.3xV
DDIO
*
—3.6 V
0.7xV
—2— pF
—20— k
DDIO
*
Minimum Pulse Width PW RST 50 — — ns
*Note: V
is determined by the IO_VDD_SEL bit. It is selectable as V
DDIO
DDA
or VDD.
Table 5. Differential Clock Output Specifications
(VDD= 1.8 V ±5%, V
= 3.3V ±5%, V
DDA
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)
DDO
V
V
Parameter Symbol Test Condition Min Typ Max Units
Output Frequency f
OUT
0.0001 — 800 MHz
Duty Cycle DC f < 400 MHz 48 — 52 %
400 MHz < f < 800 MHz 45 — 55 %
Output-Output Skew T
OUT-OUT
Skew T
SK_OUT
SK
Differential Output — — 100 ps
Measured from the positive
——100 ps
to negative output pins
Notes:
1. Normal swing mode, high swing mode, Vswing and Cmode settings are programmable through register settings and
can be stored in NVM. Each output driver can be programmed independently.
2. Not all combinations of voltage swing and common mode voltages settings are possible.
3. Common mode voltage min/max variation = ±4% from typical value
4. Driver output impedance depends on selected output mode (Normal, High).
5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/
3.3 V = 100 mVpp) and noise spur amplitude measured.
Preliminary Rev. 0.9 7
Si5341/40
OUTx
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
Vcm
Vcm
Table 5. Differential Clock Output Specifications (Continued)
(VDD= 1.8 V ±5%, V
Parameter Symbol Test Condition Min Typ Max Units
Output Voltage Swing
Common Mode Voltage
Rise and Fall Times
(20% to 80%)
Differential Output Impedance
Notes:
1. Normal swing mode, high swing mode, Vswing and Cmode settings are programmable through register settings and
can be stored in NVM. Each output driver can be programmed independently.
2. Not all combinations of voltage swing and common mode voltages settings are possible.
3. Common mode voltage min/max variation = ±4% from typical value
4. Driver output impedance depends on selected output mode (Normal, High).
5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/
3.3 V = 100 mVpp) and noise spur amplitude measured.
= 3.3V ±5%, V
DDA
1
1, 2, 3
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)
DDO
Normal Swing Mode
V
OUT
=3.3V,
DDO
2.5 V, or 1.8 V
LVDS 370 470 570 mVpp_se
LVPECL 650 820 1050
V
High Swing Mode
V
OUT
DDO
=3.3V,
LVDS 310 420 530 mVpp_se
V
2.5 V, or 1.8 V
V
DDO
=3.3V
LVPECL 590 830 1060
or 2.5 V
Normal Swing or High Swing Modes
V
V
CM
= 3.3 V LVDS 1.12 1.23 1.34 V
DDO
LVPECL 1.90 2.0 2.13
= 2.5 V LVPECL
V
DDO
1.17 1.23 1.3
LVDS
t
R/tF
Normal Swing Mode — 170 220 ps
High Swing Mode — 250 320
4
Z
O
Normal Swing Mode — 100 —
High Swing Mode — Hi-Z —
8 Preliminary Rev. 0.9
Si5341/40
OUTx
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
Vcm
Vcm
Table 5. Differential Clock Output Specifications (Continued)
(VDD= 1.8 V ±5%, V
Parameter Symbol Test Condition Min Typ Max Units
Power Supply Noise Rejection
Output-output Crosstalk XTALK Measured spur from adja-
Notes:
1. Normal swing mode, high swing mode, Vswing and Cmode settings are programmable through register settings and
can be stored in NVM. Each output driver can be programmed independently.
2. Not all combinations of voltage swing and common mode voltages settings are possible.
3. Common mode voltage min/max variation = ±4% from typical value
4. Driver output impedance depends on selected output mode (Normal, High).
5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/
3.3 V = 100 mVpp) and noise spur amplitude measured.
= 3.3V ±5%, V
DDA
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)
DDO
5
PSRR Normal Swing Mode
10 kHz sinusoidal noise — –93 — dBc
100 kHz sinusoidal noise — –93 —
500 kHz sinusoidal noise — –84 —
1 MHz sinusoidal noise — –79 —
High Swing Mode
10 kHz sinusoidal noise — –98 — dBc
100 kHz sinusoidal noise — –95 —
500 kHz sinusoidal noise — –84 —
1 MHz sinusoidal noise — –76 —
cent output
—–73— dBc
Table 6. Output Status Pin Specifications
(VDD=1.8V ±5%, V
Parameter Symbol T est Cond itio n Min Typ Max Units
Si5341 Status Output Pin s (LOL
Output Voltage V
Si5340 Status Output Pins (INTR
Output Voltage V
Si5340 Status Output Pin s (LOL
Output Voltage V
*Note: V
is determined by the IO_VDD_SEL bit. It is selectable as V
DDIO
=3.3V ±5%, V
DDA
= 3.3 V ±5%, 1.8 V ±5%, TA= –40 to 85 °C)
DDS
, INTR)
OH
V
OL
)
OH
V
OL
, LOS_XAXB)
OH
V
OL
IOH = –2 mA V
IOL = 2 mA — — V
IOH = –2 mA V
IOL = 2 mA — — V
IOH = –2 mA V
IOL = 2 mA — — V
Preliminary Rev. 0.9 9
*
x 0.75 — — V
DDIO
1
x 0.15 V
DDIO
*
x 0.75 — — V
DDIO
1
x 0.15 V
DDIO
x 0.85 — — V
DDS
x 0.15 V
DDS
or VDD.
DDA
Si5341/40
DC Test Configuration
Zs
IOL/I
OH
VOL/V
OH
50
5 pF
AC Test Configuration
Rs
Zs
Zs + Rs = 50 Ohms
Table 7. LVCMOS Clock Output Specifications
(VDD= 1.8 V ±5%, V
Parameter Symbol Test Condition Min Typ Max Units
Output Frequency 0.0001 — 250 MHz
Duty Cycle DC f < 400 MHz 47 — 53 %
=3.3V ±5%, V
DDA
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)
DDO
400MHz < f < 800MHz 45 — 55
Output-to-Output Skew T
Output Voltage High
1, 2, 3
SK
V
OH
CMOS1 I
CMOS2 I
CMOS3 I
CMOS1 I
CMOS2 I
CMOS3 I
CMOS1 I
CMOS2 I
CMOS3 I
–10 mA V
OH =
–12 mA — —
OH =
–17 mA — —
OH =
–6 mA V
OH =
–8 mA — —
OH =
–11 mA — —
OH =
–3 mA V
OH =
–4 mA — —
OH =
–5 mA — —
OH =
——100ps
V
= 3.3 V
DDO
x 0.85 — — V
DDO
= 2.5 V
V
DDO
x 0.85 — — V
DDO
= 1.8 V
V
DDO
x 0.85 — — V
DDO
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are CMOS1, CMOS2, CMOS3.
2. I
is measured at VOL/VOH as shown in the DC test configuration
OL/IOH
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ohm PCB trace. A 5 pF
capacitive load is assumed.
10 Preliminary Rev. 0.9
Table 7. LVCMOS Clock Output Specifications (Continued)
DC Test Configuration
Zs
IOL/I
OH
VOL/V
OH
50
5 pF
AC Test Configuration
Rs
Zs
Zs + Rs = 50 Ohms
(VDD= 1.8 V ±5%, V
Parameter Symbol Test Condition Min Typ Max Units
Output Voltage Low
LVCMOS Rise and Fall
3
Times
(20% to 80%)
=3.3V ±5%, V
DDA
1, 2, 3
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)
DDO
V
OL
CMOS1 I
CMOS2 I
CMOS3 I
CMOS1 I
CMOS2 I
CMOS3 I
CMOS1 I
CMOS2 I
CMOS3 I
=10mA — — V
OL
=12mA — —
OL
=17mA — —
OL
=-6mA — — V
OH
=8mA — —
OL
=11mA — —
OL
=–3mA — — V
OH
=–4mA — —
OH
=5mA — —
OL
tr/tf VDDO = 3.3V — 360 — ps
VDDO = 2.5 V — 420 — ps
VDDO = 1.8 V — 280 — ps
V
V
V
DDO
DDO
DDO
= 3.3 V
=2.5V
=1.8V
Si5341/40
x 0.15 V
DDO
x 0.15 V
DDO
x 0.15 V
DDO
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are CMOS1, CMOS2, CMOS3.
2. I
is measured at VOL/VOH as shown in the DC test configuration
OL/IOH
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ohm PCB trace. A 5 pF
capacitive load is assumed.
Preliminary Rev. 0.9 11
Si5341/40
Table 8. Performance Characteristics
(VDD=1.8V ±5%, V
Parameter Symbol Test Condition Min Typ Max Units
=3.3V ±5%, TA=–40 to 85°C)
DDA
PLL Loop Bandwidth f
Initial Start-Up Time t
1
POR
to Serial Interface
Ready
PLL Lock Time t
Output delay adjustment t
t
Jitter Generation
Locked to External Clock
1
BW
START
t
RDY
ACQ
DELAY
RANGE
J
RMS
J
PER
J
CC
J
PER
J
CC
Time from power-up to when the
device generates free-running
clocks
f
=14GHz
VCO
Delay is controlled by the Multi-
Synth
Integer Mode
2
12 kHz to 20 MHz
Fractional/DCO Mode
3
12 kHz to 20 MHz
Derived from
integrated phase noise
N = 10,000 cycles
Integer or Fractional Mode
2,3
.
Measured in the time domain.
Performance is limited by the
noise floor of the
equipment.
—1.0— MHz
—30— ms
——10 ms
——120 ms
—0.28— ps
— ±9.14 — ns
— 0.115 0.200 ps RMS
— 0.170 0.400 ps RMS
— 0.140 — ps pk-pk
— 0.250 — ps pk
— 7 .3 — ps pk-pk
—8.1— ps pk
Jitter Generation
Locked to External XTAL
J
RMS
XTAL Frequency = 48 MHz to 54 MHz
Integer Mode
2
— 0.100 0.160 ps RMS
12 kHz to 20 MHz
Fractional/DCO Mode
3
— 0.140 0.350 ps RMS
12 kHz to 20 MHz
J
J
J
J
PER
CC
PER
CC
Derived from
integrated phase noise
N = 10, 000 cycles
Integer or Fractional Mode
2,3
Measured in the time domain.
— 0.150 — ps pk-pk
— 0.270 — ps pk
— 7 .3 — ps pk-pk
.
—7.8— ps pk
Performance is limited by the
noise floor of the equipment.
Notes:
1. Jitter generation test conditions in synchronous mode: f
jitter from PLL input reference.
2. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.
3. Fractional and DCO modes assumes that the output dividers (Nn/Nd) are configured with a fractional value.
12 Preliminary Rev. 0.9
= 100 MHz, f
IN
= 156.25 MHz LVPECL. Does not include
OUT
Si5341/40
Table 9. I2C Timing Specifications (SCL,SDA)
Parameter Symbol Test Condition Min Max Min Max Units
SCL Clock
f
SCL
Frequency
SMBus Timeout — When Timeout is
Enabled
Hold time
t
HD:STA
(repeated) ST ART
condition
Low period of the
t
LOW
SCL clock
HIGH period of
t
HIGH
the SCL clock
Set-up time for a
t
SU:STA
repeated START
condition
Data hold time t
Data set-up time t
Rise time of both
HD:DAT
SU:DAT
t
r
SDA and SCL signals
Standard Mode
100 kbps
Fast Mode
400 kbps
0 100 0 400 kHz
25 35 25 35 ms
4.0 — 0.6 — µs
4.7 — 1.3 — µs
4.0 — 0.6 — µs
4.7 — 0.6 — µs
5.0 — — — µs
250 — 100 — ns
— 1000 20 300 ns
Fall time of both
SDA and SCL signals
Set-up time for
STOP condition
Bus free time
between a STOP
and START condition
Data valid time t
Data valid
acknowledge time
t
f
t
SU:STO
t
BUF
VD:DAT
t
VD:ACK
— 300 — 300 ns
4.0 — 0.6 — µs
4.7 — 1.3 — µs
—3.45 — 0.9µs
—3.45 — 0.9µs
Preliminary Rev. 0.9 13
Si5341/40
Figure 2. I2C Serial Port Timing Standard and Fast Modes
14 Preliminary Rev. 0.9
Table 10. SPI Timing Specifications
SCLK
CS
SDI
SDO
T
SU1
T
D1
T
SU2
T
D2
T
C
T
CS
T
D3
T
H2
T
H1
(VDD= 1.8 V ±5%, V
= 3.3V ±5%, TA=–40 to 85°C)
DDA
Parameter Symbol Min Typ Max Units
Si5341/40
SCLK Frequency f
SCLK Duty Cycle T
SPI
DC
——20MHz
40 — 60 %
SCLK Rise & Fall Time Tr/Tf — — 10 ns
SCLK High & Low Time T
SCLK Period T
Delay Time, SCLK Fall to SDO Active T
Delay Time, SCLK Fall to SDO T
Delay Time, CS
Setup Time, CS
Hold Time, CS
Rise to SDO Tri-State T
to SCLK T
to SCLK Rise T
Setup Time, SDI to SCLK Rise T
Hold Time, SDI to SCLK Rise T
Delay Time Between Chip Selects (CS
)TCS50 — — ns
HL
C
D1
D2
D3
SU1
H1
SU2
H2
50 — — ns
— — 12.5 ns
— — 12.5 ns
— — 12.5 ns
25 — — ns
25 — — ns
12.5 — — ns
12.5 — — ns
Figure 3. SPI Serial Interface Timing
Preliminary Rev. 0.9 15
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