Silicon Laboratories Si5338-EVB User Manual
Si5338-EVB
Si5330/34/35/38 EVALUATION BOARD USER’S GUIDE
Description
The Si5338-EVB is used for evaluating the Si5330/34/
35/38 family of any-frequency, any-output clock
generators and clock buffers.
EVB Features
Fully powered from a single USB port.
Onboard 25 MHz XTAL allows standalone
asynchronous operation on the Si5334/35/38.
GUI programmable V
operate from 3.3, 2.5, or 1.8 V.
GUI programmable V
four outputs to have its own supply voltage
selectable from 3.3, 2.5, 1.8, or 1.5 V
GUI-controlled voltage, current, and power
measurements of V
Voltage supply jumpers allow easy access for use of
external supplies or current measurements.
Input signal jumpers allow external control of pin
functions such as output enable, phase inc/dec,
frequency inc/dec, and I2C_LSB.
supply allows device to
DD
supplies allow each of the
DDO
and all four V
DD
DDO
supplies.
Rev. 1.4 11/11 Copyright © 2011 by Silicon Labs Si5338-EVB
Si5338-EVB
XTAL
MCU
USB
Connector
0
* indicates unpopulated components
IN1
0
IN2
IN5
IN6
IN3
IN4
*
*
CLK0A
CLK0B
VDDO0
VReg
VReg
VReg
VReg
CLK1A
CLK1B
VDDO1
term
*
term
*
term
*
term
*
CLK2A
CLK2B
VDDO2
term
*
term
*
CLK3A
CLK3B
VDDO3
term
*
term
*
Si5338
VReg
term
*
term
*
VDD
To
I2C
Bus
IN7/SCL
IN8/SDA
INx_CTRL
Jumpers
I2C Bus
To
I2C
Bus
Status
LEDs
Reset
Switch
VDDO
Jumpers
INTR
I2C
Jumpers
VDD
Jumpers
1. Functional Block Diagram
A functional block diagram of the EVB is shown in Figure 1. The MCU performs the USB to I2C conversion,
controls the voltage regulators, monitors the INTR pin, and controls the four status LEDS. It also provides control of
the eight input pins when the INx_CT RL jumpers are populated. There are five programmable voltage regulators
(VDD, VDDO0, VDDO1, VDDO2, VDDO3), which supply power to the Si533x device. VDD and VDDO jumpers
allow the option of powering the device from external supplies, or as a convenient point for measuring current. I
jumpers allow disconnection of the Si533x device from the I
2
C bus to allow external control from another I2C
master.
For the Si5334, Si5335, and Si5338 devices, the EVB is shipped with an onboard 25 MHz XTAL to allow
stand-alone asynchronous operation. For Si5335 emulation, synchronization to an external reference is done via
IN1 and IN2. Removal of the XTAL and addition of two 0 ohm resistors is required. IN3, IN4, IN5, and IN6 are not
available as external clock inputs for Si5335.
2
C
2. Quick Start
1. Install the ClockBuilder™ Desktop software and driver (assumes that Microsoft .NET Framework 1.1 is already
installed).
2. Connect a USB cable from the EVB to the PC where the software was installed.
3. Leave the jumpers as installed from the factory, and launch the software by clicking on Start Programs
Silicon Laboratories ClockBuilder Desktop. Click one of the shortcuts in the group.
Figure 1. EVB Functional Block Diagram
2 Rev. 1.4
Si5338-EVB
3. Jumpers
The Si5338-EVB is shipped with jumpers installed on the following positions:
VDD—Connects the Si533x VDD pin to the VDD programmable voltage regulator.
VDDO0—Connects the Si533x VDDO0 pin to the VDDO0 programmable voltage regulator.
VDDO1—Connects the Si533x VDDO1 pin to the VDDO1 programmable voltage regulator.
VDDO2—Connects the Si533x VDDO2 pin to the VDDO2 programmable voltage regulator.
VDDO3—Connects the Si533x VDDO3 pin to the VDDO3 programmable voltage regulator.
SCL—Connects the Si533x SCL pin to the I
SDA—Connects the Si533x SDA pin to the I
The INx-CTRL jumpers are optional jumpers for enabling MCU control of the Si533x input pins. This feature may
be available in future software releases.
4. Status LEDS
There are four status LEDs on the Si5338-EVB:
RDY (Green)—Indicates that the EVB is operating normally. This LED should always be on.
2
I
C (Green)—Indicates when there is active I2C communication between the MCU and the Si533x device
or between the MCU and voltage regulators.
USB (Green)—Indicates when there is active communica tion b etween th e PC and th e MCU over the USB
bus.
INTR (Red)—The MCU has detected that the interrupt pin of the Si533x device is enabled. The most
probable cause for an interrupt is beca use the Si533x h as lost its input signal or the PLL has lost lock. The
“Status” tab of the GUI will identify the event that caused the interrupt to occur.
2
C bus from the MCU.
2
C bus from the MCU.
Rev. 1.4 3
Si5338-EVB
5. Inputs
The Si5338-EVB has six SMA connectors (IN1-IN6) for receiving external signals. Two of the signals are
differential, and two are single-ended.
5.1. Differential Inputs (IN1/IN2, IN5/IN6)
The differential inputs only need a differential voltage swing of 300 mV to operate, which makes them compatible
with most differential signal types. See “AN408: Termination Options for Any-Frequency, Any-Output Clock
Generators and Clock Buffers—Si5338, Si5334, Si5330”, or Si5335 data sheet if applicable, for details on
interfacing with compatible signal types. It is also possible to lock the Si5334/35/38 to an external signal generator
using one side of the differential input and grounding its complementary side. Take care not to exceed the max
differential voltage of 1.2 V on these inputs. The board is shipped with a 25 MHz XTAL connected to IN1/IN2. The
XTAL removal and resistor changes are required for Si5335 evaluation with an input clock since only IN1 and IN2
are available for input clocking with Si5335. Note that regardless of device, an y external input to IN1 & IN2 must be
limited to 1.2 V peak-to-peak (see Figure 2 for resistor locations). When evaluating the Si5330, the XTAL must be
removed. The differential input on pins IN5/IN6 is ac-coupled with a 100 line termination (R39).
Figure 2. Optional Termination Resistors for Differential Inputs IN1/IN2
5.2. Single-Ended Inputs (IN3, IN4) [Not supported in Si5335]
These inputs are dc-coupled to the device. They are compatible with a signal swing as low as 100 mV and a
maximum of 3.63 V. The signal should have a minimum amount of dc bias to ensure that it is never below ground
level.
The EVB provides pads for optional input terminations. These may be necessary when interfacing to SSTL and
HSTL signals.
Note: For details on populated vs. non-populated components, refer to "9. Bill of Materials" on page 13.
4 Rev. 1.4
Si5338-EVB
6. Outputs (CLKxA/CLKxB)
Each of the four differential output drivers is capacitively coupled to the SMA connectors; so, the output signal will
have no dc bias. If a signal with dc bias is required, the ac coupling capacitors can be replaced with a 0 resistor.
The EVB provides pads for optional output terminations. These may be necessary when interfacing to SSTL and
HSTL signals.
6.1. Evaluating LVPECL Output Clocks
The EVB by default is populated to allow evaluating of all output clock formats with the exception of LVPECL
outputs. To evaluate LVPECL signals on the Si5338-EVB, a few components must be soldered down on the board.
Take CLK0 for example of. Note that CLK0 has R85, R121/R122, R1/R4, R2/R5, R3/R6, C4/C7, and C15/C17
attached to the nets of interest. The EVB comes with only R121/R122 and C15/C17 installed. This allows support
of all output types except LVPECL.
Evaluating an ac-coupled LVPECL clock on CLK0 requires a bias resistor of 130 or 200 to ground on each of the
output lines depending on driver VDDO. Refer to AN408, or Si5335 data sheet if applicable, for termination d etails.
Make the following changes depending on the CLK0 VDDO voltage:
For 3.3 V LVPECL (ac-coupled)
· Place 200 resistors in place of R1 and R4.
· Place 0 resistors in place of C4 and C7.
For 2.5 V LVPECL (ac-coupled)
· Place 130 resistors in place of R1 and R4.
· Place 0 resistors in place of C4 and C7.
The LVPECL output may also be dc-coupled to an LVPECL receiver. To dc-couple the CLK0 output, make the
component changes below. Note that R2, R3, R5, and R6 depend on VDDO.
Place 0 resistors in place of C15 and C17.
Place 50 resistors in place of R1 and R4.
Place C4 and C7
Select R2 and R3 (and similarly R5 and R6) to give a termination voltage of VTT = VDDO – 2 V.
For LVPECL termination on CLK1, 2, and 3 follow the guidelines above and refer to the schematics in “8.
Si5338-EVB Schematics” as needed.
6.2. Evaluating SSTL/HSTL Output Clocks
To support SSTL/HSTL outputs, either single- ended or differential, replace the output dc blocking capacitors with a
0 resistor. For example, for CLK0 output, replace C15 with 0 resistor for single-ended, or replace both C15 &
C17 with 0 for differential output. Do the same for CLK1,2,3 as needed. Remember to properly terminate at the
receiver input.
The Si5338-EVB can support on-board termination of SSTL/HSTL outputs, if on-board terminated, measurement
of the clock output at the SMA connector would require a high impedance measurement device to prevent
overloading of the output. If on-board output termination is desired, the following components must be installed
(using CLK0 as an example.)
For 1.8 or 2.5 V V
For 3.3 V V
DDO
Follow similar guidelines for CLK1,2,3 as required. Refer to AN408, or Si5335 data sheet if applicable, for more
details on clock termination.
: R2 = 2 k, R3 = 2 k, R1 = 50 , C4 = 0.1 µF
DDO
: R2 = 2.42 k, R3 = 2 k, R1 = 50 , C4 = 0.1 µF
Rev. 1.4 5
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