Silicon Laboratories SI5324 User Manual

Video Timing Solutions

FULLY INTEGRATED,

FREQUENCY FLEXIBLE GENLOCK SOLUTION

DESCRIPTION

Silicon Laboratories’ Si5324 Any-Rate Precision Clock is the industry’s lowest jitter, most

highly integrated video clock IC optimized for genlock applications. Based on Silicon Labs’

patented DSPLL® technology, the Si5324 has a fully integrated, digitally programmable

loop filter that supports loop bandwidths ranging from 4 Hz to 525 Hz as well as a low

phase noise internal VCO. By consuming less than 10% of the overall 3G-SDI jitter budget

required in next generation video applications, the Si5324 simplifies design and eases

system-level SDI jitter testing. In addition, the Si5324 provides any-rate frequency

flexibility by generating virtually any output frequency from 2 kHz to 1.4 GHz from any

input frequency ranging from 2 kHz to 710 MHz enabling a single IC design for multi-rate

video applications.

Application Example: Production Video Switcher

3G/SD/
HD-SDI

3G/SD/
HD-SDI

Cable
Equalizer

Cable
Equalizer

Si554

VCXO

SDI

Reclocker

Si554

VCXO

SDI

Reclocker

Sync

Separator

SDI

Deserializer

SDI

Deserializer

HSYNC

YCbCr

Pclk, hvf

YCbCr

Pclk, hvf

Si5324

Any-Rate

Clock

Genlock

Video

Processor/

Buffer

Si5338

Clock

Generator

Si590

XO

YCbCr

Sample Clock
3G-SDI Reference Clock

SDI

Serializer

HD (74.25 MHz)
HD (74.1758 MHz)
Audio (24.576 MHz)

Processor (66.66 MHz)

Cable Driver

3G/SD/
HD-SDI

FEATURES

• Generates any frequency from 2 kHz to

945 MHz and select frequencies to 1.4 GHz

from an input frequency of 2 kHz to 710 MHz

• Ultra-low jitter 0.58 ps RMS, 5 ps pk-pk at

3G-SDI (10 Hz to 20 MHz)

• Digitally programmable loop bandwidth with

fastlock (4 Hz to 525 Hz)

• Meets 3G-SDI (SMPTE 424M) for timing and

alignment jitter limits

• Genlock, free-run, and digital hold

• Hitless switching between input clocks with

phase build-out

• Manual or automatic (revertive, non-

revertive) input clock selection

• LOL, LOS and FOS alarm outputs

• Configurable signal format per output

(LVPECL, LVDS, CML, CMOS)

• I²C/SPI programmable

• Single supply 1.8, 2.5 or 3.3 V ±10%

with high PSNR

• Pb-free, RoHS compliant

APPLICATIONS

• Video or audio genlock and synchronization

• FPGA SDI SerDes recovered clock generation

• Triple rate 3G/HD/SD-SDI SerDes

• Video capture, conversion, editing and

distribution

• Digital audio or video recording and

playback devices

• Video server

• Video format converter

• Video switcher and frame synchronizer

SOLUTIONS GUIDE

ANY-RATE

FREQUENCY SYNTHESIS

IN A SINGLE IC

Sync Input

Master Sync Generator

2 WEEK

LEAD

TIMES

Video Timing Solutions

www.silabs.com/Timing

ANY-RATE FREQUENCY
FLEXIBILITY

High Performance

The Si5324 is the industry’s lowest jitter
genlock clock IC. The device provides any­rate frequency synthesis simplifying HD
video and audio clock generation. With
jitter performance of 5 ps pk-pk, the Si5324
delivers significant jitter margin in 3G-SDI
serializer applications, reducing design risk
and improved link performance.

Highly Integrated

The Si5324 offers the industry’s most
highly integrated video clock generator IC
requiring no external PLL components (low
pass filter, charge pump, or VCXO). Because
all PLL components are integrated, board­level noise immunity is improved reducing
design risk versus traditional video clock IC
solutions.

Any-Rate Frequency Flexibility

The Si5324’s any rate frequency flexibility
enables a single device to generate all
common genlock reference frequencies
required in next-generation SD/HD video
and audio equipment. The Si5324 is easily
reconfigurable via I2C/SPI interface and
requires no component changes for different
frequency plans, simplifying design reuse.

Industry’s Most Integrated Genlock Solution

Silicon Labs’ Si5324 replaces multi-component video clock ICs, external loop fi lter and
VCXO components with a single IC, simplifying genlock designs.

Traditional Video Clock Solution Silicon Labs Solution

Loop

VCXO

Filter

Jitter

Cleaner

3G-SDI

Clock

HSYNC

SDI

Reference

Crystal

Video

PLL with

Genlock

vs.

HSYNC

Reference

SDI

Crystal

3G-SDI

Clock

SD

Clock

Industry’s Only Quad and Any-Rate Frequency XO/VCXOs

Si534 XO/Si554 VCXO

• Eliminates multiple oscillators,
reduces system cost

• Simplifies BOM and saves board
space and inventory

• Ideal for multi-rate FPGA-based PLLs

Built to Order Samples

Silicon Labs offers an easy-to-use web utility to build and confi gure the
right XO/VCXO for your application. Samples of any frequency XO/VCXO
are available in less than two weeks. www.silabs.com/BuyXO

Recommended Silicon Labs Timing Solutions for Video

Any-Rate Jitter Attenuating Clock Multipliers, Clock Generators and Buffers

Part

Number

Si5324 2/2 Diff I2C or SPI 2 kHz to 710 MHz 2 kHz to 1.4 GHz 5 ps pk-pk 4 Hz • • • 36-QFN
Si5368 4/5 Diff I

Si5338 4/4 Diff I

Si5330

Input/
Output
Clocks

1:4 Diff

1:8 SE

Control Input Frequency Output Frequency Jitter

2

C or SPI 2 kHz to 710 MHz 2 kHz to 1.4 GHz 8 ps pk-pk 60 Hz • • • 100-TQFP

2

C or SPI

Pin

8 to 30 MHz (xtal)

160 kHz to 710 MHz (clock)

5 to 710 MHz Diff

5 to 350 MHz SE

160 kHz to

710 MHz

5 to 710 MHz Diff

5 to 350 MHz SE

36 ps pk-pk 1.6 MHz • • 24-QFN

55 fs rms

Single and Multi-Frequency Crystal-Based XO/VCXO

Part Number Type Frequency Control Frequency Range Jitter Stability/APR Options (ppm) Kv Options (ppm/V) Package

Si530/1 XO Single Pin

Si532/3 XO Dual Pin N/A 6-pad

Si534 XO Quad Pin N/A 8-pad

Si550 VCXO Single Pin

Si552 VCXO Dual Pin 6-pad

Si554 VCXO Quad Pin 8-pad

2

Si570 XO Programmable Any-Rate I

Si571 VCXO Programmable Any-Rate I

Si590/1 XO Single Pin

Si595 VCXO Single Pin 0.7 ps rms ±10 to ±370 45 to 380 6-pad

DSPLL, Silicon Laboratories and the Silicon Labs logo are trademarks of Silicon Laboratories Inc.
their respective owners. For the most up to date information please see your sales representative or visit our website at www.silabs.com.

100, August 09, Rev A SOL-VTS-2009A

C

2

C 0.5 ps rms ±12 to ±375 33 to 356 8-pad

All other product or service names are the property of

10 to 945 MHz

970 to 1134 MHz

1213 to 1417 MHz

10 to 945 MHz

970 to 1134 MHz

1213 to 1417 MHz

10 to 280 MHz
10 to 810 MHz

10 to 1417 MHz

10 to 525 MHz

0.3 ps rms

0.5 ps rms ±12 to ±375 33 to 356

0.3 ps rms ±31.5; ±61.5 N/A 8-pad

0.7 ps rms ±30; ±50; ±100 N/A 6-pad

Minimum

PLL

Bandwidth

—

Silicon Laboratories Inc.
400 West Cesar Chavez • Austin, TX 78701
Toll Free: [phone]
Email: [e-mail] or
[e-mail]
Web site: www.silabs.com

Jitter

Attenuation

±20
±31.5
±61.5

Clock

Generation

Clock

Distribution

• 24-QFN

N/A 6-pad

Package

6-pad