Silicon Laboratories Si5311-BM Datasheet

Si5311

P

RELIMINARY DATA SHEET

RECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR

P

Features

Complete precision high speed clock multiplier and regenerator device:

IC

!

Performs Clock Multiplication to
One of Four Frequency Ranges:
150–167 MHz, 600–668 MHz,

1.2–1.33 GHz, or 2.4–2.67 GHz

!

Jitter Generation as low as

0.5 ps

!

Accepts Input Clock from

for 622 MHz Output

RMS

!

Regenerates a “Clean”, Jitter­Attenuated Version of Input
Clock

!

DSPLL™ Technology Provides
Superior Jitter Performance

!

Small Footprint: 4 mm x 4 mm

!

Low Power: 310 mW typical

9.4–668 MHz

Applications

!

SONET/SDH Systems

!

Terabit Routers

!

Digital Cross Connects

!

Optical Transceiver Modules

!

Gigabit Ethernet Systems

!

Hybrid VCO Modules

Description

The Si5311 is a fully integrated high-speed clock multiplier and clock
regenerator IC. The clock multiplier generates an output clock that is an
integer multiple of the input clock. When the clock multiplier is operating in
either the 150–167 MHz range or the 600–668 MHz range, the clock
regenerator operates simultaneously. The clock regenerator creates a
“clean” version of the input clock by using the clock synthesis phase­locked loop (PLL) to remove unwanted jitter and square up the input
clock’s rising and falling edges. The Si5311 uses Silicon Laboratories
patented DSPLL
eliminating the analog loop filter found in traditional PLL designs.

The Si5311 represents a new standard in low jitter, small size, low power,
and ease-of-use for high speed clock devices. It operates from a single

2.5 V supply over the industrial temperature range (–40°C to 85°C).

™

architecture to achieve superior jitter performance while

Ordering Information:

See page 22.

Pin Assignments

Si5311

MULTSEL1

MULTSEL0

REXT

1

VDD

2

GND

3

REFCLK+

REFCLK–

4

5

6 7 8 9

LOL

Top View

VDD

GND

Pad

GND

GND

17181920

MULTOUT+

CLKIN+

16

10

MULTOUT–

15

14

13

12

11

CLKIN–

PWRDN/CAL

VDD

CLKOUT+

CLKOUT–

VDD

Functional Block Diagram

2

CLKIN+
CLKIN–

Regeneration

2

BUF

DSPLL

Phase-Locked

2

REFCLK+
REFCLK–

TM

Loop

2

MULTSEL1–0

Calibration

Bias Gen

BUF

BUF

REXT

Preliminary Rev. 0.6 6/01 Copyright © 2001 by Silicon Laboratories Si5311-DS06

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

2

CLKOUT+
CLKOUT–

PWRDN/CAL

MULTOUT+
MULTOUT–

LOL

Si5311

2 Preliminary Rev. 0.6

Si5311

T

ABLE OF

C

ONTENTS

Section Page

Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1x Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DSPLL Lock Detection (Loss-of-Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Device Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pin Descriptions: Si5311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Preliminary Rev. 0.6 3

Si5311

Detailed Block Diagram

CLKIN+

CLKIN–

REFCLK+

REFCLK+

REFCLK–

MULTSEL 1- 0

REXT

Regen

Retime

Retime

CLKOUT+

CLKOUT–

c

Phase

Phase

Phase

Detector

Detector

Detector

A/D

DSP

VCO

CLK

Divider

c

MULTOUT+

MULTOUT–

n

Lock

Detector

LOL

2

/

Bias

Bias

Bias

Generation

Generation

Generation

Calibration

PWRDN/CAL

Figure 1. Detailed Block Diagram

4 Preliminary Rev. 0.6

Electrical Specifications

Table 1. Recommended Operating Conditions

Si5311

Parameter Symbol Test Condition

Ambient Temperature T

Si5311 Supply Voltage

2

A

V

DD

1

Min

Typ

–40 25 85 °C

2.375 2.5 2.625 V

Max

1

Notes:

1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.

2. The Si5311 specifications are guaranteed when using the recommended application circuit (including component

tolerance) of Figure 5 on page 13.

V

SIGNAL +

Differential
I/Os

V

ICM

SIGNAL –

, V

OCM

V

IS

(SIGNAL +) – (SIGNAL –)

Differential
Voltage Swing

VID,V

OD

Differential Peak-to-Peak Voltage

t

Unit

Figure 2. Differential Voltage Measurement (CLKIN, REFCLK, CLKOUT, MULTOUT)

CLKIN

MULTOUT

CLKOUT

t

CI-M

1/f

t

M-CO

MULT

Figure 3. CLKIN to CLKOUT, MULTOUT Phase Relationship

CLKIN,
REFCLK,
CLKOUT,
MULTOUT

t

F

t

R

80%

20%

Figure 4. Clock Input and Output Rise/Fall Times

Preliminary Rev. 0.6 5

Si5311

Table 2. DC Characteristics, VDD = 2.5 V

(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Supply Current
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11

Power Dissipation
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11

Common Mode Input Voltage
(CLKIN, REFCLK)

Input Voltage Range*
(CLKIN+, CLKIN–, REFCLK+, REFCLK–)

Differential Input Voltage Swing*
(CLKIN, REFCLK)

Input Impedance (CLKIN, REFCLK) R

Differential Output Voltage Swing
(CLKOUT)

Differential Output Voltage Swing
(MULTOUT)

Output Common Mode Voltage
(CLKOUT, MULTOUT)

Output Impedance (CLKOUT, MULTOUT) R

Output Short to GND (CLKOUT, MULTOUT) I

Output Short to V

(CLKOUT, MULTOUT) I

DD

Input Voltage Low (LVTTL Inputs) V

Input Voltage High (LVTTL Inputs) V

Input Low Current (LVTTL Inputs) I

Input High Current (LVTTL Inputs) I

Output Voltage Low (LVTTL Outputs) V

Output Voltage High (LVTTL Outputs) V

Input Impedance (LVTTL Inputs) R

PWRDN/CAL Internal Pulldown Current I

*Note: The CLKIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage

swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (V
min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the
positive and negative input signals must exceed V
range.) In either case, the voltage applied to any individual pin (CLKIN+, CLKIN–, REFCLK+, or REFCLK–) must not
exceed the specified maximum Input Voltage Range (VIS max).

I

DD

V

V

P

ICM

V

V

D

IS

ID

IN

OD

—
—
—
—

—
—
—
—

See Figure 2 — .80"V

See Figure 2 — — 750 mV

See Figure 2 200 — 1500 mV

Line-to-Line 84 100 116 Ω
100 Ω Load

TBD 940 TBD mV

108
113
117
124

270
283
293
310

118
123
127
134

310
323
333
352

DD

Line-to-Line

V

OD

100 Ω Load

TBD 900 TBD mV

Line-to-Line

V

OCM

100 Ω Load

—VDD–0.7 — V

Line-to-Line

OUT

SC(–)

SC(+)

IL

IH

IL

IH

OL

OH

IN

PWRDNVPWRDN

Single-ended 84 100 116 Ω

—25TBDmA

TBD –15 — mA

—— .8V

2.0 — — V

—25TBDµA
—25TBDµA

IO = 2 mA — — 0.4 V

IO = 2 mA 2.0 — — V

100 — — kΩ

≥ 0.8 V TBD 25 TBD µA

min. (Each individual input signal needs to swing only half of this

ID

mA

mW

—V

(pk-pk)

(pk-pk)

(pk-pk)

ID

6 Preliminary Rev. 0.6

Si5311

Table 3. AC Characteristics

(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

CLKIN Frequency Range

*

CLKIN Duty Cycle TBD — TBD %

REFCLK Range

*

9.375 — 668 MHz

9.375 — 167 MHz

REFCLK Duty Cycle C

REFCLK Frequency
Tolerance

MULTOUT Clock Rate
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11

Output Rise Time
(CLKOUT, MULTOUT)

Output Fall Time
(CLKOUT, MULTOUT)

Input Rise Time
(CLKIN, REFCLK)

Input Fall Time
(CLKIN, REFCLK)

CLKIN to MULTOUT Delay
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11

DUTY

C

TOL

f

MULT

t

t

t

t

t

CI-M

40 50 60 %

–100 — 100 ppm

2400
1200

600
150

R

F

R

F

Figure 4 — 100 TBD ps

Figure 4 — 100 TBD ps

Figure 4 — — TBD ps

Figure 4 — — TBD ps

—
—
—
—

2672
1336

668
167

MHz

Figure 3

TBD
TBD
TBD
TBD

0
120
150

3.4

TBD
TBD
TBD
TBD

ps
ps
ps
ns

MULTOUT to CLKOUT Delay

t

M-CO

Figure 3
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11

Input Return Loss 100 kHz–2.5 GHz

2.5GHz–4.0GHz

*Note: See Table 11.

Preliminary Rev. 0.6 7

—

—
TBD
TBD

18.7
TBD

1/f

MULT

960

—
—

+ 160

—
—

—

—
TBD
TBD

—

—

ps
ps

dB

Si5311

Table 4. AC Characteristics (PLL Performance Characteristics)

(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Jitter Tolerance
(MULTSEL[1:0] = 00,
MULTOUT = 2400 to 2672 MHz)

Jitter Tolerance
(MULTSEL[1:0] = 01,
MULTOUT = 1200 to 1336 MHz)

Jitter Tolerance
(MULTSEL[1:0] = 10,
MULTOUT = 600 to 668 MHz)

Jitter Tolerance
(MULTSEL[1:0] = 11,
MULTOUT = 150 to 167 MHz)

Jitter Generation (MULTOUT)
(MULTSEL[1:0] = 00,
MULTOUT = 2400 to 2672 MHz)*

Jitter Generation (MULTOUT)
(MULTSEL[1:0] = 01,
MULTOUT = 1200 to 1336 MHz)*

Jitter Generation (MULTOUT, CLKOUT)
(MULTSEL[1:0] = 10,
MULTOUT = 600 to 668 MHz)*

Jitter Generation (MULTOUT, CLKOUT)
(MULTSEL[1:0] = 11,
MULTOUT = 150 to 167 MHz)*

Jitter Transfer Bandwidth
(MULTSEL[1:0] = 00,
MULTOUT = 2400 to 2672 MHz)*

*Note: See PLL Performance section of this document for test descriptions.

J

TOL(PP)

J

TOL(PP)

J

TOL(PP)

J

TOL(PP)

J

GEN(rms)

J

GEN(rms

J

GEN(rms)

J

GEN(rms)

J

BW

Clock Input (MHz) =

600.000 to 668.000

Clock Input (MHz) =

300.000 to 334.000

Clock Input (MHz) =

600.000 to 668.000

Clock Input (MHz) =

37.500 to 41.750

Clock Input (MHz) =

75.000 to 83.500

Clock Input (MHz) =

150.000 to 167.000

Clock Input (MHz) =

300.000 to 334.000

Clock Input (MHz) =

600.000 to 668.000

Clock Input (MHz) =

9.375 to 10.438

Clock Input (MHz) =

18.750 to 20.875

Clock Input (MHz) =

37.500 to 41.750

Clock Input (MHz) =

75.000 to 83.500

Clock Input (MHz) =

150.000 to 167.000

Clock Input (MHz) =

600.000 to 668.000

See Table 5

See Table 6

See Table 7

See Table 8

—TBDTBDps

—TBDTBDps

—TBDTBDps

—1.9TBDps

—1.2TBDps

—0.9TBDps

—0.5TBDps

—0.5TBDps

—5.8TBDps

—3.2TBDps

—2.2TBDps

—1.4TBDps

—1.3TBDps

—1360TBDkHz

RMS

RMS

RMS

RMS

RMS

RMS

RMS

RMS

RMS

RMS

RMS

RMS

RMS

8 Preliminary Rev. 0.6