Si5310-EVB
REFCLK
+
–
ZC = 50
Z
C
= 50
ZC = 50
Z
C
= 50
CLKIN
+
–
CLKOUT
+
–
MULTOUT
+
–
ZC = 50
Z
C
= 50
ZC = 50
Z
C
= 50
Pulse
Generator
Freq.
Synth.
Spectrum
Analyzer
Scope
Spectrum
Analyzer
Si5310
LOL
REXT
MULTSEL
PWRDN/CAL
10 k
Jumpers
Si5310-EVB
Rev C
Test
Point
EVALUATION BOARD FOR Si5310 PRECISION CLOCK
ULTIPLIER/REGENERATOR IC
M
Description
The Si5310 evaluation board provides a platform for
testing and characterizing the Silicon Laboratories
Si5310 precision clock multiplier/regenerator IC.
All high-speed I/Os are AC coupled to ease interfacing
to industry standard test equipment.
Function Block Diagram
Features
Single 2.5 V power supply
Differential I/Os ac coupled
Simple jumper configuration
Preliminary Rev. 0.71 1/16 Copyright © 2002 by Silicon Laboratories Si5310-EVB-071
Si5310-EVB
Functional Description
The evaluation board simplifies characterization of the
Si5310 precision clock multiplier/regenerator IC by
providing access to all of the Si5310 I/Os. Device
performance can be evaluated by following the “Test
Configuration” section. Specific performance metrics
include jitter tolerance, jitter generation, and jitter
transfer.
Power supply
The evaluation board requires one 2.5 V supply. Supply
filtering is placed on the board to filter typical system
noise components; however, initial performance testing
should use a linear supply capable of supplying 2.5 V
±5% DC.
CAUTION: The evaluation board is designed so that the
body of the SMA jacks and GND are shorted. Care must
be taken when powering the PCB at potentials other
than GND at 0.0 V and VDD at 2.5 V relative to chassis
GND.
Self-Calibration
The Si5310 device provides an internal self- calibration
function that optimizes the loop gain paramete rs within
the internal DSPLL
high-to-low transition of the PWRDN/CAL signal while a
valid reference clock is supplied to the REFCLK input.
On the Si5310-EVB board, a voltage detector IC is
utilized to initiate self-calibration. The voltage detector
drives the PWRDN/CAL signal low after the supply
voltage has reached a specific voltage level. This circuit
is described in Silicon Laboratories application note
AN42. On the Si5310-EVB, the PWRDN/CAL signal is
also accessible via a jumper located in the lower lefthand corner of the evaluation board. PWRDN/CAL is
wired to the center post (signal post) between 2.5 V and
GND.
Device Power Down
The Si5310 device can be powered down via the
PWRDN/CAL signal. When PWRDN/CAL is dr iven high
(2.5 V) the evaluation board will draw minimal current.
On the Si5310-EVB board, the PWRDN/CAL signal may
be controlled via a jumper located in the lower left-hand
corner of the evaluation board. PWRDN/CAL is wired to
the center post (signal post) between 2.5 V and GND.
CLKIN, CLKOUT, MULTOUT
These high-speed I/Os are wired to the board perimeter
on 30 mi l (0.030 inch ) 50 micros trip lines to the endlaunch SMA jacks as labeled on the PCB. These I/Os
are AC coupled to simplify direct connection to a wide
array of standard test hardware. Because each of these
signals are differential both the positive (+) and negative
(–) terminals must be terminated to 50 . Terminating
TM
. Self-calibration is initiated by a
only one side will degrade the performance of the
Si5310 device. The CLKIN inputs are terminated on the
die with 50 resistors.
Note: The 50 termination is for each termi nal/side of a dif-
ferential signal, thus the differential termination is actually 50 +50 =100.
REFCLK
REFCLK is used to center the frequency of the Si5310
DSPLL so that the device can lock to the CLKIN signal.
For a given CLKIN rate, there are five choices for the
REFCLK frequency. These five options are all multiples
of the CLKIN frequency, as indicated in Table 1. The
REFCLK frequency is automatically detected by the
Si5310 device, so no digital control inputs are needed
for REFCLK frequency selection. REFCLK may be
synchronous or asynchronous with respect to CLKIN.
However, REFCLK must be within ±100 PPM of the
target CLKIN frequency multiple. REFCLK is ac coupled
to the SMA jacks located on the top side of the
evaluation board. The REFCLK inputs are terminated
on the die with 50 resistors.
Note: The 50 termination is for each termi nal/side of a dif-
ferential signal, thus the differential termination is actually 50 +50 =100.
MULTSEL
MULTSEL is a binary input to the Si5310 device that
selects the frequency range for the MULTOUT clock
output. The MULTOUT output frequency is a multiple of
the CLKIN input frequency. The frequency for
MULTOUT will be in either the 150–167 MHz frequency
range or the 600–668 MHz frequency range depending
on the state of the MULTSEL signal as indicated in
Table 1. On the Si5310 evaluation board, MULTSEL is
controlled via a jumper located in the lower left-hand
corner of the board. MULTSEL is wired to the center
post (signal post) between 2.5 V and GND.
The jumper configurations for MULTSEL are indicated
in Figure 1.
2 Rev. 0.71
Si5310-EVB
GND
2.5 V
MULTSEL
Low Range
150–167 MHz
GND
2.5 V
MULTSEL
High Range
600–668 MHz
MULTSEL
PWRDN/
CAL
MULTSEL
PWRDN/
CAL
Table 1. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
MULTSEL CLKIN Range
(MHz)
REFCLK = 2
±100 ppm
n
x CLKIN
CLKOUT MULTOUT
(see Note 2)
37.500–41.750 n = –2, –1, 0, 1, or 2 1xCLKIN 16xCLKIN
75.000–83.500 n = –3, –2, –1, 0, or 1 1xCLKIN 8xCLKIN
0
(MULTOUT = 600–668 MHz)
150.000–167.000 n = –4, –3, –2, –1, or 0 1xCLKIN 4xCLKIN
300.000–334.000 n = –5, –4, –3, –2, or –1 1xCLKIN 2xCLKIN
600.000–668.000 n = –6, –5, –4, –3, or –2
See Note 1 1xCLKIN
9.375–10.438 n = 0, 1, 2, 3, or 4 1xCLKIN 16xCLKIN
18.750–20.875 n = –1, 0, 1, 2, or 3 1xCLKIN 8xCLKIN
1
(MULTOUT = 150–167 MHz)
37.500–41.750 n = –2, –1, 0, 1, or 2 1xCLKIN 4xCLKIN
75.000–83.500 n = –3, –2, –1, 0, or 1 1xCLKIN 2xCLKIN
150.000–167.000 n = –4, –3, –2, –1, or 0
Note:
1. The CLKOUT output is not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.)
2. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be
asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple.
See Note 1 1xCLKIN
Figure 1. MULTSEL Jumper Configurations
Loss-of-Lock (LOL)
LOL is an indicator of the relative frequency between
the REFCLK input, which is nominally a multiple of
CLKIN, and an internally generated multiple of CLKIN.
LOL will assert when the frequency difference is greater
than ±600 PPM. In order to prevent LOL from deasserting prematurely, there is hysterisis in returning
from the out of lock condition. LOL will be de-asserted
(indicating a lock condition) when the frequency
difference is less than ±300 PPM.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
Test Configuration
The characterization of clock sources typically involves
measuring the output jitter or phase noise of the source.
The overall output jitter is a function of the input jitter
(jitter transfer) and the jitter generated (output jitter) by
the internal PLL.
Jitter can be measured using several different
techniques and hardware. An oscilloscope, a spectrum
analyzer, and a phase-noise analyzer are three such
instruments capable of measuring output jitter. A
spectrum analyzer is the best choice for measuring jitter
transfer.
Output Jitter
Output jitter is a measure of the output clock short-term
stability. In Figure 2, either position A or B can be used
when measuring this parameter.
Oscilloscope
An oscilloscope can measure jitter from the clock edges
within the trigger-to-capture bandwidth. Typically the
jitter measured is expressed in picoseconds (peak-topeak and RMS) relative to the average edge position. A
histogram can be used to capture the jitter distribution.
Rev. 0.71 3
Si5310-EVB
Pulse
Generator
Synthesizer
Signal Source
Sa mp lin g
Scope
2.5 V
REFCLK
CLKIN MULTOUT
CLKOUT
Si5310-EVB
–+
+
–
+
–
+
–
+
–
Spectrum
Analyzer
Phase
Noise
Analyzer
Pulse
Generator
A
B
Modulation
Signal Source
FM
Reference Frequency
Spectrum Analyzer
A spectrum analyzer measures the power of the carrier
source and its associated phase noise. Analysis of the
offset power distribution provides the data from which
jitter can be derived. Simple integration of the offset
power distribution over the desired offset range and
filtered amplitudes provides a RMS jitter value.
Phase-noise Analyzer
A phase-noise analyzer behaves similarly to a spectrum
analyzer, but only provides details regarding the power
offset from the carrier. Simple integration of the offset
power distribution over the desired offset range and
filtered amplitudes provides a RMS jitter value.
Jitter Transfer
Jitter transfer is the ratio of the input jitter spectrum to
the output jitter spectrum. Comparing the power levels
from the input jitter spectrum with the output jitter
spectrum provides the jitter transfer details. To
characterize this parameter, a modulation source is
added to the synthesizer. The FM modulation frequency
is the jitter frequency, and its relative amplitude on the
output verses the input describes the amount
transferred. In Figure 2, position A should be used when
measuring this parameter.
Figure 2. Test Configuration for Jitter Tolerance, Transfer, and Generation
4 Rev. 0.71
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