Silicon Laboratories Si5100-BC Datasheet

Preliminary Rev. 0.41 8/01 Copyright © 2001 by Silicon Laboratories Si5100-DS041

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5100

SiPHY

TM

OC-48/STM-16 SONET/SDH TRANSCEIVER

Features

Complete low power, high speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX

Applications

Description

The Si5100 is a complete low-power transceiver for high-speed serial
communication systems operating between 2.5 Gbps and 2.7 Gbps. The receive
path consists of a fully integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer. The transmit path combines a low jitter clock
multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’
DSPLL

™

technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long haul applications, programmable slicing and sa mple phase
adjustment are supported.

The Si5100 operates from a single 1.8 V supply over the industrial temperature
range (–40°C to 85°C).

Functional Block Diagram

! Data Rates Supported:

OC-48/STM-16 and 2.7 Gbps FEC

! Low Power Operation 1.2 W (typ)
! DSPLL™ Based Clock Multiplier Unit

w/ Selectable Loop Filter Bandwidths

! Integrated Limiting Amplifier
! Loss-of-Signal (LOS) Alarm
! Diagnostic and Line Loopbacks

! SONET Compliant Loop Timed

Operation

! Programmable Slicing Level and

Sample Phase Adjustment

! LVDS Parallel Interface
! Single Supply 1.8 V Operation
! 15 x 15 mm BGA Package

! Sonet/SDH Transmission

Systems

! Optical Transceiver Modules
! Sonet/SDH Test Equipment

TXDO UT

RXDOUT[15:0]

TXDIN[15:0]

RXCLK1
RXCLK2

TXCLK16OUT

FIFORST

RXCLK2DIV

FIFOERR

1:16

DEMUX

16:1

MUX

FIFO

TXCLK16IN

RXSQLCH

DLBKLLBK

TXMSBSEL

RXMSBSEL

XCLKOUT

TXSQLCH

2

32

2

2

2

RXCLK2DSBL

2

LPTM

RXDIN

REFCLK

TXLOL

Limiting

AMP

LOSLVL

LOS

LTR

DSPLL

tm

TX CM U

CDR

CLKDSBL

2

2

Loopback Control

TXCLK16IN

REFSEL

BWSEL

2

SLICELVL

PHASEADJ

RXLOL

32

REFRATE

RESET
Control

RESET

÷

÷

Ordering Information:

See page 23.

Si5100

Bottom View

PRELIMINARY DATA SHEET

Si5100

2 Preliminary Rev. 0.41

Si5100

Preliminary Rev. 0.41 3

TABLE OF CONTENTS

Section Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DSPLL™ Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Diagnostic Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Si5100 Pinout: 195-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pin Descriptions: Si5100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Si5100

4 Preliminary Rev. 0.41

Electrical Specifications

Figure 1. Differential Voltage Measurement

(RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK16OUT, TXCLK16IN)

Figure 2. Data to Clock Delay

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition

Min

*

Typ

Max

*

Unit

Ambient Temperature T

A

–40 25 85 °C

LVTTL Output Supply Voltage V

DD33

1.71 — 3.47 V

Si5100 Supply Voltage V

DD

1.71 1.8 1.89 V

*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.

V

IS

VID,VOD (V

ID

= 2VIS)

Differential
I/Os

Differential
Voltage Swing

Single Ended Voltage

Differential Peak-to-Peak Voltage

SIGNAL +
SIGNAL –

(SIGNAL +) – (SIGNAL –)

V

ICM

, V

OCM

V

t

TXDOUT,

TXDIN

TXCLKOUT,

TXCLK16IN

t

CP

t

hd

t

su

t

CH

RXDOUT

RXCLK1

t

cq1

t

cq2

Si5100

Preliminary Rev. 0.41 5

Figure 3. Rise/Fall Time Measurement

Table 2. DC Characteristics

(VDD = 1.8 V ±5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Supply Current I

DD

—611TBDmA

Power Dissipation P

D

—1.2 TBDW

Voltage Reference (VREF) V

REF

VREF driving

10 k

Ω load

1.21 1.25 1.29 V

Common Mode Input Voltage (RXDIN) V

ICM

TBD 0.1 TBD V

Differential Input Voltage Swing (RXDIN) V

ID

See Figure 1 10 — 1.0 mV

(pk-pk)

Common Mode Output Voltage
(TXDOUT, TXCLKOUT)

V

OCM

.8 0.9 1.0 V

Differential Output Voltage Swing
(TXDOUT,TXCLKOUT), Differential pk-pk

V

OD

See Figure 1 800 1000 1200 mV

(pk-pk)

LVPECL Input Voltage HIGH (REFCLK) V

IH

1.975 2.3 2.59 V

LVPECL Input Voltage LOW (REFCLK) V

IL

1.32 1.6 1.99 V

L VPECL Input Voltage Swing,
Differential pk-pk (REFCLK)

V

ID

See Figure 1 250 — 2400 mV

(pk-pk)

L VPECL Internally Generated Input Bias
(REFCLK)

V

IB

1.6 1.95 2.3 V

LVDS Input High Voltage
(TXDIN,TXCLK16IN)

V

IH

——2.4V

LVDS Input Low Voltage
(TXDIN,TXCLK16IN)

V

IL

0.0 — — V

LVDS Input Voltage, Single Ended pk-pk
(TXDIN,TXCLK16IN)

V

ISE

100 — 600 mV

(pk-pk)

LVDS Output High Voltage
(RXDOUT,RXCLK1,RXCLK2,TXCLK16OUT)

V

OH1

100 Ω Load

Line-to-Line

TBD — 1.475 mV

LVDS Output Low Voltage
(RXDOUT,RXCLK1,RXCLK2,TXCLK16OUT)

V

OL1

100 Ω Load

Line-to-Line

0.925 — TBD V

LVDS Output Voltage, Dif fe rential pk-pk
(RXDOUT,RXCLK1,RXCLK2,TXCLK16OUT)

V

OSE

100 Ω Load

Line-to-Line,

Figure 1

500 — 800 mV

(pk-pk)

All Differential
IOs

t

F

t

R

80%
20%

Si5100

6 Preliminary Rev. 0.41

LVDS Common Mode Voltage
(RXDOUT,RXCLK1,RXCLK2,TXCLK16OUT)

V

CM

1.125 — 1.275 V

Input Impedance (TXDIN, TXCLK16IN,
REFCLK, RXDIN)

R

IN

Each input to

common mode

42 50 58 Ω

Output Short to GND
(RXDOUT,RXCLK1,RXCLK2,
TXCLK16OUT, TXDOUT,TXCLKOUT)

I

SC(–)

—25TBDmA

Output Short to V

DD

(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT, TXDOUT, TXCLKOUT)

I

SC(+)

TBD –100 — µA

LVTTL Input Voltage Low
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH

, REFSEL, L TR, RESET, MODE16

TXCLKDSBL, FIFORST, TXSQLCH

,

BWSEL, TXMSBSEL, DLBK

, LLBK, LPTM)

V

IL2

VDD33 = 3.3 V — — 0.8 V
VDD33 = 1.8 V — — 0.7

LVTTL Input Voltage High
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH

, REFSEL, L TR, RESET, MODE16

TXCLKDSBL, FIFORST,TXSQLCH

,

BWSEL, TXMSBSEL, DLBK

, LLBK, LPTM)

V

IH2

VDD33 = 3.3 V 2.0 — — V
VDD33 = 1.8 V 1.7

LVTTL Input Low Current
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH

, REFSEL, L TR, RESET, MODE16

TXCLKDSBL, FIFORST, TXSQLCH

,

BWSEL, TXMSBSEL, DLBK

, LLBK, LPTM)

I

IL

——10µA

LVTTL Input High Current
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH

, REFSEL, L TR, RESET, MODE16

TXCLKDSBL, FIFORST, TXSQLCH

,

BWSEL, TXMSBSEL, DLBK

, LLBK, LPTM)

I

IH

——10µA

LVTTL Input Impedance
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH

, REFSEL, L TR, RESET, MODE16

TXCLKDSBL, FIFORST, TXSQLCH

,

BWSEL, TXMSBSEL, DLBK

, LLBK, LPTM)

R

IN

10 — — kΩ

LVTTL Output Voltage Low
(LOS

, RXLOL, FIFOERR, TXLOL)

V

OL2

VDD33 = 1.8 V — — 0.4 V
VDD33 = 3.3 V — — 0.4

LVTTL Output Voltage High
(LOS

, RXLOL, FIFOERR, TXLOL)

V

OH2

VDD33 = 1.8 V 1.4 — — V
VDD33 = 3.3 V 2.4 — —

Table 2. DC Characteristics (Continued)

(VDD = 1.8 V ±5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Si5100

Preliminary Rev. 0.41 7

Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2)

(VDD = 1.8 V ±5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Output Clock Frequency
(RXCLK1)

f

clkout

See Figure 2 — 155 167 MHz

Duty Cycle (RXCLK1, RXCLK2) tch/tcp, Figure 2 45 — 55 %
Output Rise and Fall Times

(RXCLK1, RXCLK2, RXDOUT)

t

R,tF

Figure 3 — 50 — ps

Data Invalid Prior to RXCLK1 t

cq1

Figure 2 — — 200 ps

Data Invalid After RXCLK1 t

cq2

Figure 2 — — 200 ps

Input Return Loss (RXIN) 100 kHz–2.5 GHz

2.5 GHz–4.0 GHz

18.7
TBD

—
—

—
—

dB
dB

Slicing Adjust Dynamic Range SLICELVL = 200–800 mV –20 — 20 mV
Slicing Level Offset

1

(referred to RXDIN)

SLICELVL = 200–800 mV –500 — 500

µV

Slicing Level Accuracy VSLICE –5 — 5 %
Sampling Phase Adjustment

2

PHASEADJ = 200–800 mV –22.5° — 22.5°

LOS Threshold Dynamic Range LOSLVL = 200–800 mV 10 — 50 mV

pk-pk

LOS Threshold Offset

3

(referred to RXDIN)

LOSLVL = 200–800 mV –500 — 500

µV

LOS Threshold Accuracy VLOS –5 — 5 %

Note:

1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL – 0.4"VREF)/15.

2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 22.5°(PHASEADJ – 0.4

"

VREF)/0.3

3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30 mV + (LOS_LVL – 0.4"VREF)/15.

Si5100

8 Preliminary Rev. 0.41

Table 4. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT)

(V

DD =

1.8 V ±5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

TXCLKOUT Frequency f

clkout

—2.52.7GHz
TXCLKOUT Duty Cycle tch/tcp, Figure 2 45 — 55 %
Output Rise Time

(TXCLKOUT, TXDOUT)

t

R

Figure 3 — 25 — ps

Output Fall Time
(TXCLKOUT, TXDOUT)

t

F

Figure 3 — 25 — ps

TXCLKOUT Setup to TXDOUT t

su

Figure 2 25 — — ps

TXCLKOUT Hold From TXDOUT t

hd

Figure 2 25 — — ps

Output Return Loss 100 kHz–2.5 GHz

2.5 GHz–4.0 GHz

TBD
TBD

—
—

—
—

dB
dB

TXCLK16OUT Frequency f

CLKIN

MODE16 = 1 — 622 667 MHz

MODE16 = 0 — 155 167
TXCLK16OUT Duty Cycle tch/tcp, Figure 2 40 — 60 %
TXCLK16OUT Rise & Fall Times t

R

, t

F

100 — 300 ps

TXDIN Setup to TXCLK16IN t

DSIN

——300ps

TXDIN Hold from TXCLK16IN t

DHIN

——300ps

TXCLK16IN Frequency f

CLKIN

—155167MHz
TXCLK16IN Duty Cycle tch/tcp, Figure 2 40 — 60 %
TXCLK16IN Rise & Fall Times t

R

, t

F

100 — 300 ps