Silicon Laboratories Si5020-BM Datasheet
Si5020
SiPHY™ M
ULTI-RATE
SONET/SDH C
LOCK AND DATA RECOVERY
Features
Complete high speed, low power, CDR solution includes the following:
!
Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
!
Low Power—270 mW (TYP OC-48)
!
Small Footprint: 4 mm x 4 mm
!
DSPLL™ Eliminates External Loop
Filter Components
!
3.3 V T olerant Control Inputs
!
Exceeds All SONET/SDH
Jitter Specifications
!
Jitter Generation
3.0 mUI
!
Device Power Down
!
Loss-of-Lock Indicator
!
Single 2.5 V Supply
RMS
(TYP)
Applications
!
SONET/SDH/ATM Routers
!
Add/Drop Multiplexers
!
Digital Cross Connects
!
Gigabit Ethernet Interfaces
!
SONET/SDH Test Equipment
!
Optical Transceiver Modules
!
SONET/SDH Regenerators
!
Board Level Serial Links
Description
The Si5020 is a fully integrated low-p ower clock and d ata recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1,
or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also
provided for OC-48/STM-16 applications that employ forward error
correction (FEC). DSPLL™ technology eliminates sensitive noise entry
points thus making the P LL les s susce ptible to board- level inter actio n and
helping to ensure optimal jitter performance.
The Si5020 repres ents a new stan dard in low ji tter, low power, and small
size for high spe ed CDRs. It o perates fr om a singl e 2.5 V supply over the
industrial temperature range (–40°C to 85°C).
Ordering Information:
See page 14.
Pin Assignments
Si5020
RATESEL1
REXT
1
VDD
2
GND
3
REFCLK+
REFCLK–
4
5
6 7 8 9
LOL
Top View
VDD
RATESEL0
GND
Pad
GND
GND
IC
CLKOUT+
CLKOUT–
17181920
16
PWRDN/CAL
15
VDD
14
DOUT+
13
DOUT–
12
11
VDD
10
DIN–
DIN+
Functional Block Diagram
LOL
DIN+
DIN–
BUF
2
Bias
REXT
Preliminary Rev. 0.8 12/00 Copyright © 2000 by Silicon Laboratories Si5020-DS08
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
DSPLL™
Phase-Locked
Loop
2
RATESEL1–0
2
REFCLK+
REFCLK–
Retimer
BUF
BUF
2
2
DOUT+
DOUT–
PWRDN/CAL
CLKOUT+
CLKOUT–
Si5020
2 Preliminary Rev. 0.8
Si5020
T
ABLE OF
C
ONTENTS
Section Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Descriptions: Si5020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Preliminary Rev. 0.8 3
Si5020
Detailed Block Diagram
DIN+
DIN+
DIN–
REFCLK+
REFCLK+
REFCLK–
RATESEL1-0
RATESEL1-0
REXT
Retime
RetimeRetime
DOUT+
DOUT–
c
Phase
Phase
Phase
Detector
Detector
Detector
A/D
DSP
VCO
CLK
Divider
c
CLKOUT+
CLKOUT–
n
Lock
Detector
LOL
2
Bias
Bias
Bias
Generation
Generation
Generation
Ca libra t io n
PWRDN/CAL
Figure 1. Detailed Block Diagram
4 Preliminary Rev. 0.8
Electrical Specifications
Table 1. Recommended Operating Conditions
Si5020
Parameter
Symbol Test Condition
Ambient Temperature T
Si5020 Supply Voltage
2
V
A
DD
1
Min
Typ
–40 25 85 °C
2.375 2.5 2.625 V
Max
1
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless
otherwise stated.
2. The Si5020 specifications are guaranteed when using the recommended application circuit (including
component tolerance) of Figure 5 on page 9.
V
SIGNAL+
Differential
I/Os
V
ICM,VOCM
SIGNAL–
V
IS
Single-Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
VID,VOD (V
= 2VIS)
ID
Differential Peak-to-Peak Voltage
t
Unit
DOUT
CLKOUT
DOUT,
CLKOUT
Figure 2. Differential Voltage Measurement (DI N, REFCLK, DOUT, CLKOUT)
t
Cf-D
t
Cr-D
Figure 3. Clock to Data Timing
80%
20%
t
F
t
R
Figure 4. DOUT and CLKOUT Rise/Fall Times
Preliminary Rev. 0.8 5
Si5020
Table 2. DC Characteristics
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current
OC-48 and FEC (2.7 GHz)
GigE
OC-12
OC-3
Power Dissipation
OC-48 and FEC (2.7 GHz)
GigE
OC-12
OC-3
Common Mode Input Voltage (DIN, REFCLK) V
Single Ended Input Voltage (DIN, REFCLK) V
Differential Input Voltage Swing
(DIN, REFCLK)
Input Impedance (DIN, REFCLK) R
Differential Output Voltage Swing
(DOUT)
Differential Output Voltage Swing
(CLKOUT)
Output Common Mode Voltage
(DOUT,CLKOUT)
Output Impedance (DOUT,CLKOUT) R
Output Short to GND (DOUT,CLKOUT) I
Output Short to V
(DOUT,CLKOUT) I
DD
Input Voltage Low (LVTTL Inputs) V
Input Voltage High (LVTTL Inputs) V
Input Low Current (LVTTL Inputs) I
Input High Current (LVTTL Inputs) I
Output Voltage Low (LVTTL Outputs) V
Output Voltage High (LVTTL Outputs) V
Input Impedance (LVTTL Inputs) R
PWRDN/CAL Leakage Current I
I
DD
P
D
varies with V
See Figure 2 100 — 750 mV
See Figure 2 200 — 1500 mV
Line-to-Line 84 100 116 Ω
100 Ω Load
V
ICM
V
IS
ID
IN
OD
Line-to-Line
V
OD
100 Ω Load
Line-to-Line
V
OCM
100 Ω Load
Line-to-Line
OUT
SC(–)
SC(+)
IL
IH
IL
IH
OL
OH
IN
PWRDNVPWRDN
Single-ended 84 100 116 Ω
IO = 2 mA — — 0.4 V
IO = 2 mA 2.0 — — V
DD
—
—
—
—
—
—
—
—
—.80*VDD—V
108
113
117
124
270
283
293
310
118
123
127
134
310
323
333
352
mA
mW
(pk-pk)
TBD 940 TBD mV
(pk-pk)
TBD 900 TBD mV
(pk-pk)
—VDD –
—V
0.20
—25TBDmA
TBD –15 — mA
——.8V
2.0 — — V
——10µA
——10µA
10 — — kΩ
≥ 0.8 V TBD 25 TBD µA
6 Preliminary Rev. 0.8
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