Silicon Laboratories Si4136-BT Datasheet

Si4136

ISM RF S
F

OR

IRELESS COMMUNICATIONS

W

YNTHESIZER

ITH INTEGRATED

W

Features

!

Dual-Band RF Synthesizers

RF1: 2300 MHz to 2500 MHz

"

RF2: 2025 MHz to 2300 MHz

"

!

IF Synthesizer

62.5 MHz to 1000 MHz

"

!

Integrated VCOs, Loop Filters,
Varactors, and Resonators

!

Minimal External Components
Required

!

Low Phase Noise

!

5 µA Standby Current

!

25.7 mA Typical Supply Current

!

3.0 V to 3.6 V Operation

!

Package: 24-pin TSSOP

Applications

!

ISM Band Communications

!

Wireless LAN and WAN

!

Dual-Band Communications

Description

The Si4136 is a monolithic integrated circuit that performs both IF and RF
synthesis for wireless communications applications. The Si4136 includes
three VCOs, loo p filters, r eference a nd VCO divide rs, and pha se detector s.
Divider and power down settings are programmable through a three-wire
serial interface.

Functional Block Diagram

XIN

PWDNB

SDATA

SCLK

SENB

Reference

Am plifier

Power

Down

Control

Serial

Inte r f ace

22-bit

Data

Register

÷1/÷2

÷

R

Phase

RF1

Detect

÷

R

÷

RF2

Phase
Detect

÷

RF1

N

N

2

÷

RF1

RF2

2

÷

RF2

RFOUT

VCOS

Ordering Information:

Pin Assignments

SCLK

SDATA

GNDR

GNDR

GNDR

GNDR

GNDR

GNDR

RFOUT

VDDR

Patents pending

NC

NC

1

2

3

4

5

6

7

8

9

10

11

12

See page 28.

Si4136

24

23

22

21

20

19

18

17

16

15

14

13

SENB

VDDI

IFOUT

GNDI

IFLB

IFLA

GNDD

VDDD

GNDD

XIN

PWDNB

AUXOUT

R

÷

IF

AUXOUT

Test
Mux

Phase
Detect

IFD IV

IF

÷

N

IF

IFO UT

IFL A
IFL B

Rev. 1.0 12/00 Copyright © 2000 by Silicon Laboratories Si4136-DS10

Si4136

2 Rev. 1.0

Si4136

T

ABLE OF

C

ONTENTS

Section Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin Descriptions: Si4136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Rev. 1.0 3

Si4136

Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature T
Supply Voltage V
Supply Voltages Difference V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.

Table 2. Absolute Maximum Ratings

1,2

DD

A

(V

– V

(V

DDR

DDI

– V

∆

DDD
DDD

),
)

–40 25 85 °C

3.0 3.3 3.6 V

–0.3 — 0.3 V

Parameter Symbol Value Unit

DC Supply Voltage V
Input Current

Input Voltage

3

3

Storage Temperature Range T

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2. This device is a high performan ce RF integrated circ uit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.

3. For signals SCLK, SDATA, SENB, PWDNB and XIN.

V

DD

I

IN

STG

IN

–0.5 to 4.0 V

±10 mA

–0.3 to VDD+0.3 V

–55 to 150

o

C

4 Rev. 1.0

Si4136

Table 3. DC Characteristics

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Total Supply Current
RF1 Mode Supply Current
RF2 Mode Supply Current
IF Mode Supply Current

1

1
1

1

Standby Current PWDNB = 0 — 1 — µA
High Level Input Voltage
Low Level Input Voltage
High Level Input Current

Low Level Input Current

High Level Output Voltage
Low Level Output Voltage

Notes:

1. RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0.

2. For signals SCLK, SDATA, SENB, and PWDNB.

3. For signal AUXOUT.

2

2

2

2

3

3

V

IH

V

IL

I

IH

I

IL

V

OH

V

OL

RF1 and IF operating — 25.7 35 mA

—15.720mA
—15.420mA
—1015mA

V

V

V

=

IH

= 3.6 V

DD

V

IL

=

DD

3.6 V,

=

0 V,

3.6 V

0.7 V

DD

— — 0.3 V

–10 — 10 µA

–10 — 10 µA

——V

DD

IOH = –500 µA VDD–0.4 — — V

IOH = 500 µA — — 0.4 V

V

Rev. 1.0 5

Si4136

t

t

Table 4. Serial Interface Timing

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Parameter

1

SCLK Cycle Time t
SCLK Rise Time t
SCLK Fall Time t
SCLK High Time t
SCLK Low Time t
SDATA Setup Time to SCLK↑
SDATA Hold Time from SCLK↑
SENB↓ to SCLK↑ Delay Time
SCLK↑ to SENB↑ Delay Time
SENB↑ to SCLK↑ Delay Time

2

2
2
2
2

SENB Pulse Width t

Symbol Test Condition Min Typ Max Unit

Figure 1 40 — — ns
Figure 1 — — 50 ns
Figure 1 — — 50 ns
Figure 1 10 — — ns
Figure 1 10 — — ns
Figure 2 5 — — ns
Figure 2 0 — — ns
Figure 2 10 — — ns
Figure 2 12 — — ns
Figure 2 12 — — ns
Figure 2 10 — — ns

t

t
t
t

clk

t

su

hold

en1

en2

en3

w

r

f

h

l

Notes:

1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.

2. Timing is not referenced to 50% level of the waveform. See Figure 2.

SCLK

r

80%
50%
20%

f

t

h

t

t

l

clk

Figure 1. SCLK Timing Diagram

6 Rev. 1.0

Si4136

A

Figure 2. Serial Interface Timing Diagram

First bit

clocked in

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0A3A2A

data
field

Figure 3. Serial Word Format

A

Last bit

clocked in

1

address

field

A
0

Rev. 1.0 7

Si4136

Table 5. RF and IF Synthesizer Characteristics

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Parameter

1

XIN Input Frequency f
XIN Input Frequency f
Reference Amplifier Sensitivity V

Symbol Test Condition Min Typ Max Unit

REF

REF

REF

XINDIV2 = 0 2 — 25 MHz
XINDIV2 = 1 25 — 50 MHz

0.5 — VDD

V

PP

+0.3 V

Phase Detector Update Frequency f

φ

fφ = f

REF

/R for

0.010 — 1.0 MHz

XINDIV2 = 0

f

= f

/2R for

REF

φ

XINDIV2 = 1
RF1 VCO Tuning Range
RF2 VCO Tuning Range

2
2

IF VCO Center Frequency Range f
IFOUT Tuning Range from f
IFOUT VCO Tuning Range from f

CEN

CEN

CEN

with IFDIV 62.5 — 1000 MHz

Note: L ±10% –5 — 5 %

2300 — 2500 MHz
2025 — 2300 MHz

526 — 952 MHz

RF1 VCO Pushing Open loop — 0.75 — MHz/V
RF2 VCO Pushing — 0.65 — MHz/V
IF VCO Pushing — 0.10 — MHz/V
RF1 VCO Pulling VSWR = 2:1, all
RF2 VCO Pulling — 0.100 — MHz p-p

phases, open loop

— 0.250 — MHz p-p

IF VCO Pulling — 0.025 — MHz p- p
RF1 Phase Noise 1 MHz offset — –130 — dBc/Hz
RF1 Integrated Phase Error 100 Hz to 100 kHz — 1.2 — degrees

rms
RF2 Phase Noise 1 MHz offset — –131 — dBc/Hz
RF2 Integrated Phase Error 100 Hz to 100 kHz — 1.0 — degrees

rms
IF Phase Noise at 800 MHz 100 kHz offset — –104 — dBc/Hz
IF Integrated Phase Error 100 Hz to 100 kHz — 0.4 — degrees

rms

Notes:

1. f

(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters

φ

unless otherwise noted.

2. RF VCO tuning range limits are fixed by inductance of internally bonded wires.

3. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF

synthesizers ready (settled to within 0.1 ppm frequency error).

4. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply
current equal to I

PWDN

.

8 Rev. 1.0

Table 5. RF and IF Synthesizer Characteristics (Continued)

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Si4136

Parameter

1

Symbol Test Condition Min Typ Max Unit

RF1 Harmonic Suppression Second Harmonic — –28 –20 dBc
RF2 Harmonic Suppression — –23 –20 dBc
IF Harmonic Suppression — –26 –20 dBc
RFOUT Power Level Z
RFOUT Power Level Z
IFOUT Power Level Z

= 50 Ω, RF1 active –15 –7 0 dBm

L

= 50 Ω, RF2 active –15 –9 0 dBm

L

= 50 Ω –7 –3 1 dBm

L

RF1 Output Reference Spurs Offset = 1 MHz — –63 — dBc

Offset = 2 MHz — –68 — dBc
Offset = 3 MHz — –70 — dBc

RF2 Output Reference Spurs Offset = 1 MHz — –63 — dBc

Offset = 2 MHz — –68 — dBc
Offset = 3 MHz — –70 — dBc

Power Up Request to Synthesizer

3

Ready
Power Up Request to Synthesizer

Ready

Time

3

Time

Power Down Request to Synthesizer

4

Off

Time

Notes:

(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters

1. f

φ

unless otherwise noted.

2. RF VCO tuning range limits are fixed by inductance of internally bonded wires.

3. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF

synthesizers ready (settled to within 0.1 ppm frequency error).

4. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply
current equal to I

PWDN

.

t

t

t

pup

pup

pdn

Figures 4, 5

f

> 500 kHz

φ

Figures 4, 5

≤ 500 kHz

f

φ

—80100µs

—40/f

50/f

φ

φ

Figures 4, 5 — — 100 ns

Rev. 1.0 9