Datasheet Si4136-BT Datasheet (Silicon Laboratories)

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Si4136

ISM RF S F

IRELESS COMMUNICATIONS

YNTHESIZER

ITH INTEGRATED

Features

Dual-Band RF Synthesizers

RF1: 2300 MHz to 2500 MHz

RF2: 2025 MHz to 2300 MHz

IF Synthesizer

62.5 MHz to 1000 MHz

Integrated VCOs, Loop Filters, Varactors, and Resonators

Minimal External Components Required

Low Phase Noise

5 µA Standby Current

25.7 mA Typical Supply Current

3.0 V to 3.6 V Operation

Package: 24-pin TSSOP

Applications

ISM Band Communications

Wireless LAN and WAN

Dual-Band Communications

Description

The Si4136 is a monolithic integrated circuit that performs both IF and RF synthesis for wireless communications applications. The Si4136 includes three VCOs, loo p filters, r eference a nd VCO divide rs, and pha se detector s. Divider and power down settings are programmable through a three-wire serial interface.

Functional Block Diagram

XIN

PWDNB

SDATA

SCLK

SENB

Reference

Am plifier

Power

Down

Control

Serial

Inte r f ace

22-bit

Data

÷1/÷2

Phase

RF1

Detect

RF2

Phase Detect

RF1

RF2

RFOUT

VCOS

Ordering Information:

Pin Assignments

SCLK

SDATA

GNDR

RFOUT

VDDR

Patents pending

See page 28.

Si4136

SENB

VDDI

IFOUT

GNDI

IFLB

IFLA

GNDD

VDDD

GNDD

XIN

PWDNB

AUXOUT

Test Mux

Phase Detect

IFD IV

IFO UT

IFL A IFL B

Si4136

2 Rev. 1.0

Si4136

ABLE OF

ONTENTS

Section Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin Descriptions: Si4136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Rev. 1.0 3

Si4136

Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature T Supply Voltage V Supply Voltages Difference V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.

Table 2. Absolute Maximum Ratings

1,2

– V

DDR

DDI

– V

∆

DDD DDD

), )

–40 25 85 °C

3.0 3.3 3.6 V

–0.3 — 0.3 V

Parameter Symbol Value Unit

DC Supply Voltage V Input Current

Input Voltage

Storage Temperature Range T

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. This device is a high performan ce RF integrated circ uit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations.

3. For signals SCLK, SDATA, SENB, PWDNB and XIN.

STG

–0.5 to 4.0 V

±10 mA

–0.3 to VDD+0.3 V

–55 to 150

4 Rev. 1.0

Si4136

Table 3. DC Characteristics

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Total Supply Current RF1 Mode Supply Current RF2 Mode Supply Current IF Mode Supply Current

1 1

Standby Current PWDNB = 0 — 1 — µA High Level Input Voltage Low Level Input Voltage High Level Input Current

Low Level Input Current

High Level Output Voltage Low Level Output Voltage

Notes:

1. RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0.

2. For signals SCLK, SDATA, SENB, and PWDNB.

3. For signal AUXOUT.

RF1 and IF operating — 25.7 35 mA

—15.720mA —15.420mA —1015mA

= 3.6 V

3.6 V,

0 V,

3.6 V

0.7 V

— — 0.3 V

–10 — 10 µA

——V

IOH = –500 µA VDD–0.4 — — V

IOH = 500 µA — — 0.4 V

Rev. 1.0 5

Si4136

Table 4. Serial Interface Timing

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Parameter

SCLK Cycle Time t SCLK Rise Time t SCLK Fall Time t SCLK High Time t SCLK Low Time t SDATA Setup Time to SCLK↑ SDATA Hold Time from SCLK↑ SENB↓ to SCLK↑ Delay Time SCLK↑ to SENB↑ Delay Time SENB↑ to SCLK↑ Delay Time

2 2 2 2

SENB Pulse Width t

Symbol Test Condition Min Typ Max Unit

Figure 1 40 — — ns Figure 1 — — 50 ns Figure 1 — — 50 ns Figure 1 10 — — ns Figure 1 10 — — ns Figure 2 5 — — ns Figure 2 0 — — ns Figure 2 10 — — ns Figure 2 12 — — ns Figure 2 12 — — ns Figure 2 10 — — ns

t t t

clk

hold

en1

en2

en3

Notes:

1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.

2. Timing is not referenced to 50% level of the waveform. See Figure 2.

SCLK

80% 50% 20%

clk

Figure 1. SCLK Timing Diagram

6 Rev. 1.0

Si4136

Figure 2. Serial Interface Timing Diagram

First bit

clocked in

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0A3A2A

data field

Figure 3. Serial Word Format

Last bit

clocked in

address

field

A 0

Rev. 1.0 7

Si4136

Table 5. RF and IF Synthesizer Characteristics

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Parameter

XIN Input Frequency f XIN Input Frequency f Reference Amplifier Sensitivity V

Symbol Test Condition Min Typ Max Unit

REF

XINDIV2 = 0 2 — 25 MHz XINDIV2 = 1 25 — 50 MHz

0.5 — VDD

+0.3 V

Phase Detector Update Frequency f

fφ = f

REF

/R for

0.010 — 1.0 MHz

XINDIV2 = 0

= f

/2R for

REF

XINDIV2 = 1 RF1 VCO Tuning Range RF2 VCO Tuning Range

2 2

IF VCO Center Frequency Range f IFOUT Tuning Range from f IFOUT VCO Tuning Range from f

CEN

with IFDIV 62.5 — 1000 MHz

Note: L ±10% –5 — 5 %

2300 — 2500 MHz 2025 — 2300 MHz

526 — 952 MHz

RF1 VCO Pushing Open loop — 0.75 — MHz/V RF2 VCO Pushing — 0.65 — MHz/V IF VCO Pushing — 0.10 — MHz/V RF1 VCO Pulling VSWR = 2:1, all RF2 VCO Pulling — 0.100 — MHz p-p

phases, open loop

— 0.250 — MHz p-p

IF VCO Pulling — 0.025 — MHz p- p RF1 Phase Noise 1 MHz offset — –130 — dBc/Hz RF1 Integrated Phase Error 100 Hz to 100 kHz — 1.2 — degrees

rms RF2 Phase Noise 1 MHz offset — –131 — dBc/Hz RF2 Integrated Phase Error 100 Hz to 100 kHz — 1.0 — degrees

rms IF Phase Noise at 800 MHz 100 kHz offset — –104 — dBc/Hz IF Integrated Phase Error 100 Hz to 100 kHz — 0.4 — degrees

rms

Notes:

1. f

(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters

unless otherwise noted.

2. RF VCO tuning range limits are fixed by inductance of internally bonded wires.

3. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF

synthesizers ready (settled to within 0.1 ppm frequency error).

4. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to I

PWDN

8 Rev. 1.0

Table 5. RF and IF Synthesizer Characteristics (Continued)

(VDD = 3.0 to 3.6 V, TA = –40 to 85°C)

Si4136

Parameter

Symbol Test Condition Min Typ Max Unit

RF1 Harmonic Suppression Second Harmonic — –28 –20 dBc RF2 Harmonic Suppression — –23 –20 dBc IF Harmonic Suppression — –26 –20 dBc RFOUT Power Level Z RFOUT Power Level Z IFOUT Power Level Z

= 50 Ω, RF1 active –15 –7 0 dBm

= 50 Ω, RF2 active –15 –9 0 dBm

= 50 Ω –7 –3 1 dBm

RF1 Output Reference Spurs Offset = 1 MHz — –63 — dBc

Offset = 2 MHz — –68 — dBc Offset = 3 MHz — –70 — dBc

RF2 Output Reference Spurs Offset = 1 MHz — –63 — dBc

Offset = 2 MHz — –68 — dBc Offset = 3 MHz — –70 — dBc

Power Up Request to Synthesizer

Ready Power Up Request to Synthesizer

Ready

Time

Power Down Request to Synthesizer

Off

Time

Notes:

(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters

1. f

unless otherwise noted.

2. RF VCO tuning range limits are fixed by inductance of internally bonded wires.

3. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF

synthesizers ready (settled to within 0.1 ppm frequency error).

4. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to I

PWDN

pup

pdn

Figures 4, 5

> 500 kHz

Figures 4, 5

≤ 500 kHz

—80100µs

—40/f

50/f

Figures 4, 5 — — 100 ns

Rev. 1.0 9

Si4136

Figure 4. Software Power Management

Timing Diagram

Figure 5. Hardware Power Management

Timing Diagram

10 Rev. 1.0

Si4136

Figure 6. Typical Transient Response RF1 at 2.4 GHz

with 1 MHz Phase Detector Update Frequency

Rev. 1.0 11

Si4136

-60

-70

-80

-90

-100

-110

Phase Noise (dBc/Hz)

-120

-130

-140

1.E+02 1.E+03 1.E +04 1.E+05 1.E+06 Offset Frequency (Hz)

Typical RF1 Phase Noise at 2.4 GHz

Figure 7. Typical RF1 Phase Noise at 2.4 GHz

with 1 MHz Phase Detector Update Frequency

Figure 8. Typical RF1 Spurious Response at 2.4 GHz

with 1 MHz Phase Detector Update Frequency

12 Rev. 1.0

Si4136

-60

-70

-80

-90

-10 0

-11 0

Phase Noise (dBc/Hz)

-12 0

-13 0

-14 0

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Offset Frequency (Hz)

Typical RF2 Phase Noise at 2.1 GHz

Figure 9. Typical RF2 Phase Noise at 2.1 GHz

with 1 MHz Phase Detector Update Frequency

Figure 10. Typical RF2 Spurious Response at 2.1 GHz

with 1 MHz Phase Detector Update Frequency

Rev. 1.0 13

Si4136

-60

-70

-80

-90

-100

-110

Phase Noise (dBc/Hz)

-120

-130

-140

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Offset Frequency (Hz)

Typical IF Phase Noise at 800 MHz

Figure 11. Typical IF Phase Noise at 800 MHz

with 1 MHz Phase Detector Update Frequency

Figure 12. IF Spurious Response at 800 MHz

with 1 MHz Phase Detector Update Frequency

14 Rev. 1.0

System

Controller

RFOUT

From

560 pF

0.022µF

Si4136

Ω ∗

Ω ∗Ω ∗

0.022µF

MATCH

Printed Trace Inductor or Ch ip In d u c t o r

560 pF

IFO UT

560 pF

External Clock

PDWNB

AUXOUT

Si4136

SCLK

SDATA

GNDR

RFOUT

VDDR

PWDNB

AUXOUT

SENB

VDDI

IFO UT

GNDI

IFLB

IFLA

GNDD

VDDD

GNDD

XIN

*Add 30 Ω

Ω se ries resistor if using IF output divide values 2, 4, or 8 and f

ΩΩ

Figure 13. Typical Application Circuit: Si4136-BT

< 600 MHz.

CEN

Rev. 1.0 15

Si4136

Functional Description

The Si4136 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for many wireless communications applications. This integrated circuit (IC), along with a minimum number of external components, is a ll that is necessary to implement the frequency synthesis func tion in appli cations lik e W-LAN using the IEEE 802.11 standard.

The Si4136 has three complete phase-locked loops (PLLs), with integrated voltage-controlled oscillators (VCOs). The low ph ase noise of the VCOs mak es the Si4136 suitable for use in demanding wireless communications applications. Also integrated are phase detectors, loop filters, and reference and output frequency dividers. The IC is programmed through a three-wir e serial interface.

Two PLLs are provided for RF synthesis. These RF PLLs are multiplexe d s o tha t only one P LL is ac tiv e at a given time (as de termined by the setting of an internal register). The active PLL is the last one written. The center frequency of the VCO in each PLL is set by the internal bond wire inductance within the package. Inaccuracies in thes e induct ances are com pensa ted for by the self-tuning algorithm. The algorithm is run following power-up or following a change in the programmed output frequency.

The RF PLLs contain a divide-by-2 circuit before the Ndivider. As a result, the phase detector frequency (fφ) is equal to half the de si r ed cha nnel spacing. For ex am ple , for a 200 kHz channel spacing, fφ would equal 100 kHz. The IF PLL does not contain the divide-by-2 circuit before the N-divider. In this case, fφ is equal to the desired channel spacing. Each RF VCO is optimized for a particular frequency range. The RF1 VCO is optimized to operate from 2.3 GHz to 2.5 GHz, while the RF2 VCO is optimized to operate be tween 2.025 GHz and 2.3 GHz.

One PLL is provided for IF synthesis. The center frequency of this circuit’s VCO is set by an external inductance. The PL L c an adj ust th e IF o utpu t fr eq uen cy by ±5% of the VCO center frequency. Inaccuracies in the value of the external induct ance are compensated for by the Si4136’s proprietary self-tuning algorithm. This algorithm is initiated each time the PLL is poweredup (by either the PWDNB pin or by software) and/or each time a new output frequency is programmed. The IF VCO can have its center frequency set as low as 526 MHz and as high as 952 MHz. An IF output div ider is provided to divi de down the IF output freq uencies, if needed. The divider is programmable, capable of dividing by 1, 2, 4, or 8.

In order to accommodate designs running at XIN frequencies greater than 25 MHz, the Si4136 includes a programmable divide-by-2 option (XINDIV2 in Register 0, D6) on the XIN input. By enabling this option, the Si4136 can accept a range of TCXO frequencies from 25 MHz to 50 MHz. This feature makes the Si4136 ideal for W-LAN radio designs operating at an XIN of 44 MHz.

The unique PLL architecture used in the Si4136 produces settling (lock) times that are comparable in speed to fractional- N architec tures with out suffering the high phase noise or spurious modulation effects often associated with those designs.

Serial Inte rface

A timing diagram for the serial interface is shown in Figure 2 on page 7. Figure 3 on page 7 shows the format of the serial word.

The Si4136 is programmed serially with 22-bit words comprised of 18-bit da ta fields and 4-bit addr ess fields. When the serial interface is enabled (i.e., when SENB is low) data and address bits on the SDATA pin are clocked into an internal s hift register on the risin g edge of SCLK. Data in the shift re gis ter i s t hen trans fer red o n the rising edge of SENB into the internal data register addressed in the address field. The serial interface is disabled when SENB is high.

Table 11 on page 21 summarizes the data register functions and addresses. It is not necessary (although it is permissible) to clock into the internal shift register any leading bits that are “don’t cares.”

Setting the IF VCO Center Frequencies

The IF PLL can adjust its output frequency ±5% from the center frequency as es tablished by the value of an external inductance connected to the VCO. The RF1 and RF2 PLLs have fixed operating ranges due to the inductance set by the internal bond wires. Eac h center frequency is established by the value of the total inductance (internal and/or external) connected to the respective VCO. Manufacturing tolerance of ±10% for the external indu ctor is a cceptable for the IF V CO. The Si4136 will compens ate for i naccu racies by exec uting a self-tuning algorithm following PLL power-up or following a change in the programmed output frequency.

Because the total tank inductance is in the low nH range, the inductance of the package needs to be considered in determining the correct external inductance. The total inductance (L the IF VCO is the sum of the external indu ctanc e (L

) presented to

TOT

EXT

)

16 Rev. 1.0

Si4136

and the package in ductance (L nominal capacitance (C

NOM

). The IF VCO has a

PKG

) in parallel with the total

inductance, and the center frequency is as follows:

CEN

---------------------------------------------

2π L

⋅

TOTCNOM

----------------------------------------------------------------------==

2π L

+()C

PKGLEXT

⋅

NOM

Table 6 summarizes the characteristics of the IF VCO.

Table 6. Si4136-BT VCO Characteristics

VCO Fcen Range

(MHz)

Min Max Min Max

IF 526 952 6.5 2.1 2.2 12.0

Si4136

Cnom

(pF)

PKG

Lpkg

(nH)

Lext Range

(nH)

IFLA

EXT

IFLB

Figure 14. Example of IF External Inductor

As a design example, suppose synthesizing frequencies in a 30 MHz band between 735 MHz and 765 MHz is desired. The center frequency should be defined as midway between the two extremes, or 750 MHz. The PLL will be able to adjust the VCO output frequency ±5% of the center frequency, or ±37.5 MHz of 750 MHz (i.e., from approximately 713 MHz to 788 MHz). The IF VCO has a C

6.9 nH inductance (correc t to two digits) in paralle l with this capacitance w ill yield the desired c enter frequen cy. An external inductan ce of 4.8 nH should be connected between IFLA and IFLB, as shown in Figur e 14. Thi s, in addition to 2.1 nH of package inductance, will present the correct total inductance to the VCO. In manufacturing, the exte rnal inductance can vary ±10 % of its nominal val ue and the Si4136 will c orrect for the variation with the self-tuning algorithm.

For more information on designing the external trace inductor, please refer to Application Note 31.

of 6.5 pF, and a

NOM

Self-Tuning Algorithm

The self-tuning algorithm is initiated immediately following power-up of a PLL or, if the PLL is already powered, following a c hange in its programmed o utput frequency. This algorithm attempts t o tune the VCO so that its free-running frequency is near the desired output frequency. In so doing, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the IF VCO. It will also reduce the frequency error for which the PLL must correct to get the prec ise desi red ou tput fr equency. The self-tuning algorith m will leave the VCO oscillating at a frequency in error by somewhat less than 1% of the desired output frequency.

After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations.

The Si4136’s self-tuning algorit hm will compensate for component value errors at any temperature within the specified temperature r ange. Howeve r, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with tempe rature coefficients around ±150 ppm/°C, the PLL will be able to maintain lock for changes in temperature of approximately ±30°C.

Applications where the PLL is regularly powered-down or the frequency is perio dical ly repr ogrammed minimi ze or eliminate the potential effects of temperature drift because the VCO is re-tuned in either case. In applications where the ambient temperature can drift substantially after self-tuning, it may be necessary to monitor the lock-detect bar (LDETB) signal on the AUXOUT pin to determine whether a PLL is about to run out of locking capability. (See “Auxiliary Output (AUXOUT)” for how to select LDETB.) The LDETB signal will be low after self-tuning has completed but will rise when either the IF or RF PLL nears the limit of its compensation range. (LDETB will also be high when either PLL is executing the self-tuning algorithm.) The output frequency wi ll still be locked when LDETB goes high, but the PLL will eventually lose lock if the temperature continues to drift in the same direction. Therefore, if LDETB goes high both the IF and RF PLLs should promptly be re-tu ned by initiating the se lf-tuning algorithm.

Output Frequencies

The IF and RF output frequencies are set by programming the R- and N-Di vider registers. Eac h PLL has its own R and N registers so that each can be

Rev. 1.0 17

Si4136

programmed independ ently. Programming either the Ror N-Divider register for RF1 or RF2 automatically selects the associated output.

When XINDIV2 = 0, the referenc e fr eq uen cy on the XIN pin is divided by R and this signal is the input to the PLL’s phase detector. The other input to the phase detector is the PLL’s VCO output frequency d ivided by 2N for the RF PLLs or N for the IF PLL. After an initial transient

= (2N/R) " f

OUT

= (N/R) " f

OUT

(for the RF PLLs)

REF

(for the IF PLL).

REF

The integers R are set by programming the RF1 RDivider register (Re gister 6), the RF2 R-Divider register (Register 7) and the IF R-Divider register (Register 8).

The integers N are set by programming the RF1 NDivider register (re gister 3), the RF2 N-Divider reg ister (Register 4), and the IF N-Divider register (Register 5).

If the optional divide-by-2 circuit on the XIN pin is enabled (XINDIV2 = 1) then after an initial transient

= (N/R) " f

OUT

/N = (N/2R) " f

OUT

(for the RF PLLs)

REF

(for the IF PLL).

REF

Each N-Divider is impl emented as a conventional high speed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. However, the control of these sub-circuits is handled automatically. Only the appropriate N value should be programmed.

PLL Loop Dynamics

The transient respo nse for each PLL is deter mined by its phase detector up date rate f the phase detector gain programmed for each RF1, RF2, or IF synthesizer. (See Register 1.) Four different settings for the phase detector gain are available for each PLL. The highest gain is pro grammed by setting the two phase detector gain bits to 00, and the lowest by setting the bits to 11. The values of the ava ilable gai ns, relative to the highest gain, are listed in Table 7.

Table 7. Gain Values (Register 1)

KP Bits

00 1 01 1/2 10 1/4 11 1/8

In general, a higher pha se detector gain will decrease in-band phase noi se a nd in cr ea se th e sp eed of the PLL

(equal to f

Relative P.D.

Gain

REF

/R) and

transient until the point at which stability begins to be compromised. The optimal gain depends on N. Table 8 lists recommended settings for different values of N.

Table 8. Optimal KP Settings

RF2

KP2<1:0>IFKPI<1:0>

(Tφ equals 1/fφ).

500 kHz

. For

RF1

<1:0>

≤2047 00 00 00 2048 to 4095 00 01 01 4096 to 8191 01 10 10

8192 to 16383 10 11 11

≥16384 11 11 11

The VCO gain and loop filter characteristics are not programmable.

The settling time for each PL L is direc tly proportio nal to its phase detector update period T During the first 13 update per iods the Si4136 executes the self-tuning algorithm. Thereafter the PLL controls the output frequency. Because of the unique architecture of the Si4136 PLLs, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. Thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled—including time for self-tuning—is around 40 update periods.

Note: This settling time analysis holds for fφ ≤

fφ >

500 kHz

100 µs as specified in Table 5.

, the settling time can be a maximum of

RF and IF Outputs (RFOUT and IFOUT)

The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF V COs and I F VCO, respe ctively. The RF output amplifier receives its input from either the RF1 or RF2 VCO, depending upon which R- or NDivider register was last written. For example, programming the N-Divider register for RF1 automatically selects the RF1 VCO output.

Figure 13 on page 15 show s an appli cation di agram for the Si4136. The R F output signal must b e AC coupled to its load through a capacitor.

The IFOUT pin must also be AC coupled to its load through a capacitor. The IF output level is dependent upon the load. Figure 17 displays the output level versus load resistance. For resistive loads greater than 500 Ω the output level saturates and the bias currents in the IF output amplifier ar e higher than they need to be . The LPWR bit in the Main Configuration register

18 Rev. 1.0

Si4136

)

(Register 0) can be set to 1 to redu ce the bias currents and therefore reduce the power dissipated by the IF amplifier. For loads less than 500 Ω, LPWR should b e set to 0 to maximize the output level.

For IF frequencies greater than 500 MHz, a matching network is required in order to dr ive a 50 Ω l oad. See Figure 15 below. The value of L

MATCH

can be

determined by Table 9. Typical values range between 8 nH and 40 nH.

>500 pF

IFO UT

MATCH

Ω

Figure 15. IF Frequencies > 500 MHz

Table 9. L

MATCH

Frequency L

500–600 MHz 40 nH 600–800 MHz 27 nH 800–1 GHz 18 nH

For frequencies les s than 500 MHz , the IF output b uffer can directly drive a 200 Ω resist ive load or higher. For resistive loads greater than 500 Ω (f < 500 MHz) the LPWR bit can be set to reduc e the po wer cons umed by the IF output buffer. See Figure 16 below.

>500 pF

IFO UT

Values

MATCH

>200

Ω

Figure 16. IF Frequencies < 500 MHz

450

400

350

LPWR=0

300

250

200

Output Voltage (mVrms

150

100

0 200 400 600 800 1000 1200

LPWR=1

Load Resistance (

ΩΩΩΩ

)

Figure 17. Typical IF Output Voltage vs.

Load Resistance at 550 MHz

Reference Frequency Amplifier

The Si4136 provides a refer ence frequency amp lifier. If the driving si gn a l ha s CMO S le ve ls, it ca n be con n ec ted directly to the XIN pin. Otherwise, the reference frequency signal should be AC coupl ed to the XIN pin through a 560 pF capacitor.

Power Down Modes

Tabl e 10 summa rizes t he po wer down fun ctiona lity. The Si4136 can be powered down by taking the PWDNB pin low or by setting bits in the Power Down register (Register 2). When the PWD NB pin is low, the Si4136 will be powered down regardless of the Power Down register settings. When the PWDNB pin is high, power management is under control of the Power Down register bits.

The IF and RF sections of the Si4136 ci rcuitry can be individually power ed down by setting the Power Down register bits PDIB and PDRB low. The reference frequency amplifie r will also b e powered up if eit her the PDRB and PDIB bits are high. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register 0) is equivalent to setting both bits in the Power Down register to 1.

The serial interface remains available and can be written in all power-down modes.

Auxiliary Output (AUXOUT)

The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0).

The LDETB signal can be selected by setting the AUXSEL bits to 011. This signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambie nt temperature drift and sho uld be retuned.

Rev. 1.0 19

Si4136

Table 10. Power Down Configuration

PWDNB Pin AUTOPDB PDIB PDRB IF Circuitry

PWDNB = 0 x x x OFF OFF

000OFFOFF 001OFFON

PWDNB = 1

Note: x = don’t care.

010ONOFF 011ONON 1xxONON

Circuitry

20 Rev. 1.0

Si4136

Control Registers

T a ble 11. Register Summary

Main

Configuration

1 Phase

Detector Gain

2Power

Down

LPWR

000 0

AUXSEL

IFDIV 0 0 0

000000000000 K

XIN

DIV2

000000000000 0 0 0 0

AUTO

PDB

000

PDIB PDRB

3RF1 N

RF1

Divider

4RF2 N

RF2

Divider

5 IF N Divider 0 0 N 6RF1 R

000 0 0 R

RF1

Divider

7RF2 R

000 0 0 R

RF2

Divider

8 IF R Divider 0 0 0 0 0 R

9 Reserved

. . .

15 Reserved

Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior.

Rev. 1.0 21

Si4136

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name 0000AUXSELIFDIV000XIN

LPWR

DIV2

Bit Name Function

17:14 Reserved Program to zero. 13:12 AUXSEL Auxiliary Output Pin Definition.

00 = Reserved. 01 = Force output low. 11 = Lock Detect (LDETB).

11:10 IFDIV IF Output Divider

00 = IFOUT = IFVCO Frequency 01 = IFOUT= IFVCO Frequency/2 10 = IFOUT = IFVCO Frequency/4 11 = IFOUT = IFVCO Frequency/8

9:7 Reserved Program to zero.

6 XINDIV2 XIN Divide-By-2 Mode.

0 = XIN not divided by 2. 1 = XIN divided by 2.

5LPWROutput Power-Level Settings for IF Synthesizer Circuit.

0 = R 1 = R

< 500 Ω—normal power mode.

LOAD

≥ 500 Ω—low power mode.

LOAD

4 Reserved Program to zero.

AUTO

PDB

000

3 AUTOPDB Auto Power Down

0 = Software powerdown is controlled by Register 2. 1 = Equivalent to setting all bits in Register 2 = 1.

2:0 Reserved Program to zero.

22 Rev. 1.0

Si4136

Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name 000000000000 K

Bit Name Function

17:6 Reserved Program to zero.

5:4 K

IF Phase Detector Gain Constant.

N Value K

<2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11

3:2 K

RF2 Phase Detector Gain Constant.

N Value K

<2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11

1:0 K

RF1 Phase Detector Gain Constant.

N Value K

<4096 = 00 4096–8191 = 01 8192–16383 = 10 >16383 = 11

Rev. 1.0 23

Si4136

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name 000000000000000 0

PDIB PDRB

Bit Name Function

17:2 Reserved Program to zero.

1PDIBPower Down IF Synthesizer.

0 = IF synthesizer powered down. 1 = IF synthesizer on.

0 PDRB Power Down RF Synthesizer.

0 = RF synthesizer powered down. 1 = RF synthesizer on.

BitD17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name N

RF1

Bit Name Function

17:0 N

RF1

N Divider for RF1 Synthesizer.

≥ 992.

RF1

BitD17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name 0N

RF2

Bit Name Function

17 Reserved Program to zero.

16:0 N

24 Rev. 1.0

RF2

N Divider for RF2 Synthesizer.

≥ 240.

RF2

Si4136

Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name 00 N

Bit Name Function

17:16 Reserved Program to zero.

15:0 N

N Divider for IF Synthesizer.

≥ 56.

BitD17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name 00000 R

RF1

Name Function

17:13 Reserved Program to zero.

12:0 R

RF1

R Divider for RF1 Synthesizer.

can be any value from 7 to 8189 if KP1 = 00

RF1

8 to 8189 if K 10 to 8189 if K 14 to 8189 if K

= 01

= 10

= 11

BitD17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name 00000 R

RF2

Bit Name Function

17:13 Reserved Program to zero.

12:0 R

RF2

R Divider for RF2 Synthesizer.

can be any value from 7 to 8189 if KP2 = 00

RF2

8 to 8189 if K 10 to 8189 if K 14 to 8189 if K

Rev. 1.0 25

= 01

= 10

= 11

Si4136

BitD17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name 00000 R

Bit Name Function

17:13 Reserved Program to zero.

12:0 R

R Divider for IF Synthesizer.

can be any value from 7 to 8189 if KP1 = 00

8 to 8189 if K 10 to 8189 if K 14 to 8189 if K

= 01

= 10

= 11

26 Rev. 1.0

Pin Descriptions: Si4136

Si4136

SCLK

SDATA

GNDR

RFOUT

VDDR

SENB

VDDI

IFOUT

GNDI

IFLB

IFLA

GNDD

VDDD

GNDD

XIN

PWDNB

AUXOUT

Pin Number(s) Name Description

1 SCLK Serial cl ock input 2 SDATA Serial data input 3, 4, 6, 8–10 GNDR Common ground for RF analog circuitry 5, 7 NC No connect 11 RFOUT Radio frequency (RF) output of the selected RF VCO 12 VDDR Supply voltage for the RF analog circuitry 13 AUXOUT Auxiliary output 14 PWDNB Power down input pin 15 XIN Reference frequency amplifier input 16, 18 GNDD Common ground for digital circuitry 17 VDDD Supply voltage for digital circuitry 19, 20 IFLA, IFLB Pins for inductor connection to IF VCO 21 GNDI Common ground for IF analog circuitry 22 IFOUT Intermediate frequency (IF) output of the IF VCO 23 VDDI Supply voltage for IF analog circuitry 24 SENB Enable serial port input

Rev. 1.0 27

Si4136

Ordering Guide

Ordering Part

Number

Si4136-BT 2.5 GHz/2.3 GHz/IF OUT –40 to 85

Description Temperature

28 Rev. 1.0

Si4136

Package Outline

Figure 18 illustrates t he package de tails for the Si 4136. Table 12 lists the value s for the dimens ions shown i n the illustration.

E1 E

θ1

θ2

L L1

Figure 18. 24-pin Thin Small Shrink Outline Package (TSSOP)

Table 12. Package Diagram Dimensions

Symbol Millimeters

Min Nom Max

A — 1.10 1.20 A1 0.05 — 0.15 A2 0.80 1.00 1.05

b0.19—0.30 c0.09—0.20

D 4.85 5.00 5.15

e0.65 BSC

E6.40 BSC E1 4.30 4.40 4.50

L 0.45 0.60 0.75

L1 1.00 REF

R0.09 — —

R1 0.09 — —

S0.20— —

θ10 —8 θ2 12 REF θ3 12 REF

Rev. 1.0 29

Si4136

Contact Information

Silicon Laboratories Inc.

4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032

Email: productinfo@silabs.com Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

30 Rev. 1.0

Datasheet Si4136-BT Datasheet (Silicon Laboratories)

Specifications and Main Features

Frequently Asked Questions

User Manual

Section Page

Electrical Specifications

Functional Description

Serial Inte rface

Setting the IF VCO Center Frequencies

Self-Tuning Algorithm

Output Frequencies

PLL Loop Dynamics

RF and IF Outputs (RFOUT and IFOUT)

Reference Frequency Amplifier

Power Down Modes

Auxiliary Output (AUXOUT)

Control Registers

Pin Descriptions: Si4136

Ordering Guide

Package Outline

Contact Information