Silicon Laboratories Si4133G-XM2, Si4133G-XT2 Datasheet

Si4133G-X2

A

D

UAL-BAND

F

GSM

OR

RF S

GPRS W

AND

YNTHESIZER WITH INTEGRATED

IRELESS COMMUNICATIONS

Features

!

Dual-Band RF Synthesizers

RF1: 900 MHz to 1.8 GHz

"

RF2: 750 MHz to 1.5 GHz

"

!

IF Synthesizer

1070.4, 1080, and 1089.6 MHz

"

!

Integrated VCOs, Loop Filters,
Varactors, and Resonators

!

Minimal External Components
Required

!

Optimized for Use with Hitachi
Bright2+ Transceiver

!

Settling Time < 150 µs

!

Low Phase Noise

!

Programmable Power Down
Modes

!

1 µA Standby Current

!

18 mA Typical Supply Current

!

2.7 V to 3.6 V Operation

!

Packages: 24-Pin TSSOP and
28-Pin MLP

Applications

!

GSM900, DCS1800, and
PCS1900 Cellular Telephones

!

GPRS Data Terminals

!

HSCSD Data Terminals

Description

The Si4133G-X2 is a monolithic integrated circuit that performs both IF and
dual-band RF synthesis for GSM and GPRS wireless communications
applications. The Si4133G-X2 includes three VCOs, loop filters, reference
and VCO dividers, and phase detectors. Divider an d power down settings
are programmable through a three-wire serial interface.

Functional Block Diagram

XIN

PWDNB

SDATA

SCLK

SENB

UXOUT

Reference

Amplifier

Power

Down

Control

Serial

Interface

22-bit

Data

Register

Test
Mux

÷

65

Phase

Detector

Phase

Phase

Phase

Phase

Phase

Detector

Detector

Detector

Detector

Detector

Phase

Phase

Phase

Phase

Detector

Detector

Detector

Detector

RF1

÷

N

RF2

÷

N

IF

÷

N

RFLA
RFLB

RFOUT

RFLC
RFLD

IFOUT

IFLA
IFLB

VCO

S

Si4133G-XT2

Ordering Information

See page 27.

Pin Assignments

Si4133G-XT2

SCLK

1

SDATA

RFOUT

GNDR

RFLD

RFLC

GNDR

RFLB

RFLA

GNDR

GNDR

VDDR

2

3

4

5

6

7

8

9

10

11

12

Si4133G-XM2

GNDR

SDATA

1

GNDR

2

RFLD

3

RFLC

4

GNDR

5

RFLB

6

RFLA

7

GNDR

8 9 10 11 12 13 14

SCLK

SENB

VDDI

SENB

24

VDDI

23

IFOUT

22

GNDI

21

IFLB

20

IFLA

19

GNDD

18

VDDD

17

GNDD

16

XIN

15

PWDNB

14

AUXOUT

13

IFOUT

GNDI

22232425262728

21

GNDI

20

IFLB

19

IFLA

18

GNDD

17

VDDD

16

GNDD

15

XIN

GNDR

RFOUT

VDDR

PWDNB

AUXOUT

GNDD

GNDR

Patents pending

Rev. 0.9 8/00 Copyright © 2000 by Silicon Laboratories Si4133GX2-DS09

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si4133G-X2

2 Rev. 0.9

Si4133G-X2

T

ABLE OF

C

ONTENTS

Section Page

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pin Descriptions: Si4133G-XT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pin Descriptions: Si4133G-XM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Package Outline: Si4133G-XT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Package Outline: Si4133G-XM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Rev. 0.9 3

Si4133G-X2

Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature T
Supply Voltage V
Supply Voltages Difference V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at 3.0 V and an operating temperature of 25°C unless otherwise stated.

Table 2. Absolute Maximum Ratings

1,2

DD

A

(V

∆

(V

DDR

DDI

– V
– V

DDD
DDD

),
)

–20 25 85 °C

2.7 3.0 3.6 V

–0.3 — 0.3 V

Parameter Symbol Value Unit

DC Supply Voltage V
Input Current
Input Voltage

3
3

Storage Temperature Range T

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2. This device is a high performan ce RF integrated circ uit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.

3. For signals SCLK, SDATA, SENB, PWDNB and XIN.

I

V

DD

IN

IN

STG

–0.5 to 4.0 V

±10 mA

-0.3 to VDD+0.3 V
–55 to 150

o

C

4 Rev. 0.9

Table 3. DC Characteristics

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C

Parameter Symbol Test Condition Min Typ Max Unit

Total Supply Current
RF1 Mode Supply Current
RF2 Mode Supply Current
IF Mode Supply Current

1

1
1

1

Si4133G-X2

RF1 and IF operating — 18 31 mA

—1317mA
—1217mA
—1014mA

Standby Current PWDNB = 0,

XPDM = 0
High Level Input Voltage
Low Level Input Voltage
High Level Input Current

Low Level Input Current

High Level Output Voltage
Low Level Output Voltage

Notes:

1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 1080 MHz, RFPWR = 1

2. For signals SCLK, SDATA, SENB, and PWDNB.

3. For signal AUXOUT.

2

2

2

2

3

3

V

IH

V

IL

I

IH

I

IL

V

OH

V

OL

=

V

3.6 V,

IH

V

= 3.6 V

DD

=

V

0 V,

IL

=

V

3.6 V

DD

IOH = –500 µA VDD–0.4 — — V

IOH = 500 µA — — 0.4 V

—1—µA

0.7 V

DD

— — 0.3 V

——V

DD

V

–10 — 10 µA

–10 — 10 µA

Rev. 0.9 5

Si4133G-X2

t

t

Table 4. Serial Interface Timing

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)

Parameter

1

SCLK Cycle Time t
SCLK Rise Time t
SCLK Fall Time t
SCLK High Time t
SCLK Low Time t
SDATA Setup Time to SCLK↑
SDATA Hold Time from SCLK↑
SENB↓ to SCLK↑ Delay Time
SCLK↑ to SENB↑ Delay Time
SENB↑ to SCLK↑ Delay Time

2

2
2
2
2

SENB Pulse Width t

Symbol Test Condition Min Typ Max Unit

Figure 1 40 — — ns
Figure 1 — — 50 ns
Figure 1 — — 50 ns
Figure 1 10 — — ns
Figure 1 10 — — ns
Figure 2 5 — — ns
Figure 2 0 — — ns
Figure 2 10 — — ns
Figure 2 12 — — ns
Figure 2 12 — — ns
Figure 2 10 — — ns

t

t

hold

t
t
t

clk

r

f

h

l

su

en1

en2

en3

w

Notes:

1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.

2. Timing is not referenced to 50% level of waveform. See Figure 2.

SCLK

r

80%
50%
20%

f

t

h

t

t

l

clk

Figure 1. SCLK Timing Diagram

6 Rev. 0.9

Si4133G-X2

D

17

D

16

D

15

Figure 2. Serial Interface Timing Diagram

First bit

clocked in

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0A3A2A

data
field

Figure 3. Serial Word Format

A
1

clocked in

address

field

A

0

Last bit

A

1

0

Rev. 0.9 7

Si4133G-X2

Table 5. RF and IF Synthesizer Characteristi cs

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)

Parameter

1

XIN Input Frequency f
Reference Amplifier Sensitivity V

Symbol Test Condition Min Typ Max Unit

REF

REF

—13—MHz

0.5 — VDD

V

P-P

+0.3
Internal Phase Detector Frequency f
RF1 VCO Center Frequency Range f
RF2 VCO Center Frequency Range f
IFOUT Center Frequency f
Tuning Range from f

CEN

φ

CEN
CEN
CEN

f

φ

Note: L

= f

/R 200 KHz

REF

947 — 1720 MHz
789 — 1429 MHz

—1080— MHz

±10% –5 — +5%

EXT

RF1 VCO Pushing Open loop — 0.5 — MHz/V
RF2 VCO Pushing — 0.4 — MHz/V
IF VCO Pushing — 0.3 — MHz/V
RF1 VCO Pulling VSWR = 2:1, all
RF2 VCO Pulling — 0.1 — MHz

phases, open loop

IF VCO Pulling — 0.1 — MHz

—0.4—MHz

p-p
p-p
p-p

RF1 Phase Noise 1 MHz offset — –132 — dBc/Hz

3 MHz offset — –142 — dBc/Hz

RF2 Phase Noise 1 MHz offset — –134 — dBc/Hz

3 MHz offset — –144 — dBc/Hz
IF Phase Noise 100 kHz offset — –117 — dBc/Hz
RF1 Integrated Phase Error 100 Hz to 100 kHz — 0.9 — deg rms
RF1 Harmonic Suppression Second Harmonic — –26 dBc
RF2 Harmonic Suppressio n — –26 dB c
IF Harmonic Suppression — –26 dBc
RFOUT Power Level Z
IFOUT Power Level

Notes:

1. RF1 = 1.55 GHz, RF2 = 1.4 GHz, IF = 1080 MHz., RFPWR=0 for all parameters unless otherwise noted.

2. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PD AB, PDIB , and PDRB in regi ster 2) to RF and

IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is
120 µs.

3. From power down re quest (PWDNB↓, or SENB↑ during a write of 0 to bits PDAB, PDIB, and PDRB in register 2) to
supply current equal to I

PWDN

.

= 50 Ω –7 –2 1 dBm

L

ZL = 50 Ω

–10 –6 –3 dBm

8 Rev. 0.9

Table 5. RF and IF Synthesizer Characteristics (Continued)

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)

Si4133G-X2

Parameter

1

Symbol Test Condition Min Typ Max Unit

RF1 Reference Spurs Offset = 200 kHz — –70 — dBc

Offset = 400 kHz — –75 — dBc
Offset = 600 kHz — –80 — dBc

R

F2 Reference Spurs Offset = 200 kHz — –75 — dBc

Offset = 400 kHz — –80 — dBc
Offset = 600 kHz — –80 — dBc

Power Up Request to Synthesizer
Ready Time, RF1, RF2, IF

2

Power Down Request to Synthesizer
Off Time

Notes:

3

1. RF1 = 1.55 GHz, RF2 = 1.4 GHz, IF = 1080 MHz., RFPWR=0 for all parameters unless otherwise noted.

2. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PD AB, PDIB , and PDRB in regi ster 2) to RF and

IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is
120 µs.

3. From power down re quest (PWDNB↓, or SENB↑ during a write of 0 to bits PDAB, PDIB, and PDRB in register 2) to
supply current equal to I

PWDN

.

t

t

pup

pdn

Figures 4, 5 — 140 — µs

Figures 4, 5 — — 100 ns

Figure 4. Hardware Power Management Timing Diagram

Figure 5. Software Power Management Timing Diagram

Rev. 0.9 9

Si4133G-X2

TRACE A: Ch1 FM Gate Time

A Offset us

800

Hz

Real

160

Hz

/div

-461.24

kHz133.59375

-800
Hz

Start: 0 s Stop: 299.21875 us

Figure 6. Typical Transient Response RF1 at 1.6 GHz with

200 kHz Phase Detector Update Frequency

10 Rev. 0.9