Silicon Laboratories EMBER EM358 series Reference Manual
Ember EM358x
EMBER
This reference manual accompanies several documents to provide the complete description of Ember
devices. In the event that the device data sheet and this document contain conflicting information, the device data
sheet should be considered the authoritative source.
EM358X REFERENCE MANUAL
®
EM358x
®
Rev 0.4 8/13 Copyright © 2013 by Silicon Laboratories EM358x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
EM358x
2 Rev. 0.4
EM358x
TABLE OF CONTENTS
1 Related Documents and Conventions ............................................................................... 8
1.1 Related Documents ........................................................................................................ 8
1.1.1 EM358x Data Sheet ............................................................................................ 8
1.1.2 ZigBee Specification ........................................................................................... 8
1.1.3 ZigBee PRO Stack Profile ................................................................................... 8
1.1.4 ZigBee Stack Profile ............................................................................................ 8
1.1.5 Bluetooth Core Specification ............................................................................... 8
1.1.6 IEEE 802.15.4-2003 ............................................................................................ 8
1.1.7 IEEE 802.11g ...................................................................................................... 8
1.1.8 USB 2.0 Specification ......................................................................................... 8
1.1.9 ARM® Cortex™-M3 Reference Manual ............................................................... 8
1.2 Conventions .................................................................................................................... 9
2 ARM® Cortex™-M3 and Memory Modules ....................................................................... 12
2.1 ARM® Cortex™-M3 Microprocessor ............................................................................. 12
2.2 Embedded Memory ...................................................................................................... 13
2.2.1 Flash Memory ................................................................................................... 14
2.2.2 RAM .................................................................................................................. 17
2.2.3 Registers ........................................................................................................... 17
2.3 Memory Protection Unit ................................................................................................ 18
3 Interrupt System ................................................................................................................ 19
3.1 Nested Vectored Interrupt Controller (NVIC) ................................................................ 19
3.2 Event Manager ............................................................................................................. 22
3.3 Non-maskable Interrupt (NMI) ...................................................................................... 24
3.4 Faults ............................................................................................................................ 25
3.5 Registers ....................................................................................................................... 26
4 Radio Module ..................................................................................................................... 33
4.1 Receive (Rx) Path ......................................................................................................... 33
4.1.1 Rx Baseband .................................................................................................... 33
4.1.2 RSSI and CCA .................................................................................................. 34
4.2 Transmit (Tx) Path ........................................................................................................ 34
4.2.1 Tx Baseband ..................................................................................................... 34
4.2.2 TX_ACTIVE and nTX_ACTIVE Signals ............................................................ 34
4.3 Calibration ..................................................................................................................... 34
4.4 Integrated MAC Module ................................................................................................ 34
4.5 Packet Trace Interface (PTI) ......................................................................................... 35
4.6 Random Number Generator ......................................................................................... 35
5 System Modules ................................................................................................................ 36
5.1 Power domains ............................................................................................................. 37
5.1.1 Internally regulated power ................................................................................. 37
5.1.2 Externally regulated power ................................................................................ 37
5.2 Resets ........................................................................................................................... 37
5.2.1 Reset Sources .................................................................................................. 37
5.2.2 Reset Recording ............................................................................................... 39
5.2.3 Reset Generation Module ................................................................................. 39
5.3 Clocks ........................................................................................................................... 40
Rev. 0.4 3
EM358x
5.3.1 High-Frequency Internal RC Oscillator (OSCHF) .............................................. 42
5.3.2 High-Frequency Crystal Oscillator (OSC24M) .................................................. 42
5.3.3 Low-Frequency Internal RC Oscillator (OSCRC) .............................................. 43
5.3.4 Low-Frequency Crystal Oscillator (OSC32K) .................................................... 43
5.3.5 Clock Switching ................................................................................................. 44
5.4 System Timers .............................................................................................................. 44
5.4.1 Watchdog Timer ................................................................................................ 44
5.4.2 Sleep Timer ....................................................................................................... 45
5.4.3 Event Timer ....................................................................................................... 45
5.5 Power Management ...................................................................................................... 45
5.5.1 Wake Sources ................................................................................................... 45
5.5.2 Basic Sleep Modes ........................................................................................... 47
5.5.3 Further options for deep sleep .......................................................................... 47
5.5.4 RAM Retention in deep sleep ........................................................................... 48
5.5.5 Use of debugger with sleep modes ................................................................... 48
5.5.6 Registers ........................................................................................................... 49
5.6 Security Accelerator ...................................................................................................... 50
6 Integrated Voltage Regulator ........................................................................................... 51
7 GPIO (General Purpose Input / Output) ........................................................................... 52
7.1 GPIO Ports ................................................................................................................... 52
7.2 Configuration ................................................................................................................ 53
7.3 Forced Functions .......................................................................................................... 54
7.4 Reset ............................................................................................................................ 55
7.5 Boot Configuration ........................................................................................................ 55
7.6 GPIO Modes ................................................................................................................. 56
7.6.1 Analog Mode ..................................................................................................... 56
7.6.2 Input Mode ........................................................................................................ 56
7.6.3 SWDIO Mode .................................................................................................... 57
7.6.4 Output Mode ..................................................................................................... 57
7.6.5 Alternate Output Mode ...................................................................................... 57
7.6.6 Alternate Output SPI Slave MISO Mode ........................................................... 57
7.7 Wake Monitoring ........................................................................................................... 58
7.8 External Interrupts ........................................................................................................ 58
7.9 Debug Control and Status ............................................................................................. 59
7.10 GPIO Signal Assignment Summary ............................................................................ 59
7.11 Registers .................................................................................................................... 61
8 Serial Controllers .............................................................................................................. 74
8.1 Overview ....................................................................................................................... 74
8.2 Configuration ................................................................................................................ 75
8.2.1 Registers ........................................................................................................... 76
8.3 SPI - Master Mode ........................................................................................................ 80
8.3.1 GPIO Usage ...................................................................................................... 80
8.3.2 Set Up and Configuration .................................................................................. 80
8.3.3 Operation .......................................................................................................... 81
8.3.4 Interrupts ........................................................................................................... 82
8.3.5 Registers ........................................................................................................... 83
4 Rev. 0.4
EM358x
8.4 SPI - Slave Mode .......................................................................................................... 88
8.4.1 GPIO Usage ...................................................................................................... 88
8.4.2 Set Up and Configuration .................................................................................. 88
8.4.3 Operation .......................................................................................................... 89
8.4.4 DMA .................................................................................................................. 90
8.4.5 Interrupts ........................................................................................................... 90
8.4.6 Registers ........................................................................................................... 90
8.5 TWI - Two Wire serial Interfaces ................................................................................... 90
8.5.1 GPIO Usage ...................................................................................................... 91
8.5.2 Set Up and Configuration .................................................................................. 91
8.5.3 Constructing Frames ......................................................................................... 91
8.5.4 Interrupts ........................................................................................................... 93
8.5.5 Registers ........................................................................................................... 94
8.6 UART - Universal Asynchronous Receiver / Transmitter .............................................. 97
8.6.1 GPIO Usage ...................................................................................................... 97
8.6.2 Set Up and Configuration .................................................................................. 97
8.6.3 FIFOs ................................................................................................................ 99
8.6.4 RTS/CTS Flow control ...................................................................................... 99
8.6.5 DMA ................................................................................................................ 100
8.6.6 Interrupts ......................................................................................................... 100
8.6.7 Registers ......................................................................................................... 102
8.7 DMA Channels ............................................................................................................ 106
8.7.1 Registers ......................................................................................................... 107
9 USB Device ...................................................................................................................... 124
9.1 Overview ..................................................................................................................... 124
9.2 Host Drivers ................................................................................................................ 124
9.3 References ................................................................................................................. 124
9.4 GPIO Usage and USB Pin Assignments..................................................................... 124
9.5 Application Schematics ............................................................................................... 125
9.6 Endpoints .................................................................................................................... 125
9.7 Buffers and DMA ........................................................................................................ 126
9.8 Set Up and Configuration ............................................................................................ 126
9.9 DMA Usage and Transfers ......................................................................................... 128
9.10 Enumeration ............................................................................................................. 128
9.11 Normal COM Port Operation .................................................................................... 128
9.12 Suspend and Resume .............................................................................................. 128
9.13 Interrupts .................................................................................................................. 128
9.13.1 Registers ......................................................................................................... 129
10 General Purpose Timers (TIM1 and TIM2) ..................................................................... 139
10.1 Introduction ............................................................................................................... 139
10.2 GPIO Usage ............................................................................................................. 140
10.3 Timer Functional Description .................................................................................... 141
10.3.1 Time-Base Unit ............................................................................................... 141
10.3.2 Counter Modes ............................................................................................... 142
10.3.3 Clock Selection ............................................................................................... 147
10.3.4 Capture/Compare Channels ........................................................................... 150
Rev. 0.4 5
EM358x
10.3.5 Input Capture Mode ........................................................................................ 151
10.3.6 PWM Input Mode ............................................................................................ 152
10.3.7 Forced Output Mode ....................................................................................... 152
10.3.8 Output Compare Mode .................................................................................... 153
10.3.9 PWM Mode ..................................................................................................... 154
10.3.10One-Pulse Mode ............................................................................................ 156
10.3.11Encoder Interface Mode ................................................................................. 158
10.3.12Timer Input XOR Function ............................................................................. 159
10.3.13Timers and External Trigger Synchronization ................................................ 160
10.3.14Slave Mode: Reset Mode ............................................................................... 160
10.3.15Timer Synchronization ................................................................................... 162
10.3.16Timer Signal Descriptions .............................................................................. 166
10.4 Interrupts .................................................................................................................. 167
10.5 Registers .................................................................................................................. 168
11 ADC (Analog to Digital Converter) ................................................................................. 195
11.1 Setup and Configuration ........................................................................................... 195
11.1.1 GPIO Usage .................................................................................................... 196
11.1.2 Voltage Reference .......................................................................................... 196
11.1.3 Offset/Gain Correction .................................................................................... 196
11.1.4 DMA ................................................................................................................ 196
11.1.5 ADC Configuration Register ............................................................................ 197
11.2 Interrupts .................................................................................................................. 199
11.3 Operation .................................................................................................................. 200
11.4 Calibration ................................................................................................................ 200
11.5 ADC Key Parameters ............................................................................................... 201
11.6 Registers .................................................................................................................. 206
12 Trace Port Interface Unit (TPIU) ..................................................................................... 218
13 Instrumentation Trace Macrocell (ITM) .......................................................................... 219
14 Embedded Trace Macrocell (ETM) ................................................................................. 220
15 Data Watchpoint and Trace (DWT) ................................................................................. 221
16 Flash Patch and Breakpoint (FPB) ................................................................................. 222
17 Serial Wire and JTAG (SWJ) Interface ........................................................................... 223
A. Register Address Table .................................................................................................. 224
6 Rev. 0.4
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Rev. 0.4 7
EM358x
1 Related Documents and Conventions
1.1 Related Documents
This reference manual accompanies several documents to provide the complete description of the Ember
EM358x devices.
1.1.1 EM358x Data Sheet
The Silicon Laboratories EM358x data sheet provides the configuration information for the EM358x.
1.1.2 ZigBee Specification
The core ZigBee specification (Document 053474) defines ZigBee's smart, cost-effective and energy-efficient
mesh network. It can be downloaded from the ZigBee website (111.zigbee.org). ZigBee Alliance membership is
required.
1.1.3 ZigBee PRO Stack Profile
The ZigBee PRO Stack Profile specification (Document 074855) is optimized for low power consumption and to
support large networks with thousands of devices. It can be downloaded from the ZigBee website
(111.zigbee.org). ZigBee Alliance membership is required.
1.1.4 ZigBee Stack Profile
The ZigBee Stack Profile specification (Document 064321) is designed to support smaller networks with hundreds
of devices in a single network. It can be downloaded from the ZigBee website (111.zigbee.org). ZigBee Alliance
membership is required.
1.1.5 Bluetooth Core Specification
The Bluetooth specification is the global short-range wireless standard enabling connectivity for a broad range of
electronic devices. Version 2.1 + EDR (Enhanced Data Rate) can be found here:
http://www.bluetooth.org/docman/handlers/downloaddoc.ashx?doc_id=241363
1.1.6 IEEE 802.15.4-2003
This standard defines the protocol and compatible interconnection for data communication devices using low data
rate, low power and low complexity, short-range radio frequency (RF) transmissions in a wireless personal area
network (WPAN). It can be found here:
IEEE 802.15.4-2003 (http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf)
1.1.7 IEEE 802.11g
This version provides changes and additions to support the further higher data rate extension for operation in the
2.4 GHz band. It can be found here:
standards.ieee.org/getieee802/download/802.11g-2003.pdf
1.1.8 USB 2.0 Specification
The Universal Serial Bus Revision 2.0 specification provides the technical details to understand USB
requirements and design USB compatible products. The main specification (usb_20.pdf) is part of the zipfile found
here:
http://www.usb.org/developers/docs/usb_20_101111.zip
®
1.1.9 ARM
ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM
reference documentation. The online reference manual can be found here:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3
Cortex™-M3 Reference Manual
®
Cortex™-M3
8 Rev. 0.4
1.2 Conventions
Abbreviations and acronyms used in this data sheet are explained in Table 1-1.
Table 1-1. Acronyms and Abbreviations
Acronym/Abbreviation Meaning
ACK Acknowledgement
ADC Analog to Digital Converter
AES Advanced Encryption Standard
AGC Automatic Gain Control
AHB Advanced High Speed Bus
APB Advanced Peripheral Bus
CBC-MAC Cipher Block Chaining—Message Authentication Code
CCA Clear Channel Assessment
CCM Counter with CBC-MAC Mode for AES encryption
CCM* Improved Counter with CBC-MAC Mode for AES encryption
EM358x
CIB Customer Information Block
CLK1K 1 kHz Clock
CLK32K 32.768 kHz Crystal Clock
CPU Central Processing Unit
CRC Cyclic Redundancy Check
CSMA-CA Carrier Sense Multiple Access-Collision Avoidance
CTR Counter Mode
CTS Clear to Send
DNL Differential Non-Linearity
DMA Direct Memory Access
DWT Data Watchpoint and Trace
EEPROM Electrically Erasable Programmable Read Only Memory
EM Event Manager
ENOB effective number of bits
ESD Electro Static Discharge
ESR Equivalent Series Resistance
ETR External Trigger Input
FCLK ARM® CortexTM-M3 CPU Clock
FIB Fixed Information Block
FIFO First-in, First-out
Rev. 0.4 9
EM358x
Acronym/Abbreviation Meaning
FPB Flash Patch and Breakpoint
GPIO General Purpose I/O (pins)
HF High Frequency
I2C Inter-Integrated Circuit
IDE Integrated Development Environment
IF Intermediate Frequency
IEEE Institute of Electrical and Electronics Engineers
INL Integral Non-linearity
ITM Instrumentation Trace Macrocell
JTAG Joint Test Action Group
LF Low Frequency
LNA Low Noise Amplifier
LQI Link Quality Indicator
LSB Least significant bit
MAC Medium Access Control
MFB Main Flash Block
MISO Master in, slave out
MOS Metal Oxide Semiconductor (P-channel or N-channel)
MOSI Master out, slave in
MPU Memory Protection Unit
MSB Most significant bit
MSL Moisture Sensitivity Level
NACK Negative Acknowledge
NIST National Institute of Standards and Technology
NMI Non-Maskable Interrupt
NVIC Nested Vectored Interrupt Controller
OPM One-Pulse Mode
O-QPSK Offset-Quadrature Phase Shift Keying
OSC24M High Frequency Crystal Oscillator
OSC32K Low-Frequency 32.768 kHz Oscillator
OSCHF High-Frequency Internal RC Oscillator
OSCRC Low-Frequency RC Oscillator
PA Power Amplifier
10 Rev. 0.4
Acronym/Abbreviation Meaning
PCLK Peripheral clock
PER Packet Error Rate
PHY Physical Layer
PLL Phase-Locked Loop
POR Power-On-Reset
PRNG Pseudo Random Number Generator
PSD Power Spectral Density
PTI Packet Trace Interface
PWM Pulse Width Modulation
QFN Quad Flat Pack
RAM Random Access Memory
RC Resistive/Capacitive
RF Radio Frequency
EM358x
RMS Root Mean Square
RoHS Restriction of Hazardous Substances
RSSI Receive Signal Strength Indicator
RTS Request to Send
Rx Receive
SYSCLK System clock
SDFR Spurious Free Dynamic Range
SFD Start Frame Delimiter
SINAD Signal-to-noise and distortion ratio
SPI Serial Peripheral Interface
SWJ Serial Wire and JTAG Interface
THD Total Harmonic Distortion
TRNG True random number generator
TWI Two Wire serial interface
Tx Transmit
UART Universal Asynchronous Receiver/Transmitter
UEV Update event
USB Universal Serial Bus
VCO Voltage Controlled Oscillator
Rev. 0.4 11
EM358x
2 ARM® Cortex™-M3 and Memory Modules
This chapter discusses the ARM® CortexTM-M3 Microprocessor, and reviews the EM358x’s flash and RAM
memory modules as well as the Memory Protection Unit (MPU).
2.1 ARM® Cortex™-M3 Microprocessor
The EM358x integrates the ARM® CortexTM-M3 microprocessor, revision r1p1, developed by ARM Ltd., making
the EM358x a true System-on-Chip solution. The ARM
architecture processor that has separate internal program and data buses, but presents a unified program and
data address space to software. The word width is 32 bits for both the program and data sides. The ARM
TM
Cortex
The ARM
-M3 allows unaligned word and half-word data accesses to support efficiently-packed data structures.
®
CortexTM-M3 clock speed is configurable to 6 MHz, 12 MHz, or 24 MHz. For normal operation 24 MHz
is preferred over 12 MHz due to improved performance for all applications and improved duty cycling for
applications using sleep modes. The 6 MHz operation can only be used when radio operations are not required
since the radio requires an accurate 12 MHz clock.
®
The ARM
CortexTM-M3 in the EM358x has also been enhanced to support two separate memory protection
levels. Basic protection is available without using the MPU, but normal operation uses the MPU. The MPU allows
for protecting unimplemented areas of the memory map to prevent common software bugs from interfering with
software operation. The architecture could also allow for separation of the networking stack from the application
code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the
developer to assist in tracking down and fixing issues.
®
CortexTM-M3 is an advanced 32-bit modified Harvard
®
12 Rev. 0.4
2.2 Embedded Memory
Figure 2-1 shows the EM358x ARM® CortexTM-M3 memory map.
EM358x
Figure 2-1. EM358x ARM® CortexTM-M3 Memory Map
Rev. 0.4 13
EM358x
2.2.1 Flash Memory
2.2.1.1 Flash Overview
The EM358x provides a total of either 256 or 512 kB of flash memory. The flash memory is provided in three
separate blocks:
Main Flash Block (MFB)
Fixed Information Block (FIB)
Customer Information Block (CIB)
The MFB is divided into 2048-byte pages. The EM358x has either 128 or 256 pages. The CIB is a single 2048byte page. The FIB is a single 2048-byte page. The smallest erasable unit is one page and the smallest writable
unit is an aligned 16-bit half-word. The flash is rated to have a guaranteed 20,000 write/erase cycles. The flash
cell has been qualified for a data retention time of >100 years at room temperature.
Flash may be programmed either through the Serial Wire/JTAG interface or through bootloader software.
Programming flash through Serial Wire/JTAG requires the assistance of RAM-based utility code. Programming
through a bootloader requires Ember software for over-the-air loading or serial link loading.
2.2.1.2 Main Flash Block
The start of the MFB is mapped to both address 0x00000000 and address 0x08000000 in normal boot mode, but
is mapped only to address 0x08000000 in FIB monitor mode (see also section 7.5, Boot Configuration in Chapter
7, GPIO). Consequently, it is recommended that software intended to execute from the MFB is designed to
operate from the upper address, 0x08000000, since this address mapping is always available in all modes.
The MFB stores all program instructions and constant data. A small portion of the MFB is devoted to non-volatile
token storage using the Ember Simulated EEPROM system.
2.2.1.3 Fixed Information Block
The 2 kB FIB is used to store fixed manufacturing data including serial numbers and calibration values. The start
of the FIB is mapped to address 0x08080000. This block can only be programmed during production by Silicon
Labs.
The FIB also contains a monitor program, which is a serial-link-only way of performing low-level memory access.
In FIB monitor mode (see section 7.5, Boot Configuration in Chapter 7, GPIO), the start of the FIB is mapped to
both address 0x00000000 and address 0x08080000 so the monitor may be executed out of reset.
2.2.1.4 Customer Information Block
The 2048 byte CIB can be used to store customer data. The start of the CIB is mapped to address 0x08080800.
The CIB cannot be executed.
The first eight half-words of the CIB are dedicated to special storage called option bytes. An option byte is a 16 bit
quantity of flash where the lower 8 bits contain the data and the upper 8 contain the inverse of the lower 8 bits.
The upper 8 bits are automatically generated by hardware and cannot be written to by the user, see Table 2-1.
The option byte hardware also verifies the inverse of each option byte when exiting from reset and generates an
error, which prevents the CPU from executing code, if a discrepancy is found. All of this is transparent to the user.
14 Rev. 0.4
EM358x
Table 2-1. Option Byte Storage
Address bits [15:8] bits [7:0] Notes
0x08080800 Inverse Option Byte 0 Option Byte 0 Configures flash read protection
0x08080802 Inverse Option Byte 1 Option Byte 1 Reserved
0x08080804 Inverse Option Byte 2 Option Byte 2 Available for customer use1
0x08080806 Inverse Option Byte 3 Option Byte 3 Available for customer use1
0x08080808 Inverse Option Byte 4 Option Byte 4 Configures flash write protection
0x0808080A Inverse Option Byte 5 Option byte 5 Configures flash write protection
0x0808080C Inverse Option Byte 6 Option Byte 6 Configures flash write protection
0x0808080E Inverse Option Byte 7 Option Byte 7 Configures flash write protection
1
Option bytes 2 and 3 do not link to any specific hardware functionality other than the option byte loader. Therefore, they are best used
for storing data that requires a hardware verification of the data integrity.
Table 2-2 shows the mapping of the option bytes that are used for read and write protection of the flash. Each bit
of the flash write protection option bytes protects a 4 page region of the main flash block. The EM358x has up to
32 regions and therefore option bytes 4, 5, 6, and 7 control flash write protection. These write protection bits are
active low, and therefore the erased state of 0xFF disables write protection. Like read protection, write protection
only takes effect after a reset. Write protection not only prevents a write to the region, but also prevents page
erasure.
Option byte 0 controls flash read protection. When option byte 0 is set to 0xA5, read protection is disabled. All
other values, including the erased state 0xFF, enable read protection when coming out of reset. The internal state
of read protection (active versus disabled) can only be changed by applying a full chip reset. If a debugger is
connected to the EM358x, the intrusion state is latched. Read protection is combined with this latched intrusion
signal. When both read protection and intrusion are set, all flash is disconnected from the internal bus. As a side
effect, the CPU cannot execute code since all flash is disconnected from the bus. This functionality prevents a
debug tool from being able to read the contents of any flash. The only means of clearing the intrusion signal is to
disconnect the debugger and reset the entire chip using the nRESET pin. By requiring a chip reset, a debugger
cannot install or execute malicious code that could allow the contents of the flash to be read.
The only way to disable read protection is to program option byte 0 with the value 0xA5. Option byte 0 must be
erased before it can be programmed. Erasing option byte 0 while read protection is active automatically masserases the main flash block. By automatically erasing main flash, a debugger cannot disable read protection and
readout the contents of main flash without destroying its contents.
In general, if read protection is active then write protection should also be active. This prevents an attacker from
reprogramming flash with malicious code that could readout the flash after the debugger is disconnected. To
obtain fully protected flash, both read protection and write protection should be active.
Table 2-2. Option Byte Write Protection Bit Map
Option Byte Bit Notes
Option Byte 0 bit [7:0] Read protection of all flash (MFB, FIB, CIB)
Option Byte 1 bit [7:0] Reserved for Silicon Labs use
Option Byte 2 bit [7:0] Available for customer use
Option Byte 3 bit [7:0] Available for customer use
Rev. 0.4 15
EM358x
Option Byte Bit Notes
Option Byte 4 bit [0] Write protection of address range 0x08000000 – 0x08003FFF
bit [1] Write protection of address range 0x08004000 – 0x08007FFF
bit [2] Write protection of address range 0x08008000 – 0x0800BFFF
bit [3] Write protection of address range 0x0800C000 – 0x0800FFFF
bit [4] Write protection of address range 0x08010000 – 0x08013FFF
bit [5] Write protection of address range 0x08014000 – 0x08017FFF
bit [6] Write protection of address range 0x08018000 – 0x08013FFF
bit [7] Write protection of address range 0x0801C000 – 0x0801FFFF
Option Byte 5 bit [0] Write protection of address range 0x08020000 – 0x08023FFF
bit [1] Write protection of address range 0x08024000 – 0x08027FFF
bit [2] Write protection of address range 0x08028000 – 0x0802BFFF
bit [3] Write protection of address range 0x0802C000 – 0x0802FFFF
bit [4] Write protection of address range 0x08030000 – 0x08033FFF
bit [5] Write protection of address range 0x08034000 – 0x08037FFF
bit [6] Write protection of address range 0x08038000 – 0x0803BFFF
bit [7] Write protection of address range 0x0803C000 – 0x0803FFFF
Option Byte 6 bit [0] Write protection of address range 0x08040000 – 0x08043FFF
bit [1] Write protection of address range 0x08044000 – 0x08047FFF
bit [2] Write protection of address range 0x08048000 – 0x0804BFFF
bit [3] Write protection of address range 0x0804C000 – 0x0804FFFF
bit [4] Write protection of address range 0x08050000 – 0x08053FFF
bit [5] Write protection of address range 0x08054000 – 0x08057FFF
bit [6] Write protection of address range 0x08058000 – 0x0805BFFF
bit [7] Write protection of address range 0x0805C000 – 0x0805FFFF
Option Byte 7 bit [0] Write protection of address range 0x08060000 – 0x08063FFF
bit [1] Write protection of address range 0x08064000 – 0x08067FFF
bit [2] Write protection of address range 0x08068000 – 0x0806BFFF
bit [3] Write protection of address range 0x0806C000 – 0x0806FFFF
bit [4] Write protection of address range 0x08070000 – 0x08073FFF
bit [5] Write protection of address range 0x08074000 – 0x08077FFF
bit [6] Write protection of address range 0x08078000 – 0x0807BFFF
bit [7] Write protection of address range 0x0807C000 – 0x0807FFFF
16 Rev. 0.4
EM358x
2.2.1.5 Simulated EEPROM
Ember software reserves 8 kB of the main flash block as a simulated EEPROM storage area for stack and
customer tokens. The simulated EEPROM storage area implements a wear-leveling algorithm to extend the
number of simulated EEPROM write cycles beyond the physical limit of 20,000 write cycles for which each flash
cell is qualified.
2.2.2 RAM
2.2.2.1 RAM Overview
The EM358x has either 32 or 64 kB of static RAM on-chip. The start of RAM is mapped to address 0x20000000.
Although the ARM
does not permit use of the bit-band feature.
The RAM is physically connected to the AHB System bus and is therefore accessible to both the ARM
M3 microprocessor and the debugger. The RAM can be accessed for both instruction and data fetches as bytes,
half words, or words. The standard MPU configuration does not permit execution from the RAM, but for special
purposes the MPU may be disabled. To the bus, the RAM appears as 32-bit wide memory and in most situations
has zero wait state read or write access. In the higher CPU clock mode the RAM requires one wait state. This is
handled by hardware transparent to the user application with no configuration required.
2.2.2.2 Direct Memory Access (DMA) to RAM
Several of the peripherals are equipped with DMA controllers allowing them to transfer data into and out of RAM
autonomously. This applies to the radio (802.15.4-2003 MAC), general purpose ADC, USB device controller and
the two serial controllers. In the case of the serial controllers, the DMA is full duplex so that a read and a write to
RAM may be requested at the same time. Thus there are six DMA channels in total. See Chapter 8, Section 8.7
and Chapter 11, Section 11.1.4 for a description of how to configure the serial controllers and ADC for DMA
operation. The DMA channels do not use AHB system bus bandwidth as they access the RAM directly.
The EM358x integrates a DMA arbiter that ensures fair access to the microprocessor as well as the peripherals
through a fixed priority scheme appropriate to the memory bandwidth requirements of each master. The priority
scheme is as follows, with the top peripheral being the highest priority:
1. USB Device Controller (where applicable)
2. General Purpose ADC
3. Serial Controller 2 Receive
4. Serial Controller 2 Transmit
5. MAC
6. Serial Controller 1 Receive
7. Serial Controller 1 Transmit
®
CortexTM-M3 allows bit band accesses to this address region, the standard MPU configuration
®
CortexTM-
2.2.2.3 RAM Memory Protection
The EM358x integrates a memory protection mechanism through the ARM® CortexTM-M3 Memory Protection Unit
(MPU) described in the Memory Protection Unit section. The MPU may be used to protect any area of memory.
MPU configuration is normally handled by Ember software.
2.2.3 Registers
Appendix A, Register Address Table provides a short description of all application-accessible registers within the
EM358. Complete descriptions are provided at the end of each applicable peripheral’s description. The registers
are mapped to the system address space starting at address 0x40000000. These registers allow for the control
and configuration of the various peripherals and modules. The CPU only performs word-aligned accesses on the
system bus. The CPU performs a word aligned read-modify-write for all byte, half-word, and unaligned writes and
a word-aligned read for all reads. Silicon Labs recommends accessing all peripheral registers using word-aligned
addressing.
As with the RAM, the peripheral registers fall within an address range that allows for bit-band access by the ARM
TM
Cortex
Rev. 0.4 17
-M3, but the standard MPU configuration does not allow access to this alias address range.
®
EM358x
2.3 Memory Protection Unit
The EM358x includes the ARM® CortexTM-M3 Memory Protection Unit, or MPU. The MPU controls access rights
and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions.
Refer to the ARM
Ember software configures the MPU in a standard configuration and application software should not modify it. The
configuration is designed for optimal detection of illegal instruction or data accesses. If an illegal access is
attempted, the MPU captures information about the access type, the address being accessed, and the location of
the offending software. This simplifies software debugging and increases the reliability of deployed devices. As a
consequence of this MPU configuration, accessing RAM and register bit-band address alias regions is not
permitted, and generates a bus fault if attempted.
®
CortexTM-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU.
18 Rev. 0.4
EM358x
3 Interrupt System
The EM358x’s interrupt system is composed of two parts: a standard ARM® CortexTM-M3 Nested Vectored
Interrupt Controller (NVIC) that provides top-level interrupts, and a proprietary Event Manager (EM) that provides
second-level interrupts. The NVIC and EM provide a simple hierarchy. All second-level interrupts from the EM
feed into top-level interrupts in the NVIC. This two-level hierarchy allows for both fine granular control of interrupt
sources and coarse granular control over entire peripherals, while allowing peripherals to have their own interrupt
vector.
The Nested Vectored Interrupt Controller (NVIC) section provides a description of the NVIC and an overview of
the exception table (ARM nomenclature refers to interrupts as exceptions). The Event Manager section provides a
more detailed description of the Event Manager including a table of all top-level peripheral interrupts and their
second-level interrupt sources.
In practice, top-level peripheral interrupts are only used to enable or disable interrupts for an entire peripheral.
Second-level interrupts originate from hardware sources, and therefore are the main focus of applications using
interrupts.
3.1 Nested Vectored Interrupt Controller (NVIC)
The ARM® CortexTM-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency exception and
interrupt handling. The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late-arriving interrupts. The NVIC also maintains knowledge of the
stacked (nested) interrupts to enable tail-chaining of interrupts.
®
The ARM
management. In addition to the 10 standard interrupts, it contains 18 individually vectored peripheral interrupts
specific to the EM358x.
The NVIC defines a list of exceptions. These exceptions include not only traditional peripheral interrupts, but also
more specialized events such as faults and CPU reset. In the ARM
considered an exception of the highest priority, and the stack pointer is loaded from the first position in the NVIC
exception table. The NVIC exception table defines all exceptions and their position, including peripheral interrupts.
The position of each exception is important since it directly translates to the location of a 32-bit interrupt vector for
each interrupt, and defines the hardware priority of exceptions. Each exception in the table is a 32-bit address that
is loaded into the program counter when that exception occurs. Table 3-1 lists the entire exception table.
Exceptions 0 (stack pointer) through 15 (SysTick) are part of the standard ARM
exceptions 16 (Timer 1) through 35 (USB, where applicable) are the peripheral interrupts specific to the EM358x
peripherals. The peripheral interrupts are listed in greater detail in Table 3-2.
CortexTM-M3 NVIC contains 10 standard interrupts that are related to chip and CPU operation and
®
CortexTM-M3 NVIC, a CPU reset event is
®
CortexTM-M3 NVIC, while
Table 3-1. NVIC Exception Table
Exception Position Description
-
Reset
NMI
Hard Fault
Memory Fault
Bus Fault
Usage Fault
-
Rev. 0.4 19
0
1
2
3
4
5
6
7-10
Stack top is loaded from first entry of vector table on reset.
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (Thread mode). Asynchronous.
Cannot be stopped or preempted by any exception but reset. Asynchronous.
All classes of fault, when the fault cannot activate because of priority or the
Configurable Fault handler has been disabled. Synchronous.
MPU mismatch, including access violation and no match. Synchronous.
Pre-fetch, memory access, and other address/memory-related faults.
Synchronous when precise and asynchronous when imprecise.
Usage fault, such as ‘undefined instruction executed’ or ‘illegal state transition
attempt’. Synchronous.
Reserved.
EM358x
Exception Position Description
SVCall
Debug Monitor
-
PendSV
SysTick
Timer 1
Timer 2
Management
Baseband
Sleep Timer
Serial Controller 1
Serial Controller 2
Security
MAC Timer
MAC Transmit
MAC Receive
ADC
IRQA
IRQB
IRQC
IRQD
Debug
-
-
USB
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
System service call with SVC instruction. Synchronous.
Debug monitor, when not halting. Synchronous, but only active when enabled. It
does not activate if lower priority than the current activation.
Reserved.
Pendable request for system service. Asynchronous and only pended by software.
System tick timer has fired. Asynchronous.
Timer 1 peripheral interrupt.
Timer 2 peripheral interrupt.
Management peripheral interrupt.
Baseband peripheral interrupt.
Sleep Timer peripheral interrupt.
Serial Controller 1 peripheral interrupt.
Serial Controller 2 peripheral interrupt.
Security peripheral interrupt.
MAC Timer peripheral interrupt.
MAC Transmit peripheral interrupt.
MAC Receive peripheral interrupt.
ADC peripheral interrupt.
IRQA peripheral interrupt.
IRQB peripheral interrupt.
IRQC peripheral interrupt.
IRQD peripheral interrupt.
Debug peripheral interrupt.
Reserved.
Reserved.
USB peripheral interrupt (where applicable).
The NVIC also contains a software-configurable interrupt prioritization mechanism. The Reset, NMI, and Hard
Fault exceptions, in that order, are always the highest priority, and are not software-configurable. All other
exceptions can be assigned a 5-bit priority number, with low values representing higher priority. If any exceptions
have the same software-configurable priority, then the NVIC uses the hardware-defined priority. The hardwaredefined priority number is the same as the position of the exception in the exception table. For example, if IRQA
and IRQB both fire at the same time and have the same software-defined priority, the NVIC handles IRQA, with
priority number 28, first because it has a higher hardware priority than IRQB with priority number 29.
20 Rev. 0.4
EM358x
The top-level interrupts are controlled through five ARM® CortexTM-M3 NVIC registers: INT_CFGSET,
INT_CFGCLR, INT_PENDSET, INT_PENDCLR, and INT_ACTIVE. Writing 0 into any bit in any of these five
register is ineffective.
INT_CFGSET - Writing 1 to a bit in INT_CFGSET enables that top-level interrupt.
INT_CFGCLR - Writing 1 to a bit in INT_CFGCLR disables that top-level interrupt.
INT_PENDSET - Writing 1 to a bit in INT_PENDSET triggers that top-level interrupt.
INT_PENDCLR - Writing 1 to a bit in INT_PENDCLR clears that top-level interrupt.
INT_ACTIVE cannot be written to and is used for indicating which interrupts are currently active.
INT_PENDSET and INT_PENDCLR set and clear a simple latch; INT_CFGSET and INT_CFGCLR set and clear
a mask on the output of the latch. Interrupts may be pended and cleared at any time, but any pended interrupt will
not be taken unless the corresponding mask (INT_CFGSET) is set, which allows that interrupt to propagate. If an
INT_CFGSET bit is set and the corresponding INT_PENDSET bit is set, then the interrupt will propagate and be
taken. If INT_CFGSET is set after INT_PENDSET is set, then the interrupt will also propagate and be taken.
Interrupt flags (signals) from the top-level interrupts are level-sensitive.
The second-level interrupt registers, which provide control of the second-level Event Manager peripheral
interrupts, are described in the Event Manager section.
®
For further information on the NVIC and ARM
Reference Manual and the ARM ARMv7-M Architecture Reference Manual.
CortexTM-M3 exceptions, refer to the ARM® CortexTM-M3 Technical
Rev. 0.4 21
EM358x
3.2 Event Manager
While the standard ARM® CortexTM-M3 Nested Vectored Interrupt Controller provides top-level interrupts into the
CPU, the proprietary Event Manager provides second-level interrupts. The Event Manager takes a large variety of
hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the NVIC.
Effectively, all second-level interrupts from a peripheral are “OR’d” together into a single interrupt in the NVIC. In
addition, the Event Manager provides missed indicators for the top-level peripheral interrupts with the register
INT_MISS.
The description of each peripheral’s interrupt configuration and flag registers can be found in the chapters of this
reference manual describing each peripheral. Figure 3-1 shows the Peripheral Interrupts Block Diagram.
Figure 3-1. Peripheral Interrupts Block Diagram
Given a peripheral, ‘periph’, the Event Manager registers (INT_periphCFG and INT_periphFLAG) follow the form:
INT_periphCFG enables and disables second-level interrupts. Writing 1 to a bit in the INT_periphCFG register
enables the second-level interrupt. Writing 0 to a bit in the INT_periphCFG register disables it. The
INT_periphCFG register behaves like a mask, and is responsible for allowing the INT_periphFLAG bits to
propagate into the top-level NVIC interrupts.
INT_periphFLAG indicates second-level interrupts that have occurred. Writing 1 to a bit in a INT_periphFLAG
register clears the second-level interrupt. Writing 0 to any bit in the INT_periphFLAG register is ineffective. The
INT_periphFLAG register is always active and may be set or cleared at any time, meaning if any second-level
interrupt occurs, then the corresponding bit in the INT_periphFLAG register is set regardless of the state of
INT_periphCFG.
If a bit in the INT_periphCFG register is set after the corresponding bit in the INT_periphFLAG register is set then
the second-level interrupt propagates into the top-level interrupts. The interrupt flags (signals) from the secondlevel interrupts into the top-level interrupts are level-sensitive. If a top-level NVIC interrupt is driven by a secondlevel EM interrupt, then the top-level NVIC interrupt cannot be cleared until all second-level EM interrupts are
cleared.
22 Rev. 0.4
EM358x
The INT_periphFLAG register bits are designed to remain set if the second-level interrupt event re-occurs at the
same moment as the INT_periphFLAG register bit is being cleared. This ensures the re-occurring second-level
interrupt event is not missed.
If another enabled second-level interrupt event of the same type occurs before the first interrupt event is cleared,
the second interrupt event is lost because no counting or queuing is used. However, this condition is detected and
stored in the top-level INT_MISS register to facilitate software detection of such problems. The INT_MISS register
is “acknowledged” in the same way as the INT_periphFLAG register—by writing a 1 into the corresponding bit to
be cleared.
Table 3-2 provides a map of all peripheral interrupts. This map lists the top-level NVIC Interrupt bits and, if there is
one, the corresponding second-level EM Interrupt register bits that feed the top-level interrupts.
Table 3-2. NVIC and EM Peripheral Interrupt Map
NVIC Interrupt
(top-level)
19 INT_USB INT_USBFLAG Register 6 INT_SC2 INT_SC2FLAG register
23 INT_USBWAKEUP 12 INT_SCTXULDB
18 Reserved 4 INT_SCTXUND
17 Reserved 3 INT_SCRXOVF
16 INT_DEBUG 2 INT_SCTXIDLE
15 INT_IRQD 1 INT_SCTXFREE
EM Interrupt
(second-level)
22 INT_USBRESUME 11 INT_SCTXULDA
21 INT_USBSUSPEND 10 INT_SCRXULDB
20 INT_USBRESET 9 INT_SCRXULDA
19 INT_USBSOF 8 INT_SCNAK
18 INT_USBNAK 7 INT_SCCDMFIN
17 INT_USBPIPERXOVF 6 INT_SCTXFIN
16 INT_USBPIPETXUND 5 INT_SCRXFIN
15 INT_USBBUFRXOVF 4 INT_SCTXUND
14 INT_USBBUFTXUND 3 INT_SCRXOVF
13 INT_USBRXVALIDEP6 2 INT_SCTXIDLE
12 INT_USBRXVALIDEP5 1 INT_SCTXFREE
11 INT_USBRXVALIDEP4 0 INT_SCRXVAL
10 INT_USBRXVALIDEP3 5 INT_SC1 INT_SC1FLAG register
9 INT_USBRXVALIDEP2 14 INT_SC1PARERR
8 INT_USBRXVALIDEP1 13 INT_SC1FRMERR
7 INT_USBRXVALIDEP0 12 INT_SCTXULDB
6 INT_USBTXACTIVEEP6 11 INT_SCTXULDA
5 INT_USBTXACTIVEEP5 10 INT_SCRXULDB
4 INT_USBTXACTIVEEP4 9 INT_SCRXULDA
3 INT_USBTXACTIVEEP3 8 INT_SCNAK
2 INT_USBTXACTIVEEP2 7 INT_SCCDMFIN
1 INT_USBTXACTIVEEP1 6 INT_SCTXFIN
0 INT_USBTXACTIVEEP0 5 INT_SCRXFIN
NVIC Interrupt
(top-level)
EM Interrupt
(second-level)
Rev. 0.4 23
EM358x
NVIC Interrupt
(top-level)
14 INT_IRQC 0 INT_SCRXVAL
13 INT_IRQB 4 INT_SLEEPTMR
12 INT_IRQA 3 INT_BB
11 INT_ADC INT_ADCFLAG register 2 INT_MGMT
4 INT_ADCOVF 1 INT_TMR2 INT_TMR2FLAG register
10 INT_MACRX 1 INT_TMRCC1IF
9 INT_MACTX 0 INT_TMRUIF
8 INT_MACTMR 0 INT_TMR1 INT_TMR1FLAG register
7 INT_SEC 6 INT_TMRTIF
4 INT_TMRCC4IF
EM Interrupt
(second-level)
3 INT_ADCSAT 6 INT_TMRTIF
2 INT_ADCULDFULL 4 INT_TMRCC4IF
1 INT_ADCULDHALF 3 INT_TMRCC3IF
0 INT_ADCDATA 2 INT_TMRCC2IF
NVIC Interrupt
(top-level)
EM Interrupt
(second-level)
3 INT_TMRCC3IF
2 INT_TMRCC2IF
1 INT_TMRCC1IF
0 INT_TMRUIF
3.3 Non-maskable Interrupt (NMI)
The non-maskable interrupt (NMI) is a special case. Despite being one of the 10 standard ARM® CortexTM-M3
NVIC interrupts, it is sourced from the Event Manager like a peripheral interrupt. The NMI has two second-level
sources; failure of the 24 MHz crystal and watchdog low water mark.
1. Failure of the 24MHz crystal: If the EM358x’s main clock, SYSCLK, is operating from the 24 MHz crystal and
the crystal fails, the EM358x detects the failure and automatically switches to the internal 12 MHz RC clock.
When this failure detection and switch has occurred, the EM358x triggers the CLK24M_FAIL second-level
interrupt, which then triggers the NMI.
2. Watchdog low water mark: If the EM358x’s watchdog is active and the watchdog counter has not been reset
for nominally 1.792 seconds, the watchdog triggers the WATCHDOG_INT second-level interrupt, which then
triggers the NMI.
24 Rev. 0.4
EM358x
3.4 Faults
Four of the exceptions in the NVIC are faults: Hard Fault, Memory Fault, Bus Fault, and Usage Fault. Of these,
three (Hard Fault, Memory Fault, and Usage Fault) are standard ARM
The Bus Fault, though, is derived from EM358x-specific sources. The Bus Fault sources are recorded in the
SCS_AFSR register. Note that it is possible for one access to set multiple SCS_AFSR bits. Also note that MPU
configurations could prevent most of these bus fault accesses from occurring, with the advantage that illegal
writes are made precise faults. The four bus faults are:
WRONGSIZE – Generated by an 8-bit or 16-bit read or write of an APB peripheral register. This fault can also
result from an unaligned 32-bit access.
PROTECTED – Generated by a user mode (unprivileged) write to a system APB or AHB peripheral or
protected RAM (see Chapter 2, Section 2.2.2.3).
RESERVED – Generated by a read or write to an address within an APB peripheral’s 4 kB block range, but
the address is above the last physical register in that block range. Also generated by a read or write to an
address above the top of RAM or flash.
MISSED – Generated by a second SCS_AFSR fault. In practice, this bit is not seen since a second fault also
generates a hard fault, and the hard fault preempts the bus fault.
®
CortexTM-M3 exceptions.
Rev. 0.4 25
EM358x
3.5 Registers
INT_CFGSET
Top-Level Set Interrupts Configuration Register Address: 0xE000E100 Reset: 0x0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG
15 14 13 12 11 10 9 8
INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR
7 6 5 4 3 2 1 0
INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1
Bitname Bitfield Access Description
INT_USB [19] RW Write 1 to enable USB interrupt. (Writing 0 has no effect.) (where
applicable)
INT_RSVD18 [18] RW Reserved: this bit should be ignored.
INT_RSVD17 [17] RW Reserved: this bit should be ignored.
INT_DEBUG [16] RW Write 1 to enable debug interrupt. (Writing 0 has no effect.)
INT_IRQD [15] RW Write 1 to enable IRQD interrupt. (Writing 0 has no effect.)
INT_IRQC [14] RW Write 1 to enable IRQC interrupt. (Writing 0 has no effect.)
INT_IRQB [13] RW Write 1 to enable IRQB interrupt. (Writing 0 has no effect.)
INT_IRQA [12] RW Write 1 to enable IRQA interrupt. (Writing 0 has no effect.)
INT_ADC [11] RW Write 1 to enable ADC interrupt. (Writing 0 has no effect.)
INT_MACRX [10] RW Write 1 to enable MAC receive interrupt. (Writing 0 has no effect.)
INT_MACTX [9] RW Write 1 to enable MAC transmit interrupt. (Writing 0 has no effect.)
INT_MACTMR [8] RW Write 1 to enable MAC timer interrupt. (Writing 0 has no effect.)
INT_SEC [7] RW Write 1 to enable security interrupt. (Writing 0 has no effect.)
INT_SC2 [6] RW Write 1 to enable serial controller 2 interrupt. (Writing 0 has no effect.)
INT_SC1 [5] RW Write 1 to enable serial controller 1 interrupt. (Writing 0 has no effect.)
INT_SLEEPTMR [4] RW Write 1 to enable sleep timer interrupt. (Writing 0 has no effect.)
INT_BB [3] RW Write 1 to enable baseband interrupt. (Writing 0 has no effect.)
INT_MGMT [2] RW Write 1 to enable management interrupt. (Writing 0 has no effect.)
INT_TIM2 [1] RW Write 1 to enable timer 2 interrupt. (Writing 0 has no effect.)
INT_TIM1 [0] RW Write 1 to enable timer 1 interrupt. (Writing 0 has no effect.)
26 Rev. 0.4
EM358x
INT_CFGCLR
Top-Level Clear Interrupts Configuration Register Address: 0xE000E180 Reset: 0x0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG
15 14 13 12 11 10 9 8
INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR
7 6 5 4 3 2 1 0
INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1
Bitname Bitfield Access Description
INT_USB [19] RW Write 1 to disable USB interrupt. (Writing 0 has no effect.) (where
applicable)
INT_RSVD18 [18] RW Reserved: this bit should be ignored.
INT_RSVD17 [17] RW Reserved: this bit should be ignored.
INT_DEBUG [16] RW Write 1 to disable debug interrupt. (Writing 0 has no effect.)
INT_IRQD [15] RW Write 1 to disable IRQD interrupt. (Writing 0 has no effect.)
INT_IRQC [14] RW Write 1 to disable IRQC interrupt. (Writing 0 has no effect.)
INT_IRQB [13] RW Write 1 to disable IRQB interrupt. (Writing 0 has no effect.)
INT_IRQA [12] RW Write 1 to disable IRQA interrupt. (Writing 0 has no effect.)
INT_ADC [11] RW Write 1 to disable ADC interrupt. (Writing 0 has no effect.)
INT_MACRX [10] RW Write 1 to disable MAC receive interrupt. (Writing 0 has no effect.)
INT_MACTX [9] RW Write 1 to disable MAC transmit interrupt. (Writing 0 has no effect.)
INT_MACTMR [8] RW Write 1 to disable MAC timer interrupt. (Writing 0 has no effect.)
INT_SEC [7] RW Write 1 to disable security interrupt. (Writing 0 has no effect.)
INT_SC2 [6] RW Write 1 to disable serial controller 2 interrupt. (Writing 0 has no effect.)
INT_SC1 [5] RW Write 1 to disable serial controller 1 interrupt. (Writing 0 has no effect.)
INT_SLEEPTMR [4] RW Write 1 to disable sleep timer interrupt. (Writing 0 has no effect.)
INT_BB [3] RW Write 1 to disable baseband interrupt. (Writing 0 has no effect.)
INT_MGMT [2] RW Write 1 to disable management interrupt. (Writing 0 has no effect.)
INT_TIM2 [1] RW Write 1 to disable timer 2 interrupt. (Writing 0 has no effect.)
INT_TIM1 [0] RW Write 1 to disable timer 1 interrupt. (Writing 0 has no effect.)
Rev. 0.4 27
EM358x
INT_PENDSET
Top-Level Set Interrupts Pending Register Address: 0xE000E200 Reset: 0x0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG
15 14 13 12 11 10 9 8
INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR
7 6 5 4 3 2 1 0
INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1
Bitname Bitfield Access Description
INT_USB [19] RW Write 1 to pend USB interrupt. (Writing 0 has no effect.) (where applicable)
INT_RSVD18 [18] RW Reserved: this bit should be ignored.
INT_RSVD17 [17] RW Reserved: this bit should be ignored.
INT_DEBUG [16] RW Write 1 to pend debug interrupt. (Writing 0 has no effect.)
INT_IRQD [15] RW Write 1 to pend IRQD interrupt. (Writing 0 has no effect.)
INT_IRQC [14] RW Write 1 to pend IRQC interrupt. (Writing 0 has no effect.).
INT_IRQB [13] RW Write 1 to pend IRQB interrupt. (Writing 0 has no effect.)
INT_IRQA [12] RW Write 1 to pend IRQA interrupt. (Writing 0 has no effect.)
INT_ADC [11] RW Write 1 to pend ADC interrupt. (Writing 0 has no effect.)
INT_MACRX [10] RW Write 1 to pend MAC receive interrupt. (Writing 0 has no effect.)
INT_MACTX [9] RW Write 1 to pend MAC transmit interrupt. (Writing 0 has no effect.)
INT_MACTMR [8] RW Write 1 to pend MAC timer interrupt. (Writing 0 has no effect.)
INT_SEC [7] RW Write 1 to pend security interrupt. (Writing 0 has no effect.)
INT_SC2 [6] RW Write 1 to pend serial controller 2 interrupt. (Writing 0 has no effect.)
INT_SC1 [5] RW Write 1 to pend serial controller 1 interrupt. (Writing 0 has no effect.)
INT_SLEEPTMR [4] RW Write 1 to pend sleep timer interrupt. (Writing 0 has no effect.)
INT_BB [3] RW Write 1 to pend baseband interrupt. (Writing 0 has no effect.)
INT_MGMT [2] RW Write 1 to pend management interrupt. (Writing 0 has no effect.)
INT_TIM2 [1] RW Write 1 to pend timer 2 interrupt. (Writing 0 has no effect.)
INT_TIM1 [0] RW Write 1 to pend timer 1 interrupt. (Writing 0 has no effect.)
28 Rev. 0.4
EM358x
INT_PENDCLR
Top-Level Clear Interrupts Pending Register Address: 0xE000E280 Reset: 0x0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG
15 14 13 12 11 10 9 8
INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR
7 6 5 4 3 2 1 0
INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1
Bitname Bitfield Access Description
INT_USB [19] RW Write 1 to unpend USB interrupt. (Writing 0 has no effect.) (where
applicable)
INT_RSVD18 [18] RW Reserved: this bit should be ignored.
INT_RSVD17 [17] RW Reserved: this bit should be ignored.
INT_DEBUG [16] RW Write 1 to unpend debug interrupt. (Writing 0 has no effect.)
INT_IRQD [15] RW Write 1 to unpend IRQD interrupt. (Writing 0 has no effect.)
INT_IRQC [14] RW Write 1 to unpend IRQC interrupt. (Writing 0 has no effect.)
INT_IRQB [13] RW Write 1 to unpend IRQB interrupt. (Writing 0 has no effect.)
INT_IRQA [12] RW Write 1 to unpend IRQA interrupt. (Writing 0 has no effect.)
INT_ADC [11] RW Write 1 to unpend ADC interrupt. (Writing 0 has no effect.)
INT_MACRX [10] RW Write 1 to unpend MAC receive interrupt. (Writing 0 has no effect.)
INT_MACTX [9] RW Write 1 to unpend MAC transmit interrupt. (Writing 0 has no effect.)
INT_MACTMR [8] RW Write 1 to unpend MAC timer interrupt. (Writing 0 has no effect.)
INT_SEC [7] RW Write 1 to unpend security interrupt. (Writing 0 has no effect.)
INT_SC2 [6] RW Write 1 to unpend serial controller 2 interrupt. (Writing 0 has no effect.)
INT_SC1 [5] RW Write 1 to unpend serial controller 1 interrupt. (Writing 0 has no effect.)
INT_SLEEPTMR [4] RW Write 1 to unpend sleep timer interrupt. (Writing 0 has no effect.)
INT_BB [3] RW Write 1 to unpend baseband interrupt. (Writing 0 has no effect.)
INT_MGMT [2] RW Write 1 to unpend management interrupt. (Writing 0 has no effect.)
INT_TIM2 [1] RW Write 1 to unpend timer 2 interrupt. (Writing 0 has no effect.)
INT_TIM1 [0] RW Write 1 to unpend timer 1 interrupt. (Writing 0 has no effect.)
Rev. 0.4 29
EM358x
INT_ACTIVE
Top-Level Active Interrupts Register Address: 0xE000E300 Reset: 0x0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG
15 14 13 12 11 10 9 8
INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR
7 6 5 4 3 2 1 0
INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1
Bitname Bitfield Access Description
INT_USB [19] RW USB interrupt active (where applicable)
INT_RSVD18 [18] RW Reserved: this bit should be ignored.
INT_RSVD17 [17] RW Reserved: this bit should be ignored.
INT_DEBUG [16] R Debug interrupt active.
INT_IRQD [15] R IRQD interrupt active.
INT_IRQC [14] R IRQC interrupt active.
INT_IRQB [13] R IRQB interrupt active.
INT_IRQA [12] R IRQA interrupt active.
INT_ADC [11] R ADC interrupt active.
INT_MACRX [10] R MAC receive interrupt active.
INT_MACTX [9] R MAC transmit interrupt active.
INT_MACTMR [8] R MAC timer interrupt active.
INT_SEC [7] R Security interrupt active.
INT_SC2 [6] R Serial controller 2 interrupt active.
INT_SC1 [5] R Serial controller 1 interrupt active.
INT_SLEEPTMR [4] R Sleep timer interrupt active.
INT_BB [3] R Baseband interrupt active.
INT_MGMT [2] R Management interrupt active.
INT_TIM2 [1] R Timer 2 interrupt active.
INT_TIM1 [0] R Timer 1 interrupt active.
30 Rev. 0.4
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