Silicon Laboratories EFR32FG12 User Manual

EFR32FG12 Gecko Proprietary Protocol
SoC Family Data Sheet

The Gecko proprietary protocol family of SoCs is part of the Wire­less Gecko portfolio. Gecko SoCs are ideal for enabling energy­friendly proprietary protocol networking for IoT devices.

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea­tures.

Gecko applications include:

• Home and Building Automation and Security

• Metering

• Electronic Shelf Labels

• Industrial Automation

• Commercial and Retail Lighting and Sensing

Core / Memory

TM

ARM Cortex

with DSP extensions and FPU

Flash Program

Memory

M4 processor

RAM Memory

Memory

Protection Unit

Debug Interface

with ETM

Radio Transceiver

RFSENSE

RFSENSE

Lowest power mode with peripheral operational:

BALUN

Sub GHz

LNA

RF Frontend

PA

2.4 GHz

LNA

RF Frontend

PA

I

Q

I

Q

PGA

To Sub GHz
receive I/Q
mixers and PA

Frequency

Synthesizer

To 2.4 GHz receive
I/Q mixers and PA

Controller

DEMOD

IFADC

AGC

MOD

To Sub GHz
and 2.4 GHz PA

LDMA

FRC

CRC

BUFC

RAC

Clock Management

High Frequency

Crystal

Oscillator

Low Frequency

RC Oscillator

Low Frequency

Crystal

Oscillator

Peripheral Reflex System

Serial

Interfaces

USART

Low Energy

UART

2

I

32-bit bus

TM

C

High Frequency

RC Oscillator

Auxiliary High
Frequency RC

Oscillator

Ultra Low

Frequency RC

Oscillator

I/O Ports Analog I/F

External

Interrupts

General

Purpose I/O

Pin Reset

Pin Wakeup

EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active

KEY FEATURES

• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency

• Up to 1 MB of flash and 256 kB of RAM

• Pin-compatible across EFR32FG families
(exceptions apply for 5V-tolerant pins)

• 12-channel Peripheral Reflex System,
Low-Energy Sensor Interface & Multi­channel Capacitive Sense Interface

• Autonomous Hardware Crypto Accelerator
and True Random Number Generator

• Integrated PA with up to 19 dBm (2.4
GHz) or 20 dBm (Sub-GHz) TX power

• Integrated balun for 2.4 GHz

• Robust peripheral set and up to 65 GPIO

Energy Management

Voltage

Regulator

DC-DC

Converter

Brown-Out

Detector

Voltage Monitor

Power-On Reset

Timers and Triggers

Timer/Counter

Low Energy

Timer

Pulse Counter

Low Energy

Sensor Interface

Watchdog Timer

Protocol Timer

Real Time

Counter and

Calendar

Cryotimer

Other

CRYPTO

CRC

True Random

Number Generator

SMU

ADC

Analog

Comparator

IDAC

Capacitive Sense

VDAC

Op-Amp

silabs.com | Building a more connected world. Rev. 1.6

1. Feature List

The EFR32FG12 highlighted features are listed below.

• Low Power Wireless System-on-Chip

•

High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing

• Embedded Trace Macrocell (ETM) for advanced debugging

• Up to 1024 kB flash program memory

• Up to 256 kB RAM data memory

• 2.4 GHz and Sub-GHz radio operation

• Transmit power:

• 2.4 GHz radio: Up to 19 dBm

• Sub-GHz radio: Up to 20 dBm

• Low Energy Consumption

• 8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz

• 10.0 mA RX current at 1 Mbps, GFSK, 2.4 GHz

• 11 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz

• 8.5 mA TX current at 0 dBm output power at 2.4 GHz

• 35.3 mA TX current at 14 dBm output power at 868 MHz

• 70 μA/MHz in Active Mode (EM0)

• 1.5 μA EM2 DeepSleep current (16 kB RAM retention and
RTCC running from LFRCO)

• High Receiver Performance

• -94.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz

• -102.7 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz

• -126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz

• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz

• -107.4 dBm sensitivity at 4.8 kbps, OOK, 433 MHz

• -112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz

• Supported Modulation Formats

• 2/4 (G)FSK with fully configurable shaping

• BPSK / DBPSK TX

• OOK / ASK

• Shaped OQPSK / (G)MSK

• Configurable DSSS and FEC

• Supported Protocols

• Proprietary Protocols

• Wireless M-Bus

• Selected IEEE 802.15.4g SUN-FSK PHYs

• Low Power Wide Area Networks

• Suitable for Systems Targeting Compliance With:

• FCC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249

• ETSI Category I Operation, EN 300 220, EN 300 328

• ARIB T-108, T-96

• China regulatory

EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Feature List

Wide selection of MCU peripherals

•

• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)

• 2 × Analog Comparator (ACMP)

• 2 × Digital to Analog Converter (VDAC)

• 3 × Operational Amplifier (Opamp)

• Digital to Analog Current Converter (IDAC)

• Low-Energy Sensor Interface (LESENSE)

• Multi-channel Capacitive Sense Interface (CSEN)

• Up to 54 pins connected to analog channels (APORT)
shared between analog peripherals

• Up to 65 General Purpose I/O pins with output state reten­tion and asynchronous interrupts

• 8 Channel DMA Controller

• 12 Channel Peripheral Reflex System (PRS)

• 2 × 16-bit Timer/Counter

• 3 or 4 Compare/Capture/PWM channels

• 2 × 32-bit Timer/Counter

• 3 or 4 Compare/Capture/PWM channels

• 32-bit Real Time Counter and Calendar

• 16-bit Low Energy Timer for waveform generation

• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode

• 3 × 16-bit Pulse Counter with asynchronous operation

• 2 × Watchdog Timer with dedicated RC oscillator

• 4 × Universal Synchronous/Asynchronous Receiver/Trans­mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)

•

Low Energy UART (LEUART™)

•

2 × I2C interface with SMBus support and address recogni­tion in EM3 Stop

• Wide Operating Range

• 1.8 V to 3.8 V single power supply

• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system

• Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C)
temperature grades available

• Support for Internet Security

• General Purpose CRC

• True Random Number Generator

• 2 × Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC

• QFN48 7x7 mm Package

• QFN68 8x8 mm Package

• BGA125 7x7 mm Package

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2. Ordering Information

EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Ordering Information

Table 2.1. Ordering Information

Protocol

Ordering Code

EFR32FG12P433F1024GL125-C Proprietary 2.4 GHz @ 19 dBm

EFR32FG12P433F1024GM68-C Proprietary 2.4 GHz @ 19 dBm

EFR32FG12P433F1024GM48-C Proprietary 2.4 GHz @ 19 dBm

EFR32FG12P432F1024GL125-C Proprietary 2.4 GHz @ 19 dBm 1024 256 65 BGA125 -40 to +85°C

EFR32FG12P432F1024GM48-C Proprietary 2.4 GHz @ 19 dBm 1024 256 31 QFN48 -40 to +85°C

EFR32FG12P431F1024GL125-C Proprietary Sub-GHz @ 20 dBm 1024 256 65 BGA125 -40 to +85°C

EFR32FG12P431F1024GM68-C Proprietary Sub-GHz @ 20 dBm 1024 256 46 QFN68 -40 to +85°C

EFR32FG12P431F512GM68-C Proprietary Sub-GHz @ 20 dBm 512 128 46 QFN68 -40 to +85°C

EFR32FG12P431F1024GM48-C Proprietary Sub-GHz @ 20 dBm 1024 256 31 QFN48 -40 to +85°C

EFR32FG12P431F1024IM48-C Proprietary Sub-GHz @ 20 dBm 1024 256 31 QFN48 -40 to +125°C

EFR32FG12P232F1024GL125-C Proprietary 2.4 GHz @ 19 dBm 1024 128 65 BGA125 -40 to +85°C

Stack

Frequency Band

@ Max TX Power

Sub-GHz @ 20 dBm

Sub-GHz @ 20 dBm

Sub-GHz @ 20 dBm

Flash

(kB)

1024 256 65 BGA125 -40 to +85°C

1024 256 46 QFN68 -40 to +85°C

1024 256 28 QFN48 -40 to +85°C

RAM

(kB) GPIO Package Temp Range

EFR32FG12P232F1024GM48-C Proprietary 2.4 GHz @ 19 dBm 1024 128 31 QFN48 -40 to +85°C

EFR32FG12P231F1024GL125-C Proprietary Sub-GHz @ 20 dBm 1024 128 65 BGA125 -40 to +85°C

EFR32FG12P231F1024GM68-C Proprietary Sub-GHz @ 20 dBm 1024 128 46 QFN68 -40 to +85°C

EFR32FG12P231F512GM68-C Proprietary Sub-GHz @ 20 dBm 512 64 46 QFN68 -40 to +85°C

EFR32FG12P231F1024GM48-C Proprietary Sub-GHz @ 20 dBm 1024 128 31 QFN48 -40 to +85°C

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Ordering Information

EFR32

G

X

Wireless Gecko 32-bit

2

Series

Gecko

Family – M, B, F

132 1024 L 125

Flash Memory Size in kB

Memory Type (Flash)

Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)

Performance Grade – P (Performance), B (Basic), V (Value)

Device Configuration

–1 P F G A R

Pin Count

Package – M (QFN), L (BGA)

Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)

Tape and Reel (Optional)

Revision

Figure 2.1. Ordering Code Key

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Table of Contents

1. Feature List ................................2

2. Ordering Information ............................3

3. System Overview ..............................8

3.1 Introduction ...............................8

3.2 Radio .................................8

3.2.1 Antenna Interface ...........................8

3.2.2 Fractional-N Frequency Synthesizer .....................9

3.2.3 Receiver Architecture ..........................9

3.2.4 Transmitter Architecture .........................9

3.2.5 Wake on Radio ............................9

3.2.6 RFSENSE ..............................10

3.2.7 Flexible Frame Handling .........................10

3.2.8 Packet and State Trace .........................10

3.2.9 Data Buffering.............................10

3.2.10 Radio Controller (RAC) .........................10

3.2.11 Random Number Generator .......................11

3.3 Power .................................12

3.3.1 Energy Management Unit (EMU) ......................12

3.3.2 DC-DC Converter ...........................12

3.3.3 Power Domains ............................12

3.4 General Purpose Input/Output (GPIO) ......................13

3.5 Clocking ................................13

3.5.1 Clock Management Unit (CMU) .......................13

3.5.2 Internal and External Oscillators.......................13

3.6 Counters/Timers and PWM ..........................13

3.6.1 Timer/Counter (TIMER) .........................13

3.6.2 Wide Timer/Counter (WTIMER) .......................13

3.6.3 Real Time Counter and Calendar (RTCC) ...................13

3.6.4 Low Energy Timer (LETIMER) .......................14

3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) .................14

3.6.6 Pulse Counter (PCNT) ..........................14

3.6.7 Watchdog Timer (WDOG) .........................14

3.7 Communications and Other Digital Peripherals ...................14

3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ..........14

3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) ..........14

3.7.3 Inter-Integrated Circuit Interface (I2C) .....................14

3.7.4 Peripheral Reflex System (PRS) ......................14

3.7.5 Low Energy Sensor Interface (LESENSE) ...................15

3.8 Security Features .............................15

3.8.1 General Purpose Cyclic Redundancy Check (GPCRC) ...............15

3.8.2 Crypto Accelerator (CRYPTO) .......................15

3.8.3 True Random Number Generator (TRNG) ...................15

3.8.4 Security Management Unit (SMU) ......................15

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3.9 Analog.................................15

3.9.1 Analog Port (APORT) ..........................15

3.9.2 Analog Comparator (ACMP) ........................15

3.9.3 Analog to Digital Converter (ADC) ......................16

3.9.4 Capacitive Sense (CSEN) .........................16

3.9.5 Digital to Analog Current Converter (IDAC) ...................16

3.9.6 Digital to Analog Converter (VDAC) .....................16

3.9.7 Operational Amplifiers ..........................16

3.10 Reset Management Unit (RMU) ........................16

3.11 Core and Memory ............................16

3.11.1 Processor Core ............................16

3.11.2 Memory System Controller (MSC) .....................17

3.11.3 Linked Direct Memory Access Controller (LDMA) ................17

3.12 Memory Map ..............................18

3.13 Configuration Summary ..........................20

4. Electrical Specifications ..........................21

4.1 Electrical Characteristics ..........................21

4.1.1 Absolute Maximum Ratings ........................22

4.1.2 Operating Conditions ..........................24

4.1.3 Thermal Characteristics .........................26

4.1.4 DC-DC Converter ...........................27

4.1.5 Current Consumption ..........................29

4.1.6 Wake Up Times ............................39

4.1.7 Brown Out Detector (BOD) ........................40

4.1.8 Frequency Synthesizer ..........................41

4.1.9 2.4 GHz RF Transceiver Characteristics ....................42

4.1.10 Sub-GHz RF Transceiver Characteristics ...................53

4.1.11 Modem...............................77

4.1.12 Oscillators .............................78

4.1.13 Flash Memory Characteristics .......................82

4.1.14 General-Purpose I/O (GPIO) .......................83

4.1.15 Voltage Monitor (VMON) .........................85

4.1.16 Analog to Digital Converter (ADC) .....................86

4.1.17 Analog Comparator (ACMP) .......................88

4.1.18 Digital to Analog Converter (VDAC) .....................91

4.1.19 Current Digital to Analog Converter (IDAC) ..................94

4.1.20 Capacitive Sense (CSEN) ........................96

4.1.21 Operational Amplifier (OPAMP) ......................98

4.1.22 Pulse Counter (PCNT) ........................101

4.1.23 Analog Port (APORT) .........................101

4.1.24 I2C ...............................102

4.1.25 USART SPI ............................105

4.2 Typical Performance Curves ........................106

4.2.1 Supply Current ...........................107

4.2.2 DC-DC Converter ..........................112

4.2.3 2.4 GHz Radio ...........................114

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5. Typical Connection Diagrams ........................116

5.1 Power ................................116

5.2 RF Matching Networks ..........................118

5.3 Other Connections............................119

6. Pin Definitions ..............................120

6.1 BGA125 2.4 GHz and Sub-GHz Device Pinout ..................120

6.2 BGA125 2.4 GHz Device Pinout .......................124

6.3 BGA125 Sub-GHz Device Pinout .......................127

6.4 QFN68 2.4 GHz and Sub-GHz Device Pinout...................130

6.5 QFN68 Sub-GHz Device Pinout .......................133

6.6 QFN48 2.4 GHz and Sub-GHz Device Pinout...................135

6.7 QFN48 2.4 GHz Device Pinout .......................137

6.8 QFN48 Sub-GHz Device Pinout .......................139

6.9 GPIO Functionality Table .........................141

6.10 Alternate Functionality Overview ......................184

6.11 Analog Port (APORT) Client Maps ......................199

7. BGA125 Package Specifications .......................208

7.1 BGA125 Package Dimensions ........................208

7.2 BGA125 PCB Land Pattern .........................210

7.3 BGA125 Package Marking .........................212

8. QFN48 Package Specifications........................213

8.1 QFN48 Package Dimensions ........................213

8.2 QFN48 PCB Land Pattern .........................215

8.3 QFN48 Package Marking .........................217

9. QFN68 Package Specifications........................218

9.1 QFN68 Package Dimensions ........................218

9.2 QFN68 PCB Land Pattern .........................220

9.3 QFN68 Package Marking .........................222

10. Revision History.............................223

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3. System Overview

3.1 Introduction

The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG12 Wireless
Gecko Reference Manual.

A block diagram of the EFR32FG12 family is shown in Figure 3.1 Detailed EFR32FG12 Block Diagram on page 8. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult

Ordering Information.

SUBGRF_IP

SUBGRF_IN
SUBGRF_OP
SUBGRF_ON

2G4RF_IOP

2G4RF_ION

RESETn

Debug Signals

(shared w/GPIO)

PAVDD

RFVDD

IOVDD

AVDD

DVDD

VREGVDD

VREGSW

DECOUPLE

LFXTAL_P

LFXTAL_N

HFXTAL_P

HFXTAL_N

Sub-GHz RF

LNA

PA

RFSENSE

BALUN

Serial Wire

and ETM

Debug /

Programming

2.4 GHz RF

LNA

PA

Energy Management

bypass

DC-DC

Converter

Voltage

Regulator

Radio Transceiver

I

PGA

Q

I

Frequency

Synthesizer

To RF

Frontend

Q

Circuits

Reset

Management

Unit

Brown Out /

Power-On

Reset

Voltage
Monitor

DEMOD

IFADC

AGC

MOD

FRC

CRC

ARM Cortex-M4 Core

Up to 1024 KB ISP Flash

Program Memory

Up to 256 KB RAM

Memory Protection Unit

Floating Point Unit

LDMA Controller

Watchdog

Timer

Clock Management

ULFRCO

AUXHFRCO

LFRCO

LFXO

HFRCO

HFXO

BUFC

RAC

Port I/O Configuration

IOVDD

Digital Peripherals

LETIMER

TIMER

CRYOTIMER

PCNT

RTC / RTCC

USART

LEUART

I2C

CRYPTO

A

A

H

P

B

B

CRC

LESENSE

Port

Mapper

Analog Peripherals

IDAC

-

Mux & FB

Input Mux

+

-

+

Op-Amp

VDD

Temp

Sense

APORT

VDAC

Internal

Reference

12-bit ADC

Capacitive

Sense

Analog Comparator

Port A

Drivers

Port B

Drivers

Port C

Drivers

Port D

Drivers

Port F

Drivers

Port I

Drivers

Port J

Drivers

Port K

Drivers

PAn

PBn

PCn

PDn

PFn

PIn

PJn

PKn

Figure 3.1. Detailed EFR32FG12 Block Diagram

3.2 Radio

The Gecko family features a radio transceiver supporting proprietary wireless protocols.

3.2.1 Antenna Interface

The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.

The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3.2.2 Fractional-N Frequency Synthesizer

The EFR32FG12 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.

The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.

3.2.3 Receiver Architecture

The EFR32FG12 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid­ing flexibility with respect to known interferers at the image frequency.

The Automatic Gain Control (AGC) block adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity
and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz radio
can be calibrated on-demand by the user for the desired frequency band.

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re­ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan­nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.

The EFR32FG12 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multipath
propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and sub-GHz
bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF receive detec­tion operations.

Note: Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.

3.2.4 Transmitter Architecture

The EFR32FG12 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap­ing.

Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32FG12. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be­tween devices that otherwise lack synchronized RF channel access.

3.2.5 Wake on Radio

The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us­ing a subsystem of the EFR32FG12 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher­als.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3.2.6 RFSENSE

The RFSENSE peripheral generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, provid­ing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.

RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con­sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.

Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.

3.2.7 Flexible Frame Handling

EFR32FG12 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula­tor:

• Highly adjustable preamble length

• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts

• Frame disassembly and address matching (filtering) to accept or reject frames

• Automatic ACK frame assembly and transmission

• Fully flexible CRC generation and verification:

• Multiple CRC values can be embedded in a single frame

• 8, 16, 24 or 32-bit CRC value

• Configurable CRC bit and byte ordering

• Selectable bit-ordering (least significant or most significant bit first)

• Optional data whitening

• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding

• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing

• Optional symbol interleaving, typically used in combination with FEC

• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware

• UART encoding over air, with start and stop bit insertion / removal

• Test mode support, such as modulated or unmodulated carrier output

• Received frame timestamping

3.2.8 Packet and State Trace

The EFR32FG12 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:

• Non-intrusive trace of transmit data, receive data and state information

• Data observability on a single-pin UART data output, or on a two-pin SPI data output

• Configurable data output bitrate / baudrate

• Multiplexed transmitted data, received data and state / meta information in a single serial data stream

3.2.9 Data Buffering

The EFR32FG12 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.

3.2.10 Radio Controller (RAC)

The Radio Controller controls the top level state of the radio subsystem in the EFR32FG12. It performs the following tasks:

• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry

• Run-time calibration of receiver, transmitter and frequency synthesizer

• Detailed frame transmission timing, including optional LBT or CSMA-CA

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3.2.11 Random Number Generator

The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.

Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num­ber generator algorithms such as Fortuna.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3.3 Power

The EFR32FG12 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci­tor.

The EFR32FG12 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.

AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.

3.3.1 Energy Management Unit (EMU)

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi­ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.

3.3.2 DC-DC Converter

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran­sients.

3.3.3 Power Domains

The EFR32FG12 has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power do­main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur­rent consumption of the device.

Table 3.1. Peripheral Power Subdomains

Peripheral Power Domain 1 Peripheral Power Domain 2

ACMP0 ACMP1

PCNT0 PCNT1

ADC0 PCNT2

LETIMER0 CSEN

LESENSE DAC0

APORT LEUART0

- I2C0

- I2C1

- IDAC

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System Overview

3.4 General Purpose Input/Output (GPIO)

EFR32FG12 has up to 65 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or in­put. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher­als. The GPIO subsystem supports asynchronous external pin interrupts.

3.5 Clocking

3.5.1 Clock Management Unit (CMU)

The Clock Management Unit controls oscillators and clocks in the EFR32FG12. Individual enabling and disabling of clocks to all periph­erals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows
software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscilla­tors.

3.5.2 Internal and External Oscillators

The EFR32FG12 supports two crystal oscillators and fully integrates four RC oscillators, listed below.

• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer­ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.

• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.

• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.

• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.

• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys­tal accuracy is not required.

• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con­sumption in low energy modes.

3.6 Counters/Timers and PWM

3.6.1 Timer/Counter (TIMER)

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.

3.6.2 Wide Timer/Counter (WTIMER)

WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh­old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.

3.6.3 Real Time Counter and Calendar (RTCC)

The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla­tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes down to EM4H.

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System Overview

3.6.4 Low Energy Timer (LETIMER)

The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave­forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con­figured to start counting on compare matches from the RTCC.

3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)

The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter­rupt periods, facilitating flexible ultra-low energy operation.

3.6.6 Pulse Counter (PCNT)

The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,
EM2 Deep Sleep, and EM3 Stop.

3.6.7 Watchdog Timer (WDOG)

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.

3.7 Communications and Other Digital Peripherals

3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup­porting:

• ISO7816 SmartCards

• IrDA

•

I2S

3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)

The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.

3.7.3 Inter-Integrated Circuit Interface (I2C)

The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave
and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates
from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.

The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated
transfers. Automatic recognition of slave addresses is provided in active and low energy modes.

3.7.4 Peripheral Reflex System (PRS)

The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripher­als producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in
turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied
by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.

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System Overview

3.7.5 Low Energy Sensor Interface (LESENSE)

The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura­ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.

3.8 Security Features

3.8.1 General Purpose Cyclic Redundancy Check (GPCRC)

The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The suppor­ted 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.

3.8.2 Crypto Accelerator (CRYPTO)

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup­port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and

SHA-256).

Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.

Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.

The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on
data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.

CRYPTO also provides trigger signals for DMA read and write operations.

3.8.3 True Random Number Generator (TRNG)

The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22
and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).

Note: TRNG operation is only supported at VSCALE2. TRNG cannot be used at VSCALE0.

3.8.4 Security Management Unit (SMU)

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.

3.9 Analog

3.9.1 Analog Port (APORT)

The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.

3.9.2 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high­er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.

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System Overview

3.9.3 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.

3.9.4 Capacitive Sense (CSEN)

The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a
switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in
adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin
or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the
combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an aver­aging filter, as well as digital threshold comparators to reduce software overhead.

3.9.5 Digital to Analog Current Converter (IDAC)

The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC
input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of
various step sizes.

3.9.6 Digital to Analog Converter (VDAC)

The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single­ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.

3.9.7 Operational Amplifiers

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to
rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB
space, and cost as compared with standalone opamps because they are integrated on-chip.

3.10 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the EFR32FG12. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

3.11 Core and Memory

3.11.1 Processor Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz

• Memory Protection Unit (MPU) supporting up to 8 memory segments

• Up to 1024 kB flash program memory

• Up to 256 kB RAM data memory

• Configuration and event handling of all peripherals

• 2-pin Serial-Wire debug interface

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System Overview

3.11.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en­ergy modes EM0 Active and EM1 Sleep.

3.11.3 Linked Direct Memory Access Controller (LDMA)

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so­phisticated operations to be implemented.

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System Overview

3.12 Memory Map

The EFR32FG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

Figure 3.2. EFR32FG12 Memory Map — Core Peripherals and Code Space

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System Overview

Figure 3.3. EFR32FG12 Memory Map — Peripherals

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System Overview

3.13 Configuration Summary

The features of the EFR32FG12 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.

Table 3.2. Configuration Summary

Module Configuration Pin Connections

USART0 IrDA

US0_TX, US0_RX, US0_CLK, US0_CS

SmartCard

USART1

I2S

US1_TX, US1_RX, US1_CLK, US1_CS

SmartCard

USART2 IrDA

US2_TX, US2_RX, US2_CLK, US2_CS

SmartCard

USART3

I2S

US3_TX, US3_RX, US3_CLK, US3_CS

SmartCard

TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 - TIM1_CC[3:0]

WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]

WTIMER1 - WTIM1_CC[3:0]

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Electrical Specifications

4. Electrical Specifications

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T

• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow­er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.

• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.

Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.

=25 °C and VDD= 3.3 V, by production test and/or technology characterization.

AMB

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Electrical Specifications

4.1.1 Absolute Maximum Ratings

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia­bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter Symbol Test Condition Min Typ Max Unit

Storage temperature range T

Voltage on any supply pin V

Voltage ramp rate on any
supply pin

DC voltage on any GPIO pin V

Voltage on HFXO pins V

Input RF level on pins
2G4RF_IOP and
2G4RF_ION

Voltage differential between
RF pins (2G4RF_IOP ­2G4RF_ION)

Absolute voltage on RF pins
2G4RF_IOP and
2G4RF_ION

Absolute voltage on Sub­GHz RF pins

STG

DDMAX

V

DDRAMPMAX

DIGPIN

HFXOPIN

P

RFMAX2G4

V

MAXDIFF2G4

V

MAX2G4

V

MAXSUBG

-50 — 150 °C

-0.3 — 3.8 V

— — 1 V / µs

5V tolerant GPIO pins1 2

3

-0.3 — Min of 5.25
and IOVDD

+2

Standard GPIO pins -0.3 — IOVDD+0.3 V

-0.3 — 1.4 V

— — 10 dBm

-50 — 50 mV

-0.3 — 3.8 V

Pins SUBGRF_OP and

-0.3 — 3.8 V

SUBGRF_ON

V

Total current into VDD power
lines

Total current into VSS
ground lines

Current per I/O pin I

Current for all I/O pins I

Junction temperature T

I

VDDMAX

I

VSSMAX

IOMAX

IOALLMAX

J

Pins SUBGRF_IP and

-0.3 — 0.3 V

SUBGRF_IN,

Source — — 200 mA

Sink — — 200 mA

Sink — — 50 mA

Source — — 50 mA

Sink — — 200 mA

Source — — 200 mA

-G grade devices -40 — 105 °C

-I grade devices -40 — 125 °C

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Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Note:

1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.

2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the
maximum IO current specifications.

3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

4.1.2 Operating Conditions

When assigning supply sources, the following requirements must be observed:

• VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.

• VREGVDD = AVDD

• DVDD ≤ AVDD

• IOVDD ≤ AVDD

• RFVDD ≤ AVDD

• PAVDD ≤ AVDD

Electrical Specifications

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Electrical Specifications

4.1.2.1 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Operating ambient tempera­ture range

AVDD supply voltage

1

2

VREGVDD operating supply
voltage2

3

VREGVDD current I

RFVDD operating supply
voltage

DVDD operating supply volt­age

PAVDD operating supply
voltage

IOVDD operating supply volt­age

DECOUPLE output capaci-

6

tor5

T

A

V

AVDD

V

VREGVDD

VREGVDD

V

RFVDD

V

DVDD

V

PAVDD

V

IOVDD

C

DECOUPLE

-G temperature grade -40 25 85 °C

-I temperature grade -40 25 125 °C

1.8 3.3 3.8 V

DCDC in regulation 2.4 3.3 3.8 V

DCDC in bypass, 50mA load 1.8 3.3 3.8 V

DCDC not in use. DVDD external-

1.8 3.3 3.8 V

ly shorted to VREGVDD

DCDC in bypass, T ≤ 85 °C — — 200 mA

DCDC in bypass, T > 85 °C — — 100 mA

All IOVDD pins

1.62 — V

1.62 — V

1.62 — V

4

1.62 — V

VREGVDD

VREGVDD

VREGVDD

VREGVDD

V

V

V

V

0.75 1.0 2.75 µF

Difference between AVDD
and VREGVDD, ABS(AVDD-

VREGVDD)

2

HFCORECLK frequency f

HFCLK frequency f

dV

DD

CORE

HFCLK

— — 0.1 V

VSCALE2, MODE = WS1 — — 40 MHz

VSCALE2, MODE = WS0 — — 25 MHz

VSCALE0, MODE = WS2 — — 20 MHz

VSCALE0, MODE = WS1 — — 14 MHz

VSCALE0, MODE = WS0 — — 7 MHz

VSCALE2 — — 40 MHz

VSCALE0 — — 20 MHz

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Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Note:

1. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific appli­cation. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Characteristics table for TJ and THETAJA.

2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.

3. The minimum voltage required in bypass mode is calculated using R
other loads can be calculated as V

DVDD_min+ILOAD

* R

BYP_max

.

4. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.

5. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val­ue stays within the specified bounds across temperature and DC bias.

6. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi­tion, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70
mA (with a 2.7 µF capacitor).

4.1.3 Thermal Characteristics

from the DCDC specification table. Requirements for

BYP

Table 4.3. Thermal Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Thermal resistance, QFN48
Package

THETA

JA_QFN48

2-Layer PCB, Air velocity = 0 m/s — 75.7 — °C/W

2-Layer PCB, Air velocity = 1 m/s — 61.5 — °C/W

2-Layer PCB, Air velocity = 2 m/s — 55.4 — °C/W

4-Layer PCB, Air velocity = 0 m/s — 30.2 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 26.3 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 24.9 — °C/W

Thermal resistance, BGA125
Package

THE­TA

JA_BGA125

2-Layer PCB, Air velocity = 0 m/s — 90.7 — °C/W

2-Layer PCB, Air velocity = 1 m/s — 73.7 — °C/W

2-Layer PCB, Air velocity = 2 m/s — 66.4 — °C/W

4-Layer PCB, Air velocity = 0 m/s — 45 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 39.6 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 37.6 — °C/W

Thermal resistance, QFN68
Package

THETA

JA_QFN68

4-Layer PCB, Air velocity = 0 m/s — 21.5 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 18.9 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 17.1 — °C/W

silabs.com | Building a more connected world. Rev. 1.6 | 26

EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.4 DC-DC Converter

Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.

Table 4.4. DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range V

Output voltage programma­ble range

1

DCDC_I

V

DCDC_O

Regulation DC accuracy ACC

Regulation window

2

Steady-state output ripple V

Output voltage under/over-

WIN

R

V

OV

shoot

DC

REG

Bypass mode, I

DCDC_LOAD

mA

Low noise (LN) mode, 1.8 V out­put, I

DCDC_LOAD

= 100 mA, or

= 50

1.8 — V

2.4 — V

VREGVDD_

MAX

VREGVDD_

MAX

V

V

Low power (LP) mode, 1.8 V out­put, I

DCDC_LOAD

Low noise (LN) mode, 1.8 V out­put, I

DCDC_LOAD

Low Noise (LN) mode, 1.8 V tar-

= 10 mA

= 200 mA

2.6 — V

1.8 — V

VREGVDD_

MAX

VREGVDD

1.7 — 1.9 V

V

V

get output

Low Power (LP) mode,

1.63 — 2.2 V

LPCMPBIASEMxx3 = 0, 1.8 V tar­get output, I

DCDC_LOAD

Low Power (LP) mode,

≤ 75 µA

1.63 — 2.1 V

LPCMPBIASEMxx3 = 3, 1.8 V tar­get output, I

DCDC_LOAD

≤ 10 mA

Radio disabled — 3 — mVpp

CCM Mode (LNFORCECCM3 =

— 25 60 mV

1), Load changes between 0 mA
and 100 mA

DC line regulation V

DC load regulation I

REG

REG

DCM Mode (LNFORCECCM3 =

0), Load changes between 0 mA
and 10 mA

Overshoot during LP to LN
CCM/DCM mode transitions com­pared to DC level in LN mode

Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode

transitions compared to DC level
in LN mode

Undershoot during BYP/LP to LN
DCM (LNFORCECCM3 = 0) mode

transitions compared to DC level
in LN mode

Input changes between
V

VREGVDD_MAX

and 2.4 V

Load changes between 0 mA and
100 mA in CCM mode

— 45 90 mV

— 200 — mV

— 40 — mV

— 100 — mV

— 0.1 — %

— 0.1 — %

silabs.com | Building a more connected world. Rev. 1.6 | 27

EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Max load current I

LOAD_MAX

Low noise (LN) mode, Heavy

— — 200 mA

Drive4, T ≤ 85 °C

Low noise (LN) mode, Heavy

— — 100 mA

Drive4, T > 85 °C

Low noise (LN) mode, Medium

4

Drive

Low noise (LN) mode, Light

4

Drive

Low power (LP) mode,

— — 100 mA

— — 50 mA

— — 75 µA

LPCMPBIASEMxx3 = 0

Low power (LP) mode,

— — 10 mA

LPCMPBIASEMxx3 = 3

DCDC nominal output ca-

5

pacitor

DCDC nominal output induc-

C

DCDC

L

DCDC

25% tolerance 1 4.7 4.7 µF

20% tolerance 4.7 4.7 4.7 µH

tor

Resistance in Bypass mode R

BYP

— 1.2 2.5 Ω

Note:

1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, V

VREGVDD

.

2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.

3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.

4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi­um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.

5. Output voltage under/over-shoot and regulation are specified with C
must be used if C

is lower than 4.7 µF. See Application Note AN0948 for details.

DCDC

4.7 µF. Different settings for DCDCLNCOMPCTRL

DCDC

silabs.com | Building a more connected world. Rev. 1.6 | 28

EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.5 Current Consumption

4.1.5.1 Current Consumption 3.3 V without DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

Table 4.5. Current Consumption 3.3 V without DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0
mode with all peripherals dis­abled

Current consumption in EM0
mode with all peripherals dis­abled and voltage scaling
enabled

Current consumption in EM1
mode with all peripherals dis­abled

I

ACTIVE

I

ACTIVE_VS

I

EM1

38.4 MHz crystal, CPU running
while loop from flash

1

38 MHz HFRCO, CPU running

— 130 — µA/MHz

— 99 — µA/MHz

Prime from flash

38 MHz HFRCO, CPU running

— 99 105 µA/MHz

while loop from flash

38 MHz HFRCO, CPU running

— 124 — µA/MHz

CoreMark from flash

26 MHz HFRCO, CPU running

— 102 108 µA/MHz

while loop from flash

1 MHz HFRCO, CPU running

— 280 435 µA/MHz

while loop from flash

19 MHz HFRCO, CPU running

— 88 — µA/MHz

while loop from flash

1 MHz HFRCO, CPU running

— 234 — µA/MHz

while loop from flash

38.4 MHz crystal

1

— 80 — µA/MHz

38 MHz HFRCO — 50 54 µA/MHz

26 MHz HFRCO — 52 58 µA/MHz

Current consumption in EM1
mode with all peripherals dis­abled and voltage scaling
enabled

Current consumption in EM2
mode, with voltage scaling
enabled

Current consumption in EM3
mode, with voltage scaling
enabled

Current consumption in
EM4H mode, with voltage
scaling enabled

I

EM1_VS

I

EM2_VS

I

EM3_VS

I

EM4H_VS

1 MHz HFRCO — 230 400 µA/MHz

19 MHz HFRCO — 47 — µA/MHz

1 MHz HFRCO — 193 — µA/MHz

Full 256 kB RAM retention and

— 2.9 — µA

RTCC running from LFXO

Full 256 kB RAM retention and

— 3.2 — µA

RTCC running from LFRCO

16 kB (1 bank) RAM retention and
RTCC running from LFRCO

2

Full 256 kB RAM retention and

— 2.1 3.5 µA

— 2.56 4.8 µA
CRYOTIMER running from ULFR­CO

128 byte RAM retention, RTCC

— 1.0 — µA
running from LFXO

128 byte RAM retention, CRYO-

— 0.45 — µA
TIMER running from ULFRCO

128 byte RAM retention, no RTCC — 0.43 0.9 µA

silabs.com | Building a more connected world. Rev. 1.6 | 29

EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in

I

EM4S

No RAM retention, no RTCC — 0.04 0.1 µA

EM4S mode

Note:

1. CMU_HFXOCTRL_LOWPOWER=0.

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

silabs.com | Building a more connected world. Rev. 1.6 | 30