Silicon Laboratories EFR32 1 Series Layout Design Manual
AN928.1: EFR32 Series 1 Layout Design
Guide
The purpose of this application note is to help users design PCBs
for the EFR32 Wireless Gecko Portfolio using design practices
that allow for good RF performance.
The 2.4 GHz matching principles are described in the application note, AN930.1:
EFR32 Series 1 2.4GHz Matching Guide, and the matching process for the sub-GHz
section is discussed in AN923: EFR32 sub-GHz Matching Guide. The MCU-related
subjects are detailed in the following application notes: AN0918.1: MCU Series 0 to
EFM32GG1x/TG11 Compatibility and Migration Guide, AN0948: Power Configurations
and DC-DC, and AN0955: CRYPTO.
The Silicon Labs MCU and Wireless Starter Kits and Simplicity Studio provide a powerful development and debug environment. In order to take advantage of the capabilities
and features on custom hardware, Silicon Labs recommends including debugging and
programming interface connector(s) in custom hardware designs. The details and benefits of including these connector interfaces are detailed in AN958: Debugging and Pro-
gramming Interfaces for Custom Designs.
The power configurations and the proper usage of the internal DC-DC converter of
EFR32 is described in AN0948: Power Configurations and DC-DC. The RF performance strongly depends on the PCB layout, as well as the design of the matching networks. For optimal performance, Silicon Labs recommends using the PCB layout design guidelines described in the following sections.
KEY POINTS
• Provides a reference schematic and PCB
layout
• Lists and describes all main design
principles
• Provides a summary checklist of all design
principles
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AN928.1: EFR32 Series 1 Layout Design Guide
Design Recommendations When Using EFR32 Series 1 Wireless MCUs
1. Design Recommendations When Using EFR32 Series 1 Wireless MCUs
• Extensive testing has been completed using reference designs provided by Silicon Labs. It is recommended that designers use the
reference designs “as-is” since they minimize detuning effects caused by parasitics or generated by poor component placement and
PCB routing. EFR32 reference design files are available in Simplicity Studio under the Kit Documentation tab.
• The compact RF part of the designs (excluding the 50 Ω single-ended antenna) is highlighted by a blue frame, and it is strongly
recommended to use the same framed RF layout in order to avoid any possibility of detuning effects. The figure below shows the
framed compact RF part of the designs.
Figure 1.1. Top Layer of the Radio Board (Left Side) and Assembly Drawing of the RF Part (Right Side)
• The layout of the MCU VDD filtering capacitors should also be copied from the reference design as much as possible. When layouts
cannot be followed as shown by the reference designs (due to PCB size and shape limitations), the layout design rules described in
the following sections are recommended.
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AN928.1: EFR32 Series 1 Layout Design Guide
Design Recommendations When Using EFR32 Series 1 Wireless MCUs
1.1 Matching Network Types for the 2.4 GHz EFR32 Series 1 Wireless MCU
The antenna and radio interface schematic for the EFR32 Series 1 Dual-band (2.4 GHz and sub-GHz) Reference Radio Board is shown
in the figure below, the 2.4 GHz matching is highlighted by a red frame.
Figure 1.2. Schematic of the RF Section for the EFR32 Series 1 Dual-band Reference Radio Board (2.4 GHz Matching is High-
lighted)
Note: Matching network component values for the 2.4 GHz frequency band should be chosen based on power range. For the correct
component values, refer to the reference designs. The 2.4 GHz-only EFR32 and the dual-band EFR32 have different pinouts. For the
correct pinout information, refer to the data sheet and reference designs.
The 2.4 GHz EFR32 Series 1 wireless MCU can provide maximum +19.5 dBm power. All EFR32 Series 1 reference designs for 2.4
GHz use a series-L parallel-C ladder structured matching network. For low power applications (≤10 dBm) a 2-element L-C network is
sufficient, while high power solutions (>10 dBm) require a 4-element match.
It is not surprising that the increased TX output power of the EFR32 devices is accompanied by a corresponding increase in the absolute level of harmonic signals. Since most regulatory standards (e.g. FCC, ETSI, ARIB etc.) require the harmonic signals to be attenuated below some absolute power level (in watts or dBm), the amount of low-pass filtering required is generally greater on an RF radioboard using an EFR32 that was designed for higher output power.
In the figure above, there is an additional component (R1) beside the 4-element matching, which is basically not part of the matching
network. The default value of R1 is 0 Ω. On 2.4 GHz-only radio boards that use the 2-element matching network, R1 is replaced by an
inductor to suppress the radiated 2nd harmonic. The proper value varies with antenna structure, in most cases 0 Ω can be used. For a
custom design, it is recommended to leave option for this series element, and its default value should be 0 Ω.
Further details on the 2.4 GHz matching network principles can be found in the application note, AN930.1: EFR32 Series 1 2.4GHz
Matching Guide.
All EFR32 Series 1 radio boards for 2.4 GHz comprise a 50 Ω IFA (Inverted-F Antenna) connected to the 50 Ω output of the matching
network to be able to measure radiated performance. Optional conducted measurements are possible on these radio boards through an
U.FL connector.
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AN928.1: EFR32 Series 1 Layout Design Guide
Design Recommendations When Using EFR32 Series 1 Wireless MCUs
1.2 Matching Network Types for the sub-GHz EFR32 Series 1 Wireless MCU
The antenna and radio interface schematic for the EFR32 Series 1 Dual-band (2.4 GHz and sub-GHz) Reference Radio Board is shown
in the figure below, the sub-GHz matching is highlighted by a red frame.
Figure 1.3. Schematic of the RF Section for the EFR32 Series 1 Dual-band Reference Radio Board (sub-GHz Matching is High-
lighted)
Note: Matching network component values should be chosen based on frequency band. Matching network structure can be slightly
different for different frequency bands. For the correct matching network information, refer to the datasheet and reference designs.
The sub-GHz EFR32 Series 1 wireless MCU can provide maximum +19.5 dBm power. All sub-GHz EFR32 matching network consist of
the following sections: impedance transformation circuit, differential to single-ended balun and low-pass filter.
For further details on the sub-GHz matching network principles, refer to the application note, AN923: EFR32 sub-GHz Matching Guide.
All radio boards for sub-GHz comprise an SMA connector, which can be used for conducted measurements or to connect an external
antenna for radiated test purposes.
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AN928.1: EFR32 Series 1 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
2. Guidelines for Layout Design When Using EFR32 Wireless MCUs
Some general guidelines for designing RF-related layouts for good RF performance are:
• For custom designs, use the same number of PCB layers as are present in the reference design whenever possible. Deviation from
the reference PCB layer count can cause different PCB parasitic capacitances, which can detune the matching network from its optimal form. If a design with a different number of layers than the reference design is necessary, make sure that the distance between
the top layer and the first inner layer is similar to that found in the reference design, because this distance determines the parasitic
capacitance value to ground. Otherwise, detuning of the matching network is possible, and fine tuning of the component values may
be required.
• Use as much continuous and unified ground plane metallization as possible, especially on the top and bottom layers.
• Avoid the separation of the ground plane metallization, especially between the ground of the matching network and the RFIC GND
pins / exposed pad.
• Use as many grounding vias (especially near the GND pins) as possible to minimize series parasitic inductance between the ground
pours of different layers and between the GND pins.
• Use a series of GND stitching vias along the PCB edges and internal GND metal pouring edges. The maximum distance between
the vias should be less than lambda/10 of the 10th harmonic (the typical distance between vias on reference radio boards is 40–50
mil). This distance is required to reduce the PCB radiation at higher harmonics caused by the fringing field of these edges.
• For designs with more than two layers, it is recommended to put as many traces (even the digital traces) as possible in an inner
layer and ensure large, continuous GND pours on the top and bottom layers.
• Avoid using long and/or thin transmission lines to connect the RF related components. Otherwise, due to their distributed parasitic
inductance, some detuning effects can occur. Also shorten the interconnection lines as much as possible to reduce the parallel parasitic caps to the ground. However, couplings between neighbor discretes may increase in this way.
• To reduce the coupling between the nearby discrete inductors, avoid placing them in the same orientation.
• Use tapered line between transmission lines with different width (i.e., different impedance) to reduce internal reflections.
• Avoid using loops and long wires to obviate their resonances. They also work well as unwanted radiators, especially at the harmonics.
• Always ensure good VDD filtering by using some bypass capacitors (especially at the range of the operating frequency). The series
self-resonance of the capacitor should be close to the filtered frequency. The bypass capacitor which filters the highest frequency
should be placed closest to the VDD pins of the EFR32. In addition to the fundamental frequency, the crystal/clock frequency and its
harmonics (up to the 3rd) should be filtered to avoid up-converted spurs.
• Connect the crystal case to the ground using many vias to avoid radiation of the ungrounded parts. Do not leave any metal unconnected and floating that may be an unwanted radiator. Avoid leading supply traces close or beneath the crystal or parallel with a
crystal signal or clock trace.
• Place the RF related parts (especially the antenna) far away from the DC-DC converter output and the related DC-DC components.
• Avoid routing GPIO lines close or beneath the RF lines, antenna or crystal, or in parallel with a crystal signal. Use the lowest slew
rate possible on GPIO lines to decrease crosstalk to RF or crystal signals.
• Use as short VDD traces as possible. The VDD trace can be a hidden, unwanted radiator so it is important to simplify the VDD routing
as much as possible and use large, continuous GND pours with many stitching vias. To achieve the simplified VDD routing, try to
avoid star topology of VDD traces (i.e., avoid connecting all VDD traces in one common point).
• Using silkscreen near the antenna could slightly affect the dielectric environment of the antenna. Although this effect is usually negligible, if possible, try to avoid using silkscreen on the antenna or on the antenna copper pour keep out areas.
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AN928.1: EFR32 Series 1 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
2.1 Layout for the 2.4 GHz Frequency Band EFR32 Series 1 Wireless MCU Based on the Dual-band (2.4 GHz and sub-GHz) Reference Radio Board
Examples shown in this section are based on the layout of the EFR32 Series 1 Dual-band Reference Radio Board. The main layout
design concepts are shown with this layout to demonstrate the basic principles. Although these rules will be shown through a design
that uses a 4-element matching, similar design practices should be applied with a 2-element matching network as well. Most of the
layout guidelines in this section are general, and should be applied in the sub-GHz layout design as well.
The layout structure for the RF part of the EFR32 Series 1 Dual-band Reference Radio Board is shown in the figure below, the 2.4 GHz
matching is highlighted by a blue frame.
Figure 2.1. Layout of the RF Section for the EFR32 Series 1 Dual-band Reference Radio Board (2.4 GHz Matching is Highligh-
ted)
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