Silicon Laboratories EFR32 User manual

AN930.2: EFR32 Series 2 2.4 GHz
Matching Guide

The EFR32 Series 2 devices include chip variants that provide

2.4 GHz-only operation. In addition, the EFR32xG21 chips are
only available in a 4x4 mm 32-pin QFN package while the
EFR32xG22 parts have both 32- and 40-pin package variants
available (QFN32, TQFN32, QFN40). This application note de­scribes the matching techniques applied to the EFR32 Series 2
Wireless Gecko Portfolio in the 2.4 GHz band.

For information on PCB layout requirements for proper 2.4 GHz operation, refer to ap­plication note, AN928.2: EFR32 Series 2 Layout Design Guide.

KEY POINTS

• Description of the applied 2.4 GHz
matching networks and techniques for the
EFR32 Series 2 devices

• Detailed discussion of the design steps
and design examples

• Measured TX fundamental and harmonic
performance

• Measured receive sensitivity values

silabs.com | Building a more connected world. Rev. 0.6

1. Device Compatibility

This application note supports the following devices:

EFR32 Wireless Gecko Series 2:

• EFR32MG21

• EFR32MG22

• EFR32BG21

• EFR32BG22

• EFR32FG22

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide

Device Compatibility

silabs.com | Building a more connected world. Rev. 0.6 | 2

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide

Introduction

2. Introduction

This application note is intended to help users achieve the best 2.4 GHz RF match for targeted applications. It describes the details of
matching network design procedures and presents additional test results.

Thorough derivations of four different matching options are presented for EFR32xG21:

• 4-element discrete LC match for up to 0 dBm power levels

• 3-element discrete LC match for up to +10 dBm power levels

• 5-element discrete LC match for up to +20 dBm power levels

• 4-element combined discrete LC match for both +10 and 0 dBm power levels

A 4-element discrete LC match for up to +6 dBm power levels is also presented for EFR32xG22.

The 4x4 mm, 32-pin 2.4 GHz-only version's package pinouts are shown in the figures below for each EFR32xG21 and EFR32xG22
part. The 2.4 GHz RF IO pins are highlighted with a red box.

Figure 2.1. EFR32xG21 2.4 GHz RF IO Pins

silabs.com | Building a more connected world. Rev. 0.6 | 3

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide

Introduction

Figure 2.2. EFR32xG22 2.4 GHz RF IO Pin

2.1 Related Literature

Related documentation includes:

• AN928.2: EFR32 Series 2 Layout Design Guide

• AN0002.2: EFM32 and EFR32 Wireless Gecko Series 2 Hardware Design Considerations

silabs.com | Building a more connected world. Rev. 0.6 | 4

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide

RF Architecture Overview

3. RF Architecture Overview

3.1 EFR32xG21 RF Front-End Overview

The EFR32 Series 2 xG21 chip family has 2.4 GHz RF front ends only. The 2.4 GHz RF front-end architecture is shown in the figure
below. The 2.4 GHz antenna interface consists of two pins (RF2G4_IO1 and RF2G4_IO2) that interface directly to the on-chip BALUN.

Figure 3.1. 2.4 GHz RF Front-end Configuration

Several changes compared to the EFR32 Series 1 chip variants are highlighted below:

• New RF front-end topology: Three PAs included that require an optimal load impedance for each TX power level, i.e., different
matches are required per max TX power.

• Power supply scheme: There is no on-chip DCDC converter available. Optimized for mains-power applications.

• Pre-Regulator for the Power Amplifiers: Linear regulator with an input of PAVDD and output of PA blocks. Regulates to a target volt­age when PAVDD > Vtarget. Follows supply with a ~30 mV offset when PAVDD ≤ Vtarget (and PA power will trail off also).

• For +10 and 0 dBm PA modes: Vtarget = 1.8 V.

• For +20 dBm PA mode: Vtarget = 3.3 V.

• RFSENSE removed, instead a wide-band power sensing block introduced for better out-of-band blocker detection and coexistence
performance.

The on-chip part of the front-end comprises three PA structures optimized for the TX power levels of 0, 10, and 20 dBm, two differential
LNAs, and an integrated balun. Each PA is biased through the PAVDD pin. Externally, a single-ended matching network and harmonic
filtering are required.

• Differential Class-AB mode PA and an internal balun for TX power of +20 dBm

• Single-ended Class-D mode PA for TX power of +10 dBm

• Single-ended Class-D mode PA for TX power of 0 dBm

• Two LNAs

• Two RF IO ports available: Internal switches ground one of the two sides to create single-ended inputs / outputs on either RFIO pin.

silabs.com | Building a more connected world. Rev. 0.6 | 5

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide

RF Architecture Overview

Figure 3.2. 2.4 GHz RF Front-end Block Diagram

3.2 EFR32xG22 RF Front-End Overview

The EFR32 Series 2 xG22 chip family has 2.4 GHz RF front ends only. The radio subsystem is shown in the figure below. The RF front­end consists of an integrated LNA and two separate PAs with an internal switch to select between them, while one RF IO port is availa­ble (RF2G4_IO) at a chip pin.

Figure 3.3. EFR32xG22 Radio Subsystem

A few highlights on the RF front-end blocks:

• Two separate Class-D PAs, optimized for maximum TX power levels of 0 and +6 dBm.

• Each PA is biased through the PAVDD pin

• Externally, a single-ended matching network and harmonic filtering are required

• Power supply scheme: An on-chip, dc-dc converter is available, so this chip variant is optimized for low-power applications with high
efficiency.

silabs.com | Building a more connected world. Rev. 0.6 | 6

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide

2.4 GHz RF Matching Design Steps

4. 2.4 GHz RF Matching Design Steps

2.4 GHz RF matching design for EFR32 chips consists of the following steps:

1. Determine the optimum termination impedance for the PA. Note that different matching topologies are recommended for different
TX power levels as shown in the Introduction section.

2. Choose the RF matching topology.

3. Create the initial design with ideal, loss-free elements. This ideal design can be used as a starting point for a design with parasitics.

4. Design with parasitics and losses. At 2.4 GHz, the parasitics of the SMD elements and the pcb have a major effect, so tuning/
optimization of the design is required. Here an optional EM simulation can be done, but simulations with well-estimated pcb parasit­ics and SMD equivalent models usually give adequate results.

5. Conduct bench testing and tuning.

4.1 Determining the Optimum Termination Impedance for the PA

The first step of the matching design procedure is to determine the optimum termination impedance at the PA. The realized matching
network should present this impedance for the PA at the RF2G4_IO1/2 pin if 50 Ω termination is applied at the antenna port.

The RF2G4_IO1/2 RF port termination determines the major RF parameters, such as the delivered PA power and harmonic content in
TX mode or the sensitivity in RX mode. As part of the design process, the goal is to deliver maximum power to a 50 Ω output termina­tion (e.g., to a 50 Ω antenna) in TX mode. In addition, proper harmonic suppression and good RX sensitivity in reception mode are
required.

4.1.1 EFR32xG21 Optimum PA Load Impedance

The design target of optimum load impedance looking from the PA to the antenna is 14 + j5 Ω at the PA. However, the optimum termi­nation impedance for both delivering the desired power and achieving the best PA efficiency in TX mode is determined by load-pull
testing. The optimum termination impedance at the chip pin is determined for each PA of the EFR32xG21 parts and it slightly differs for
the different power levels, i.e., for the +20, +10, and 0 dBm PAs, and also differs from the design target at the PA due to bonding wire
inductances and parasitics. This termination impedance has to be shown by the matching network at the PA side if its antenna output is
terminated with a 50 Ω load. The optimum termination impedance at chip RF2G4_IO pin is the following:

• For the +20 dBm PA: Zload_opt = 12.6 - j11 Ω

• For the +10 dBm PA: Zload_opt = 12.2 - j8.3 Ω

• For the 0 dBm PA: Zload_opt = 17.4 + j3.9 Ω

The load-pull curves for each PA are shown in 6. Appendix 1 PA Optimum Termination Impedance on EFR32xG21.

Applications with one antenna typically require using only one of the RF IO ports available on the EFR32xG21 parts, in which case the
recommended active RF IO port is RF2G4_IO2. Because this pin has a shorter on-chip, internal connection to the PA blocks so slightly
lower parasitics appear on this pin.

The proper impedance at one of the single-ended RF2G4_IO pins also depends on the loading of the other RF2G4_IO pin. To keep its
effect negligible, for applications with one antenna with both +10 and +20 dBm PAs, it is recommended to directly tie the un-used
RF2G4_IO pin back to the center GND pad of the chip. However, the 0 dBm PA requires to be DC blocked externally so the method
described for the +10 and +20 dBm PAs doesn't work. The 0 dBm PA recommended match includes a series capacitor in the RF path
but for proper operation a DC-blocking 0.5pF capacitor to GND needs to also be used on the unused RF port. Silicon Labs' reference
radio boards are suitable and optimized to be used with the +10 and +20 dBm PAs because of the short between the chip pin and
center GND pad under the chip. More detailed information about proper layout design can be found in application note, "AN928.2:
EFR32 Series 2 Layout Design Guide".

In real radio links, the TX power and the receiver sensitivity together (i.e., the link budget) determine the range. So, with the applied TX
termination impedance, the impedance match in RX mode should also be acceptable. Fortunately, the RX sensitivity is quite immune to
impedance variations. The sensitivity variation is less than 0.5 dB if the termination changes from 50 Ω to the PA optimum impedance
(Zload_opt) given above.

silabs.com | Building a more connected world. Rev. 0.6 | 7

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide

2.4 GHz RF Matching Design Steps

4.1.2 EFR32xG22 Optimum PA Load Impedance

The design target of optimum load impedance looking from the PA to the antenna is 50 Ω at the PA for both 0 and +6 dBm PA. Howev­er, the optimum termination impedance at the chip pin determined for each PA of the EFR32xG22 parts differs from the design target at
the PA due to bonding wire inductances and parasitics. Also, the output match plus low-pass filter (LPF) section is designed to enhance
the suppression of the 2nd- and 3rd-order harmonics. Thus, the optimum termination impedance at the chip pin is about 37 + j5 Ω for
both 0 and +6 dBm PA and this impedance has to be shown by the matching network at the PA side if its antenna output is terminated
with a 50 Ω load.

Because the optimum termination impedance is the same for both 0 and +6 dBm PA, the matching network is also identical for these
different power levels. Silicon Labs provides radio boards with one matching network applied, however, the series dc-blocking capacitor
in the match plus LPF section must be needed only when the 0 dBm PA is being utilized.

4.2 Choosing the RF Matching Topology

The second step of the matching design procedure is to choose the appropriate RF matching topology.

In addition to creating an optimum termination impedance on the IC side, the matching solution must exhibit sufficiently robust harmonic
filtering characteristics to comply with emissions standards. There are many different types of RF matching topologies. Separate match­ing and harmonic filtering sections can be utilized, or they can be combined in one circuit. To minimize the number of elements, all
matches presented here are of the combined type, with low-pass circuits employed for their inherent harmonic suppression characteris­tics.

Four 2.4 GHz matching topologies for EFR32xG21 are presented here:

• 4-element discrete LC match for the 0 dBm PA, i.e., for power levels equal or below 0 dBm

• 4-element combined discrete LC match for both 0 and +10 dBm PA, i.e., for power levels equal or below +10 dBm

• 3-element discrete LC match for the +10 dBm PA, i.e., for power levels equal or below +10 dBm, but not suitable to operate with the
0 dBm PA (i.e., equal or below 0 dBm the required PA to be used is still the +10 dBm PA which has less power efficiency at that
lower power range)

• 5-element discrete LC match for the +20dBm PA, i.e., for power levels equal or below +20 dBm (not suitable to operate with the 0
dBm PA)

For EFR32xG22, a single 4-element discrete LC match is provided that is optimized for both 0 and +6 dBm PA, i.e., for any power level
available with this part.

4.3 Initial Design with Ideal, Loss-Free Elements

After choosing the appropriate topology for the application based on the TX power level requirements, the third step of the matching
design procedure is to generate a lumped element schematic of the match with ideal loss-free elements and without PCB parasitics.

The matching circuit should show an input impedance of Zload_opt at the RF IO port of the chip while it is terminated by 50 Ω load at its
output (ANT port). The impedance procedure is shown in the next sections, where, for simplification, the matching design is started
from a termination impedance (ZL) which is the complex conjugate of the Zload_opt impedance. The reason is that the matching net­work will show the required Zload_opt impedance at its RF port only if it is perfectly matched there to a termination impedance which is
the complex conjugate of the Zload_opt impedance.

The matching design process starts with a simplified case in which all losses and parasitics are eliminated. Here, parasitic-free ideal
capacitors and inductors are used, and there are no PCB losses or parasitics. The real-world case can be derived later from this ideal
design by means of incremental tuning and optimization.

silabs.com | Building a more connected world. Rev. 0.6 | 8