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EFM8 Universal Bee Family
EFM8UB3 Reference Manual
The EFM8UB3, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set in
small packages.
These devices offer high value by integrating an innovative energy-smart USB peripheral
interface, charger detect circuit, 8 kV ESD protection, and enhanced high speed communication interfaces into small packages, making them ideal for space-constrained USB
applications. With an efficient 8051 core and precision analog, the EFM8UB3 family is
also optimal for embedded applications.
EFM8UB3 applications include the following:
• USB I/O controls
• Docking stations/USB hubs
• Dongles
Core / Memory Clock Management
CIP-51 8051 Core
(48 MHz)
Flash Memory
40 KB
RAM Memory
3328 bytes
• Consumer electronics
• USB Type-C converters
• USB Type-C billboard/alternate mode
External CMOS
Oscillator
Debug Interface
with C2
Low Frequency
RC Oscillator
High Frequency
48 MHz RC
Oscillator
High Frequency
24.5 MHz RC
Oscillator
KEY FEATURES
• Pipelined 8-bit C8051 core with 48 MHz
maximum operating frequency
• Up to 17 multifunction I/O pins
• Low Energy USB with full- and low-speed
support saves up to 90% of the USB
energy
• USB charger detect circuit (USB-BCS 1.2
compliant)
• One 12-bit ADC and two analog
comparators with internal voltage DAC as
reference input
• Six 16-bit timers
• UART and SMBus master/slave
• Priority crossbar for flexible pin mapping
Energy Management
Internal LDO
Regulator
Brown-Out
Detector
Power-On Reset
5 V-to 3.3 V LDO
Regulator
8-bit SFR bus
Serial Interfaces Timers and Triggers Analog Interfaces
UART
SMBus
Lowest power mode with peripheral operational:
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USB
SPI
IdleNormal ShutdownSuspend Snooze
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
Timers
0/1/2
Watchdog
Timer
4 x Configurable Logic Units
PCA/PWM
Timer 3/4/5
ADC
Internal Voltage
Reference
Charger Det
Comparator 1
Comparator 0
SecurityI/O Ports
16-bit CRC
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Table of Contents
1. System Overview .............................13
1.1 Introduction ...............................13
1.2 Power .................................14
1.3 I/O ..................................14
1.4 Clocking ................................15
1.5 Counters/Timers and PWM ..........................15
1.6 Communications and Other Digital Peripherals ...................17
1.7 Analog.................................19
1.8 Reset Sources ..............................20
1.9 Debugging ...............................20
1.10 Bootloader ...............................21
2. Memory ................................23
2.1 Memory Organization............................23
2.2 Program Memory .............................23
2.3 Data Memory ..............................23
2.4 Memory Map ..............................25
2.5 XRAM Control Registers...........................27
2.5.1 EMI0CN: External Memory Interface Control ..................27
3. Special Function Registers .........................28
3.1 Special Function Register Access .......................28
3.2 Special Function Register Memory Map .....................30
3.3 SFR Access Control Registers.........................37
3.3.1 SFRPAGE: SFR Page ..........................37
3.3.2 SFRPGCN: SFR Page Control .......................38
3.3.3 SFRSTACK: SFR Page Stack .......................38
4. Flash Memory ..............................39
4.1 Introduction ...............................39
4.2 Features ................................39
4.3 Functional Description ...........................40
4.3.1 Security Options ............................40
4.3.2 Programming the Flash Memory ......................41
4.3.3 Flash Write and Erase Precautions......................42
4.4 Flash Control Registers ...........................43
4.4.1 PSCTL: Program Store Control .......................43
4.4.2 FLKEY: Flash Lock and Key ........................44
5. Device Identification ...........................45
5.1 Device Identification ............................45
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5.2 Unique Identifier .............................45
5.3 Device Identification Registers.........................45
5.3.1 DEVICEID: Device Identification.......................45
5.3.2 DERIVID: Derivative Identification ......................46
5.3.3 REVID: Revision Identifcation .......................46
6. Interrupts ................................ 47
6.1 Introduction ...............................47
6.2 Interrupt Sources and Vectors .........................47
6.2.1 Interrupt Priorities ...........................47
6.2.2 Interrupt Latency ............................48
6.2.3 Interrupt Summary ...........................49
6.3 Interrupt Control Registers ..........................51
6.3.1 IE: Interrupt Enable ...........................51
6.3.2 IP: Interrupt Priority ...........................53
6.3.3 IPH: Interrupt Priority High ........................54
6.3.4 EIE1: Extended Interrupt Enable 1 ......................55
6.3.5 EIP1: Extended Interrupt Priority 1 Low ....................57
6.3.6 EIP1H: Extended Interrupt Priority 1 High ...................58
6.3.7 EIE2: Extended Interrupt Enable 2 ......................59
6.3.8 EIP2: Extended Interrupt Priority 2 ......................60
6.3.9 EIP2H: Extended Interrupt Priority 2 High ...................61
7. Power Management and Internal Regulators ..................62
7.1 Introduction ...............................62
7.2 Features ................................63
7.3 Idle Mode................................64
7.4 Stop Mode ...............................64
7.5 Suspend Mode ..............................64
7.6 Snooze Mode ..............................65
7.7 Shutdown Mode .............................65
7.8 5V-to-3.3V Regulator ............................65
7.9 Power Management Control Registers ......................66
7.9.1 PCON0: Power Control..........................66
7.9.2 PCON1: Power Control 1 .........................67
7.9.3 PSTAT0: Power Status..........................68
7.9.4 REG0CN: Voltage Regulator 0 Control ....................69
7.9.5 REG1CN: Voltage Regulator 1 Control ....................70
8. Clocking and Oscillators ..........................71
8.1 Introduction ...............................71
8.2 Features ................................71
8.3 Functional Description ...........................71
8.3.1 Clock Selection ............................71
8.3.2 HFOSC0 24.5 MHz Internal Oscillator .....................72
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8.3.3 HFOSC1 48 MHz Internal Oscillator .....................72
8.3.4 LFOSC0 80 kHz Internal Oscillator ......................72
8.3.5 External Clock.............................72
8.4 Clocking and Oscillator Control Registers .....................73
8.4.1 CLKSEL: Clock Select ..........................73
8.4.2 HFO0CAL: High Frequency Oscillator 0 Calibration ................74
8.4.3 HFO1CAL: High Frequency Oscillator 1 Calibration ................74
8.4.4 HFOCN: High Frequency Oscillator Control ...................75
8.4.5 LFO0CN: Low Frequency Oscillator Control...................76
9. Reset Sources and Power Supply Monitor ...................77
9.1 Introduction ...............................77
9.2 Features ................................77
9.3 Functional Description ...........................78
9.3.1 Device Reset .............................78
9.3.2 Power-On Reset ............................79
9.3.3 Supply Monitor Reset ..........................80
9.3.4 External Reset ............................80
9.3.5 Missing Clock Detector Reset .......................80
9.3.6 Comparator (CMP0) Reset ........................81
9.3.7 Watchdog Timer Reset ..........................81
9.3.8 Flash Error Reset ...........................81
9.3.9 Software Reset ............................81
9.3.10 USB Reset .............................81
9.4 Reset Sources and Supply Monitor Control Registers .................82
9.4.1 RSTSRC: Reset Source .........................82
9.4.2 VDM0CN: Supply Monitor Control ......................83
10. CIP-51 Microcontroller Core ........................84
10.1 Introduction ..............................84
10.2 Features ...............................85
10.3 Functional Description ...........................85
10.3.1 Programming and Debugging Support ....................85
10.3.2 Prefetch Engine............................85
10.3.3 Instruction Set ............................86
10.4 CPU Core Registers ...........................90
10.4.1 DPL: Data Pointer Low .........................90
10.4.2 DPH: Data Pointer High .........................90
10.4.3 SP: Stack Pointer ...........................90
10.4.4 ACC: Accumulator ...........................91
10.4.5 B: B Register.............................91
10.4.6 PSW: Program Status Word .......................92
10.4.7 PFE0CN: Prefetch Engine Control .....................93
11. Port I/O, Crossbar, External Interrupts, and Port Match ..............94
11.1 Introduction ..............................94
11.2 Features ...............................94
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11.3 Functional Description ...........................95
11.3.1 Port I/O Modes of Operation .......................95
11.3.2 Analog and Digital Functions .......................96
11.3.3 Priority Crossbar Decoder ........................98
11.3.4 INT0 and INT1 ...........................100
11.3.5 Port Match ............................100
11.3.6 Direct Port I/O Access (Read/Write) ....................100
11.4 Port I/O Control Registers .........................101
11.4.1 XBR0: Port I/O Crossbar 0 .......................101
11.4.2 XBR1: Port I/O Crossbar 1 .......................103
11.4.3 XBR2: Port I/O Crossbar 2 .......................104
11.4.4 PRTDRV: Port Drive Strength ......................105
11.4.5 P0MASK: Port 0 Mask ........................106
11.4.6 P0MAT: Port 0 Match .........................107
11.4.7 P0: Port 0 Pin Latch .........................108
11.4.8 P0MDIN: Port 0 Input Mode .......................109
11.4.9 P0MDOUT: Port 0 Output Mode .....................110
11.4.10 P0SKIP: Port 0 Skip .........................111
11.4.11 P1MASK: Port 1 Mask ........................112
11.4.12 P1MAT: Port 1 Match ........................113
11.4.13 P1: Port 1 Pin Latch .........................114
11.4.14 P1MDIN: Port 1 Input Mode ......................115
11.4.15 P1MDOUT: Port 1 Output Mode .....................116
11.4.16 P1SKIP: Port 1 Skip .........................117
11.4.17 P2MASK: Port 2 Mask ........................118
11.4.18 P2MAT: Port 2 Match ........................118
11.4.19 P2: Port 2 Pin Latch .........................119
11.4.20 P2MDIN: Port 2 Input Mode ......................119
11.4.21 P2MDOUT: Port 2 Output Mode .....................120
11.5 INT0 and INT1 Control Registers ......................121
11.5.1 IT01CF: INT0/INT1 Configuration .....................121
12. Analog-to-Digital Converter (ADC0) .....................123
12.1 Introduction .............................123
12.2 Features ..............................124
12.3 Functional Description ..........................124
12.3.1 Clocking .............................124
12.3.2 Voltage Reference Options .......................124
12.3.3 Input Selection ...........................125
12.3.4 Gain Setting ............................126
12.3.5 Initiating Conversions .........................126
12.3.6 Input Tracking ...........................126
12.3.7 Burst Mode ............................129
12.3.8 8-Bit Mode ............................129
12.3.9 12-Bit Mode ............................130
12.3.10 Output Formatting .........................131
12.3.11 Power Considerations ........................132
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12.3.12 Window Comparator .........................134
12.3.13 Temperature Sensor .........................136
12.4 ADC0 Control Registers .........................137
12.4.1 ADC0CN0: ADC0 Control 0 .......................137
12.4.2 ADC0CN1: ADC0 Control 1 .......................138
12.4.3 ADC0CF: ADC0 Configuration ......................139
12.4.4 ADC0AC: ADC0 Accumulator Configuration .................140
12.4.5 ADC0PWR: ADC0 Power Control .....................142
12.4.6 ADC0TK: ADC0 Burst Mode Track Time ..................143
12.4.7 ADC0H: ADC0 Data Word High Byte ...................143
12.4.8 ADC0L: ADC0 Data Word Low Byte ....................144
12.4.9 ADC0GTH: ADC0 Greater-Than High Byte .................144
12.4.10 ADC0GTL: ADC0 Greater-Than Low Byte .................144
12.4.11 ADC0LTH: ADC0 Less-Than High Byte ..................145
12.4.12 ADC0LTL: ADC0 Less-Than Low Byte ..................145
12.4.13 ADC0MX: ADC0 Multiplexer Selection ...................145
12.4.14 REF0CN: Voltage Reference Control ...................146
13. Comparators (CMP0 and CMP1) .......................147
13.1 Introduction .............................147
13.2 Features ..............................147
13.3 Functional Description ..........................148
13.3.1 Response Time and Supply Current ....................148
13.3.2 Hysteresis ............................148
13.3.3 Input Selection ...........................148
13.3.4 Output Routing ...........................153
13.4 CMP0 Control Registers .........................155
13.4.1 CMP0CN0: Comparator 0 Control 0 ....................155
13.4.2 CMP0MD: Comparator 0 Mode .....................157
13.4.3 CMP0MX: Comparator 0 Multiplexer Selection ................158
13.4.4 CMP0CN1: Comparator 0 Control 1 ....................159
13.5 CMP1 Control Registers .........................160
13.5.1 CMP1CN0: Comparator 1 Control 0 ....................160
13.5.2 CMP1MD: Comparator 1 Mode .....................162
13.5.3 CMP1MX: Comparator 1 Multiplexer Selection ................163
13.5.4 CMP1CN1: Comparator 1 Control 1 ....................164
14. Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) ...............165
14.1 Introduction .............................165
14.2 Features ..............................166
14.3 Functional Description ..........................167
14.3.1 Configuration Sequence ........................167
14.3.2 Input Multiplexer Selection .......................167
14.3.3 Output Configuration .........................169
14.3.4 LUT Configuration ..........................169
14.4 Configurable Logic Control Registers .....................170
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14.4.1 CLEN0: Configurable Logic Enable 0 ...................170
14.4.2 CLIE0: Configurable Logic Interrupt Enable 0 .................171
14.4.3 CLIF0: Configurable Logic Interrupt Flag 0 ..................172
14.4.4 CLOUT0: Configurable Logic Output 0 ...................173
14.4.5 CLU0MX: Configurable Logic Unit 0 Multiplexer ................173
14.4.6 CLU0FN: Configurable Logic Unit 0 Function Select ..............174
14.4.7 CLU0CF: Configurable Logic Unit 0 Configuration ...............175
14.4.8 CLU1MX: Configurable Logic Unit 1 Multiplexer ................176
14.4.9 CLU1FN: Configurable Logic Unit 1 Function Select ..............176
14.4.10 CLU1CF: Configurable Logic Unit 1 Configuration ...............177
14.4.11 CLU2MX: Configurable Logic Unit 2 Multiplexer ...............178
14.4.12 CLU2FN: Configurable Logic Unit 2 Function Select ..............178
14.4.13 CLU2CF: Configurable Logic Unit 2 Configuration ...............179
14.4.14 CLU3MX: Configurable Logic Unit 3 Multiplexer ...............180
14.4.15 CLU3FN: Configurable Logic Unit 3 Function Select ..............180
14.4.16 CLU3CF: Configurable Logic Unit 3 Configuration ...............181
15. Cyclic Redundancy Check (CRC0) ......................182
15.1 Introduction .............................182
15.2 Features ..............................182
15.3 Functional Description ..........................183
15.3.1 16-bit CRC Algorithm .........................183
15.3.2 Using the CRC on a Data Stream .....................184
15.3.3 Using the CRC to Check Code Memory ...................184
15.3.4 Bit Reversal ............................184
15.4 CRC0 Control Registers .........................185
15.4.1 CRC0CN0: CRC0 Control 0.......................185
15.4.2 CRC0IN: CRC0 Data Input .......................185
15.4.3 CRC0DAT: CRC0 Data Output......................186
15.4.4 CRC0ST: CRC0 Automatic Flash Sector Start ................186
15.4.5 CRC0CNT: CRC0 Automatic Flash Sector Count ...............186
15.4.6 CRC0FLIP: CRC0 Bit Flip .......................187
15.4.7 CRC0CN1: CRC0 Control 1.......................187
16. Programmable Counter Array (PCA0) .....................188
16.1 Introduction .............................188
16.2 Features ..............................189
16.3 Functional Description ..........................189
16.3.1 Counter / Timer ...........................189
16.3.2 Interrupt Sources ..........................190
16.3.3 Capture/Compare Modules .......................190
16.3.4 Edge-Triggered Capture Mode ......................191
16.3.5 Software Timer (Compare) Mode .....................192
16.3.6 High-Speed Output Mode .......................193
16.3.7 Frequency Output Mode ........................194
16.3.8 PWM Waveform Generation ......................194
16.4 PCA0 Control Registers .........................201
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16.4.1 PCA0CN0: PCA Control ........................201
16.4.2 PCA0MD: PCA Mode .........................202
16.4.3 PCA0PWM: PCA PWM Configuration ...................203
16.4.4 PCA0CLR: PCA Comparator Clear Control .................204
16.4.5 PCA0L: PCA Counter/Timer Low Byte ...................204
16.4.6 PCA0H: PCA Counter/Timer High Byte ...................205
16.4.7 PCA0POL: PCA Output Polarity .....................205
16.4.8 PCA0CENT: PCA Center Alignment Enable .................206
16.4.9 PCA0CPM0: PCA Channel 0 Capture/Compare Mode ..............207
16.4.10 PCA0CPL0: PCA Channel 0 Capture Module Low Byte .............208
16.4.11 PCA0CPH0: PCA Channel 0 Capture Module High Byte ............208
16.4.12 PCA0CPM1: PCA Channel 1 Capture/Compare Mode .............209
16.4.13 PCA0CPL1: PCA Channel 1 Capture Module Low Byte .............210
16.4.14 PCA0CPH1: PCA Channel 1 Capture Module High Byte ............210
16.4.15 PCA0CPM2: PCA Channel 2 Capture/Compare Mode .............211
16.4.16 PCA0CPL2: PCA Channel 2 Capture Module Low Byte .............212
16.4.17 PCA0CPH2: PCA Channel 2 Capture Module High Byte ............212
17. Serial Peripheral Interface (SPI0) ......................213
17.1 Introduction .............................213
17.2 Features ..............................213
17.3 Functional Description ..........................214
17.3.1 Signals ..............................214
17.3.2 Master Mode Operation ........................215
17.3.3 Slave Mode Operation ........................216
17.3.4 Clock Phase and Polarity .......................217
17.3.5 Basic Data Transfer .........................218
17.3.6 Using the SPI FIFOs .........................218
17.3.7 SPI Timing Diagrams .........................221
17.4 SPI0 Control Registers ..........................224
17.4.1 SPI0CFG: SPI0 Configuration ......................224
17.4.2 SPI0CN0: SPI0 Control ........................226
17.4.3 SPI0CKR: SPI0 Clock Rate .......................227
17.4.4 SPI0DAT: SPI0 Data .........................227
17.4.5 SPI0FCN0: SPI0 FIFO Control 0 .....................228
17.4.6 SPI0FCN1: SPI0 FIFO Control 1 .....................229
17.4.7 SPI0FCT: SPI0 FIFO Count.......................230
17.4.8 SPI0PCF: SPI0 Pin Configuration .....................231
18. System Management Bus / I2C (SMB0) ....................232
18.1 Introduction .............................232
18.2 Features ..............................232
18.3 Functional Description ..........................232
18.3.1 Supporting Documents ........................232
18.3.2 SMBus Protocol ...........................233
18.3.3 Configuring the SMBus Module .....................235
18.3.4 Operational Modes ..........................240
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18.4 SMB0 Control Registers .........................248
18.4.1 SMB0CF: SMBus 0 Configuration .....................248
18.4.2 SMB0TC: SMBus 0 Timing and Pin Control .................249
18.4.3 SMB0CN0: SMBus 0 Control ......................250
18.4.4 SMB0ADR: SMBus 0 Slave Address ....................251
18.4.5 SMB0ADM: SMBus 0 Slave Address Mask .................252
18.4.6 SMB0DAT: SMBus 0 Data .......................252
18.4.7 SMB0FCN0: SMBus 0 FIFO Control 0 ...................253
18.4.8 SMB0FCN1: SMBus 0 FIFO Control 1 ...................254
18.4.9 SMB0RXLN: SMBus 0 Receive Length Counter ................255
18.4.10 SMB0FCT: SMBus 0 FIFO Count ....................255
19. Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) ............256
19.1 Introduction .............................256
19.2 Features ..............................256
19.3 Functional Description ..........................257
19.3.1 System Connections .........................257
19.3.2 Timer 0 and Timer 1 .........................258
19.3.3 Timer 2, Timer 3, Timer 4, and Timer 5 ...................262
19.4 Timer 0, 1, 2, 3, 4, and 5 Control Registers ...................268
19.4.1 CKCON0: Clock Control 0 .......................268
19.4.2 CKCON1: Clock Control 1 .......................270
19.4.3 TCON: Timer 0/1 Control .......................271
19.4.4 TMOD: Timer 0/1 Mode ........................272
19.4.5 TL0: Timer 0 Low Byte ........................273
19.4.6 TL1: Timer 1 Low Byte ........................273
19.4.7 TH0: Timer 0 High Byte ........................274
19.4.8 TH1: Timer 1 High Byte ........................274
19.4.9 TMR2CN0: Timer 2 Control 0 ......................275
19.4.10 TMR2RLL: Timer 2 Reload Low Byte ...................276
19.4.11 TMR2RLH: Timer 2 Reload High Byte ...................276
19.4.12 TMR2L: Timer 2 Low Byte .......................276
19.4.13 TMR2H: Timer 2 High Byte ......................277
19.4.14 TMR2CN1: Timer 2 Control 1 ......................278
19.4.15 TMR3CN0: Timer 3 Control 0 ......................279
19.4.16 TMR3RLL: Timer 3 Reload Low Byte ...................280
19.4.17 TMR3RLH: Timer 3 Reload High Byte ...................280
19.4.18 TMR3L: Timer 3 Low Byte .......................280
19.4.19 TMR3H: Timer 3 High Byte ......................281
19.4.20 TMR3CN1: Timer 3 Control 1 ......................282
19.4.21 TMR4CN0: Timer 4 Control 0 ......................284
19.4.22 TMR4RLL: Timer 4 Reload Low Byte ...................285
19.4.23 TMR4RLH: Timer 4 Reload High Byte ...................285
19.4.24 TMR4L: Timer 4 Low Byte .......................285
19.4.25 TMR4H: Timer 4 High Byte ......................286
19.4.26 TMR4CN1: Timer 4 Control 1 ......................287
19.4.27 TMR5RLL: Timer 5 Reload Low Byte ...................288
19.4.28 TMR5RLH: Timer 5 Reload High Byte ...................288
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19.4.29 TMR5L: Timer 5 Low Byte .......................288
19.4.30 TMR5H: Timer 5 High Byte ......................289
19.4.31 TMR5CN0: Timer 5 Control 0 ......................290
19.4.32 TMR5CN1: Timer 5 Control 1 ......................291
20. Universal Asynchronous Receiver/Transmitter 1 (UART1) .............292
20.1 Introduction .............................292
20.2 Features ..............................292
20.3 Functional Description ..........................293
20.3.1 Baud Rate Generation ........................293
20.3.2 Data Format ............................293
20.3.3 Flow Control ............................294
20.3.4 Basic Data Transfer .........................294
20.3.5 Data Transfer With FIFO ........................294
20.3.6 Multiprocessor Communications .....................297
20.3.7 LIN Break and Sync Detect .......................297
20.3.8 Autobaud Detection .........................297
20.3.9 Routing RX Through Configurable Logic ..................298
20.4 UART1 Control Registers .........................299
20.4.1 SCON1: UART1 Serial Port Control ....................299
20.4.2 SMOD1: UART1 Mode ........................301
20.4.3 SBUF1: UART1 Serial Port Data Buffer ...................302
20.4.4 SBCON1: UART1 Baud Rate Generator Control ................303
20.4.5 SBRLH1: UART1 Baud Rate Generator High Byte ...............303
20.4.6 SBRLL1: UART1 Baud Rate Generator Low Byte ...............304
20.4.7 UART1FCN0: UART1 FIFO Control 0 ...................305
20.4.8 UART1FCN1: UART1 FIFO Control 1 ...................307
20.4.9 UART1FCT: UART1 FIFO Count .....................308
20.4.10 UART1LIN: UART1 LIN Configuration ...................309
20.4.11 UART1PCF: UART1 Configuration ....................310
21. Universal Serial Bus (USB0) ........................311
21.1 Introduction .............................311
21.2 Features ..............................311
21.3 Functional Description ..........................312
21.3.1 Endpoint Addressing .........................312
21.3.2 Transceiver Control .........................312
21.3.3 Clock Configuration .........................312
21.3.4 VBUS Control ...........................312
21.3.5 Register Access...........................313
21.3.6 FIFO Management ..........................315
21.3.7 Function Addressing .........................316
21.3.8 Function Configuration and Control ....................317
21.3.9 Interrupts .............................317
21.3.10 Serial Interface Engine ........................317
21.3.11 Endpoint 0 ............................318
21.3.12 Endpoints 1, 2, and 3 ........................319
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21.3.13 Low Energy Mode .........................321
21.3.14 Charger Detect Function .......................321
21.4 USB0 Control Registers .........................326
21.4.1 USB0XCN: USB0 Transceiver Control ...................326
21.4.2 USB0ADR: USB0 Indirect Address ....................327
21.4.3 USB0DAT: USB0 Data ........................328
21.4.4 INDEX: USB0 Endpoint Index ......................328
21.4.5 CLKREC: USB0 Clock Recovery Control ..................329
21.4.6 FIFO0: USB0 Endpoint 0 FIFO Access ...................330
21.4.7 FIFO1: USB0 Endpoint 1 FIFO Access ...................330
21.4.8 FIFO2: USB0 Endpoint 2 FIFO Access ...................330
21.4.9 FIFO3: USB0 Endpoint 3 FIFO Access ...................331
21.4.10 FADDR: USB0 Function Address ....................331
21.4.11 POWER: USB0 Power ........................332
21.4.12 FRAMEL: USB0 Frame Number Low ...................333
21.4.13 FRAMEH: USB0 Frame Number High ...................333
21.4.14 IN1INT: USB0 IN Endpoint Interrupt ...................334
21.4.15 OUT1INT: USB0 OUT Endpoint Interrupt ..................335
21.4.16 CMINT: USB0 Common Interrupt ....................336
21.4.17 IN1IE: USB0 IN Endpoint Interrupt Enable .................337
21.4.18 OUT1IE: USB0 OUT Endpoint Interrupt Enable ................338
21.4.19 CMIE: USB0 Common Interrupt Enable ..................339
21.4.20 E0CSR: USB0 Endpoint0 Control ....................340
21.4.21 E0CNT: USB0 Endpoint0 Data Count ...................341
21.4.22 EENABLE: USB0 Endpoint Enable ....................342
21.4.23 EINCSRL: USB0 IN Endpoint Control Low .................343
21.4.24 EINCSRH: USB0 IN Endpoint Control High .................344
21.4.25 EOUTCSRL: USB0 OUT Endpoint Control Low................345
21.4.26 EOUTCSRH: USB0 OUT Endpoint Control High ...............346
21.4.27 EOUTCNTL: USB0 OUT Endpoint Count Low ................346
21.4.28 EOUTCNTH: USB0 OUT Endpoint Count High ................347
21.4.29 USB0CF: USB0 Configuration .....................348
21.4.30 USB0AEC: USB0 Advanced Energy Control.................350
21.4.31 USB0CDCF: USB0 Charger Detect Configuration ...............351
21.4.32 USB0CDCN: USB0 Charger Detect Control .................352
21.4.33 USB0CDSTA: USB0 Charger Detect Status .................353
22. Watchdog Timer (WDT0)..........................355
22.1 Introduction .............................355
22.2 Features ..............................355
22.3 Using the Watchdog Timer ........................355
22.4 WDT0 Control Registers .........................357
22.4.1 WDTCN: Watchdog Timer Control ....................357
23. C2 Debug and Programming Interface ....................358
23.1 Introduction .............................358
23.2 Features ..............................358
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23.3 Pin Sharing .............................358
23.4 C2 Interface Registers ..........................359
23.4.1 C2ADD: C2 Address .........................359
23.4.2 C2DEVID: C2 Device ID ........................359
23.4.3 C2REVID: C2 Revision ID .......................359
23.4.4 C2FPCTL: C2 Flash Programming Control..................360
23.4.5 C2FPDAT: C2 Flash Programming Data ..................360
24. Revision History.............................361
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1. System Overview
1.1 Introduction
EFM8UB3 Reference Manual
System Overview
C2CK/RSTb
VDD
VREGIN
GND
D+
VBUS
CIP-51 8051 Controller
C2D
Programming
Power-On
Independent
Watchdog
Timer
Debug /
Hardware
Reset
Reset
Supply
Monitor
Core
40 KB ISP Flash
Program Memory
256 Byte SRAM
2048 Byte XRAM
SYSCLK
System Clock
Configuration
EXTCLK
Voltage
Regulators
Power
Net
Low Freq.
Oscillator
CMOS Oscillator
Input
48 MHz 1.5%
Oscillator
Clock
Recovery
24.5 MHz 2%
Oscillator
SFR
Bus
USB Peripheral
D-
Full / Low
Speed
Transceiver
1 KB RAM Low Power
Controller
Charge
Detection
Port I/O Configuration
Digital Peripherals
UART1
Timers 0,
1, 2, 3, 4, 5
3-ch PCA
I2C /
SMBus
SPI
CRC
Config.
Logic
Units (4)
Analog Peripherals
Internal
Reference
VREFVDD
12/10 bit
ADC
2 Comparators
Priority
Crossbar
Decoder
Crossbar
Control
AMUX
Sensor
+
+
-
-
VDD
Temp
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
P0.n
P1.n
P2.n
Figure 1.1. Detailed EFM8UB3 Block Diagram
This section describes the EFM8UB3 family at a high level.
For more information on the device packages and pinout, electrical specifications, and typical connection diagrams, see the EFM8UB3
Data Sheet. For more information on each module including register definitions, see the EFM8UB3 Reference Manual. For more information on any errata, see the EFM8UB3 Errata.
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System Overview
1.2 Power
Control over the device power consumption can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their
clocks gated off and draw little power when they are not in use.
Table 1.1. Power Modes
Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational — —
Idle • Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Suspend • Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in normal bias mode for fast wake
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
Stop • All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO on
• Pins retain state
• Exit on any reset source
Snooze • Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in low bias current mode for energy savings
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
Set IDLE bit in PCON0 Any interrupt
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• Port Match Event
• Comparator 0 Falling
Edge
• CLUn Interrupt-Enabled
Event
1. Clear STOPCF bit in
Any reset source
REG0CN
2. Set STOP bit in
PCON0
1. Switch SYSCLK to
HFOSC0
2. Set SNOOZE bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• Port Match Event
• Comparator 0 Falling
Edge
• CLUn Interrupt-Enabled
Event
Shutdown • All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO off to save energy
• Pins retain state
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
• RSTb pin reset
• Power-on reset
• Exit on pin or power-on reset
1.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.6 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0.
The port control block offers the following features:
• Up to 17 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each port.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 17 direct-pin interrupt sources with shared interrupt vector (Port Match).
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System Overview
1.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
The clock control system offers the following features:
• Provides clock to core and peripherals.
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
• 48 MHz internal oscillator (HFOSC1), accurate to ±1.5% over supply and temperature corners.
• 80 kHz low-frequency oscillator (LFOSC0).
• External CMOS clock input (EXTCLK).
• Clock divider with eight settings for flexible clock scaling:
• Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
• HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility.
1.5 Counters/Timers and PWM
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
• 16-bit time base
• Programmable clock divisor and clock source selection
• Up to three independently-configurable channels
• 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)
• Output polarity control
• Frequency output mode
• Capture on rising, falling or any edge
• Compare function for arbitrary waveform generation
• Software timer (internal compare) mode
• Can accept hardware “kill” signal from comparator 0 or comparator 1
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System Overview
Timers (Timer 0, Timer 1, Timer 2, Timer 3, Timer 4, and Timer 5)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2, Timer 3, Timer 4, and Timer 5 are 16-bit timers including the following features:
• Clock sources for all timers include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8
• LFOSC0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend/snooze power modes
• Timer 4 is a low-power wake source, and can be chained together with Timer 3
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• External pin capture
• LFOSC0 capture
• Comparator 0 capture
• USB Start-of-Frame (SOF) capture
• Configurable Logic output capture
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.
The state of the RST pin is unaffected by this reset.
The Watchdog Timer has the following features:
• Programmable timeout interval
• Runs from the low-frequency oscillator
• Lock-out feature to prevent any modification until a system reset
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System Overview
1.6 Communications and Other Digital Peripherals
Universal Serial Bus (USB0)
The USB0 peripheral provides a full-speed USB 2.0 compliant device controller and PHY with additional Low Energy USB features. The
device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock recovery mechanism for crystal-free operation. No external components are required. The USB function controller (USB0) consists of a
Serial Interface Engine (SIE), USB transceiver (including matching resistors and configurable pull-up resistors), and 1 KB FIFO block.
The Low Energy Mode ensures the current consumption is optimized and enables USB communication on a strict power budget.
The USB0 module includes the following features:
• Full and Low Speed functionality.
• Implements 4 bidirectional endpoints.
• Low Energy Mode to reduce active supply current based on bus bandwidth.
• USB 2.0 compliant USB peripheral support (no host capability).
• Direct module access to 1 KB of RAM for FIFO memory.
• Clock recovery to meet USB clocking requirements with no external components.
• Charger detection circuitry with automatic detection of SDP, CDP, and DCP interfaces.
• D+ and D- can be routed to ADC input to support ACM and proprietary charger architectures.
Universal Asynchronous Receiver/Transmitter (UART1)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a
16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1
to receive multiple bytes before data is lost and an overflow occurs.
UART1 provides the following features:
• Asynchronous transmissions and receptions.
• Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).
• 5, 6, 7, 8, or 9 bit data.
• Automatic start and stop generation.
• Automatic parity generation and checking.
• Four byte FIFO on transmit and receive.
• Auto-baud detection.
• LIN break and sync field detection.
• CTS / RTS hardware flow control.
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
• Supports 3- or 4-wire master or slave modes.
• Supports external clock frequencies up to 12 Mbps in master or slave mode.
• Support for all clock phase and polarity modes.
• 8-bit programmable clock rate (master).
• Programmable receive timeout (slave).
• Two byte FIFO on transmit and receive.
• Can operate in suspend or snooze modes and wake the CPU on reception of a byte.
• Support for multiple masters on the same data lines.
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System Overview
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps), Fast (400 kbps), and Fast Mode Plus (1 Mbps) transfer speeds
• Support for master, slave, and multi-master modes
• Hardware synchronization and arbitration for multi-master mode
• Clock low extending (clock stretching) to interface with faster masters
• Hardware support for 7-bit slave and general call address recognition
• Firmware support for 10-bit slave address decoding
• Ability to inhibit all slave states
• Programmable data setup/hold times
• Transmit and receive FIFOs (two-byte) to help increase throughput in faster applications
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
• Support for CCITT-16 polynomial
• Byte-level bit reversal
• Automatic CRC of flash contents on one or more 256-byte blocks
• Initial seed selection of 0x0000 or 0xFFFF
Configurable Logic Units (CLU0, CLU1, CLU2, and CLU3)
The Configurable Logic block consists of multiple Configurable Logic Units (CLUs). CLUs are flexible logic functions which may be used
for a variety of digital functions, such as replacing system glue logic, aiding in the generation of special waveforms, or synchronizing
system event triggers.
• Four configurable logic units (CLUs), with direct-pin and internal logic connections
• Each unit supports 256 different combinatorial logic functions (AND, OR, XOR, muxing, etc.) and includes a clocked flip-flop for synchronous operations
• Units may be operated synchronously or asynchronously
• May be cascaded together to perform more complicated logic functions
• Can operate in conjunction with serial peripherals such as UART and SPI or timing peripherals such as timers and PCA channels
• Can be used to synchronize and trigger multiple on-chip resources (ADC, Timers, etc.)
• Asynchronous output may be used to wake from low-power states
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System Overview
1.7 Analog
12-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a programmable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to
measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external
reference sources.
• Up to 16 external inputs.
• Single-ended 12-bit and 10-bit modes.
• Supports an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps samples per second in 10-bit mode.
• Operation in low power modes at lower conversion speeds.
• Asynchronous hardware conversion trigger, selectable between software, external I/O, internal timer sources, and configurable logic
(CLU) sources.
• Output data window comparator allows automatic range checking.
• Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time.
• Conversion complete and window compare interrupts supported.
• Flexible output data formatting.
• Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for external reference and signal ground.
• Integrated temperature sensor.
Low Current Comparators (CMP0, CMP1)
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator includes the following features:
• Up to 8 (CMP0) or 8 (CMP1) external positive inputs
• Up to 8 (CMP0) or 8 (CMP1) external negative inputs
• Additional input options:
• Internal connection to LDO output
• Direct connection to GND
• Direct connection to VDD
• Dedicated 6-bit reference DAC
• Synchronous and asynchronous outputs can be routed to pins via crossbar
• Programmable hysteresis between 0 and ±20 mV
• Programmable response time
• Interrupts generated on rising, falling, or both edges
• PWM output kill feature
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System Overview
1.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• USB reset
1.9 Debugging
The EFM8UB3 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
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System Overview
1.10 Bootloader
All devices come pre-programmed with a USB bootloader. This bootloader resides in the code security page and last pages of code
flash; it can be erased if it is not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the bootloader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The bootloader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
More information about the bootloader protocol and usage can be found in AN945: EFM8 Factory Bootloader User Guide. Application
notes can be found on the Silicon Labs website (www.silabs.com/8bit-appnotes) or within Simplicity Studio in the [Documentation]
area.
0xFFFF
0xFFC0
0xFBFF
0xFBFE
0xFBFD
0xFA00
0x9DFF
0x9A00
Read-Only
64 Bytes
Reserved
Lock Byte
Bootloader Signature Byte
Security Page
512 Bytes
Reserved
Bootloader
Bootloader Vector
Bootloader
Memory Lock
Read-Only
64 Bytes
128-bit UUID
0xFFFF
0xFFFE
0xFFD0
0xFFCF
0xFFC0
40 KB Flash
(79 x 512 Byte pages)
0x0000
Figure 1.2. Flash Memory Map with Bootloader—40 KB Devices
Table 1.2. Summary of Pins for Bootloader Communication
Bootloader Pins for Bootload Communication
USB VBUS
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Reset Vector
D+
D-
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EFM8UB3 Reference Manual
Table 1.3. Summary of Pins for Bootload Mode Entry
Device Package Pin for Bootload Mode Entry
QFN24 P2.0 / C2D
QSOP24 P2.0 / C2D
QFN20 P2.0 / C2D
System Overview
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EFM8UB3 Reference Manual
Memory
2. Memory
2.1 Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory
spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different
instruction types. Program memory consists of a non-volatile storage area that may be used for either program code or non-volatile
data storage. The data memory, consisting of "internal" and "external" data space, is implemented as RAM, and may be used only for
data storage. Program execution is not supported from the data memory space.
2.2 Program Memory
The CIP-51 core has a 64 KB program memory space. The product family implements some of this program memory space as in-system, re-programmable flash memory. Flash security is implemented by a user-programmable location in the flash block and provides
read, write, and erase protection. All addresses not specified in the device memory map are reserved and may not be used for code or
data storage.
MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the devices, the MOVX instruction is
normally used to read and write on-chip XRAM, but can be re-configured to write and erase on-chip flash memory space. MOVC instructions are always used to read flash memory, while MOVX write instructions are used to erase and write flash. This flash access
feature provides a mechanism for the product to update program code and use the program memory space for non-volatile data storage.
2.3 Data Memory
The RAM space on the chip includes both an "internal" RAM area which is accessed with MOV instructions, and an on-chip "external"
RAM area which is accessed using MOVX instructions. Total RAM varies, based on the specific device. The device memory map has
more details about the specific amount of RAM available in each area for the different device variants.
Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower
128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit
locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the
Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when
accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper
128 bytes of data memory.
General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each
bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in
the program status word (PSW) register, RS0 and RS1, select the active register bank. This allows fast context switching when entering
subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
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Memory
Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address
0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished
from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B
is the bit position within the byte. For example, the instruction:
Mov C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer
(SP) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which
is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a
location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes.
External RAM
On devices with more than 256 bytes of on-chip RAM, the additional RAM is mapped into the external data memory space (XRAM).
Addresses in XRAM area accessed using the external move (MOVX) instructions.
Note: The 16-bit MOVX write instruction is also used for writing and erasing the flash memory. More details may be found in the flash
memory section.
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2.4 Memory Map
EFM8UB3 Reference Manual
Memory
0xFFFF
0xFFC0
0xFBFF
0xFBFE
0xFBFD
0xFA00
0x9DFF
0x9A00
Read-Only
64 Bytes
Reserved
Lock Byte
Bootloader Signature Byte
Security Page
512 Bytes
Reserved
Bootloader
Bootloader Vector
Bootloader
Memory Lock
Read-Only
64 Bytes
128-bit UUID
0xFFFF
0xFFFE
0xFFD0
0xFFCF
0xFFC0
0x0000
40 KB Flash
(79 x 512 Byte pages)
Reset Vector
Figure 2.1. Flash Memory Map — 40 KB Devices
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0xFF
EFM8UB3 Reference Manual
Memory
On-Chip RAM
Accessed with MOV Instructions as Indicated
Upper 128 Bytes
RAM
(Indirect Access)
0x80
0x7F
Lower 128 Bytes RAM
(Direct or Indirect Access)
0x30
0x2F
0x20
0x1F
0x00
Figure 2.2. Direct / Indirect RAM Memory
General-Purpose Register Banks
Bit-Addressable
On-Chip XRAM
Accessed with MOVX Instructions
Special Function
Registers
(Direct Access)
0xFFFF
0x0C00
0x0BFF
0x0800
0x07FF
0x0000
Shadow XRAM
Duplicates 0x0000-0x0BFF
On 3 KB boundaries
USB FIFO XRAM
1024 Bytes
(USBCLK Domain)
XRAM
2048 Bytes
(SYSCLK Domain)
Figure 2.3. XRAM Memory
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2.5 XRAM Control Registers
2.5.1 EMI0CN: External Memory Interface Control
Bit 7 6 5 4 3 2 1 0
Name Reserved PGSEL
Access R RW
Reset 0x0 0x0
SFR Page = ALL; SFR Address: 0xE7
Bit Name Reset Access Description
7:4 Reserved Must write reset value.
3:0 PGSEL 0x0 RW XRAM Page Select.
The XRAM Page Select field provides the high byte of the 16-bit data memory address when using 8-bit MOVX commands,
effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
field determines which page of XRAM is accessed.
For example, if PGSEL = 0x01, addresses 0x0100 to 0x01FF will be accessed by 8-bit MOVX instructions.
Memory
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Special Function Registers
3. Special Function Registers
3.1 Special Function Register Access
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control
and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addi-
tion of new functionality while retaining compatibility with the MCS-51 ™ instruction set.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs
with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs
are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an
indeterminate effect and should be avoided.
SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory address space. The SFR
memory space has 256 pages. In this way, each memory location from 0x80 to 0xFF can access up to 256 SFRs. The EFM8UB3
devices utilize multiple SFR pages. All of the common 8051 SFRs are available on all pages. Certain SFRs are only available on a
subset of pages. SFR pages are selected using the SFRPAGE register. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
The SFRPAGE register only needs to be changed in the case that the SFR to be accessed does not exist on the currently-selected
page. See the SFR memory map for details on the locations of each SFR.
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Special Function Registers
Interrupts and the SFR Page Stack
When an interrupt occurs, the current SFRPAGE is pushed onto an SFR page stack to preserve the current context of SFRPAGE.
Upon execution of the RETI instruction, the SFRPAGE register is automatically restored to the SFR page that was in use prior to the
interrupt. The stack is five elements deep to accomodate interrupts of different priority levels pre-empting lower priority interrupts. Firmware can read any element of the SFR page stack by setting the SFRPGIDX field in the SFRPGCN register and reading the
SFRSTACK register.
Table 3.1. SFR Page Stack Access
SFRPGIDX Value SFRSTACK Contains
0 Value of the first/top byte of the stack
1 Value of the second byte of the stack
2 Value of the third byte of the stack
3 Value of the fourth byte of the stack
4 Value of the fifth/bottom byte of the stack
Notes:
1. The top of the stack is the current SFRPAGE setting, and can also be directly accessed via the SFRPAGE register.
SFRPGEN
Interrupt
Logic
SFR Page
SFRPAGE
SFRPGIDX
000
001
010
SFRSTACK
Stack
011
100
Figure 3.1. SFR Page Stack Block Diagram
When an interrupt occurs, hardware performs the following operations:
1. The value (if any) in the SFRPGIDX = 011b location is pushed to the SFRPAGE = 100b location.
2. The value (if any) in the SFRPGIDX = 010b location is pushed to the SFRPAGE = 011b location.
3. The value (if any) in the SFRPGIDX = 001b location is pushed to the SFRPAGE = 010b location.
4. The current SFRPAGE value is pushed to the SFRPGIDX = 001b location in the stack.
5. SFRPAGE is set to the page associated with the flag that generated the interrupt.
On a return from interrupt, hardware performs the following operations:
1. The SFR page stack is popped to the SFRPAGE register. This restores the SFR page context prior to the interrupt, without software intervention.
2. The value in the SFRPGIDX = 010b location of the stack is placed in the SFRPGIDX = 001b location.
3. The value in the SFRPGIDX = 011b location of the stack is placed in the SFRPGIDX = 010b location.
4. The value in the SFRPGIDX = 100b location of the stack is placed in the SFRPGIDX = 011b location.
Automatic hardware switching of the SFR page upon interrupt entries and exits may be enabled or disabled using the SFRPGEN located in SFRPGCN. Automatic SFR page switching is enabled after any reset.
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Special Function Registers
3.2 Special Function Register Memory Map
Table 3.2. Special Function Registers by Address
Address SFR Page Address SFR Page
(*bit-addressable)
0x00 0x10 0x20 (*bit-address-
able)
0x00 0x10 0x20
0x80* P0 0xC0* SMB0CN0 TMR5CN0 SMB0CN0
0x81 SP 0xC1 SMB0CF PFE0CN SMB0CF
0x82 DPL 0xC2 SMB0DAT - SMB0DAT
0x83 DPH 0xC3 ADC0GTL SMB0FCN0
0x84 - CLU0MX 0xC4 ADC0GTH SMB0FCN1
0x85 IT01CF CLU1MX 0xC5 ADC0LTL SMB0RXLN
0x86 CRC0CN1 - CRC0CN1 0xC6 ADC0LTH REG1CN
0x87 PCON0 0xC7 HFO0CAL CLU3FN
0x88* TCON 0xC8* TMR2CN0 -
0x89 TMOD 0xC9 REG0CN - REG0CN
0x8A TL0 0xCA TMR2RLL CLU3CF
0x8B TL1 0xCB TMR2RLH CLEN0
0x8C TH0 0xCC TMR2L -
0x8D TH1 0xCD TMR2H CLIE0
0x8E CKCON0 0xCE CRC0CN0 EIE2 CRC0CN0
0x8F PSCTL 0xCF CRC0FLIP SFRPGCN CRC0FLIP
0x90* P1 0xD0* PSW
0x91 TMR3CN0 CLU2MX 0xD1 REF0CN -
0x92 TMR3RLL CLU3MX 0xD2 CRC0ST TMR5RLL CRC0ST
0x93 TMR3RLH SMOD1 0xD3 CRC0CNT TMR5RLH CRC0CNT
0x94 TMR3L SBCON1 0xD4 P0SKIP TMR5L P0SKIP
0x95 TMR3H SBRLL1 0xD5 P1SKIP TMR5H P1SKIP
0x96 PCA0POL SBRLH1 0xD6 SMB0ADM HFO1CAL SMB0ADM
0x97 WDTCN 0xD7 SMB0ADR SFRSTACK SMB0ADR
0x98* SCON1 TMR4CN0 SCON1 0xD8* PCA0CN0 UART1FCN1
0x99 SBUF1 CMP0CN1 SBUF1 0xD9 PCA0MD CLOUT0
0x9A - SPI0FCN0 0xDA PCA0CPM0 UART1PCF
0x9B CMP0CN0 SPI0FCN1 0xDB PCA0CPM1 -
0x9C PCA0CLR - 0xDC PCA0CPM2 -
0x9D CMP0MD UART1FCN0 0xDD CRC0IN - CRC0IN
0x9E PCA0CENT UART1LIN 0xDE CRC0DAT - CRC0DAT
0x9F CMP0MX - 0xDF ADC0PWR SPI0PCF
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Special Function Registers
Address SFR Page Address SFR Page
(*bit-addressable)
0x00 0x10 0x20 (*bit-address-
able)
0x00 0x10 0x20
0xA0* P2 0xE0* ACC
0xA1 SPI0CFG - SPI0CFG 0xE1 XBR0 - XBR0
0xA2 SPI0CKR TMR4RLL SPI0CKR 0xE2 XBR1 - XBR1
0xA3 SPI0DAT TMR4RLH SPI0DAT 0xE3 XBR2 - XBR2
0xA4 P0MDOUT TMR4L P0MDOUT 0xE4 PCON1
0xA5 P1MDOUT TMR4H P1MDOUT 0xE5 -
0xA6 P2MDOUT CKCON1 P2MDOUT 0xE6 EIE1 -
0xA7 SFRPAGE 0xE7 EMI0CN
0xA8* IE 0xE8* ADC0CN0 CLIF0
0xA9 CLKSEL 0xE9 PCA0CPL1 -
0xAA CMP1MX - 0xEA PCA0CPH1 -
0xAB CMP1MD - 0xEB PCA0CPL2 -
0xAC SMB0TC CMP1CN1 SMB0TC 0xEC PCA0CPH2 -
0xAD DERIVID PSTAT0 CLU0FN 0xED P1MAT - P1MAT
0xAE USB0ADR 0xEE P1MASK - P1MASK
0xAF USB0DAT 0xEF RSTSRC HFOCN SMB0FCT
0xB0* - 0xF0* B
0xB1 LFO0CN CLU0CF 0xF1 P0MDIN TMR5CN1 P0MDIN
0xB2 ADC0CN1 USB0AEC 0xF2 P1MDIN IPH P1MDIN
0xB3 ADC0AC USB0XCN 0xF3 EIP1 P2MDIN
0xB4 - 0xF4 - EIP2 -
0xB5 DEVICEID - USB0CF 0xF5 - EIP1H -
0xB6 REVID - USB0CDCF 0xF6 PRTDRV EIP2H PRTDRV
0xB7 FLKEY 0xF7 PCA0PWM SPI0FCT
0xB8* IP 0xF8* SPI0CN0 - SPI0CN0
0xB9 ADC0TK CLU1FN 0xF9 PCA0L -
0xBA - 0xFA PCA0H UART1FCT
0xBB ADC0MX CLU1CF 0xFB PCA0CPL0 P2MAT
0xBC ADC0CF CLU2FN 0xFC PCA0CPH0 P2MASK
0xBD ADC0L CLU2CF 0xFD P0MAT TMR2CN1 P0MAT
0xBE ADC0H USB0CDCN 0xFE P0MASK TMR3CN1 P0MASK
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Special Function Registers
Address SFR Page Address SFR Page
(*bit-addressable)
0x00 0x10 0x20 (*bit-address-
able)
0x00 0x10 0x20
0xBF CMP1CN0 USB0CDSTA 0xFF VDM0CN TMR4CN1 -
Table 3.3. Special Function Registers by Name
Register Address SFR Pages Description
ACC 0xE0 ALL Accumulator
ADC0AC 0xB3 0x00, 0x10 ADC0 Accumulator Configuration
ADC0CF 0xBC 0x00, 0x10 ADC0 Configuration
ADC0CN0 0xE8 0x00, 0x10 ADC0 Control 0
ADC0CN1 0xB2 0x00, 0x10 ADC0 Control 1
ADC0GTH 0xC4 0x00, 0x10 ADC0 Greater-Than High Byte
ADC0GTL 0xC3 0x00, 0x10 ADC0 Greater-Than Low Byte
ADC0H 0xBE 0x00, 0x10 ADC0 Data Word High Byte
ADC0L 0xBD 0x00, 0x10 ADC0 Data Word Low Byte
ADC0LTH 0xC6 0x00, 0x10 ADC0 Less-Than High Byte
ADC0LTL 0xC5 0x00, 0x10 ADC0 Less-Than Low Byte
ADC0MX 0xBB 0x00, 0x10 ADC0 Multiplexer Selection
ADC0PWR 0xDF 0x00, 0x10 ADC0 Power Control
ADC0TK 0xB9 0x00, 0x10 ADC0 Burst Mode Track Time
B 0xF0 ALL B Register
CKCON0 0x8E ALL Clock Control 0
CKCON1 0xA6 0x10 Clock Control 1
CLEN0 0xCB 0x20 Configurable Logic Enable 0
CLIE0 0xCD 0x20 Configurable Logic Interrupt Enable 0
CLIF0 0xE8 0x20 Configurable Logic Interrupt Flag 0
CLKSEL 0xA9 ALL Clock Select
CLOUT0 0xD9 0x20 Configurable Logic Output 0
CLU0CF 0xB1 0x20 Configurable Logic Unit 0 Configuration
CLU0FN 0xAD 0x20 Configurable Logic Unit 0 Function Select
CLU0MX 0x84 0x20 Configurable Logic Unit 0 Multiplexer
CLU1CF 0xBB 0x20 Configurable Logic Unit 1 Configuration
CLU1FN 0xB9 0x20 Configurable Logic Unit 1 Function Select
CLU1MX 0x85 0x20 Configurable Logic Unit 1 Multiplexer
CLU2CF 0xBD 0x20 Configurable Logic Unit 2 Configuration
CLU2FN 0xBC 0x20 Configurable Logic Unit 2 Function Select
CLU2MX 0x91 0x20 Configurable Logic Unit 2 Multiplexer
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Special Function Registers
Register Address SFR Pages Description
CLU3CF 0xCA 0x20 Configurable Logic Unit 3 Configuration
CLU3FN 0xC7 0x20 Configurable Logic Unit 3 Function Select
CLU3MX 0x92 0x20 Configurable Logic Unit 3 Multiplexer
CMP0CN0 0x9B 0x00, 0x10 Comparator 0 Control 0
CMP0CN1 0x99 0x10 Comparator 0 Control 1
CMP0MD 0x9D 0x00, 0x10 Comparator 0 Mode
CMP0MX 0x9F 0x00, 0x10 Comparator 0 Multiplexer Selection
CMP1CN0 0xBF 0x00, 0x10 Comparator 1 Control 0
CMP1CN1 0xAC 0x10 Comparator 1 Control 1
CMP1MD 0xAB 0x00, 0x10 Comparator 1 Mode
CMP1MX 0xAA 0x00, 0x10 Comparator 1 Multiplexer Selection
CRC0CN0 0xCE 0x00, 0x20 CRC0 Control 0
CRC0CN1 0x86 0x00, 0x20 CRC0 Control 1
EFM8UB3 Reference Manual
CRC0CNT 0xD3 0x00, 0x20 CRC0 Automatic Flash Sector Count
CRC0DAT 0xDE 0x00, 0x20 CRC0 Data Output
CRC0FLIP 0xCF 0x00, 0x20 CRC0 Bit Flip
CRC0IN 0xDD 0x00, 0x20 CRC0 Data Input
CRC0ST 0xD2 0x00, 0x20 CRC0 Automatic Flash Sector Start
DERIVID 0xAD 0x00 Derivative Identification
DEVICEID 0xB5 0x00 Device Identification
DPH 0x83 ALL Data Pointer High
DPL 0x82 ALL Data Pointer Low
EIE1 0xE6 0x00, 0x10 Extended Interrupt Enable 1
EIE2 0xCE 0x10 Extended Interrupt Enable 2
EIP1 0xF3 0x00, 0x10 Extended Interrupt Priority 1 Low
EIP1H 0xF5 0x10 Extended Interrupt Priority 1 High
EIP2 0xF4 0x10 Extended Interrupt Priority 2
EIP2H 0xF6 0x10 Extended Interrupt Priority 2 High
EMI0CN 0xE7 ALL External Memory Interface Control
FLKEY 0xB7 ALL Flash Lock and Key
HFO0CAL 0xC7 0x00, 0x10 High Frequency Oscillator 0 Calibration
HFO1CAL 0xD6 0x10 High Frequency Oscillator 1 Calibration
HFOCN 0xEF 0x10 High Frequency Oscillator Control
IE 0xA8 ALL Interrupt Enable
IP 0xB8 ALL Interrupt Priority
IPH 0xF2 0x10 Interrupt Priority High
IT01CF 0x85 0x00, 0x10 INT0/INT1 Configuration
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Register Address SFR Pages Description
LFO0CN 0xB1 0x00, 0x10 Low Frequency Oscillator Control
P0 0x80 ALL Port 0 Pin Latch
P0MASK 0xFE 0x00, 0x20 Port 0 Mask
P0MAT 0xFD 0x00, 0x20 Port 0 Match
P0MDIN 0xF1 0x00, 0x20 Port 0 Input Mode
P0MDOUT 0xA4 0x00, 0x20 Port 0 Output Mode
P0SKIP 0xD4 0x00, 0x20 Port 0 Skip
P1 0x90 ALL Port 1 Pin Latch
P1MASK 0xEE 0x00, 0x20 Port 1 Mask
P1MAT 0xED 0x00, 0x20 Port 1 Match
P1MDIN 0xF2 0x00, 0x20 Port 1 Input Mode
P1MDOUT 0xA5 0x00, 0x20 Port 1 Output Mode
P1SKIP 0xD5 0x00, 0x20 Port 1 Skip
EFM8UB3 Reference Manual
Special Function Registers
P2 0xA0 ALL Port 2 Pin Latch
P2MASK 0xFC 0x20 Port 2 Mask
P2MAT 0xFB 0x20 Port 2 Match
P2MDIN 0xF3 0x20 Port 2 Input Mode
P2MDOUT 0xA6 0x00, 0x20 Port 2 Output Mode
PCA0CENT 0x9E 0x00, 0x10 PCA Center Alignment Enable
PCA0CLR 0x9C 0x00, 0x10 PCA Comparator Clear Control
PCA0CN0 0xD8 0x00, 0x10 PCA Control
PCA0CPH0 0xFC 0x00, 0x10 PCA Channel 0 Capture Module High Byte
PCA0CPH1 0xEA 0x00, 0x10 PCA Channel 1 Capture Module High Byte
PCA0CPH2 0xEC 0x00, 0x10 PCA Channel 2 Capture Module High Byte
PCA0CPL0 0xFB 0x00, 0x10 PCA Channel 0 Capture Module Low Byte
PCA0CPL1 0xE9 0x00, 0x10 PCA Channel 1 Capture Module Low Byte
PCA0CPL2 0xEB 0x00, 0x10 PCA Channel 2 Capture Module Low Byte
PCA0CPM0 0xDA 0x00, 0x10 PCA Channel 0 Capture/Compare Mode
PCA0CPM1 0xDB 0x00, 0x10 PCA Channel 1 Capture/Compare Mode
PCA0CPM2 0xDC 0x00, 0x10 PCA Channel 2 Capture/Compare Mode
PCA0H 0xFA 0x00, 0x10 PCA Counter/Timer High Byte
PCA0L 0xF9 0x00, 0x10 PCA Counter/Timer Low Byte
PCA0MD 0xD9 0x00, 0x10 PCA Mode
PCA0POL 0x96 0x00, 0x10 PCA Output Polarity
PCA0PWM 0xF7 0x00, 0x10 PCA PWM Configuration
PCON0 0x87 ALL Power Control
PCON1 0xE4 ALL Power Control 1
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Special Function Registers
Register Address SFR Pages Description
PFE0CN 0xC1 0x10 Prefetch Engine Control
PRTDRV 0xF6 0x00, 0x20 Port Drive Strength
PSCTL 0x8F ALL Program Store Control
PSTAT0 0xAD 0x10 Power Status
PSW 0xD0 ALL Program Status Word
REF0CN 0xD1 0x00, 0x10 Voltage Reference Control
REG0CN 0xC9 0x00, 0x20 Voltage Regulator 0 Control
REG1CN 0xC6 0x20 Voltage Regulator 1 Control
REVID 0xB6 0x00 Revision Identifcation
RSTSRC 0xEF 0x00 Reset Source
SBCON1 0x94 0x20 UART1 Baud Rate Generator Control
SBRLH1 0x96 0x20 UART1 Baud Rate Generator High Byte
SBRLL1 0x95 0x20 UART1 Baud Rate Generator Low Byte
EFM8UB3 Reference Manual
SBUF1 0x99 0x00, 0x20 UART1 Serial Port Data Buffer
SCON1 0x98 0x00, 0x20 UART1 Serial Port Control
SFRPAGE 0xA7 ALL SFR Page
SFRPGCN 0xCF 0x10 SFR Page Control
SFRSTACK 0xD7 0x10 SFR Page Stack
SMB0ADM 0xD6 0x00, 0x20 SMBus 0 Slave Address Mask
SMB0ADR 0xD7 0x00, 0x20 SMBus 0 Slave Address
SMB0CF 0xC1 0x00, 0x20 SMBus 0 Configuration
SMB0CN0 0xC0 0x00, 0x20 SMBus 0 Control
SMB0DAT 0xC2 0x00, 0x20 SMBus 0 Data
SMB0FCN0 0xC3 0x20 SMBus 0 FIFO Control 0
SMB0FCN1 0xC4 0x20 SMBus 0 FIFO Control 1
SMB0FCT 0xEF 0x20 SMBus 0 FIFO Count
SMB0RXLN 0xC5 0x20 SMBus 0 Receive Length Counter
SMB0TC 0xAC 0x00, 0x20 SMBus 0 Timing and Pin Control
SMOD1 0x93 0x20 UART1 Mode
SP 0x81 ALL Stack Pointer
SPI0CFG 0xA1 0x00, 0x20 SPI0 Configuration
SPI0CKR 0xA2 0x00, 0x20 SPI0 Clock Rate
SPI0CN0 0xF8 0x00, 0x20 SPI0 Control
SPI0DAT 0xA3 0x00, 0x20 SPI0 Data
SPI0FCN0 0x9A 0x20 SPI0 FIFO Control 0
SPI0FCN1 0x9B 0x20 SPI0 FIFO Control 1
SPI0FCT 0xF7 0x20 SPI0 FIFO Count
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Register Address SFR Pages Description
SPI0PCF 0xDF 0x20 SPI0 Pin Configuration
TCON 0x88 ALL Timer 0/1 Control
TH0 0x8C ALL Timer 0 High Byte
TH1 0x8D ALL Timer 1 High Byte
TL0 0x8A ALL Timer 0 Low Byte
TL1 0x8B ALL Timer 1 Low Byte
TMOD 0x89 ALL Timer 0/1 Mode
TMR2CN0 0xC8 0x00, 0x10 Timer 2 Control 0
TMR2CN1 0xFD 0x10 Timer 2 Control 1
TMR2H 0xCD 0x00, 0x10 Timer 2 High Byte
TMR2L 0xCC 0x00, 0x10 Timer 2 Low Byte
TMR2RLH 0xCB 0x00, 0x10 Timer 2 Reload High Byte
TMR2RLL 0xCA 0x00, 0x10 Timer 2 Reload Low Byte
EFM8UB3 Reference Manual
Special Function Registers
TMR3CN0 0x91 0x00, 0x10 Timer 3 Control 0
TMR3CN1 0xFE 0x10 Timer 3 Control 1
TMR3H 0x95 0x00, 0x10 Timer 3 High Byte
TMR3L 0x94 0x00, 0x10 Timer 3 Low Byte
TMR3RLH 0x93 0x00, 0x10 Timer 3 Reload High Byte
TMR3RLL 0x92 0x00, 0x10 Timer 3 Reload Low Byte
TMR4CN0 0x98 0x10 Timer 4 Control 0
TMR4CN1 0xFF 0x10 Timer 4 Control 1
TMR4H 0xA5 0x10 Timer 4 High Byte
TMR4L 0xA4 0x10 Timer 4 Low Byte
TMR4RLH 0xA3 0x10 Timer 4 Reload High Byte
TMR4RLL 0xA2 0x10 Timer 4 Reload Low Byte
TMR5CN0 0xC0 0x10 Timer 5 Control 0
TMR5CN1 0xF1 0x10 Timer 5 Control 1
TMR5H 0xD5 0x10 Timer 5 High Byte
TMR5L 0xD4 0x10 Timer 5 Low Byte
TMR5RLH 0xD3 0x10 Timer 5 Reload High Byte
TMR5RLL 0xD2 0x10 Timer 5 Reload Low Byte
UART1FCN0 0x9D 0x20 UART1 FIFO Control 0
UART1FCN1 0xD8 0x20 UART1 FIFO Control 1
UART1FCT 0xFA 0x20 UART1 FIFO Count
UART1LIN 0x9E 0x20 UART1 LIN Configuration
UART1PCF 0xDA 0x20 UART1 Configuration
USB0ADR 0xAE ALL USB0 Indirect Address
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Register Address SFR Pages Description
USB0AEC 0xB2 0x20 USB0 Advanced Energy Control
USB0CDCF 0xB6 0x20 USB0 Charger Detect Configuration
USB0CDCN 0xBE 0x20 USB0 Charger Detect Control
USB0CDSTA 0xBF 0x20 USB0 Charger Detect Status
USB0CF 0xB5 0x20 USB0 Configuration
USB0DAT 0xAF ALL USB0 Data
USB0XCN 0xB3 0x20 USB0 Transceiver Control
VDM0CN 0xFF 0x00 Supply Monitor Control
WDTCN 0x97 ALL Watchdog Timer Control
XBR0 0xE1 0x00, 0x20 Port I/O Crossbar 0
XBR1 0xE2 0x00, 0x20 Port I/O Crossbar 1
XBR2 0xE3 0x00, 0x20 Port I/O Crossbar 2
EFM8UB3 Reference Manual
Special Function Registers
3.3 SFR Access Control Registers
3.3.1 SFRPAGE: SFR Page
Bit 7 6 5 4 3 2 1 0
Name SFRPAGE
Access RW
Reset 0x00
SFR Page = ALL; SFR Address: 0xA7
Bit Name Reset Access Description
7:0 SFRPAGE 0x00 RW SFR Page.
Specifies the SFR Page used when reading, writing, or modifying special function registers.
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Special Function Registers
3.3.2 SFRPGCN: SFR Page Control
Bit 7 6 5 4 3 2 1 0
Name Reserved SFRPGIDX Reserved SFRPGEN
Access RW RW RW RW
Reset 0 0x0 0x0 1
SFR Page = 0x10; SFR Address: 0xCF
Bit Name Reset Access Description
7 Reserved Must write reset value.
6:4 SFRPGIDX 0x0 RW SFR Page Stack Index.
This field can be used to access the SFRPAGE values stored in the SFR page stack. It selects the level of the stack firmware can access when reading the SFRSTACK register.
Value Name Description
0x0 FIRST_BYTE SFRSTACK contains the value of SFRPAGE, the first/top byte of the
SFR page stack.
0x1 SECOND_BYTE SFRSTACK contains the value of the second byte of the SFR page
stack.
0x2 THIRD_BYTE SFRSTACK contains the value of the third byte of the SFR page stack.
0x3 FOURTH_BYTE SFRSTACK contains the value of the fourth byte of the SFR page
stack.
0x4 FIFTH_BYTE SFRSTACK contains the value of the fifth byte of the SFR page stack.
3:1 Reserved Must write reset value.
0 SFRPGEN 1 RW SFR Automatic Page Control Enable.
This bit is used to enable automatic page switching on ISR entry/exit. When set to 1, the current SFRPAGE value will be
pushed onto the SFR page stack and SFRPAGE will be set to the page corresponding to the flag which generated the interrupt; upon ISR exit, hardware will pop the value from the SFR page stack and restore SFRPAGE.
Value Name Description
0 DISABLED Disable automatic SFR paging.
1 ENABLED Enable automatic SFR paging.
3.3.3 SFRSTACK: SFR Page Stack
Bit
7 6 5 4 3 2 1 0
Name SFRSTACK
Access R
Reset 0x00
SFR Page = 0x10; SFR Address: 0xD7
Bit Name Reset Access Description
7:0 SFRSTACK 0x00 R SFR Page Stack.
This register is used to read the contents of the SFR page stack. The SFRPGIDX field in the SFRPGCN register controls
the level of the stack this register will access.
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Flash Memory
4. Flash Memory
4.1 Introduction
On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The flash memory is organized in
512-byte pages. It can be erased and written through the C2 interface or from firmware by overloading the MOVX instruction. Any individual byte in flash memory must only be written once between page erase operations.
0xFFFF
0xFFC0
0xFBFF
0xFBFE
0xFBFD
0xFA00
0x9DFF
0x9A00
Read-Only
64 Bytes
Reserved
Lock Byte
Bootloader Signature Byte
Security Page
512 Bytes
Reserved
Bootloader
Bootloader Vector
Bootloader
Memory Lock
Read-Only
64 Bytes
128-bit UUID
0xFFFF
0xFFFE
0xFFD0
0xFFCF
0xFFC0
40 KB Flash
(79 x 512 Byte pages)
0x0000
Figure 4.1. Flash Memory Map — 40 KB Devices
4.2 Features
The flash memory has the following features:
• Up to 40 KB in 512-byte sectors, and 1 KB in 64-byte sectors.
• In-system programmable from user firmware.
• Security lock to prevent unwanted read/write/erase access.
Reset Vector
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Flash Memory
4.3 Functional Description
4.3.1 Security Options
The CIP-51 provides security options to protect the flash memory from inadvertent modification by software as well as to prevent the
viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program
Store Erase Enable (bit PSEE in register PSCTL) bits protect the flash memory from accidental modification by software. PSWE must
be explicitly set to 1 before software can modify the flash memory; both PSWE and PSEE must be set to 1 before software can erase
flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the
C2 interface.
A Security Lock Byte located in flash user space offers protection of the flash program memory from access (reads, writes, or erases)
by unprotected code or the C2 interface. See the specific device memory map for the location of the security byte. The flash security
mechanism allows the user to lock "n" flash pages, starting at page 0, where "n" is the 1s complement number represented by the
Security Lock Byte. Some devices may also include a read-only area in the flash memory space for constants such as UID and calibration values.
Note: The page containing the flash Security Lock Byte is unlocked when no other flash pages are locked (all bits of the Lock Byte are
1) and locked when any other flash pages are locked (any bit of the Lock Byte is 0).
Table 4.1. Security Byte Decoding
Security Lock Byte 111111101b
1s Complement 00000010b
Flash Pages Locked 3 (First two flash pages + Lock Byte Page)
The level of flash security depends on the flash access method. The three flash access methods that can be restricted are reads,
writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked
pages.
Table 4.2. Flash Security Summary—Firmware Permissions
Permissions according to the area firmware is executing
from:
Target Area for Read / Write / Erase Unlocked Page Locked Page
Any Unlocked Page [R] [W] [E] [R] [W] [E]
Locked Page (except security page) reset [R] [W] [E]
Locked Security Page reset [R] [W]
Read-Only Area [R] [R]
Reserved Area reset reset
[R] = Read permitted
[W] = Write permitted
[E] = Erase permitted
reset = Flash error reset triggered
n/a = Not applicable
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Table 4.3. Flash Security Summary—C2 Permissions
Target Area for Read / Write / Erase Permissions from C2 interface
Any Unlocked Page [R] [W] [E]
Any Locked Page Device Erase Only
Read-Only Area [R]
Reserved Area None
[R] = Read permitted
[W] = Write permitted
[E] = Erase permitted
Device Erase Only = No read, write, or individual page erase is allowed. Must erase entire flash space.
None = Read, write and erase are not permitted
4.3.2 Programming the Flash Memory
EFM8UB3 Reference Manual
Flash Memory
Writes to flash memory clear bits from logic 1 to logic 0 and can be performed on single byte locations. Flash erasures set bits back to
logic 1 and occur only on full pages. The write and erase operations are automatically timed by hardware for proper execution; data
polling to determine the end of the write/erase operation is not required. Code execution is stalled during a flash write/erase operation.
The simplest means of programming the flash memory is through the C2 interface using programming tools provided by Silicon Labs or
a third party vendor. Firmware may also be loaded into the device to implement code-loader functions or allow non-volatile data storage. To ensure the integrity of flash contents, it is strongly recommended that the on-chip supply monitor be enabled in any system that
includes code that writes and/or erases flash memory from software.
4.3.2.1 Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The FLKEY register must be written with the correct key codes, in sequence, before flash operations may be performed. The key codes are 0xA5 and 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order or the wrong codes are written, flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a flash write or erase is attempted
before the key codes have been written properly. The flash lock resets after each write or erase; the key codes must be written again
before another flash write or erase operation can be performed.
4.3.2.2 Flash Page Erase Procedure
The flash memory is erased one page at a time by firmware using the MOVX write instruction with the address targeted to any byte
within the page. Before erasing a page of flash memory, flash write and erase operations must be enabled by setting the PSWE and
PSEE bits in the PSCTL register to logic 1 (this directs the MOVX writes to target flash memory and enables page erasure) and writing
the flash key codes in sequence to the FLKEY register. The PSWE and PSEE bits remain set until cleared by firmware.
Erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire page, perform the following steps:
1. Disable interrupts (recommended).
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSEE bit (register PSCTL).
5. Set the PSWE bit (register PSCTL).
6. Using the MOVX instruction, write a data byte to any location within the page to be erased.
7. Clear the PSWE and PSEE bits.
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Flash Memory
4.3.2.3 Flash Byte Write Procedure
The flash memory is written by firmware using the MOVX write instruction with the address and data byte to be programmed provided
as normal operands in DPTR and A. Before writing to flash memory using MOVX, flash write operations must be enabled by setting the
PSWE bit in the PSCTL register to logic 1 (this directs the MOVX writes to target flash memory) and writing the flash key codes in
sequence to the FLKEY register. The PSWE bit remains set until cleared by firmware. A write to flash memory can clear bits to logic 0
but cannot set them. A byte location to be programmed should be erased (already set to 0xFF) before a new value is written.
To write a byte of flash, perform the following steps:
1. Disable interrupts (recommended).
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSWE bit (register PSCTL).
5. Clear the PSEE bit (register PSCTL).
6. Using the MOVX instruction, write a single data byte to the desired location within the desired page.
7. Clear the PSWE bit.
4.3.3 Flash Write and Erase Precautions
Any system which contains routines which write or erase flash memory from software involves some risk that the write or erase routines
will execute unintentionally if the CPU is operating outside its specified operating range of supply voltage, system clock frequency or
temperature. This accidental execution of flash modifying code can result in alteration of flash memory contents causing a system failure that is only recoverable by re-flashing the code in the device.
To help prevent the accidental modification of flash by firmware, hardware restricts flash writes and erasures when the supply monitor is
not active and selected as a reset source. As the monitor is enabled and selected as a reset source by default, it is recommended that
systems writing or erasing flash simply maintain the default state.
The following sections provide general guidelines for any system which contains routines which write or erase flash from code. Additional flash recommendations and example code can be found in AN201: Writing to Flash From Firmware, available from the Silicon
Laboratories website.
Voltage Supply Maintenance and the Supply Monitor
• If the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to
ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded.
• Make certain that the minimum supply rise time specification is met. If the system cannot meet this rise time specification, then add
an external supply brownout circuit to the RSTb pin of the device that holds the device in reset until the voltage supply reaches the
lower limit, and re-asserts RSTb if the supply drops below the low supply limit.
• Do not disable the supply monitor. If the supply monitor must be disabled in the system, firmware should be added to the startup
routine to enable the on-chip supply monitor and enable the supply monitor as a reset source as early in code as possible. This
should be the first set of instructions executed after the reset vector. For C-based systems, this may involve modifying the startup
code added by the C compiler. See your compiler documentation for more details. Make certain that there are no delays in software
between enabling the supply monitor and enabling the supply monitor as a reset source.
Note: The supply monitor must be enabled and enabled as a reset source when writing or erasing flash memory. A flash error reset
will occur if either condition is not met.
• As an added precaution if the supply monitor is ever disabled, explicitly enable the supply monitor and enable the supply monitor as
a reset source inside the functions that write and erase flash memory. The supply monitor enable instructions should be placed just
after the instruction to set PSWE to a 1, but before the flash write or erase operation instruction.
• Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and explicitly do not use the
bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
• Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check are initialization code which
enables other reset sources, such as the Missing Clock Detector or Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this.
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Flash Memory
PSWE Maintenance
• Reduce the number of places in code where the PSWE bit (in register PSCTL) is set to a 1. There should be exactly one routine in
code that sets PSWE to a 1 to write flash bytes and one routine in code that sets PSWE and PSEE both to a 1 to erase flash pages.
• Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates and loop variable maintenance
outside the "PSWE = 1;... PSWE = 0;" area.
• Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been reset to 0. Any interrupts posted
during the flash write or erase operation will be serviced in priority order after the flash operation has been completed and interrupts
have been re-enabled by software.
• Make certain that the flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas.
• Add address bounds checking to the routines that write or erase flash memory to ensure that a routine called with an illegal address
does not result in modification of the flash.
System Clock
• If operating from an external source, be advised that performance is susceptible to electrical interference and is sensitive to layout
and to changes in temperature. If the system is operating in an electrically noisy environment, use the internal oscillator or use an
external CMOS clock.
• If operating from the external oscillator, switch to the internal oscillator during flash write or erase operations. The external oscillator
can continue to run, and the CPU can switch back to the external oscillator after the flash operation has completed.
4.4 Flash Control Registers
4.4.1 PSCTL: Program Store Control
Bit 7 6 5 4 3 2 1 0
Name Reserved PSEE PSWE
Access R RW RW
Reset 0x00 0 0
SFR Page = ALL; SFR Address: 0x8F
Bit Name Reset Access Description
7:2 Reserved Must write reset value.
1 PSEE 0 RW Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of flash program memory to be erased. If this bit is logic 1
and flash writes are enabled (PSWE is logic 1), a write to flash memory using the MOVX instruction will erase the entire
page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter.
Value Name Description
0 ERASE_DISABLED Flash program memory erasure disabled.
1 ERASE_ENABLED Flash program memory erasure enabled.
0 PSWE 0 RW Program Store Write Enable.
Setting this bit allows writing a byte of data to the flash program memory using the MOVX write instruction. The flash location should be erased before writing data.
Value Name Description
0 WRITE_DISABLED Writes to flash program memory disabled.
1 WRITE_ENABLED Writes to flash program memory enabled; the MOVX write instruction
targets flash memory.
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Flash Memory
4.4.2 FLKEY: Flash Lock and Key
Bit 7 6 5 4 3 2 1 0
Name FLKEY
Access RW
Reset 0x00
SFR Page = ALL; SFR Address: 0xB7
Bit Name Reset Access Description
7:0 FLKEY 0x00 RW Flash Lock and Key.
Write:
This register provides a lock and key function for flash erasures and writes. Flash writes and erases are enabled by writing
0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or
erase is complete. If any writes to FLKEY are performed incorrectly, or if a flash write or erase operation is attempted while
these operations are disabled, the flash will be permanently locked from writes or erasures until the next device reset. If an
application never writes to flash, it can intentionally lock the flash by writing a non-0xA5 value to FLKEY from firmware.
Read:
When read, bits 1-0 indicate the current flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases are disabled until the next reset.
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Device Identification
5. Device Identification
5.1 Device Identification
The SFR map includes registers that may be used to identify the device family (DEVICEID), derivative (DERIVID), and revision (REVID). These SFRs can be read by firmware at runtime to determine the capabilities of the MCU that is executing code. This allows the
same firmware image to run on MCUs with different memory sizes and peripherals, and dynamically change functionality to suit the
capabilities of that MCU.
5.2 Unique Identifier
A128-bit universally unique identifier (UUID) is pre-programmed into all devices. The value assigned to a device is random and not
sequential, but it is guaranteed unique. The UUID resides in the read-only area of flash memory which cannot be erased or written in
the end application. The UUID can be read by firmware or through the debug interface at flash locations 0xFFC0-0xFFCF.
Table 5.1. UID Location in Memory
Device Flash Addresses
EFM8UB30F40G
EFM8UB31F40G
EFM8UB32F40G
5.3 Device Identification Registers
5.3.1 DEVICEID: Device Identification
Bit 7 6 5 4 3 2 1 0
Name DEVICEID
Access R
Reset 0x36
SFR Page = 0x0; SFR Address: 0xB5
Bit Name Reset Access Description
7:0 DEVICEID 0x36 R Device ID.
(MSB)
0xFFCF, 0xFFCE, 0xFFCD, 0xFFCC,
0xFFCB, 0xFFCA, 0xFFC9, 0xFFC8,
0xFFC7, 0xFFC6, 0xFFC5, 0xFFC4,
0xFFC3, 0xFFC2, 0xFFC1, 0xFFC0
(LSB)
This read-only register returns the 8-bit device ID.
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Device Identification
5.3.2 DERIVID: Derivative Identification
Bit 7 6 5 4 3 2 1 0
Name DERIVID
Access R
Reset Varies
SFR Page = 0x0; SFR Address: 0xAD
Bit Name Reset Access Description
7:0 DERIVID Varies R Derivative ID.
This read-only register returns the 8-bit derivative ID, which can be used by firmware to identify which device in the product
family the code is executing on. The '{R}' tag in the part numbers indicates the device revision letter in the ordering code.
The revision letter may be determined by decoding the REVID register.
Value Name Description
0x00 EFM8UB30F40G_QFN20EFM8UB30F40G-{R}-QFN20
0x01 EFM8UB31F40G_QFN24EFM8UB31F40G-{R}-QFN24
0x02 EFM8UB31F40G_QSO
EFM8UB31F40G-{R}-QSOP24
P24
5.3.3 REVID: Revision Identifcation
Bit 7 6 5 4 3 2 1 0
Name REVID
Access R
Reset Varies
SFR Page = 0x0; SFR Address: 0xB6
Bit Name Reset Access Description
7:0 REVID Varies R Revision ID.
This read-only register returns the revision ID.
Value Name Description
0x00 REV_A Revision A.
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Interrupts
6. Interrupts
6.1 Introduction
The MCU core includes an extended interrupt system supporting multiple interrupt sources and priority levels. The allocation of interrupt
sources between on-chip peripherals and external input pins varies according to the specific version of the device.
Interrupt sources may have one or more associated interrupt-pending flag(s) located in an SFR local to the associated peripheral.
When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of
the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service
routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have
been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. The interrupt-pending flag is set to logic 1 regardless of whether the interrupt is enabled.
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the IE and EIEn
registers. However, interrupts must first be globally enabled by setting the EA bit to logic 1 before the individual interrupt enables are
recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR or by other hardware conditions. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interruptpending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated
immediately and the CPU will re-enter the ISR after the completion of the next instruction.
6.2 Interrupt Sources and Vectors
The CIP51 core supports interrupt sources for each peripheral on the device. Software can simulate an interrupt for many peripherals
by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. Refer to the data sheet section associated with a particular onchip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
6.2.1 Interrupt Priorities
Each interrupt source can be individually programmed to one of four priority levels. This differs from the traditional two priority levels on
the 8051 core. However, the implementation of the extra levels is backwards- compatible with legacy 8051 code.
An interrupt service routine can be preempted by any interrupt of higher priority. Interrupts at the highest priority level cannot be preempted. Each interrupt has two associated priority bits which are used to configure the priority level. For backwards compatibility, the
bits are spread across two different registers. The LSBs of the priority setting are located in the IP and EIPn registers, while the MSBs
are located in the IPH and EIPnH registers. Priority levels according to the MSB and LSB are decoded in Table 6.1 Configurable Inter-
rupt Priority Decoding on page 47. The lowest priority setting is the default for all interrupts. If two or more interrupts are recognized
simultaneously, the interrupt with the highest priority is serviced first. If both interrupts have the same priority level, a fixed order is used
to arbitrate, based on the interrupt source's location in the interrupt vector table. Interrupts with a lower number in the vector table have
priority. If legacy 8051 operation is desired, the bits of the “high” priority registers (IPH and EIPnH) should all be configured to 0.
Table 6.1. Configurable Interrupt Priority Decoding
Priority MSB
(from IPH or EIPnH)
Priority LSB
(from IP or EIPn)
Priority Level
0 0 Priority 0 (lowest priority, default)
0 1 Priority 1
1 0 Priority 2
1 1 Priority 3 (highest priority)
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Interrupts
6.2.2 Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded on every system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the
interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is
executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the
interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to
the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction. If more than one interrupt is pending when the CPU exits an ISR,
the CPU will service the next highest priority interrupt that is pending.
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6.2.3 Interrupt Summary
Table 6.2. Interrupt Priority Table
Interrupt Source Vector Priority Primary Enable Auxiliary Enable(s) Pending Flag(s)
Reset 0x0000 Top - - -
External Interrupt 0 0x0003 0 IE_EX0 - TCON_IE0
Timer 0 Overflow 0x000B 1 IE_ET0 - TCON_TF0
External Interrupt 1 0x0013 2 IE_EX1 - TCON_IE1
Timer 1 Overflow 0x001B 3 IE_ET1 - TCON_TF1
Interrupts
UART1 0x0023 4 IE_ES1 UART1FCN0_RFRQE
UART1FCN0_TFRQE
UART1FCN1_RIE
UART1FCN1_RXTO
SCON1_RI
SCON1_TI
UART1FCN1_RFRQ
UART1FCN1_TFRQ
UART1FCN1_TIE
Timer 2 Overflow / Cap-
0x002B 5 IE_ET2 TMR2CN0_TF2CEN
TMR2CN0_TF2H
ture
TMR2CN0_TF2LEN
SPI0 0x0033 6 IE_ESPI0 SPI0FCN0_RFRQE
SPI0FCN0_TFRQE
SPI0FCN1_SPIFEN
TMR2CN0_TF2L
SPI0CN0_MODF
SPI0CN0_RXOVRN
SPI0CN0_SPIF
SPI0CN0_WCOL
SPI0FCN1_RFRQ
SPI0FCN1_TFRQ
SMBus 0 0x003B 7 EIE1_ESMB0 - SMB0CN0_SI
Port Match 0x0043 8 EIE1_EMAT - -
ADC0 Window Compare 0x004B 9 EIE1_EWADC0 - ADC0CN0_ADWINT
ADC0 End of Conversion 0x0053 10 EIE1_EADC0 - ADC0CN0_ADINT
PCA0 0x005B 11 EIE1_EPCA0 PCA0CPM0_ECCF
PCA0CPM1_ECCF
PCA0CPM2_ECCF
PCA0PWM_ECOV
PCA0CN0_CCF0
PCA0CN0_CCF1
PCA0CN0_CCF2
PCA0CN0_CF
PCA0PWM_COVF
Comparator 0 0x0063 12 EIE1_ECP0 CMP0MD_CPRIE
CMP0MD_CPFIE
Comparator 1 0x006B 13 EIE1_ECP1 CMP1MD_CPFIE
CMP1MD_CPRIE
Timer 3 Overflow / Cap-
0x0073 14 EIE1_ET3 TMR3CN0_TF3CEN
CMP0CN0_CPFIF
CMP0CN0_CPRIF
CMP1CN0_CPFIF
CMP1CN0_CPRIF
TMR3CN0_TF3H
ture
TMR3CN0_TF3LEN
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Interrupt Source Vector Priority Primary Enable Auxiliary Enable(s) Pending Flag(s)
Interrupts
USB0 Events 0x007B 15 EIE2_EUSB0
VBUS / USB Charge De-
0x0083 16 EIE2_EVBUS USB0CDCF_DCDIE
tect
CMIE_RSTINTE
CMIE_RSUINTE
CMIE_SOFE
CMIE_SUSINTE
IN1IE_EP0E
IN1IE_IN1E
IN1IE_IN2E
IN1IE_IN3E
OUT1IE_OUT1E
OUT1IE_OUT2E
OUT1IE_OUT3E
USB0CDCF_PDIE
USB0CDCF_SDIE
USB0CF_VBUSIE
CMINT_RSTINT
CMINT_RSUINT
CMINT_SOF
CMINT_SUSINT
IN1INT_EP0
IN1INT_IN1
IN1INT_IN2
IN1INT_IN3
OUT1INT_OUT1
OUT1INT_OUT2
OUT1INT_OUT3
USB0CDSTA_DCDI
USB0CDSTA_ERR
USB0CDSTA_PDI
USB0CDSTA_SDI
USB0CF_VBUSI
Timer 4 Overflow / Cap-
0x008B 17 EIE2_ET4 TMR4CN0_TF4CEN
TMR4CN0_TF4H
ture
Timer 5 Overflow / Cap-
TMR4CN0_TF4LEN
0x0093 18 EIE2_ET5 TMR5CN0_TF5CEN
TMR4CN0_TF4L
TMR5CN0_TF5H
ture
TMR5CN0_TF5LEN
TMR5CN0_TF5L
Reserved 0x009B 19 - - -
Reserved 0x00A3 20 - - -
Configurable Logic 0x00AB 21 EIE2_CL0
CLIE0_C0FIE
CLIE0_C0RIE
CLIE0_C1FIE
CLIE0_C1RIE
CLIE0_C2FIE
CLIE0_C2RIE
CLIE0_C3FIE
CLIE0_C3RIE
CLIF0_C0FIF
CLIF0_C0RIF
CLIF0_C1FIF
CLIF0_C1RIF
CLIF0_C2FIF
CLIF0_C2RIF
CLIF0_C3FIF
CLIF0_C3RIF
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Interrupts
6.3 Interrupt Control Registers
6.3.1 IE: Interrupt Enable
Bit 7 6 5 4 3 2 1 0
Name EA ESPI0 ET2 ES1 ET1 EX1 ET0 EX0
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
SFR Page = ALL; SFR Address: 0xA8 (bit-addressable)
Bit Name Reset Access Description
7 EA 0 RW All Interrupts Enable.
Globally enables/disables all interrupts and overrides individual interrupt mask settings.
Value Name Description
0 DISABLED Disable all interrupt sources.
1 ENABLED Enable each interrupt according to its individual mask setting.
6 ESPI0 0 RW SPI0 Interrupt Enable.
This bit sets the masking of the SPI0 interrupts.
Value Name Description
0 DISABLED Disable all SPI0 interrupts.
1 ENABLED Enable interrupt requests generated by SPI0.
5 ET2 0 RW Timer 2 Interrupt Enable.
This bit sets the masking of the Timer 2 interrupt.
Value Name Description
0 DISABLED Disable Timer 2 interrupt.
1 ENABLED Enable interrupt requests generated by the TF2L or TF2H flags.
4 ES1 0 RW UART1 Interrupt Enable.
This bit sets the masking of the UART1 interrupts.
Value Name Description
0 DISABLED Disable UART1 interrupts.
1 ENABLED Enable UART1 interrupts.
3 ET1 0 RW Timer 1 Interrupt Enable.
This bit sets the masking of the Timer 1 interrupt.
Value Name Description
0 DISABLED Disable all Timer 1 interrupt.
1 ENABLED Enable interrupt requests generated by the TF1 flag.
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Bit Name Reset Access Description
2 EX1 0 RW External Interrupt 1 Enable.
This bit sets the masking of External Interrupt 1.
Value Name Description
0 DISABLED Disable external interrupt 1.
1 ENABLED Enable interrupt requests generated by the INT1 input.
1 ET0 0 RW Timer 0 Interrupt Enable.
This bit sets the masking of the Timer 0 interrupt.
Value Name Description
0 DISABLED Disable all Timer 0 interrupt.
1 ENABLED Enable interrupt requests generated by the TF0 flag.
0 EX0 0 RW External Interrupt 0 Enable.
This bit sets the masking of External Interrupt 0.
EFM8UB3 Reference Manual
Interrupts
Value Name Description
0 DISABLED Disable external interrupt 0.
1 ENABLED Enable interrupt requests generated by the INT0 input.
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Interrupts
6.3.2 IP: Interrupt Priority
Bit 7 6 5 4 3 2 1 0
Name Reserved PSPI0 PT2 PS1 PT1 PX1 PT0 PX0
Access R RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0
SFR Page = ALL; SFR Address: 0xB8 (bit-addressable)
Bit Name Reset Access Description
7 Reserved Must write reset value.
6 PSPI0 0 RW Serial Peripheral Interface (SPI0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the SPI0 interrupt.
5 PT2 0 RW Timer 2 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 2 interrupt.
4 PS1 0 RW UART1 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the UART1 interrupt.
3 PT1 0 RW Timer 1 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 1 interrupt.
2 PX1 0 RW External Interrupt 1 Priority Control LSB.
This bit sets the LSB of the priority field for the External Interrupt 1 interrupt.
1 PT0 0 RW Timer 0 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 0 interrupt.
0 PX0 0 RW External Interrupt 0 Priority Control LSB.
This bit sets the LSB of the priority field for the External Interrupt 0 interrupt.
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6.3.3 IPH: Interrupt Priority High
Bit 7 6 5 4 3 2 1 0
Name Reserved PHSPI0 PHT2 PHS1 PHT1 PHX1 PHT0 PHX0
Access R RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0
SFR Page = 0x10; SFR Address: 0xF2
Bit Name Reset Access Description
7 Reserved Must write reset value.
6 PHSPI0 0 RW Serial Peripheral Interface (SPI0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the SPI0 interrupt.
5 PHT2 0 RW Timer 2 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 2 interrupt.
4 PHS1 0 RW UART1 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the UART1 interrupt.
3 PHT1 0 RW Timer 1 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 1 interrupt.
2 PHX1 0 RW External Interrupt 1 Priority Control MSB.
This bit sets the MSB of the priority field for the External Interrupt 1 interrupt.
1 PHT0 0 RW Timer 0 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 0 interrupt.
0 PHX0 0 RW External Interrupt 0 Priority Control MSB.
This bit sets the MSB of the priority field for the External Interrupt 0 interrupt.
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6.3.4 EIE1: Extended Interrupt Enable 1
Bit 7 6 5 4 3 2 1 0
Name ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EMAT ESMB0
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
SFR Page = 0x0, 0x10; SFR Address: 0xE6
Bit Name Reset Access Description
7 ET3 0 RW Timer 3 Interrupt Enable.
This bit sets the masking of the Timer 3 interrupt.
Value Name Description
0 DISABLED Disable Timer 3 interrupts.
1 ENABLED Enable interrupt requests generated by the TF3L or TF3H flags.
6 ECP1 0 RW Comparator1 (CP1) Interrupt Enable.
This bit sets the masking of the CP1 interrupt.
Value Name Description
0 DISABLED Disable CP1 interrupts.
1 ENABLED Enable interrupt requests generated by the comparator 1 CPRIF or
CPFIF flags.
5 ECP0 0 RW Comparator0 (CP0) Interrupt Enable.
This bit sets the masking of the CP0 interrupt.
Value Name Description
0 DISABLED Disable CP0 interrupts.
1 ENABLED Enable interrupt requests generated by the comparator 0 CPRIF or
CPFIF flags.
4 EPCA0 0 RW Programmable Counter Array (PCA0) Interrupt Enable.
This bit sets the masking of the PCA0 interrupts.
Value Name Description
0 DISABLED Disable all PCA0 interrupts.
1 ENABLED Enable interrupt requests generated by PCA0.
3 EADC0 0 RW ADC0 Conversion Complete Interrupt Enable.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
Value Name Description
0 DISABLED Disable ADC0 Conversion Complete interrupt.
1 ENABLED Enable interrupt requests generated by the ADINT flag.
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Bit Name Reset Access Description
2 EWADC0 0 RW ADC0 Window Comparison Interrupt Enable.
This bit sets the masking of ADC0 Window Comparison interrupt.
Value Name Description
0 DISABLED Disable ADC0 Window Comparison interrupt.
1 ENABLED Enable interrupt requests generated by ADC0 Window Compare flag
(ADWINT).
1 EMAT 0 RW Port Match Interrupts Enable.
This bit sets the masking of the Port Match Event interrupt.
Value Name Description
0 DISABLED Disable all Port Match interrupts.
1 ENABLED Enable interrupt requests generated by a Port Match.
0 ESMB0 0 RW SMBus (SMB0) Interrupt Enable.
EFM8UB3 Reference Manual
Interrupts
This bit sets the masking of the SMB0 interrupt.
Value Name Description
0 DISABLED Disable all SMB0 interrupts.
1 ENABLED Enable interrupt requests generated by SMB0.
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6.3.5 EIP1: Extended Interrupt Priority 1 Low
Bit 7 6 5 4 3 2 1 0
Name PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PMAT PSMB0
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
SFR Page = 0x0, 0x10; SFR Address: 0xF3
Bit Name Reset Access Description
7 PT3 0 RW Timer 3 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 3 interrupt.
6 PCP1 0 RW Comparator1 (CP1) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the CP1 interrupt.
5 PCP0 0 RW Comparator0 (CP0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the CP0 interrupt.
4 PPCA0 0 RW Programmable Counter Array (PCA0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the PCA0 interrupt.
3 PADC0 0 RW ADC0 Conversion Complete Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the ADC0 Conversion Complete interrupt.
2 PWADC0 0 RW ADC0 Window Comparator Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the ADC0 Window interrupt.
1 PMAT 0 RW Port Match Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Port Match Event interrupt.
0 PSMB0 0 RW SMBus (SMB0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the SMB0 interrupt.
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6.3.6 EIP1H: Extended Interrupt Priority 1 High
Bit 7 6 5 4 3 2 1 0
Name PHT3 PHCP1 PHCP0 PHPCA0 PHADC0 PHWADC0 PHMAT PHSMB0
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
SFR Page = 0x10; SFR Address: 0xF5
Bit Name Reset Access Description
7 PHT3 0 RW Timer 3 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 3 interrupt.
6 PHCP1 0 RW Comparator1 (CP1) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the CP1 interrupt.
5 PHCP0 0 RW Comparator0 (CP0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the CP0 interrupt.
4 PHPCA0 0 RW Programmable Counter Array (PCA0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the PCA0 interrupt.
3 PHADC0 0 RW ADC0 Conversion Complete Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the ADC0 Conversion Complete interrupt.
2 PHWADC0 0 RW ADC0 Window Comparator Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the ADC0 Window interrupt.
1 PHMAT 0 RW Port Match Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Port Match Event interrupt.
0 PHSMB0 0 RW SMBus (SMB0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the SMB0 interrupt.
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6.3.7 EIE2: Extended Interrupt Enable 2
Bit 7 6 5 4 3 2 1 0
Name Reserved ECL0 Reserved ET5 ET4 EVBUS EUSB0
Access RW RW RW RW RW RW RW
Reset 0 0 0x0 0 0 0 0
SFR Page = 0x10; SFR Address: 0xCE
Bit Name Reset Access Description
7 Reserved Must write reset value.
6 ECL0 0 RW Configurable Logic (CL0) Interrupt Enable.
This bit sets the masking of the CL0 interrupts.
Value Name Description
0 DISABLED Disable CL0 interrupts.
1 ENABLED Enable interrupt requests generated by CL0.
5:4 Reserved Must write reset value.
3 ET5 0 RW Timer 5 Interrupt Enable.
This bit sets the masking of the Timer 5 interrupt.
Value Name Description
0 DISABLED Disable Timer 5 interrupts.
1 ENABLED Enable interrupt requests generated by the TF5L or TF5H flags.
2 ET4 0 RW Timer 4 Interrupt Enable.
This bit sets the masking of the Timer 4 interrupt.
Value Name Description
0 DISABLED Disable Timer 4 interrupts.
1 ENABLED Enable interrupt requests generated by the TF4L or TF4H flags.
1 EVBUS 0 RW VBUS and USB Charger Detect Interrupt.
This bit sets the masking of the VBUS and VBUS and USB Charger Detect interrupts.
Value Name Description
0 DISABLED Disable all VBUS and VBUS and USB Charger Detect interrupts.
1 ENABLED Enable interrupt requests generated by VBUS and VBUS and USB
Charger Detect.
0 EUSB0 0 RW USB (USB0) Interrupt Enable.
This bit sets the masking of the USB0 interrupt.
Value Name Description
0 DISABLED Disable all USB0 interrupts.
1 ENABLED Enable interrupt requests generated by USB0.
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6.3.8 EIP2: Extended Interrupt Priority 2
Bit 7 6 5 4 3 2 1 0
Name Reserved PCL0 Reserved PT5 PT4 PVBUS PUSB0
Access RW RW RW RW RW RW RW
Reset 0 0 0x0 0 0 0 0
SFR Page = 0x10; SFR Address: 0xF4
Bit Name Reset Access Description
7 Reserved Must write reset value.
6 PCL0 0 RW Configurable Logic (CL0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the CL0 interrupt.
5:4 Reserved Must write reset value.
3 PT5 0 RW Timer 5 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 5 interrupt.
2 PT4 0 RW Timer 4 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 4 interrupt.
1 PVBUS 0 RW VBUS and USB Charger Detect Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the VBUS and USB Charger Detect interrupt.
0 PUSB0 0 RW USB (USB0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for USB0 interrupts.
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6.3.9 EIP2H: Extended Interrupt Priority 2 High
Bit 7 6 5 4 3 2 1 0
Name Reserved PHCL0 Reserved PHT5 PHT4 PHVBUS PHUSB0
Access RW RW RW RW RW RW RW
Reset 0 0 0x0 0 0 0 0
SFR Page = 0x10; SFR Address: 0xF6
Bit Name Reset Access Description
7 Reserved Must write reset value.
6 PHCL0 0 RW Configurable Logic (CL0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the CL0 interrupt.
5:4 Reserved Must write reset value.
3 PHT5 0 RW Timer 5 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 5 interrupt.
2 PHT4 0 RW Timer 4 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 4 interrupt.
1 PHVBUS 0 RW VBUS and USB Charger Detect Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the VBUS and USB Charger Detect interrupt.
0 PHUSB0 0 RW USB (USB0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for USB0 interrupts.
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Power Management and Internal Regulators
7. Power Management and Internal Regulators
7.1 Introduction
Control over the device power consumption can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their
clocks gated off and draw little power when they are not in use.
Power Distribution
VREGIN
VDD
GND
5V LDO
3.3V
USB PHY
Core LDO
Figure 7.1. Power System Block Diagram
1.8V
CPU Core
Oscillators
Peripheral
RAM
Flash
Logic
Digital I/O
Interface
Analog
Muxes
D+
D-
VIO
Port I/O Pins
Table 7.1. Power Modes
Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational — —
Idle • Core halted
Set IDLE bit in PCON0 Any interrupt
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Suspend • Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in normal bias mode for fast wake
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• Port Match Event
• Comparator 0 Falling
Edge
• CLUn Interrupt-Enabled
Event
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Power Mode Details Mode Entry Wake-Up Sources
Stop • All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO on
• Pins retain state
1. Clear STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
Any reset source
• Exit on any reset source
Snooze • Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in low bias current mode for energy savings
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SNOOZE bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• Port Match Event
• Comparator 0 Falling
Edge
• CLUn Interrupt-Enabled
Event
Shutdown • All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO off to save energy
• Pins retain state
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
• RSTb pin reset
• Power-on reset
• Exit on pin or power-on reset
7.2 Features
The power management features of these devices include:
• Supports five power modes:
1. Normal mode: Core and all peripherals fully operational.
2. Idle mode: Core halted, peripherals fully operational, core waiting for interrupt to continue.
3. Suspend mode: High-frequency internal clocks halted, select peripherals active, waiting for wake signal to continue.
4. Snooze mode: High-frequency internal clocks halted, select peripherals active, regulators in low-power mode, waiting for wake
signal to continue.
5. Shutdown mode: All clocks stopped and internal LDO shut off, device waiting for POR or pin reset.
Note: Legacy 8051 Stop mode is also supported, but Suspend and Snooze offer more functionality with better power consumption.
• Internal Core LDO:
• Supplies power to majority of blocks.
• Low power consumption in Snooze mode, can be shut down completely in Shutdown mode.
• 5V-to-3.3V Regulator:
• Allows direct connection to USB supply net.
• Provides up to 100 mA for system-level use.
• Low power consumption in Snooze mode.
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7.3 Idle Mode
In idle mode, CPU core execution is halted while any enabled peripherals and clocks remain active. Power consumption in idle mode is
dependent upon the system clock frequency and any active peripherals.
Setting the IDLE bit in the PCON0 register causes the hardware to halt the CPU and enter idle mode as soon as the instruction that
sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can
remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the
IDLE bit to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed
after the return from interrupt (RETI) will be the instruction immediately following the one that set the IDLE bit. If idle mode is terminated
by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the execution phase
of the instruction that sets the IDLE bit, the CPU may not wake from idle mode when a future interrupt occurs. Therefore, instructions
that set the IDLE bit should be followed by an instruction that has two or more opcode bytes. For example:
// in ‘C’:
PCON0 |= 0x01; // set IDLE bit
PCON0 = PCON0; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON0, #01h ; set IDLE bit
MOV PCON0, PCON0 ; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON0 register. If this
behavior is not desired, the WDT may be disabled by software prior to entering the idle mode if the WDT was initially configured to
allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the idle mode indefinitely, waiting for an external stimulus to wake up the system.
7.4 Stop Mode
In stop mode, the CPU is halted and peripheral clocks are stopped. Analog peripherals remain in their selected states.
Setting the STOP bit in the PCON0 register causes the controller core to enter stop mode as soon as the instruction that sets the bit
completes execution. Before entering stop mode, the system clock must be sourced by HFOSC0. In stop mode, the CPU and internal
clocks are stopped. Analog peripherals may remain enabled, but will not be provided a clock. Each analog peripheral may be shut down
individually by firmware prior to entering stop mode. Stop mode can only be terminated by an internal or external reset. On reset, the
device performs the normal reset sequence and begins program execution at address 0x0000.
If enabled as a reset source, the missing clock detector will cause an internal reset and thereby terminate the stop mode. If this reset is
undesirable in the system, and the CPU is to be placed in stop mode for longer than the missing clock detector timeout, the missing
clock detector should be disabled in firmware prior to setting the STOP bit.
7.5 Suspend Mode
Suspend mode is entered by setting the SUSPEND bit while operating from the internal 24.5 MHz oscillator (HFOSC0). Upon entry into
suspend mode, the hardware halts both of the high-frequency internal oscillators and goes into a low power state as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data.
Suspend mode is terminated by any enabled wake or reset source. When suspend mode is terminated, the device will continue execution on the instruction following the one that set the SUSPEND bit. If the wake event was configured to generate an interrupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an internal or external reset, the CIP-51 performs a
normal reset sequence and begins program execution at address 0x0000.
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7.6 Snooze Mode
Snooze mode is entered by setting the SNOOZE bit while operating from the internal 24.5 MHz oscillator (HFOSC0). Upon entry into
snooze mode, the hardware halts both of the high-frequency internal oscillators and goes into a low power state as soon as the instruction that sets the bit completes execution. The internal LDO is then placed into a low-current standby mode. All internal registers and
memory maintain their original data.
Snooze mode is terminated by any enabled wake or reset source. When snooze mode is terminated, the LDO is returned to normal
operating conditions and the device will continue execution on the instruction following the one that set the SNOOZE bit. If the wake
event was configured to generate an interrupt, the interrupt will be serviced upon waking the device. If snooze mode is terminated by an
internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
7.7 Shutdown Mode
In shutdown mode, the CPU is halted and the internal LDO is powered down. External I/O will retain their configured states.
To enter Shutdown mode, firmware should set the STOPCF bit in the regulator control register to 1, and then set the STOP bit in
PCON0. In Shutdown, the RSTb pin and a full power cycle of the device are the only methods of generating a reset and waking the
device.
Note: In Shutdown mode, all internal device circuitry is powered down, and no RAM nor registers are retained. The debug circuitry will
not be able to connect to a device while it is in Shutdown. Coming out of Shutdown mode, whether by POR or pin reset, will appear as
a power-on reset of the device.
7.8 5V-to-3.3V Regulator
The 5-to-3.3 V regulator is powered from the VREGIN pin on the device. When active, it regulates the input voltage to 3.3 V at the VDD
pin, providing up to 100 mA for the device and system. In addition to the normal mode of operation, the regulator has two low power
modes which may be used to reduce the supply current, and may be disabled when not in use.
Table 7.2. Voltage Regulator Operational Modes
Regulator Condition SUSEN Bit BIASENB Bit REG1ENB Bit Relative Power Consumption
Normal 0 0 0 highest
Suspend 1 0 0 low
Bias Disabled x 1 0 extremely low
Disabled x 1 1 off
The voltage regulator is enabled in normal mode by default. Normal mode offers the fastest response times, for systems with dynamically-changing loads.
For applications which can tolerate a lower regulator bandwidth but still require a tightly regulated output voltage, the regulator may be
placed in suspend mode. Suspend mode is activated when firmware sets the SUSEN bit. Suspend mode reduces the regulator bias
current at the expense of bandwidth.
For low power applications that can tolerate reduced output voltage accuracy and load regulation, the internal bias current may be disabled completely using the BIASENB bit. If firmware sets the BIASENB bit, the regulator will regulate the voltage using a method that is
more susceptible to process and temperature variations. In addition, the actual output voltage may drop substantially under heavy
loads. The bias should only be disabled for light loads (5 mA or less) or when the voltage regulator is disabled.
If the regulator is not used in a system, the VREGIN and VDD pins should be connected together. Firmware may disable the regulator
by writing both the REG1ENB and BIASENB bits in REG1CN to turn off the regulator and all associated bias currents.
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7.9 Power Management Control Registers
7.9.1 PCON0: Power Control
Bit 7 6 5 4 3 2 1 0
Name GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
SFR Page = ALL; SFR Address: 0x87
Bit Name Reset Access Description
7 GF5 0 RW General Purpose Flag 5.
This flag is a general purpose flag for use under firmware control.
6 GF4 0 RW General Purpose Flag 4.
This flag is a general purpose flag for use under firmware control.
5 GF3 0 RW General Purpose Flag 3.
This flag is a general purpose flag for use under firmware control.
4 GF2 0 RW General Purpose Flag 2.
This flag is a general purpose flag for use under firmware control.
3 GF1 0 RW General Purpose Flag 1.
This flag is a general purpose flag for use under firmware control.
2 GF0 0 RW General Purpose Flag 0.
This flag is a general purpose flag for use under firmware control.
1 STOP 0 RW Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
0 IDLE 0 RW Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
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7.9.2 PCON1: Power Control 1
Bit 7 6 5 4 3 2 1 0
Name SNOOZE SUSPEND Reserved
Access RW RW R
Reset 0 0 0x00
SFR Page = ALL; SFR Address: 0xE4
Bit Name Reset Access Description
7 SNOOZE 0 RW Snooze Mode Select.
Setting this bit will place the device in snooze mode. High speed oscillators will be halted the SYSCLK signal will be gated
off, and the internal regulator will be placed in a low power state.
6 SUSPEND 0 RW Suspend Mode Select.
Setting this bit will place the device in suspend mode. High speed oscillators will be halted and the SYSCLK signal will be
gated off.
5:0 Reserved Must write reset value.
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7.9.3 PSTAT0: Power Status
Bit 7 6 5 4 3 2 1 0
Name Reserved CL0WK USB0RWK SPI0WK TMR4WK PMATWK CPT0WK
Access RW RW RW RW RW RW RW
Reset 0x0 0 0 0 0 0 0
SFR Page = 0x10; SFR Address: 0xAD
Bit Name Reset Access Description
7:6 Reserved Must write reset value.
5 CL0WK 0 RW CL0 Wake-up Event.
Value Name Description
0 NOT_SET A CL0 interrupt-enabled event did not occur.
1 SET A CL0 interrupt-enabled event occurred.
4 USB0RWK 0 RW USB0 Resume Wake-up Event.
Value Name Description
0 NOT_SET A USB Resume wake up event did not occur.
1 SET A USB Resume wake up event occurred.
3 SPI0WK 0 RW SPI0 Slave Wake-up Event.
Value Name Description
0 NOT_SET The SPI0 Slave did not receive a byte.
1 SET The SPI0 Slave received a byte.
2 TMR4WK 0 RW Timer 4 Wake-up Event.
Value Name Description
0 NOT_SET A Timer 4 overflow event did not occur.
1 SET A Timer 4 overflow event occurred.
1 PMATWK 0 RW Port Match Wake-up Event.
Value Name Description
0 NOT_SET A Port Match event did not occur.
1 SET A Port Match event occurred.
0 CPT0WK 0 RW Comparator 0 Wake-up Event.
Value Name Description
0 NOT_SET A comparator 0 output falling edge event did not occur.
1 SET A comparator 0 output falling edge event occurred.
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7.9.4 REG0CN: Voltage Regulator 0 Control
Bit 7 6 5 4 3 2 1 0
Name Reserved STOPCF Reserved
Access R RW R
Reset 0x0 0 0x0
SFR Page = 0x0, 0x20; SFR Address: 0xC9
Bit Name Reset Access Description
7:4 Reserved Must write reset value.
3 STOPCF 0 RW Stop and Shutdown Mode Configuration.
This bit configures the regulator's behavior when the device enters stop mode.
Value Name Description
0 ACTIVE Regulator is still active in stop mode. Any enabled reset source will re-
set the device.
1 SHUTDOWN Regulator is shut down in stop mode (device enters Shutdown mode).
Only the RSTb pin or power cycle can reset the device.
2:0 Reserved Must write reset value.
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7.9.5 REG1CN: Voltage Regulator 1 Control
Bit 7 6 5 4 3 2 1 0
Name REG1ENB Reserved BIASENB SUSEN Reserved
Access RW R RW RW R
Reset 0 0x0 0 0 0
SFR Page = 0x20; SFR Address: 0xC6
Bit Name Reset Access Description
7 REG1ENB 0 RW Voltage Regulator 1 Disable.
This bit may be used to disable the 5V regulator if an external regulator is used to power VDD. VREGIN should be tied to
VDD in any system that disables this regulator.
6:3 Reserved Must write reset value.
2 BIASENB 0 RW Regulator Bias Disable.
The BIASENB bit disables the regulator bias voltage when set to 1.
Value Name Description
0 ENABLED Regulator bias is enabled.
1 DISABLED Regulator bias is disabled.
1 SUSEN 0 RW Voltage Regulator 1 Suspend Enable.
When set to 1, this bit places the 5V regulator into suspend mode.
Value Name Description
0 NORMAL The 5V regulator is in normal power mode. Normal mode is the highest
performance mode for the regulator.
1 SUSPEND The 5V regulator is in suspend power mode. Suspend mode reduces
the regulator bias current, but increases the response times.
0 Reserved Must write reset value.
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8. Clocking and Oscillators
8.1 Introduction
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
Clock Control
48 MHz Oscillator
(HFOSC1)
24.5 MHz
Oscillator
(HFOSC0)
External Clock
Input (EXTCLK)
80 kHz Oscillator
(LFOSC0)
/1.5
/1.5
Divider:
1, 2, 4, 8
Programmable
Divider:
1, 2, 4...128
To core and peripherals
Figure 8.1. Clock Control Block Diagram
8.2 Features
The clock control system offers the following features:
• Provides clock to core and peripherals.
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
• 48 MHz internal oscillator (HFOSC1), accurate to ±1.5% over supply and temperature corners.
• 80 kHz low-frequency oscillator (LFOSC0).
• External CMOS clock input (EXTCLK).
• Clock divider with eight settings for flexible clock scaling:
• Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
• HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility.
SYSCLK
To WDT
8.3 Functional Description
8.3.1 Clock Selection
The CLKSEL register is used to select the clock source for the system (SYSCLK). The CLKSL field selects which oscillator source is
used as the system clock, while CLKDIV controls the programmable divider. When an internal oscillator source is selected as the
SYSCLK, the external oscillator may still clock certain peripherals. In these cases, the external oscillator source is synchronized to the
SYSCLK source. The system clock may be switched on-the-fly between any of the oscillator sources so long as the selected clock
source is enabled and has settled, and CLKDIV may be changed at any time.
Note: Some device families do place restrictions on the difference in operating frequency when switching clock sources. Please see the
CLKSEL register description for details.
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8.3.2 HFOSC0 24.5 MHz Internal Oscillator
HFOSC0 is a programmable internal high-frequency oscillator that is factory-calibrated to 24.5 MHz. The oscillator is automatically enabled when it is requested. The oscillator period can be adjusted via the HFO0CAL register to obtain other frequencies.
Note: Changing the HFO0CAL register value from its default value may degrade the frequency stability of the oscillator across temperature and supply voltage.
8.3.3 HFOSC1 48 MHz Internal Oscillator
HFOSC1 is a programmable internal high-frequency oscillator that is factory-calibrated to 48 MHz. The oscillator is automatically enabled when it is requested. The oscillator period can be adjusted via the HFO1CAL register to obtain other frequencies.
Note: Changing the HFO1CAL register value from its default value may degrade the frequency stability of the oscillator across temperature and supply voltage.
Note: HFOSC0 consumes less current when enabled than HFOSC1.
8.3.4 LFOSC0 80 kHz Internal Oscillator
LFOSC0 is a progammable low-frequency oscillator, factory calibrated to a nominal frequency of 80 kHz. A dedicated divider at the
oscillator output is capable of dividing the output clock by 1, 2, 4, or 8, using the OSCLD bits in the LFO0CN register. The OSCLF bits
can be used to coarsely adjust the oscillator’s output frequency.
The LFOSC0 circuit requires very little start-up time and may be selected as the system clock immediately following the register write
which enables the oscillator.
Calibrating LFOSC0
On-chip calibration of the LFOSC0 can be performed using a timer to capture the oscillator period, when running from a known time
base. When a timer is configured for L-F Oscillator capture mode, a falling edge of the low-frequency oscillator’s output will cause a
capture event on the corresponding timer. As a capture event occurs, the current timer value is copied into the timer reload registers.
By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The
OSCLF bits can then be adjusted to produce the desired oscillator frequency.
8.3.5 External Clock
An external CMOS clock source is also supported as a core clock source. The EXTCLK pin on the device serves as the external clock
input when running in this mode. The EXTCLK input may also be used to clock certain digital peripherals (e.g., Timers, PCA, etc.) while
SYSCLK runs from one of the internal oscillator sources. When not selected as the SYSCLK source, the EXTCLK input is always resynchronized to SYSCLK.
Note: When selecting the EXTCLK pin as a clock input source, the pin should be skipped in the crossbar and configured as a digital
input. Firmware should ensure that the external clock source is present or enable the missing clock detector before switching the
CLKSL field.
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Clocking and Oscillators
8.4 Clocking and Oscillator Control Registers
8.4.1 CLKSEL: Clock Select
Bit 7 6 5 4 3 2 1 0
Name DIVRDY CLKDIV Reserved CLKSL
Access R RW R RW
Reset 1 0x3 0 0x0
SFR Page = ALL; SFR Address: 0xA9
Bit Name Reset Access Description
7 DIVRDY 1 R Clock Divider Ready.
Indicates when the clock has propagated through the divider with the current CLKDIV setting.
Value Name Description
0 NOT_READY Clock has not propagated through divider yet.
1 READY Clock has propagated through divider.
6:4 CLKDIV 0x3 RW Clock Source Divider.
This field controls the divider applied to the clock source selected by CLKSL. The output of this divider is the system clock
(SYSCLK).
Value Name Description
0x0 SYSCLK_DIV_1 SYSCLK is equal to selected clock source divided by 1.
0x1 SYSCLK_DIV_2 SYSCLK is equal to selected clock source divided by 2.
0x2 SYSCLK_DIV_4 SYSCLK is equal to selected clock source divided by 4.
0x3 SYSCLK_DIV_8 SYSCLK is equal to selected clock source divided by 8.
0x4 SYSCLK_DIV_16 SYSCLK is equal to selected clock source divided by 16.
0x5 SYSCLK_DIV_32 SYSCLK is equal to selected clock source divided by 32.
0x6 SYSCLK_DIV_64 SYSCLK is equal to selected clock source divided by 64.
0x7 SYSCLK_DIV_128 SYSCLK is equal to selected clock source divided by 128.
3 Reserved Must write reset value.
2:0 CLKSL 0x0 RW Clock Source Select.
Selects the system clock source.
Value Name Description
0x0 HFOSC0 Clock derived from the Internal High Frequency Oscillator 0.
0x1 EXTOSC Clock derived from the External Oscillator circuit.
0x2 LFOSC Clock derived from the Internal Low-Frequency Oscillator.
0x3 HFOSC1 Clock derived from the Internal High Frequency Oscillator 1.
0x4 HFOSC0_DIV_1P5 Clock derived from the Internal High Frequency Oscillator 0, pre-scaled
by 1.5.
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Bit Name Reset Access Description
0x7 HFOSC1_DIV_1P5 Clock derived from the Internal High Frequency Oscillator 1, pre-scaled
by 1.5.
This device family has restrictions when switching to clock sources that are greater than 25 MHz. SYSCLK must be running at a frequency of 24 MHz or greater before switching the CLKSL field to HFOSC1. When transitioning from slower clock frequencies, firmware should make two writes to CLKSEL.
8.4.2 HFO0CAL: High Frequency Oscillator 0 Calibration
Bit 7 6 5 4 3 2 1 0
Name HFO0CAL
Access RW
Reset Varies
SFR Page = 0x0, 0x10; SFR Address: 0xC7
Bit Name Reset Access Description
7:0 HFO0CAL Varies RW Oscillator Calibration.
These bits determine the period for high frequency oscillator 0. When set to 0x00, the oscillator operates at its fastest setting. When set to 0xFF, the oscillator operates at its slowest setting. The reset value is factory calibrated, and the oscillator
will revert to the calibrated frequency upon reset.
8.4.3 HFO1CAL: High Frequency Oscillator 1 Calibration
Bit 7 6 5 4 3 2 1 0
Name Reserved HFO1CAL
Access R RW
Reset 0 Varies
SFR Page = 0x10; SFR Address: 0xD6
Bit Name Reset Access Description
7 Reserved Must write reset value.
6:0 HFO1CAL Varies RW Oscillator Calibration.
These bits determine the period for high frequency oscillator 1. When set to 0x00, the oscillator operates at its fastest setting. When set to 0x7F, the oscillator operates at its slowest setting. The reset value is factory calibrated, and the oscillator
will revert to the calibrated frequency upon reset.
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8.4.4 HFOCN: High Frequency Oscillator Control
Bit 7 6 5 4 3 2 1 0
Name HFO1EN Reserved HFO0EN Reserved
Access RW R RW R
Reset 0 0x0 0 0x0
SFR Page = 0x10; SFR Address: 0xEF
Bit Name Reset Access Description
7 HFO1EN 0 RW HFOSC1 Oscillator Enable.
Value Name Description
0 DISABLED Disable High Frequency Oscillator 1 (HFOSC1 will still turn on if re-
quested by any block in the device or selected as the SYSCLK source).
1 ENABLED Force High Frequency Oscillator 1 to run.
6:4 Reserved Must write reset value.
3 HFO0EN 0 RW HFOSC0 Oscillator Enable.
Value Name Description
0 DISABLED Disable High Frequency Oscillator 0 (HFOSC0 will still turn on if re-
quested by any block in the device or selected as the SYSCLK source).
1 ENABLED Force High Frequency Oscillator 0 to run.
2:0 Reserved Must write reset value.
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Clocking and Oscillators
8.4.5 LFO0CN: Low Frequency Oscillator Control
Bit 7 6 5 4 3 2 1 0
Name OSCLEN OSCLRDY OSCLF OSCLD
Access RW R RW RW
Reset 0 1 Varies 0x3
SFR Page = 0x0, 0x10; SFR Address: 0xB1
Bit Name Reset Access Description
7 OSCLEN 0 RW Internal L-F Oscillator Enable.
This bit enables the internal low-frequency oscillator. Note that the low-frequency oscillator is automatically enabled when
the watchdog timer is active.
Value Name Description
0 DISABLED Internal L-F Oscillator Disabled.
1 ENABLED Internal L-F Oscillator Enabled.
6 OSCLRDY 1 R Internal L-F Oscillator Ready.
Value Name Description
0 NOT_SET Internal L-F Oscillator frequency not stabilized.
1 SET Internal L-F Oscillator frequency stabilized.
5:2 OSCLF Varies RW Internal L-F Oscillator Frequency Control.
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the L-F oscillator operates at its fastest
setting. When set to 1111b, the L-F oscillator operates at its slowest setting. The OSCLF bits should only be changed by
firmware when the L-F oscillator is disabled (OSCLEN = 0).
1:0 OSCLD 0x3 RW Internal L-F Oscillator Divider Select.
Value Name Description
0x0 DIVIDE_BY_8 Divide by 8 selected.
0x1 DIVIDE_BY_4 Divide by 4 selected.
0x2 DIVIDE_BY_2 Divide by 2 selected.
0x3 DIVIDE_BY_1 Divide by 1 selected.
OSCLRDY is only set back to 0 in the event of a device reset or a change to the OSCLD bits.
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Reset Sources and Power Supply Monitor
9. Reset Sources and Power Supply Monitor
9.1 Introduction
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset Sources
RSTb
Supply Monitor or
Power-up
Missing Clock Detector
Watchdog Timer
Software Reset
Comparator 0
Flash Error
USB Reset
9.2 Features
Reset sources on the device include:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• USB reset
system reset
Figure 9.1. Reset Sources Block Diagram
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9.3 Functional Description
9.3.1 Device Reset
Upon entering a reset state from any source, the following events occur:
• The processor core halts program execution.
• Special Function Registers (SFRs) are initialized to their defined reset values.
• External port pins are placed in a known state.
• Interrupts and timers are disabled.
SFRs are reset to the predefined reset values noted in the detailed register descriptions. The contents of internal data memory are
unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For
Supply Monitor and power-on resets, the RSTb pin is driven low until the device exits the reset state.
Note: During a power-on event, there may be a short delay before the POR circuitry fires and the RSTb pin is driven low. During that
time, the RSTb pin will be weakly pulled to the supply pin.
On exit from the reset state, the program counter (PC) is reset, the watchdog timer is enabled, and the system clock defaults to an
internal oscillator. Program execution begins at location 0x0000.
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9.3.2 Power-On Reset
During power-up, the POR circuit fires. When POR fires, the device is held in a reset state and the RSTb pin is driven low until the
supply voltage settles above V
. Two delays are present during the supply ramp time. First, a delay occurs before the POR circuitry
RST
fires and pulls the RSTb pin low. A second delay occurs before the device is released from reset; the delay decreases as the supply
ramp time (T
supply must reach V
) increases (supply ramp time is defined as how fast the supply pin ramps from 0 V to V
RMP
before the POR circuit releases the device from reset.
RST
). Additionally, the power
RST
On exit from a power-on reset, the PORSF flag is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the
RSTSRC register are indeterminate. (PORSF is cleared by all other resets.) Since all resets cause program execution to begin at the
same location (0x0000), software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal
data memory should be assumed to be undefined after a power-on reset. The supply monitor is enabled following a power-on reset.
volts
Logic HIGH
Logic LOW
RSTb
Supply Voltage
T
POR
Power-On Reset
t
Figure 9.2. Power-On Reset Timing
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9.3.3 Supply Monitor Reset
The supply monitor senses the voltage on the device's supply pin and can generate a reset if the supply drops below the corresponding
threshold. This monitor is enabled and enabled as a reset source after initial power-on to protect the device until the supply is an adequate and stable voltage. When enabled and selected as a reset source, any power down transition or power irregularity that causes
the supply to drop below the reset threshold will drive the RSTb pin low and hold the core in a reset state. When the supply returns to a
level above the reset threshold, the monitor will release the core from the reset state. The reset status can then be read using the device reset sources module. After a power-fail reset, the PORF flag reads 1 and all of the other reset flags in the RSTSRC register are
indeterminate. The power-on reset delay (t
invalid after a supply monitor reset. The enable state of the supply monitor and its selection as a reset source is not altered by device
resets. For example, if the supply monitor is de-selected as a reset source and disabled by software using the VDMEN bit in the
VDM0CN register, and then firmware performs a software reset, the supply monitor will remain disabled and de-selected after the reset.
To protect the integrity of flash contents, the supply monitor must be enabled and selected as a reset source if software contains routines that erase or write flash memory. If the supply monitor is not enabled, any erase or write performed on flash memory will be ignored.
) is not incurred after a supply monitor reset. The contents of RAM should be presumed
POR
Reset Threshold
(V
RST
RSTb
volts
)
Supply Monitor
Reset
Supply Voltage
t
Figure 9.3. Reset Sources
9.3.4 External Reset
The external RSTb pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on
the RSTb pin generates a reset; an external pullup and/or decoupling of the RSTb pin may be necessary to avoid erroneous noiseinduced resets. The PINRSF flag is set on exit from an external reset.
9.3.5 Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock remains high or low for
more than the MCD time window, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag will read 1,
signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector;
writing a 0 disables it. The state of the RSTb pin is unaffected by this reset.
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9.3.6 Comparator (CMP0) Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag. Comparator0 should be enabled and allowed to
settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0
reset is active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag will read 1 signifying Comparator0 as the reset source; otherwise, this bit
reads 0. The state of the RSTb pin is unaffected by this reset.
9.3.7 Watchdog Timer Reset
The programmable Watchdog Timer (WDT) can be used to prevent software from running out of control during a system malfunction.
The WDT function can be enabled or disabled by software as described in the watchdog timer section. If a system malfunction prevents
user software from updating the WDT, a reset is generated and the WDTRSF bit is set to 1. The state of the RSTb pin is unaffected by
this reset.
9.3.8 Flash Error Reset
If a flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the
following:
• A flash write or erase is attempted above user code space.
• A flash read is attempted above user code space.
• A program read is attempted above user code space (i.e., a branch instruction to the reserved area).
• A flash read, write or erase attempt is restricted due to a flash security setting.
The FERROR bit is set following a flash error reset. The state of the RSTb pin is unaffected by this reset.
9.3.9 Software Reset
Software may force a reset by writing a 1 to the SWRSF bit. The SWRSF bit will read 1 following a software forced reset. The state of
the RSTb pin is unaffected by this reset.
9.3.10 USB Reset
Writing 1 to the USBRSF bit selects USB0 as a reset source. With USB0 selected as a reset source, a system reset will be generated
when either of the following occur:
• RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be enabled for RESET signaling to be
detected.
• A falling or rising voltage on the VBUS pin.
The USBRSF bit will read 1 following a USB reset. The state of the RSTb pin is unaffected by this reset.
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Reset Sources and Power Supply Monitor
9.4 Reset Sources and Supply Monitor Control Registers
9.4.1 RSTSRC: Reset Source
Bit 7 6 5 4 3 2 1 0
Name USBRSF FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Access RW R RW RW R RW RW R
Reset Varies Varies Varies Varies Varies Varies Varies Varies
SFR Page = 0x0; SFR Address: 0xEF
Bit Name Reset Access Description
7 USBRSF Varies RW USB Reset Enable and Flag.
Read: This bit reads 1 if USB caused the last reset.
Write: Writing a 1 to this bit enables the USB0 module as a reset source.
6 FERROR Varies R Flash Error Reset Flag.
This read-only bit is set to '1' if a flash read/write/erase error caused the last reset.
5 C0RSEF Varies RW Comparator0 Reset Enable and Flag.
Read: This bit reads 1 if Comparator 0 caused the last reset.
Write: Writing a 1 to this bit enables Comparator 0 (active-low) as a reset source.
4 SWRSF Varies RW Software Reset Force and Flag.
Read: This bit reads 1 if last reset was caused by a write to SWRSF.
Write: Writing a 1 to this bit forces a system reset.
3 WDTRSF Varies R Watchdog Timer Reset Flag.
This read-only bit is set to '1' if a watchdog timer overflow caused the last reset.
2 MCDRSF Varies RW Missing Clock Detector Enable and Flag.
Read: This bit reads 1 if a missing clock detector timeout caused the last reset.
Write: Writing a 1 to this bit enables the missing clock detector. The MCD triggers a reset if a missing clock condition is
detected.
1 PORSF Varies RW Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset
Enable.
Read: This bit reads 1 anytime a power-on or supply monitor reset has occurred.
Write: Writing a 1 to this bit enables the supply monitor as a reset source.
0 PINRSF Varies R HW Pin Reset Flag.
This read-only bit is set to '1' if the RSTb pin caused the last reset.
Reads and writes of the RSTSRC register access different logic in the device. Reading the register always returns status information
to indicate the source of the most recent reset. Writing to the register activates certain options as reset sources. It is recommended to
not use any kind of read-modify-write operation on this register.
When the PORSF bit reads back '1' all other RSTSRC flags are indeterminate.
Writing '1' to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset.
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9.4.2 VDM0CN: Supply Monitor Control
Bit 7 6 5 4 3 2 1 0
Name VDMEN VDDSTAT Reserved
Access RW R R
Reset Varies Varies Varies
SFR Page = 0x0; SFR Address: 0xFF
Bit Name Reset Access Description
7 VDMEN Varies RW Supply Monitor Enable.
This bit turns the supply monitor circuit on/off. The supply monitor cannot generate system resets until it is also selected as
a reset source in register RSTSRC. Selecting the supply monitor as a reset source before it has stabilized may generate a
system reset. In systems where this reset would be undesirable, a delay should be introduced between enabling the supply
monitor and selecting it as a reset source.
Value Name Description
0 DISABLED Supply Monitor Disabled.
1 ENABLED Supply Monitor Enabled.
6 VDDSTAT Varies R Supply Status.
This bit indicates the current power supply status (supply monitor output).
Value Name Description
0 BELOW VDD is at or below the supply monitor threshold.
1 ABOVE VDD is above the supply monitor threshold.
5:0 Reserved Must write reset value.
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DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE
POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
D8
STACK POINTER
D8
EFM8UB3 Reference Manual
CIP-51 Microcontroller Core
10. CIP-51 Microcontroller Core
10.1 Introduction
The CIP-51 microcontroller core is a high-speed, pipelined, 8-bit core utilizing the standard MCS-51™ instruction set. Any standard
803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included
with a standard 8051. The CIP-51 includes on-chip debug hardware and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control system solution.
Figure 10.1. CIP-51 Block Diagram
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CIP-51 Microcontroller Core
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. The
CIP-51 core executes 76 of its 109 instructions in one or two clock cycles, with no instructions taking more than eight clock cycles. The
table below shows the distribution of instructions vs. the number of clock cycles required for execution.
Table 10.1. Instruction Execution Timing
Clocks to
1 2 2 or 3* 3 3 or 4* 4 4 or 5* 5 8
Execute
Number of
26 50 5 14 7 3 1 2 1
Instructions
Notes:
1. Conditional branch instructions (indicated by "2 or 3*", "3 or 4*" and "4 or 5*") require extra clock cycles if the branch is taken. See
the instruction table for more information.
10.2 Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals
and functions to extend its capability. The CIP-51 includes the following features:
• Fast, efficient, pipelined architecture.
• Fully compatible with MCS-51 instruction set.
• 0 to 50 MHz operating clock frequency.
• 50 MIPS peak throughput with 50 MHz clock.
• Extended interrupt handler.
• Power management modes.
• On-chip debug logic.
• Program and data memory security.
10.3 Functional Description
10.3.1 Programming and Debugging Support
In-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire development interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and
reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM,
stack, timers, or other on-chip resources.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via
the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.
10.3.2 Prefetch Engine
The CIP-51 core incorporates a multi-byte prefetch engine to enable faster core clock speeds. Because the access time of the flash
memory is 40 ns, and the minimum instruction time is 13.6 ns, the prefetch engine is necessary for full-speed code execution. Multiple
instruction bytes are read from flash memory by the prefetch engine and given to the CIP-51 processor core to execute. When running
linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed. When a code
branch occurs, the processor may be stalled for up to five clock cycles (FLRT = 2) or three clock cycles (FLRT = 1) while the next set of
code bytes is retrieved from flash memory.
When operating at speeds greater than 25 MHz, the prefetch engine must be used. To enable the prefetch engine, the FLRT bit field
should be configured to the desired speed setting. For example, if running between 25 and 48 MHz, FLRT should be set to 1. When
changing clocks, the FLRT field should be set to the higher number during the clock change, to ensure that flash is never read too
quickly.
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10.3.3 Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their
MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is much faster
than that of the standard 8051.
All instruction timing on the CIP-51 controller is based directly on the core clock timing. This is in contrast to many other 8-bit architectures, where a distinction is made between machine cycles and clock cycles, with machine cycles taking multiple core clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program
bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed
to when the branch is taken. The following table summarizes the instruction set, including the mnemonic, number of bytes, and number
of clock cycles for each instruction.
Table 10.2. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock Cycles
prefetch off prefetch on
Arithmetic Operations
ADD A, Rn Add register to A 1 1 1
ADD A, direct Add direct byte to A 2 2 2
ADD A, @Ri Add indirect RAM to A 1 2 2
ADD A, #data Add immediate to A 2 2 2
ADDC A, Rn Add register to A with carry 1 1 1
ADDC A, direct Add direct byte to A with carry 2 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2 2
ADDC A, #data Add immediate to A with carry 2 2 2
SUBB A, Rn Subtract register from A with borrow 1 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2 2
SUBB A, #data Subtract immediate from A with borrow 2 2 2
INC A Increment A 1 1 1
INC Rn Increment register 1 1 1
INC direct Increment direct byte 2 2 2
INC @Ri Increment indirect RAM 1 2 2
DEC A Decrement A 1 1 1
DEC Rn Decrement register 1 1 1
DEC direct Decrement direct byte 2 2 2
DEC @Ri Decrement indirect RAM 1 2 2
INC DPTR Increment Data Pointer 1 1 1
MUL AB Multiply A and B 1 4 4
DIV AB Divide A by B 1 8 8
DA A Decimal adjust A 1 1 1
Logical Operations
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Mnemonic Description Bytes Clock Cycles
prefetch off prefetch on
ANL A, Rn AND Register to A 1 1 1
ANL A, direct AND direct byte to A 2 2 2
ANL A, @Ri AND indirect RAM to A 1 2 2
ANL A, #data AND immediate to A 2 2 2
ANL direct, A AND A to direct byte 2 2 2
ANL direct, #data AND immediate to direct byte 3 3 3
ORL A, Rn OR Register to A 1 1 1
ORL A, direct OR direct byte to A 2 2 2
ORL A, @Ri OR indirect RAM to A 1 2 2
ORL A, #data OR immediate to A 2 2 2
ORL direct, A OR A to direct byte 2 2 2
ORL direct, #data OR immediate to direct byte 3 3 3
XRL A, Rn Exclusive-OR Register to A 1 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2 2
XRL A, #data Exclusive-OR immediate to A 2 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3 3
CLR A Clear A 1 1 1
CPL A Complement A 1 1 1
RL A Rotate A left 1 1 1
RLC A Rotate A left through Carry 1 1 1
RR A Rotate A right 1 1 1
RRC A Rotate A right through Carry 1 1 1
SWAP A Swap nibbles of A 1 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1 1
MOV A, direct Move direct byte to A 2 2 2
MOV A, @Ri Move indirect RAM to A 1 2 2
MOV A, #data Move immediate to A 2 2 2
MOV Rn, A Move A to Register 1 1 1
MOV Rn, direct Move direct byte to Register 2 2 2
MOV Rn, #data Move immediate to Register 2 2 2
MOV direct, A Move A to direct byte 2 2 2
MOV direct, Rn Move Register to direct byte 2 2 2
MOV direct, direct Move direct byte to direct byte 3 3 3
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Mnemonic Description Bytes Clock Cycles
prefetch off prefetch on
MOV direct, @Ri Move indirect RAM to direct byte 2 2 2
MOV direct, #data Move immediate to direct byte 3 3 3
MOV @Ri, A Move A to indirect RAM 1 2 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3 7
MOVC A, @A+PC Move code byte relative PC to A 1 3 7
MOVX A, @Ri Move external data (8-bit address) to A 1 3 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3 3
PUSH direct Push direct byte onto stack 2 2 2
POP direct Pop direct byte from stack 2 2 2
XCH A, Rn Exchange Register with A 1 1 1
XCH A, direct Exchange direct byte with A 2 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2 2
Boolean Manipulation
CLR C Clear Carry 1 1 1
CLR bit Clear direct bit 2 2 2
SETB C Set Carry 1 1 2
SETB bit Set direct bit 2 2 2
CPL C Complement Carry 1 1 1
CPL bit Complement direct bit 2 2 2
ANL C, bit AND direct bit to Carry 2 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2 2
ORL C, bit OR direct bit to carry 2 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2 2
MOV C, bit Move direct bit to Carry 2 2 2
MOV bit, C Move Carry to direct bit 2 2 2
JC rel Jump if Carry is set 2 2 or 3 2 or 6
JNC rel Jump if Carry is not set 2 2 or 3 2 or 6
JB bit, rel Jump if direct bit is set 3 3 or 4 3 or 7
JNB bit, rel Jump if direct bit is not set 3 3 or 4 3 or 7
JBC bit, rel Jump if direct bit is set and clear bit 3 3 or 4 3 or 7
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Mnemonic Description Bytes Clock Cycles
prefetch off prefetch on
Program Branching
ACALL addr11 Absolute subroutine call 2 3 6
LCALL addr16 Long subroutine call 3 4 7
RET Return from subroutine 1 5 8
RETI Return from interrupt 1 5 8
AJMP addr11 Absolute jump 2 3 6
LJMP addr16 Long jump 3 4 7
SJMP rel Short jump (relative address) 2 3 6
JMP @A+DPTR Jump indirect relative to DPTR 1 3 6
JZ rel Jump if A equals zero 2 2 or 3 2 or 6
JNZ rel Jump if A does not equal zero 2 2 or 3 2 or 6
CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 4 or 5 4 or 8
CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3 or 4 3 or 7
CJNE Rn, #data, rel Compare immediate to Register and jump if not
3 3 or 4 3 or 7
equal
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
3 4 or 5 4 or 8
equal
DJNZ Rn, rel Decrement Register and jump if not zero 2 2 or 3 2 or 6
DJNZ direct, rel Decrement direct byte and jump if not zero 3 3 or 4 3 or 7
NOP No operation 1 1 1
Notes:
• Rn: Register R0–R7 of the currently selected register bank.
• @Ri: Data RAM location addressed indirectly through R0 or R1.
• rel: 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional
jumps.
• direct: 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–0x7F) or an SFR (0x80–
0xFF).
• #data: 8-bit constant.
• #data16: 16-bit constant.
• bit: Direct-accessed bit in Data RAM or SFR.
• addr11: 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2 KB page of program
memory as the first byte of the following instruction.
• addr16: 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8 KB program memory
space.
• There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation
1980.
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10.4 CPU Core Registers
10.4.1 DPL: Data Pointer Low
Bit 7 6 5 4 3 2 1 0
Name DPL
Access RW
Reset 0x00
SFR Page = ALL; SFR Address: 0x82
Bit Name Reset Access Description
7:0 DPL 0x00 RW Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed flash memory or XRAM.
10.4.2 DPH: Data Pointer High
Bit 7 6 5 4 3 2 1 0
Name DPH
Access RW
Reset 0x00
SFR Page = ALL; SFR Address: 0x83
Bit Name Reset Access Description
7:0 DPH 0x00 RW Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed flash memory or XRAM.
10.4.3 SP: Stack Pointer
Bit 7 6 5 4 3 2 1 0
Name SP
Access RW
Reset 0x07
SFR Page = ALL; SFR Address: 0x81
Bit Name Reset Access Description
7:0 SP 0x07 RW Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation.
The SP register defaults to 0x07 after reset.
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10.4.4 ACC: Accumulator
Bit 7 6 5 4 3 2 1 0
Name ACC
Access RW
Reset 0x00
SFR Page = ALL; SFR Address: 0xE0 (bit-addressable)
Bit Name Reset Access Description
7:0 ACC 0x00 RW Accumulator.
This register is the accumulator for arithmetic operations.
10.4.5 B: B Register
Bit 7 6 5 4 3 2 1 0
Name B
Access RW
Reset 0x00
SFR Page = ALL; SFR Address: 0xF0 (bit-addressable)
Bit Name Reset Access Description
7:0 B 0x00 RW B Register.
This register serves as a second accumulator for certain arithmetic operations.
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10.4.6 PSW: Program Status Word
Bit 7 6 5 4 3 2 1 0
Name CY AC F0 RS OV F1 PARITY
Access RW RW RW RW RW RW R
Reset 0 0 0 0x0 0 0 0
SFR Page = ALL; SFR Address: 0xD0 (bit-addressable)
Bit Name Reset Access Description
7 CY 0 RW Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic
0 by all other arithmetic operations.
6 AC 0 RW Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high
order nibble. It is cleared to logic 0 by all other arithmetic operations.
5 F0 0 RW User Flag 0.
This is a bit-addressable, general purpose flag for use under firmware control.
4:3 RS 0x0 RW Register Bank Select.
These bits select which register bank is used during register accesses.
Value Name Description
0x0 BANK0 Bank 0, Addresses 0x00-0x07
0x1 BANK1 Bank 1, Addresses 0x08-0x0F
0x2 BANK2 Bank 2, Addresses 0x10-0x17
0x3 BANK3 Bank 3, Addresses 0x18-0x1F
2 OV 0 RW Overflow Flag.
This bit is set to 1 under the following circumstances:
1. An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
2. A MUL instruction results in an overflow (result is greater than 255).
3. A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.
1 F1 0 RW User Flag 1.
This is a bit-addressable, general purpose flag for use under firmware control.
0 PARITY 0 R Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even.
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10.4.7 PFE0CN: Prefetch Engine Control
Bit 7 6 5 4 3 2 1 0
Name Reserved FLRT Reserved
Access R RW R
Reset 0x0 0 0x0
SFR Page = 0x10; SFR Address: 0xC1
Bit Name Reset Access Description
7:5 Reserved Must write reset value.
4 FLRT 0 RW Flash Read Timing.
This field should be programmed to the smallest allowed value, according to the system clock speed. When transitioning to
a faster clock speed, program FLRT before changing the clock. When changing to a slower clock speed, change the clock
before changing FLRT.
Value Name Description
0 SYSCLK_BE-
LOW_25_MHZ
1 SYSCLK_BE-
LOW_50_MHZ
3:0 Reserved Must write reset value.
SYSCLK < 25 MHz.
SYSCLK < 50 MHz.
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Port I/O, Crossbar, External Interrupts, and Port Match
11. Port I/O, Crossbar, External Interrupts, and Port Match
11.1 Introduction
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.6 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0.
UART1
SPI0
SMB0
CMP0 Out
CMP1 Out
SYSCLK
PCA (CEXn)
PCA (ECI)
Timer 0
Timer 1
Timer 2/3/4/5
UART1
2
Priority Crossbar
4
2
2
2
1
3
1
1
1
1
Decoder
ADC0 In
CMP0 In
CMP1 In
Port Match
INT0 / INT1
P0, P1
P0, P1, P2
P0
P1, P2
P0, P1
P0
Port
Control
and
Config
P0.0 / VREF
P0.1 / AGND
P0.2
P0.3 / EXTCLK
P0.4
P0.5
P0.6 / CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
Configurable Logic
4
Figure 11.1. Port I/O Block Diagram
11.2 Features
The port control block offers the following features:
• Up to 17 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each port.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 17 direct-pin interrupt sources with shared interrupt vector (Port Match).
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11.3 Functional Description
11.3.1 Port I/O Modes of Operation
Port pins are configured by firmware as digital or analog I/O using the special function registers. Port I/O initialization consists of the
following general steps:
1. Select the input mode (analog or digital) for all port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all port pins, using the Port Output Mode register (PnMDOUT).
3. Select any pins to be skipped by the I/O crossbar using the Port Skip registers (PnSKIP).
4. Assign port pins to desired peripherals.
5. Enable the crossbar (XBARE = 1).
A diagram of the port I/O cell is shown in the following figure.
WEAKPUD
(Weak Pull-Up Disable)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDIN.x
(1 for digital)
To/From Analog
Peripheral
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
(0 for analog)
VDD
GND
VDD
(WEAK)
PORT
PAD
Figure 11.2. Port I/O Cell Block Diagram
Configuring Port Pins For Analog Modes
Any pins to be used for analog functions should be configured for analog mode. When a pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. This saves power by eliminating crowbar current, and reduces noise on the analog
input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. Port pins
configured for analog functions will always read back a value of 0 in the corresponding Pn Port Latch register. To configure a pin as
analog, the following steps should be taken:
1. Clear the bit associated with the pin in the PnMDIN register to 0. This selects analog mode for the pin.
2. Set the bit associated with the pin in the Pn register to 1.
3. Skip the bit associated with the pin in the PnSKIP register to ensure the crossbar does not attempt to assign a function to the pin.
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Configuring Port Pins For Digital Modes
Any pins to be used by digital peripherals or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of
two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the port pad to the supply rails based on the output logic value of the port pin. Open-drain
outputs have the high side driver disabled; therefore, they only drive the port pad to the lowside rail when the output logic value is 0 and
become high impedance inputs (both high low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the high side rail to ensure
the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is driven low to minimize power consumption,
and they may be globally disabled by setting WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally
pulled or driven to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back the logic
state of the port pad, regardless of the output logic value of the port pin.
To configure a pin as a digital input:
1. Set the bit associated with the pin in the PnMDIN register to 1. This selects digital mode for the pin.
2. lear the bit associated with the pin in the PnMDOUT register to 0. This configures the pin as open-drain.
3. Set the bit associated with the pin in the Pn register to 1. This tells the output driver to “drive” logic high. Because the pin is configured as open-drain, the high-side driver is disabled, and the pin may be used as an input.
Open-drain outputs are configured exactly as digital inputs. The pin may be driven low by an assigned peripheral, or by writing 0 to the
associated bit in the Pn register if the signal is a GPIO.
To configure a pin as a digital, push-pull output:
1. Set the bit associated with the pin in the PnMDIN register to 1. This selects digital mode for the pin.
2. Set the bit associated with the pin in the PnMDOUT register to 1. This configures the pin as push-pull.
If a digital pin is to be used as a general-purpose I/O, or with a digital function that is not part of the crossbar, the bit associated with the
pin in the PnSKIP register can be set to 1 to ensure the crossbar does not attempt to assign a function to the pin. The crossbar must be
enabled to use port pins as standard port I/O in output mode. Port output drivers of all I/O pins are disabled whenever the crossbar is
disabled.
11.3.1.1 Port Drive Strength
Port drive strength can be controlled on a port-by-port basis using the PRTDRV register. Each port has a bit in PRTDRV to select the
high or low drive strength setting for all pins on that port. By default, all ports are configured for high drive strength.
11.3.2 Analog and Digital Functions
11.3.2.1 Port I/O Analog Assignments
The following table displays the potential mapping of port I/O to each analog function.
Table 11.1. Port I/O Assignment for Analog Functions
Analog Function Potentially Assignable Port Pins SFR(s) Used For Assignment
QFN24 / QSOP24 QFN20
ADC Input P0.0 – P1.6, P2.1 P0.0 – P1.2, P2.1 ADC0MX, PnSKIP, PnMDIN
D+, D- (USB)
D+, D- (USB)
VREGIN / 4
VREGIN / 4
Comparator 0 Input P0.0 – P0.7 CMP0MX, PnSKIP, PnMDIN
Comparator 1 Input P1.0 – P1.6, P2.1 P1.0 – P1.2, P2.1 CMP1MX, PnSKIP, PnMDIN
Voltage Reference (VREF) P0.0 REF0CN, PnSKIP, PnMDIN
Reference Ground (AGND) P0.1 REF0CN, PnSKIP, PnMDIN
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11.3.2.2 Port I/O Digital Assignments
The following table displays the potential mapping of port I/O to each digital function.
Table 11.2. Port I/O Assignment for Digital Functions
Digital Function Potentially Assignable Port Pins SFR(s) Used For Assignment
UART1, SPI0, SMB0, CP0, CP0A, CP1,
CP1A, SYSCLK, PCA0 (CEX0-2 and ECI),
T0, T1, T2/3/4/5
Any port pin available for assignment by
the crossbar. This includes P0.0 – P1.6
pins which have their PnSKIP bit set to ‘0’.
XBR0, XBR1, XBR2
The crossbar will always assign UART1
pins to P0.4 and P0.5 if the URT1EL bit in
XBR0 is set to 1.
External Interrupt 0, External Interrupt 1 P0.0 – P0.7 IT01CF
Conversion Start (CNVSTR) P0.6 ADC0CN0
External Clock Input (EXTCLK) P0.3 CLKSEL
Port Match P0.0 – P1.6, P2.1 P0MASK, P0MAT, P1MASK, P1MAT,
P2MASK, P2MAT
VBUS P2.1 USB0CF
Configurable Logic Inputs A and B
P0.0 – P1.6 CLUnMX
(Assignable pins vary across CLUs)
Configurable Logic Unit 0 Output
P0.2 CLU0CF
(CLU0OUT)
Configurable Logic Unit 1 Output
P0.4 CLU1CF
(CLU1OUT)
Configurable Logic Unit 2 Output
P0.6 CLU2CF
(CLU2OUT)
Configurable Logic Unit 3 Output
P1.0 CLU3CF
(CLU3OUT)
Any pin used for GPIO P0.0 – P1.6, P2.1 P0SKIP, P1SKIP
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11.3.3 Priority Crossbar Decoder
The priority crossbar decoder assigns a priority to each I/O function, starting at the top with UART0. The XBRn registers are used to
control which crossbar resources are assigned to physical I/O port pins.
When a digital resource is selected, the least-significant unassigned port pin is assigned to that resource (excluding UART0, which is
always assigned to dedicated pins). If a port pin is assigned, the crossbar skips that pin when assigning the next selected resource.
Additionally, the the PnSKIP registers allow software to skip port pins that are to be used for analog functions, dedicated digital functions, or GPIO. If a port pin is to be used by a function which is not assigned through the crossbar, its corresponding PnSKIP bit should
be set to 1 in most cases. The crossbar skips these pins as if they were already assigned, and moves to the next unassigned pin.
It is possible for crossbar-assigned peripherals and dedicated functions to coexist on the same pin. For example, the port match function could be configured to watch for a falling edge on a UART RX line and generate an interrupt or wake up the device from a lowpower state. However, if two functions share the same pin, the crossbar will have control over the output characteristics of that pin and
the dedicated function will only have input access. Likewise, it is possible for firmware to read the logic state of any digital I/O pin assigned to a crossbar peripheral, but the output state cannot be directly modified.
Figure 11.3 Crossbar Priority Decoder Example Assignments on page 98 shows an example of the resulting pin assignments of the
device with UART1 and SPI0 enabled and P0.3 skipped (P0SKIP = 0x08). UART1 is the highest priority when URT1EL in XBR0 is set
to 1 and it will be assigned first. When URT1EL is set to 1, the UART1 pins can only appear at fixed locations (P0.4 and P0.5), so it
occupies those pins. The next-highest enabled peripheral is SPI0. P0.0, P0.1 and P0.2 are free, so SPI0 takes these three pins. The
fourth pin, NSS, is routed to P0.6 because P0.3 is skipped and P0.4 and P0.5 are already occupied by the UART. Any other pins on the
device are available for use as general-purpose digital I/O or analog functions.
P0Port
Pin Number
0 1 2 3 4 5 6 7
UART1-TX
UART1-RX
SPI0-SCK
SPI0-MISO
SPI0-MOSI
SPI0-NSS
0 0 0 0 0 0 0
1
Pin Skip Settings
P0SKIP
UART1 is assigned to fixed pins and has priority over SPI0.
SPI0 is assigned to available, un-skipped pins.
Port pins assigned to the associated peripheral.
P0.3 is skipped by setting P0SKIP.3 to 1.
Figure 11.3. Crossbar Priority Decoder Example Assignments
Note: UART1 pins appear in P0.4 and P0.5 when URT1EL is set in the XBR0 register for backwards compatibility with UART0 place-
ment on other devices. When URT1E in the XBR2 register is set, UART1 is available on any crossbar pin in standard priority order.
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Port I/O, Crossbar, External Interrupts, and Port Match
11.3.3.1 Crossbar Functional Map
The figure below shows all of the potential peripheral-to-pin assignments available to the crossbar. Note that this does not mean any
peripheral can always be assigned to the highlighted pins. The actual pin assignments are determined by the priority of the enabled
peripherals.
Pin Number
QFN-20 Package
QSOP-24 Package
QFN-24 Package
UART1-TX
UART1-RX
P0Port
0 1 2 3 4 5 6 7
VREF
AGND
EXTCLK
CLU1OUT
CLU0OUT
1
1
0 1 2 3 4 5 6
CLU3OUT
CNVSTR / CLU2OUT
P1
N/A
SPI0-SCK
SPI0-MISO
SPI0-MOSI
SPI0-NSS
2
SMB0-SDA
SMB0-SCL
CMP0-CP0
CMP0-CP0A
CMP1-CP1
CMP1-CP1A
SYSCLK
PCA0-CEX0
PCA0-CEX1
PCA0-CEX2
PCA0-ECI
Timer0-T0
Timer1-T1
Timer2-T2
UART1-TX
UART1-RX
UART1-RTS
UART1-CTS
Pin Skip Settings
0 0 0 0 0 0 0 0
P0SKIP
0 0 0 0 0 0 0
P1SKIP
The crossbar peripherals are assigned in priority order from top to bottom.
N/A
N/A
0 1
N/A
P2
C2D
VBUS
C2D
Pins Not Available on Crossbar
These boxes represent Port pins which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are
enabled, the Crossbar should be manually configured to skip the corresponding port pins.
Pins can be “skipped” by setting the corresponding bit in PnSKIP to 1.
Notes:
1. UART1 pins are available in these locations to be backwards compatible with UART0 on
other devices. UART1 is available either in the fixed P0.4 and P0.5 locations or the
standard UART1 crossbar locations. The pins should not be enabled in both locations at the
same time.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Figure 11.4. Full Crossbar Map
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EFM8UB3 Reference Manual
Port I/O, Crossbar, External Interrupts, and Port Match
11.3.4 INT0 and INT1
Two direct-pin digital interrupt sources (INT0 and INT1) are included, which can be routed to port 0 pins. Additional I/O interrupts are
available through the port match function. As is the case on a standard 8051 architecture, certain controls for these two interrupt sources are available in the Timer0/1 registers. Extensions to these controls which provide additional functionality are available in the
IT01CF register. INT0 and INT1 are configurable as active high or low, edge- or level-sensitive. The IN0PL and IN1PL bits in the
IT01CF register select active high or active low; the IT0 and IT1 bits in TCON select level- or edge-sensitive. The table below lists the
possible configurations.
Table 11.3. INT0/INT1 configuration
IT0 or IT1 IN0PL or IN1PL INT0 or INT1 Interrupt
1 0 Interrupt on falling edge
1 1 Interrupt on rising edge
0 0 Interrupt on low level
0 1 Interrupt on high level
INT0 and INT1 are assigned to port pins as defined in the IT01CF register. INT0 and INT1 port pin assignments are independent of any
crossbar assignments, and may be assigned to pins used by crossbar peripherals. INT0 and INT1 will monitor their assigned port pins
without disturbing the peripheral that was assigned the port pin via the crossbar. To assign a port pin only to INT0 and/or INT1, configure the crossbar to skip the selected pin(s).
IE0 and IE1 in the TCON register serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0
or INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is
active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external
interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before
execution of the ISR completes or another interrupt request will be generated.
11.3.5 Port Match
Port match functionality allows system events to be triggered by a logic value change on one or more port I/O pins. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of the associated port pins (for example,
P0MATCH.0 would correspond to P0.0). A port mismatch event occurs if the logic levels of the port’s input pins no longer match the
software controlled value. This allows software to be notified if a certain change or pattern occurs on the input pins regardless of the
XBRn settings.
The PnMASK registers can be used to individually select which pins should be compared against the PnMATCH registers. A port mismatch event is generated if (Pn & PnMASK) does not equal (PnMATCH & PnMASK) for all ports with a PnMAT and PnMASK register.
A port mismatch event may be used to generate an interrupt or wake the device from low power modes. See the interrupts and power
options chapters for more details on interrupt and wake-up sources.
11.3.6 Direct Port I/O Access (Read/Write)
All port I/O are accessed through corresponding special function registers. When writing to a port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the port's input pins are returned regardless of the
XBRn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding
port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write instructions when operating on a port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a port SFR. For these instructions, the value of the latch register
(not the pin) is read, modified, and written back to the SFR.
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