EFM8 Universal Bee Family
EFM8UB3 Reference Manual
The EFM8UB3, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set in
small packages.
These devices offer high value by integrating an innovative energy-smart USB peripheral
interface, charger detect circuit, 8 kV ESD protection, and enhanced high speed commuÂnication interfaces into small packages, making them ideal for space-constrained USB
applications. With an efficient 8051 core and precision analog, the EFM8UB3 family is
also optimal for embedded applications.
EFM8UB3 applications include the following:
• USB I/O controls
• Docking stations/USB hubs
• Dongles
Core / Memory Clock Management
CIP-51 8051 Core
(48 MHz)
Flash Memory
40 KB
RAM Memory
3328 bytes
• Consumer electronics
• USB Type-C converters
• USB Type-C billboard/alternate mode
External CMOS
Oscillator
Debug Interface
with C2
Low Frequency
RC Oscillator
High Frequency
48 MHz RC
Oscillator
High Frequency
24.5 MHz RC
Oscillator
KEY FEATURES
• Pipelined 8-bit C8051 core with 48 MHz
maximum operating frequency
• Up to 17 multifunction I/O pins
• Low Energy USB with full- and low-speed
support saves up to 90% of the USB
energy
• USB charger detect circuit (USB-BCS 1.2
compliant)
• One 12-bit ADC and two analog
comparators with internal voltage DAC as
reference input
• Six 16-bit timers
• UART and SMBus master/slave
• Priority crossbar for flexible pin mapping
Energy Management
Internal LDO
Regulator
Brown-Out
Detector
Power-On Reset
5 V-to 3.3 V LDO
Regulator
8-bit SFR bus
Serial Interfaces Timers and Triggers Analog Interfaces
UART
SMBus
Lowest power mode with peripheral operational:
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USB
SPI
IdleNormal ShutdownSuspend Snooze
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
Timers
0/1/2
Watchdog
Timer
4 x Configurable Logic Units
PCA/PWM
Timer 3/4/5
ADC
Internal Voltage
Reference
Charger Det
Comparator 1
Comparator 0
SecurityI/O Ports
16-bit CRC
Table of Contents
1. System Overview .............................13
1.1 Introduction ...............................13
1.2 Power .................................14
1.3 I/O ..................................14
1.4 Clocking ................................15
1.5 Counters/Timers and PWM ..........................15
1.6 Communications and Other Digital Peripherals ...................17
1.7 Analog.................................19
1.8 Reset Sources ..............................20
1.9 Debugging ...............................20
1.10 Bootloader ...............................21
2. Memory ................................23
2.1 Memory Organization............................23
2.2 Program Memory .............................23
2.3 Data Memory ..............................23
2.4 Memory Map ..............................25
2.5 XRAM Control Registers...........................27
2.5.1 EMI0CN: External Memory Interface Control ..................27
3. Special Function Registers .........................28
3.1 Special Function Register Access .......................28
3.2 Special Function Register Memory Map .....................30
3.3 SFR Access Control Registers.........................37
3.3.1 SFRPAGE: SFR Page ..........................37
3.3.2 SFRPGCN: SFR Page Control .......................38
3.3.3 SFRSTACK: SFR Page Stack .......................38
4. Flash Memory ..............................39
4.1 Introduction ...............................39
4.2 Features ................................39
4.3 Functional Description ...........................40
4.3.1 Security Options ............................40
4.3.2 Programming the Flash Memory ......................41
4.3.3 Flash Write and Erase Precautions......................42
4.4 Flash Control Registers ...........................43
4.4.1 PSCTL: Program Store Control .......................43
4.4.2 FLKEY: Flash Lock and Key ........................44
5. Device Identification ...........................45
5.1 Device Identification ............................45
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5.2 Unique Identifier .............................45
5.3 Device Identification Registers.........................45
5.3.1 DEVICEID: Device Identification.......................45
5.3.2 DERIVID: Derivative Identification ......................46
5.3.3 REVID: Revision Identifcation .......................46
6. Interrupts ................................ 47
6.1 Introduction ...............................47
6.2 Interrupt Sources and Vectors .........................47
6.2.1 Interrupt Priorities ...........................47
6.2.2 Interrupt Latency ............................48
6.2.3 Interrupt Summary ...........................49
6.3 Interrupt Control Registers ..........................51
6.3.1 IE: Interrupt Enable ...........................51
6.3.2 IP: Interrupt Priority ...........................53
6.3.3 IPH: Interrupt Priority High ........................54
6.3.4 EIE1: Extended Interrupt Enable 1 ......................55
6.3.5 EIP1: Extended Interrupt Priority 1 Low ....................57
6.3.6 EIP1H: Extended Interrupt Priority 1 High ...................58
6.3.7 EIE2: Extended Interrupt Enable 2 ......................59
6.3.8 EIP2: Extended Interrupt Priority 2 ......................60
6.3.9 EIP2H: Extended Interrupt Priority 2 High ...................61
7. Power Management and Internal Regulators ..................62
7.1 Introduction ...............................62
7.2 Features ................................63
7.3 Idle Mode................................64
7.4 Stop Mode ...............................64
7.5 Suspend Mode ..............................64
7.6 Snooze Mode ..............................65
7.7 Shutdown Mode .............................65
7.8 5V-to-3.3V Regulator ............................65
7.9 Power Management Control Registers ......................66
7.9.1 PCON0: Power Control..........................66
7.9.2 PCON1: Power Control 1 .........................67
7.9.3 PSTAT0: Power Status..........................68
7.9.4 REG0CN: Voltage Regulator 0 Control ....................69
7.9.5 REG1CN: Voltage Regulator 1 Control ....................70
8. Clocking and Oscillators ..........................71
8.1 Introduction ...............................71
8.2 Features ................................71
8.3 Functional Description ...........................71
8.3.1 Clock Selection ............................71
8.3.2 HFOSC0 24.5 MHz Internal Oscillator .....................72
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8.3.3 HFOSC1 48 MHz Internal Oscillator .....................72
8.3.4 LFOSC0 80 kHz Internal Oscillator ......................72
8.3.5 External Clock.............................72
8.4 Clocking and Oscillator Control Registers .....................73
8.4.1 CLKSEL: Clock Select ..........................73
8.4.2 HFO0CAL: High Frequency Oscillator 0 Calibration ................74
8.4.3 HFO1CAL: High Frequency Oscillator 1 Calibration ................74
8.4.4 HFOCN: High Frequency Oscillator Control ...................75
8.4.5 LFO0CN: Low Frequency Oscillator Control...................76
9. Reset Sources and Power Supply Monitor ...................77
9.1 Introduction ...............................77
9.2 Features ................................77
9.3 Functional Description ...........................78
9.3.1 Device Reset .............................78
9.3.2 Power-On Reset ............................79
9.3.3 Supply Monitor Reset ..........................80
9.3.4 External Reset ............................80
9.3.5 Missing Clock Detector Reset .......................80
9.3.6 Comparator (CMP0) Reset ........................81
9.3.7 Watchdog Timer Reset ..........................81
9.3.8 Flash Error Reset ...........................81
9.3.9 Software Reset ............................81
9.3.10 USB Reset .............................81
9.4 Reset Sources and Supply Monitor Control Registers .................82
9.4.1 RSTSRC: Reset Source .........................82
9.4.2 VDM0CN: Supply Monitor Control ......................83
10. CIP-51 Microcontroller Core ........................84
10.1 Introduction ..............................84
10.2 Features ...............................85
10.3 Functional Description ...........................85
10.3.1 Programming and Debugging Support ....................85
10.3.2 Prefetch Engine............................85
10.3.3 Instruction Set ............................86
10.4 CPU Core Registers ...........................90
10.4.1 DPL: Data Pointer Low .........................90
10.4.2 DPH: Data Pointer High .........................90
10.4.3 SP: Stack Pointer ...........................90
10.4.4 ACC: Accumulator ...........................91
10.4.5 B: B Register.............................91
10.4.6 PSW: Program Status Word .......................92
10.4.7 PFE0CN: Prefetch Engine Control .....................93
11. Port I/O, Crossbar, External Interrupts, and Port Match ..............94
11.1 Introduction ..............................94
11.2 Features ...............................94
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11.3 Functional Description ...........................95
11.3.1 Port I/O Modes of Operation .......................95
11.3.2 Analog and Digital Functions .......................96
11.3.3 Priority Crossbar Decoder ........................98
11.3.4 INT0 and INT1 ...........................100
11.3.5 Port Match ............................100
11.3.6 Direct Port I/O Access (Read/Write) ....................100
11.4 Port I/O Control Registers .........................101
11.4.1 XBR0: Port I/O Crossbar 0 .......................101
11.4.2 XBR1: Port I/O Crossbar 1 .......................103
11.4.3 XBR2: Port I/O Crossbar 2 .......................104
11.4.4 PRTDRV: Port Drive Strength ......................105
11.4.5 P0MASK: Port 0 Mask ........................106
11.4.6 P0MAT: Port 0 Match .........................107
11.4.7 P0: Port 0 Pin Latch .........................108
11.4.8 P0MDIN: Port 0 Input Mode .......................109
11.4.9 P0MDOUT: Port 0 Output Mode .....................110
11.4.10 P0SKIP: Port 0 Skip .........................111
11.4.11 P1MASK: Port 1 Mask ........................112
11.4.12 P1MAT: Port 1 Match ........................113
11.4.13 P1: Port 1 Pin Latch .........................114
11.4.14 P1MDIN: Port 1 Input Mode ......................115
11.4.15 P1MDOUT: Port 1 Output Mode .....................116
11.4.16 P1SKIP: Port 1 Skip .........................117
11.4.17 P2MASK: Port 2 Mask ........................118
11.4.18 P2MAT: Port 2 Match ........................118
11.4.19 P2: Port 2 Pin Latch .........................119
11.4.20 P2MDIN: Port 2 Input Mode ......................119
11.4.21 P2MDOUT: Port 2 Output Mode .....................120
11.5 INT0 and INT1 Control Registers ......................121
11.5.1 IT01CF: INT0/INT1 Configuration .....................121
12. Analog-to-Digital Converter (ADC0) .....................123
12.1 Introduction .............................123
12.2 Features ..............................124
12.3 Functional Description ..........................124
12.3.1 Clocking .............................124
12.3.2 Voltage Reference Options .......................124
12.3.3 Input Selection ...........................125
12.3.4 Gain Setting ............................126
12.3.5 Initiating Conversions .........................126
12.3.6 Input Tracking ...........................126
12.3.7 Burst Mode ............................129
12.3.8 8-Bit Mode ............................129
12.3.9 12-Bit Mode ............................130
12.3.10 Output Formatting .........................131
12.3.11 Power Considerations ........................132
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12.3.12 Window Comparator .........................134
12.3.13 Temperature Sensor .........................136
12.4 ADC0 Control Registers .........................137
12.4.1 ADC0CN0: ADC0 Control 0 .......................137
12.4.2 ADC0CN1: ADC0 Control 1 .......................138
12.4.3 ADC0CF: ADC0 Configuration ......................139
12.4.4 ADC0AC: ADC0 Accumulator Configuration .................140
12.4.5 ADC0PWR: ADC0 Power Control .....................142
12.4.6 ADC0TK: ADC0 Burst Mode Track Time ..................143
12.4.7 ADC0H: ADC0 Data Word High Byte ...................143
12.4.8 ADC0L: ADC0 Data Word Low Byte ....................144
12.4.9 ADC0GTH: ADC0 Greater-Than High Byte .................144
12.4.10 ADC0GTL: ADC0 Greater-Than Low Byte .................144
12.4.11 ADC0LTH: ADC0 Less-Than High Byte ..................145
12.4.12 ADC0LTL: ADC0 Less-Than Low Byte ..................145
12.4.13 ADC0MX: ADC0 Multiplexer Selection ...................145
12.4.14 REF0CN: Voltage Reference Control ...................146
13. Comparators (CMP0 and CMP1) .......................147
13.1 Introduction .............................147
13.2 Features ..............................147
13.3 Functional Description ..........................148
13.3.1 Response Time and Supply Current ....................148
13.3.2 Hysteresis ............................148
13.3.3 Input Selection ...........................148
13.3.4 Output Routing ...........................153
13.4 CMP0 Control Registers .........................155
13.4.1 CMP0CN0: Comparator 0 Control 0 ....................155
13.4.2 CMP0MD: Comparator 0 Mode .....................157
13.4.3 CMP0MX: Comparator 0 Multiplexer Selection ................158
13.4.4 CMP0CN1: Comparator 0 Control 1 ....................159
13.5 CMP1 Control Registers .........................160
13.5.1 CMP1CN0: Comparator 1 Control 0 ....................160
13.5.2 CMP1MD: Comparator 1 Mode .....................162
13.5.3 CMP1MX: Comparator 1 Multiplexer Selection ................163
13.5.4 CMP1CN1: Comparator 1 Control 1 ....................164
14. Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) ...............165
14.1 Introduction .............................165
14.2 Features ..............................166
14.3 Functional Description ..........................167
14.3.1 Configuration Sequence ........................167
14.3.2 Input Multiplexer Selection .......................167
14.3.3 Output Configuration .........................169
14.3.4 LUT Configuration ..........................169
14.4 Configurable Logic Control Registers .....................170
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14.4.1 CLEN0: Configurable Logic Enable 0 ...................170
14.4.2 CLIE0: Configurable Logic Interrupt Enable 0 .................171
14.4.3 CLIF0: Configurable Logic Interrupt Flag 0 ..................172
14.4.4 CLOUT0: Configurable Logic Output 0 ...................173
14.4.5 CLU0MX: Configurable Logic Unit 0 Multiplexer ................173
14.4.6 CLU0FN: Configurable Logic Unit 0 Function Select ..............174
14.4.7 CLU0CF: Configurable Logic Unit 0 Configuration ...............175
14.4.8 CLU1MX: Configurable Logic Unit 1 Multiplexer ................176
14.4.9 CLU1FN: Configurable Logic Unit 1 Function Select ..............176
14.4.10 CLU1CF: Configurable Logic Unit 1 Configuration ...............177
14.4.11 CLU2MX: Configurable Logic Unit 2 Multiplexer ...............178
14.4.12 CLU2FN: Configurable Logic Unit 2 Function Select ..............178
14.4.13 CLU2CF: Configurable Logic Unit 2 Configuration ...............179
14.4.14 CLU3MX: Configurable Logic Unit 3 Multiplexer ...............180
14.4.15 CLU3FN: Configurable Logic Unit 3 Function Select ..............180
14.4.16 CLU3CF: Configurable Logic Unit 3 Configuration ...............181
15. Cyclic Redundancy Check (CRC0) ......................182
15.1 Introduction .............................182
15.2 Features ..............................182
15.3 Functional Description ..........................183
15.3.1 16-bit CRC Algorithm .........................183
15.3.2 Using the CRC on a Data Stream .....................184
15.3.3 Using the CRC to Check Code Memory ...................184
15.3.4 Bit Reversal ............................184
15.4 CRC0 Control Registers .........................185
15.4.1 CRC0CN0: CRC0 Control 0.......................185
15.4.2 CRC0IN: CRC0 Data Input .......................185
15.4.3 CRC0DAT: CRC0 Data Output......................186
15.4.4 CRC0ST: CRC0 Automatic Flash Sector Start ................186
15.4.5 CRC0CNT: CRC0 Automatic Flash Sector Count ...............186
15.4.6 CRC0FLIP: CRC0 Bit Flip .......................187
15.4.7 CRC0CN1: CRC0 Control 1.......................187
16. Programmable Counter Array (PCA0) .....................188
16.1 Introduction .............................188
16.2 Features ..............................189
16.3 Functional Description ..........................189
16.3.1 Counter / Timer ...........................189
16.3.2 Interrupt Sources ..........................190
16.3.3 Capture/Compare Modules .......................190
16.3.4 Edge-Triggered Capture Mode ......................191
16.3.5 Software Timer (Compare) Mode .....................192
16.3.6 High-Speed Output Mode .......................193
16.3.7 Frequency Output Mode ........................194
16.3.8 PWM Waveform Generation ......................194
16.4 PCA0 Control Registers .........................201
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16.4.1 PCA0CN0: PCA Control ........................201
16.4.2 PCA0MD: PCA Mode .........................202
16.4.3 PCA0PWM: PCA PWM Configuration ...................203
16.4.4 PCA0CLR: PCA Comparator Clear Control .................204
16.4.5 PCA0L: PCA Counter/Timer Low Byte ...................204
16.4.6 PCA0H: PCA Counter/Timer High Byte ...................205
16.4.7 PCA0POL: PCA Output Polarity .....................205
16.4.8 PCA0CENT: PCA Center Alignment Enable .................206
16.4.9 PCA0CPM0: PCA Channel 0 Capture/Compare Mode ..............207
16.4.10 PCA0CPL0: PCA Channel 0 Capture Module Low Byte .............208
16.4.11 PCA0CPH0: PCA Channel 0 Capture Module High Byte ............208
16.4.12 PCA0CPM1: PCA Channel 1 Capture/Compare Mode .............209
16.4.13 PCA0CPL1: PCA Channel 1 Capture Module Low Byte .............210
16.4.14 PCA0CPH1: PCA Channel 1 Capture Module High Byte ............210
16.4.15 PCA0CPM2: PCA Channel 2 Capture/Compare Mode .............211
16.4.16 PCA0CPL2: PCA Channel 2 Capture Module Low Byte .............212
16.4.17 PCA0CPH2: PCA Channel 2 Capture Module High Byte ............212
17. Serial Peripheral Interface (SPI0) ......................213
17.1 Introduction .............................213
17.2 Features ..............................213
17.3 Functional Description ..........................214
17.3.1 Signals ..............................214
17.3.2 Master Mode Operation ........................215
17.3.3 Slave Mode Operation ........................216
17.3.4 Clock Phase and Polarity .......................217
17.3.5 Basic Data Transfer .........................218
17.3.6 Using the SPI FIFOs .........................218
17.3.7 SPI Timing Diagrams .........................221
17.4 SPI0 Control Registers ..........................224
17.4.1 SPI0CFG: SPI0 Configuration ......................224
17.4.2 SPI0CN0: SPI0 Control ........................226
17.4.3 SPI0CKR: SPI0 Clock Rate .......................227
17.4.4 SPI0DAT: SPI0 Data .........................227
17.4.5 SPI0FCN0: SPI0 FIFO Control 0 .....................228
17.4.6 SPI0FCN1: SPI0 FIFO Control 1 .....................229
17.4.7 SPI0FCT: SPI0 FIFO Count.......................230
17.4.8 SPI0PCF: SPI0 Pin Configuration .....................231
18. System Management Bus / I2C (SMB0) ....................232
18.1 Introduction .............................232
18.2 Features ..............................232
18.3 Functional Description ..........................232
18.3.1 Supporting Documents ........................232
18.3.2 SMBus Protocol ...........................233
18.3.3 Configuring the SMBus Module .....................235
18.3.4 Operational Modes ..........................240
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18.4 SMB0 Control Registers .........................248
18.4.1 SMB0CF: SMBus 0 Configuration .....................248
18.4.2 SMB0TC: SMBus 0 Timing and Pin Control .................249
18.4.3 SMB0CN0: SMBus 0 Control ......................250
18.4.4 SMB0ADR: SMBus 0 Slave Address ....................251
18.4.5 SMB0ADM: SMBus 0 Slave Address Mask .................252
18.4.6 SMB0DAT: SMBus 0 Data .......................252
18.4.7 SMB0FCN0: SMBus 0 FIFO Control 0 ...................253
18.4.8 SMB0FCN1: SMBus 0 FIFO Control 1 ...................254
18.4.9 SMB0RXLN: SMBus 0 Receive Length Counter ................255
18.4.10 SMB0FCT: SMBus 0 FIFO Count ....................255
19. Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) ............256
19.1 Introduction .............................256
19.2 Features ..............................256
19.3 Functional Description ..........................257
19.3.1 System Connections .........................257
19.3.2 Timer 0 and Timer 1 .........................258
19.3.3 Timer 2, Timer 3, Timer 4, and Timer 5 ...................262
19.4 Timer 0, 1, 2, 3, 4, and 5 Control Registers ...................268
19.4.1 CKCON0: Clock Control 0 .......................268
19.4.2 CKCON1: Clock Control 1 .......................270
19.4.3 TCON: Timer 0/1 Control .......................271
19.4.4 TMOD: Timer 0/1 Mode ........................272
19.4.5 TL0: Timer 0 Low Byte ........................273
19.4.6 TL1: Timer 1 Low Byte ........................273
19.4.7 TH0: Timer 0 High Byte ........................274
19.4.8 TH1: Timer 1 High Byte ........................274
19.4.9 TMR2CN0: Timer 2 Control 0 ......................275
19.4.10 TMR2RLL: Timer 2 Reload Low Byte ...................276
19.4.11 TMR2RLH: Timer 2 Reload High Byte ...................276
19.4.12 TMR2L: Timer 2 Low Byte .......................276
19.4.13 TMR2H: Timer 2 High Byte ......................277
19.4.14 TMR2CN1: Timer 2 Control 1 ......................278
19.4.15 TMR3CN0: Timer 3 Control 0 ......................279
19.4.16 TMR3RLL: Timer 3 Reload Low Byte ...................280
19.4.17 TMR3RLH: Timer 3 Reload High Byte ...................280
19.4.18 TMR3L: Timer 3 Low Byte .......................280
19.4.19 TMR3H: Timer 3 High Byte ......................281
19.4.20 TMR3CN1: Timer 3 Control 1 ......................282
19.4.21 TMR4CN0: Timer 4 Control 0 ......................284
19.4.22 TMR4RLL: Timer 4 Reload Low Byte ...................285
19.4.23 TMR4RLH: Timer 4 Reload High Byte ...................285
19.4.24 TMR4L: Timer 4 Low Byte .......................285
19.4.25 TMR4H: Timer 4 High Byte ......................286
19.4.26 TMR4CN1: Timer 4 Control 1 ......................287
19.4.27 TMR5RLL: Timer 5 Reload Low Byte ...................288
19.4.28 TMR5RLH: Timer 5 Reload High Byte ...................288
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19.4.29 TMR5L: Timer 5 Low Byte .......................288
19.4.30 TMR5H: Timer 5 High Byte ......................289
19.4.31 TMR5CN0: Timer 5 Control 0 ......................290
19.4.32 TMR5CN1: Timer 5 Control 1 ......................291
20. Universal Asynchronous Receiver/Transmitter 1 (UART1) .............292
20.1 Introduction .............................292
20.2 Features ..............................292
20.3 Functional Description ..........................293
20.3.1 Baud Rate Generation ........................293
20.3.2 Data Format ............................293
20.3.3 Flow Control ............................294
20.3.4 Basic Data Transfer .........................294
20.3.5 Data Transfer With FIFO ........................294
20.3.6 Multiprocessor Communications .....................297
20.3.7 LIN Break and Sync Detect .......................297
20.3.8 Autobaud Detection .........................297
20.3.9 Routing RX Through Configurable Logic ..................298
20.4 UART1 Control Registers .........................299
20.4.1 SCON1: UART1 Serial Port Control ....................299
20.4.2 SMOD1: UART1 Mode ........................301
20.4.3 SBUF1: UART1 Serial Port Data Buffer ...................302
20.4.4 SBCON1: UART1 Baud Rate Generator Control ................303
20.4.5 SBRLH1: UART1 Baud Rate Generator High Byte ...............303
20.4.6 SBRLL1: UART1 Baud Rate Generator Low Byte ...............304
20.4.7 UART1FCN0: UART1 FIFO Control 0 ...................305
20.4.8 UART1FCN1: UART1 FIFO Control 1 ...................307
20.4.9 UART1FCT: UART1 FIFO Count .....................308
20.4.10 UART1LIN: UART1 LIN Configuration ...................309
20.4.11 UART1PCF: UART1 Configuration ....................310
21. Universal Serial Bus (USB0) ........................311
21.1 Introduction .............................311
21.2 Features ..............................311
21.3 Functional Description ..........................312
21.3.1 Endpoint Addressing .........................312
21.3.2 Transceiver Control .........................312
21.3.3 Clock Configuration .........................312
21.3.4 VBUS Control ...........................312
21.3.5 Register Access...........................313
21.3.6 FIFO Management ..........................315
21.3.7 Function Addressing .........................316
21.3.8 Function Configuration and Control ....................317
21.3.9 Interrupts .............................317
21.3.10 Serial Interface Engine ........................317
21.3.11 Endpoint 0 ............................318
21.3.12 Endpoints 1, 2, and 3 ........................319
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21.3.13 Low Energy Mode .........................321
21.3.14 Charger Detect Function .......................321
21.4 USB0 Control Registers .........................326
21.4.1 USB0XCN: USB0 Transceiver Control ...................326
21.4.2 USB0ADR: USB0 Indirect Address ....................327
21.4.3 USB0DAT: USB0 Data ........................328
21.4.4 INDEX: USB0 Endpoint Index ......................328
21.4.5 CLKREC: USB0 Clock Recovery Control ..................329
21.4.6 FIFO0: USB0 Endpoint 0 FIFO Access ...................330
21.4.7 FIFO1: USB0 Endpoint 1 FIFO Access ...................330
21.4.8 FIFO2: USB0 Endpoint 2 FIFO Access ...................330
21.4.9 FIFO3: USB0 Endpoint 3 FIFO Access ...................331
21.4.10 FADDR: USB0 Function Address ....................331
21.4.11 POWER: USB0 Power ........................332
21.4.12 FRAMEL: USB0 Frame Number Low ...................333
21.4.13 FRAMEH: USB0 Frame Number High ...................333
21.4.14 IN1INT: USB0 IN Endpoint Interrupt ...................334
21.4.15 OUT1INT: USB0 OUT Endpoint Interrupt ..................335
21.4.16 CMINT: USB0 Common Interrupt ....................336
21.4.17 IN1IE: USB0 IN Endpoint Interrupt Enable .................337
21.4.18 OUT1IE: USB0 OUT Endpoint Interrupt Enable ................338
21.4.19 CMIE: USB0 Common Interrupt Enable ..................339
21.4.20 E0CSR: USB0 Endpoint0 Control ....................340
21.4.21 E0CNT: USB0 Endpoint0 Data Count ...................341
21.4.22 EENABLE: USB0 Endpoint Enable ....................342
21.4.23 EINCSRL: USB0 IN Endpoint Control Low .................343
21.4.24 EINCSRH: USB0 IN Endpoint Control High .................344
21.4.25 EOUTCSRL: USB0 OUT Endpoint Control Low................345
21.4.26 EOUTCSRH: USB0 OUT Endpoint Control High ...............346
21.4.27 EOUTCNTL: USB0 OUT Endpoint Count Low ................346
21.4.28 EOUTCNTH: USB0 OUT Endpoint Count High ................347
21.4.29 USB0CF: USB0 Configuration .....................348
21.4.30 USB0AEC: USB0 Advanced Energy Control.................350
21.4.31 USB0CDCF: USB0 Charger Detect Configuration ...............351
21.4.32 USB0CDCN: USB0 Charger Detect Control .................352
21.4.33 USB0CDSTA: USB0 Charger Detect Status .................353
22. Watchdog Timer (WDT0)..........................355
22.1 Introduction .............................355
22.2 Features ..............................355
22.3 Using the Watchdog Timer ........................355
22.4 WDT0 Control Registers .........................357
22.4.1 WDTCN: Watchdog Timer Control ....................357
23. C2 Debug and Programming Interface ....................358
23.1 Introduction .............................358
23.2 Features ..............................358
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23.3 Pin Sharing .............................358
23.4 C2 Interface Registers ..........................359
23.4.1 C2ADD: C2 Address .........................359
23.4.2 C2DEVID: C2 Device ID ........................359
23.4.3 C2REVID: C2 Revision ID .......................359
23.4.4 C2FPCTL: C2 Flash Programming Control..................360
23.4.5 C2FPDAT: C2 Flash Programming Data ..................360
24. Revision History.............................361
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1. System Overview
1.1 Introduction
EFM8UB3 Reference Manual
System Overview
C2CK/RSTb
VDD
VREGIN
GND
D+
VBUS
CIP-51 8051 Controller
C2D
Programming
Power-On
Independent
Watchdog
Timer
Debug /
Hardware
Reset
Reset
Supply
Monitor
Core
40 KB ISP Flash
Program Memory
256 Byte SRAM
2048 Byte XRAM
SYSCLK
System Clock
Configuration
EXTCLK
Voltage
Regulators
Power
Net
Low Freq.
Oscillator
CMOS Oscillator
Input
48 MHz 1.5%
Oscillator
Clock
Recovery
24.5 MHz 2%
Oscillator
SFR
Bus
USB Peripheral
D-
Full / Low
Speed
Transceiver
1 KB RAM Low Power
Controller
Charge
Detection
Port I/O Configuration
Digital Peripherals
UART1
Timers 0,
1, 2, 3, 4, 5
3-ch PCA
I2C /
SMBus
SPI
CRC
Config.
Logic
Units (4)
Analog Peripherals
Internal
Reference
VREFVDD
12/10 bit
ADC
2 Comparators
Priority
Crossbar
Decoder
Crossbar
Control
AMUX
Sensor
+
+
-
-
VDD
Temp
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
P0.n
P1.n
P2.n
Figure 1.1. Detailed EFM8UB3 Block Diagram
This section describes the EFM8UB3 family at a high level.
For more information on the device packages and pinout, electrical specifications, and typical connection diagrams, see the EFM8UB3
Data Sheet. For more information on each module including register definitions, see the EFM8UB3 Reference Manual. For more inforÂmation on any errata, see the EFM8UB3 Errata.
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EFM8UB3 Reference Manual
System Overview
1.2 Power
Control over the device power consumption can be achieved by enabling/disabling individual peripherals as needed. Each analog peÂripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their
clocks gated off and draw little power when they are not in use.
Table 1.1. Power Modes
Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational — —
Idle • Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Suspend • Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in normal bias mode for fast wake
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
Stop • All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO on
• Pins retain state
• Exit on any reset source
Snooze • Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in low bias current mode for energy savÂings
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
Set IDLE bit in PCON0 Any interrupt
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• Port Match Event
• Comparator 0 Falling
Edge
• CLUn Interrupt-Enabled
Event
1. Clear STOPCF bit in
Any reset source
REG0CN
2. Set STOP bit in
PCON0
1. Switch SYSCLK to
HFOSC0
2. Set SNOOZE bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• Port Match Event
• Comparator 0 Falling
Edge
• CLUn Interrupt-Enabled
Event
Shutdown • All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO off to save energy
• Pins retain state
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
• RSTb pin reset
• Power-on reset
• Exit on pin or power-on reset
1.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.6 can be defined as genÂeral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0.
The port control block offers the following features:
• Up to 17 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each port.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 17 direct-pin interrupt sources with shared interrupt vector (Port Match).
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EFM8UB3 Reference Manual
System Overview
1.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
The clock control system offers the following features:
• Provides clock to core and peripherals.
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
• 48 MHz internal oscillator (HFOSC1), accurate to ±1.5% over supply and temperature corners.
• 80 kHz low-frequency oscillator (LFOSC0).
• External CMOS clock input (EXTCLK).
• Clock divider with eight settings for flexible clock scaling:
• Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
• HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility.
1.5 Counters/Timers and PWM
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare modÂule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
• 16-bit time base
• Programmable clock divisor and clock source selection
• Up to three independently-configurable channels
• 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)
• Output polarity control
• Frequency output mode
• Capture on rising, falling or any edge
• Compare function for arbitrary waveform generation
• Software timer (internal compare) mode
• Can accept hardware “kill” signal from comparator 0 or comparator 1
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EFM8UB3 Reference Manual
System Overview
Timers (Timer 0, Timer 1, Timer 2, Timer 3, Timer 4, and Timer 5)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time interÂvals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2, Timer 3, Timer 4, and Timer 5 are 16-bit timers including the following features:
• Clock sources for all timers include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8
• LFOSC0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend/snooze power modes
• Timer 4 is a low-power wake source, and can be chained together with Timer 3
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• External pin capture
• LFOSC0 capture
• Comparator 0 capture
• USB Start-of-Frame (SOF) capture
• Configurable Logic output capture
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.
The state of the RST pin is unaffected by this reset.
The Watchdog Timer has the following features:
• Programmable timeout interval
• Runs from the low-frequency oscillator
• Lock-out feature to prevent any modification until a system reset
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EFM8UB3 Reference Manual
System Overview
1.6 Communications and Other Digital Peripherals
Universal Serial Bus (USB0)
The USB0 peripheral provides a full-speed USB 2.0 compliant device controller and PHY with additional Low Energy USB features. The
device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock reÂcovery mechanism for crystal-free operation. No external components are required. The USB function controller (USB0) consists of a
Serial Interface Engine (SIE), USB transceiver (including matching resistors and configurable pull-up resistors), and 1 KB FIFO block.
The Low Energy Mode ensures the current consumption is optimized and enables USB communication on a strict power budget.
The USB0 module includes the following features:
• Full and Low Speed functionality.
• Implements 4 bidirectional endpoints.
• Low Energy Mode to reduce active supply current based on bus bandwidth.
• USB 2.0 compliant USB peripheral support (no host capability).
• Direct module access to 1 KB of RAM for FIFO memory.
• Clock recovery to meet USB clocking requirements with no external components.
• Charger detection circuitry with automatic detection of SDP, CDP, and DCP interfaces.
• D+ and D- can be routed to ADC input to support ACM and proprietary charger architectures.
Universal Asynchronous Receiver/Transmitter (UART1)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a
16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1
to receive multiple bytes before data is lost and an overflow occurs.
UART1 provides the following features:
• Asynchronous transmissions and receptions.
• Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).
• 5, 6, 7, 8, or 9 bit data.
• Automatic start and stop generation.
• Automatic parity generation and checking.
• Four byte FIFO on transmit and receive.
• Auto-baud detection.
• LIN break and sync field detection.
• CTS / RTS hardware flow control.
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
• Supports 3- or 4-wire master or slave modes.
• Supports external clock frequencies up to 12 Mbps in master or slave mode.
• Support for all clock phase and polarity modes.
• 8-bit programmable clock rate (master).
• Programmable receive timeout (slave).
• Two byte FIFO on transmit and receive.
• Can operate in suspend or snooze modes and wake the CPU on reception of a byte.
• Support for multiple masters on the same data lines.
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EFM8UB3 Reference Manual
System Overview
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus SpecificaÂtion, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps), Fast (400 kbps), and Fast Mode Plus (1 Mbps) transfer speeds
• Support for master, slave, and multi-master modes
• Hardware synchronization and arbitration for multi-master mode
• Clock low extending (clock stretching) to interface with faster masters
• Hardware support for 7-bit slave and general call address recognition
• Firmware support for 10-bit slave address decoding
• Ability to inhibit all slave states
• Programmable data setup/hold times
• Transmit and receive FIFOs (two-byte) to help increase throughput in faster applications
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
• Support for CCITT-16 polynomial
• Byte-level bit reversal
• Automatic CRC of flash contents on one or more 256-byte blocks
• Initial seed selection of 0x0000 or 0xFFFF
Configurable Logic Units (CLU0, CLU1, CLU2, and CLU3)
The Configurable Logic block consists of multiple Configurable Logic Units (CLUs). CLUs are flexible logic functions which may be used
for a variety of digital functions, such as replacing system glue logic, aiding in the generation of special waveforms, or synchronizing
system event triggers.
• Four configurable logic units (CLUs), with direct-pin and internal logic connections
• Each unit supports 256 different combinatorial logic functions (AND, OR, XOR, muxing, etc.) and includes a clocked flip-flop for synÂchronous operations
• Units may be operated synchronously or asynchronously
• May be cascaded together to perform more complicated logic functions
• Can operate in conjunction with serial peripherals such as UART and SPI or timing peripherals such as timers and PCA channels
• Can be used to synchronize and trigger multiple on-chip resources (ADC, Timers, etc.)
• Asynchronous output may be used to wake from low-power states
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EFM8UB3 Reference Manual
System Overview
1.7 Analog
12-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a programÂmable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to
measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external
reference sources.
• Up to 16 external inputs.
• Single-ended 12-bit and 10-bit modes.
• Supports an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps samples per second in 10-bit mode.
• Operation in low power modes at lower conversion speeds.
• Asynchronous hardware conversion trigger, selectable between software, external I/O, internal timer sources, and configurable logic
(CLU) sources.
• Output data window comparator allows automatic range checking.
• Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on setÂtling and tracking time.
• Conversion complete and window compare interrupts supported.
• Flexible output data formatting.
• Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for external reference and signal ground.
• Integrated temperature sensor.
Low Current Comparators (CMP0, CMP1)
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator includes the following features:
• Up to 8 (CMP0) or 8 (CMP1) external positive inputs
• Up to 8 (CMP0) or 8 (CMP1) external negative inputs
• Additional input options:
• Internal connection to LDO output
• Direct connection to GND
• Direct connection to VDD
• Dedicated 6-bit reference DAC
• Synchronous and asynchronous outputs can be routed to pins via crossbar
• Programmable hysteresis between 0 and ±20 mV
• Programmable response time
• Interrupts generated on rising, falling, or both edges
• PWM output kill feature
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EFM8UB3 Reference Manual
System Overview
1.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latchÂes are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• USB reset
1.9 Debugging
The EFM8UB3 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugÂging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
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EFM8UB3 Reference Manual
System Overview
1.10 Bootloader
All devices come pre-programmed with a USB bootloader. This bootloader resides in the code security page and last pages of code
flash; it can be erased if it is not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the bootÂloader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The bootÂloader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
More information about the bootloader protocol and usage can be found in AN945: EFM8 Factory Bootloader User Guide. Application
notes can be found on the Silicon Labs website (www.silabs.com/8bit-appnotes) or within Simplicity Studio in the [Documentation]
area.
0xFFFF
0xFFC0
0xFBFF
0xFBFE
0xFBFD
0xFA00
0x9DFF
0x9A00
Read-Only
64 Bytes
Reserved
Lock Byte
Bootloader Signature Byte
Security Page
512 Bytes
Reserved
Bootloader
Bootloader Vector
Bootloader
Memory Lock
Read-Only
64 Bytes
128-bit UUID
0xFFFF
0xFFFE
0xFFD0
0xFFCF
0xFFC0
40 KB Flash
(79 x 512 Byte pages)
0x0000
Figure 1.2. Flash Memory Map with Bootloader—40 KB Devices
Table 1.2. Summary of Pins for Bootloader Communication
Bootloader Pins for Bootload Communication
USB VBUS
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Reset Vector
D+
D-
EFM8UB3 Reference Manual
Table 1.3. Summary of Pins for Bootload Mode Entry
Device Package Pin for Bootload Mode Entry
QFN24 P2.0 / C2D
QSOP24 P2.0 / C2D
QFN20 P2.0 / C2D
System Overview
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EFM8UB3 Reference Manual
Memory
2. Memory
2.1 Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory
spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different
instruction types. Program memory consists of a non-volatile storage area that may be used for either program code or non-volatile
data storage. The data memory, consisting of "internal" and "external" data space, is implemented as RAM, and may be used only for
data storage. Program execution is not supported from the data memory space.
2.2 Program Memory
The CIP-51 core has a 64 KB program memory space. The product family implements some of this program memory space as in-sysÂtem, re-programmable flash memory. Flash security is implemented by a user-programmable location in the flash block and provides
read, write, and erase protection. All addresses not specified in the device memory map are reserved and may not be used for code or
data storage.
MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the devices, the MOVX instruction is
normally used to read and write on-chip XRAM, but can be re-configured to write and erase on-chip flash memory space. MOVC inÂstructions are always used to read flash memory, while MOVX write instructions are used to erase and write flash. This flash access
feature provides a mechanism for the product to update program code and use the program memory space for non-volatile data storÂage.
2.3 Data Memory
The RAM space on the chip includes both an "internal" RAM area which is accessed with MOV instructions, and an on-chip "external"
RAM area which is accessed using MOVX instructions. Total RAM varies, based on the specific device. The device memory map has
more details about the specific amount of RAM available in each area for the different device variants.
Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memoÂry are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower
128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank conÂsisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit
locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the
Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when
accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. InÂstructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper
128 bytes of data memory.
General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each
bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in
the program status word (PSW) register, RS0 and RS1, select the active register bank. This allows fast context switching when entering
subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
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EFM8UB3 Reference Manual
Memory
Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also acÂcessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address
0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished
from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B
is the bit position within the byte. For example, the instruction:
Mov C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer
(SP) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremenÂted. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which
is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a
location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes.
External RAM
On devices with more than 256 bytes of on-chip RAM, the additional RAM is mapped into the external data memory space (XRAM).
Addresses in XRAM area accessed using the external move (MOVX) instructions.
Note: The 16-bit MOVX write instruction is also used for writing and erasing the flash memory. More details may be found in the flash
memory section.
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2.4 Memory Map
EFM8UB3 Reference Manual
Memory
0xFFFF
0xFFC0
0xFBFF
0xFBFE
0xFBFD
0xFA00
0x9DFF
0x9A00
Read-Only
64 Bytes
Reserved
Lock Byte
Bootloader Signature Byte
Security Page
512 Bytes
Reserved
Bootloader
Bootloader Vector
Bootloader
Memory Lock
Read-Only
64 Bytes
128-bit UUID
0xFFFF
0xFFFE
0xFFD0
0xFFCF
0xFFC0
0x0000
40 KB Flash
(79 x 512 Byte pages)
Reset Vector
Figure 2.1. Flash Memory Map — 40 KB Devices
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0xFF
EFM8UB3 Reference Manual
Memory
On-Chip RAM
Accessed with MOV Instructions as Indicated
Upper 128 Bytes
RAM
(Indirect Access)
0x80
0x7F
Lower 128 Bytes RAM
(Direct or Indirect Access)
0x30
0x2F
0x20
0x1F
0x00
Figure 2.2. Direct / Indirect RAM Memory
General-Purpose Register Banks
Bit-Addressable
On-Chip XRAM
Accessed with MOVX Instructions
Special Function
Registers
(Direct Access)
0xFFFF
0x0C00
0x0BFF
0x0800
0x07FF
0x0000
Shadow XRAM
Duplicates 0x0000-0x0BFF
On 3 KB boundaries
USB FIFO XRAM
1024 Bytes
(USBCLK Domain)
XRAM
2048 Bytes
(SYSCLK Domain)
Figure 2.3. XRAM Memory
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EFM8UB3 Reference Manual
2.5 XRAM Control Registers
2.5.1 EMI0CN: External Memory Interface Control
Bit 7 6 5 4 3 2 1 0
Name Reserved PGSEL
Access R RW
Reset 0x0 0x0
SFR Page = ALL; SFR Address: 0xE7
Bit Name Reset Access Description
7:4 Reserved Must write reset value.
3:0 PGSEL 0x0 RW XRAM Page Select.
The XRAM Page Select field provides the high byte of the 16-bit data memory address when using 8-bit MOVX commands,
effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
field determines which page of XRAM is accessed.
For example, if PGSEL = 0x01, addresses 0x0100 to 0x01FF will be accessed by 8-bit MOVX instructions.
Memory
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EFM8UB3 Reference Manual
Special Function Registers
3. Special Function Registers
3.1 Special Function Register Access
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control
and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementaÂtion as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addi-
tion of new functionality while retaining compatibility with the MCS-51 ™ instruction set.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs
with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs
are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an
indeterminate effect and should be avoided.
SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory address space. The SFR
memory space has 256 pages. In this way, each memory location from 0x80 to 0xFF can access up to 256 SFRs. The EFM8UB3
devices utilize multiple SFR pages. All of the common 8051 SFRs are available on all pages. Certain SFRs are only available on a
subset of pages. SFR pages are selected using the SFRPAGE register. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
The SFRPAGE register only needs to be changed in the case that the SFR to be accessed does not exist on the currently-selected
page. See the SFR memory map for details on the locations of each SFR.
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EFM8UB3 Reference Manual
Special Function Registers
Interrupts and the SFR Page Stack
When an interrupt occurs, the current SFRPAGE is pushed onto an SFR page stack to preserve the current context of SFRPAGE.
Upon execution of the RETI instruction, the SFRPAGE register is automatically restored to the SFR page that was in use prior to the
interrupt. The stack is five elements deep to accomodate interrupts of different priority levels pre-empting lower priority interrupts. FirmÂware can read any element of the SFR page stack by setting the SFRPGIDX field in the SFRPGCN register and reading the
SFRSTACK register.
Table 3.1. SFR Page Stack Access
SFRPGIDX Value SFRSTACK Contains
0 Value of the first/top byte of the stack
1 Value of the second byte of the stack
2 Value of the third byte of the stack
3 Value of the fourth byte of the stack
4 Value of the fifth/bottom byte of the stack
Notes:
1. The top of the stack is the current SFRPAGE setting, and can also be directly accessed via the SFRPAGE register.
SFRPGEN
Interrupt
Logic
SFR Page
SFRPAGE
SFRPGIDX
000
001
010
SFRSTACK
Stack
011
100
Figure 3.1. SFR Page Stack Block Diagram
When an interrupt occurs, hardware performs the following operations:
1. The value (if any) in the SFRPGIDX = 011b location is pushed to the SFRPAGE = 100b location.
2. The value (if any) in the SFRPGIDX = 010b location is pushed to the SFRPAGE = 011b location.
3. The value (if any) in the SFRPGIDX = 001b location is pushed to the SFRPAGE = 010b location.
4. The current SFRPAGE value is pushed to the SFRPGIDX = 001b location in the stack.
5. SFRPAGE is set to the page associated with the flag that generated the interrupt.
On a return from interrupt, hardware performs the following operations:
1. The SFR page stack is popped to the SFRPAGE register. This restores the SFR page context prior to the interrupt, without softÂware intervention.
2. The value in the SFRPGIDX = 010b location of the stack is placed in the SFRPGIDX = 001b location.
3. The value in the SFRPGIDX = 011b location of the stack is placed in the SFRPGIDX = 010b location.
4. The value in the SFRPGIDX = 100b location of the stack is placed in the SFRPGIDX = 011b location.
Automatic hardware switching of the SFR page upon interrupt entries and exits may be enabled or disabled using the SFRPGEN locaÂted in SFRPGCN. Automatic SFR page switching is enabled after any reset.
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Special Function Registers
3.2 Special Function Register Memory Map
Table 3.2. Special Function Registers by Address
Address SFR Page Address SFR Page
(*bit-addressÂable)
0x00 0x10 0x20 (*bit-address-
able)
0x00 0x10 0x20
0x80* P0 0xC0* SMB0CN0 TMR5CN0 SMB0CN0
0x81 SP 0xC1 SMB0CF PFE0CN SMB0CF
0x82 DPL 0xC2 SMB0DAT - SMB0DAT
0x83 DPH 0xC3 ADC0GTL SMB0FCN0
0x84 - CLU0MX 0xC4 ADC0GTH SMB0FCN1
0x85 IT01CF CLU1MX 0xC5 ADC0LTL SMB0RXLN
0x86 CRC0CN1 - CRC0CN1 0xC6 ADC0LTH REG1CN
0x87 PCON0 0xC7 HFO0CAL CLU3FN
0x88* TCON 0xC8* TMR2CN0 -
0x89 TMOD 0xC9 REG0CN - REG0CN
0x8A TL0 0xCA TMR2RLL CLU3CF
0x8B TL1 0xCB TMR2RLH CLEN0
0x8C TH0 0xCC TMR2L -
0x8D TH1 0xCD TMR2H CLIE0
0x8E CKCON0 0xCE CRC0CN0 EIE2 CRC0CN0
0x8F PSCTL 0xCF CRC0FLIP SFRPGCN CRC0FLIP
0x90* P1 0xD0* PSW
0x91 TMR3CN0 CLU2MX 0xD1 REF0CN -
0x92 TMR3RLL CLU3MX 0xD2 CRC0ST TMR5RLL CRC0ST
0x93 TMR3RLH SMOD1 0xD3 CRC0CNT TMR5RLH CRC0CNT
0x94 TMR3L SBCON1 0xD4 P0SKIP TMR5L P0SKIP
0x95 TMR3H SBRLL1 0xD5 P1SKIP TMR5H P1SKIP
0x96 PCA0POL SBRLH1 0xD6 SMB0ADM HFO1CAL SMB0ADM
0x97 WDTCN 0xD7 SMB0ADR SFRSTACK SMB0ADR
0x98* SCON1 TMR4CN0 SCON1 0xD8* PCA0CN0 UART1FCN1
0x99 SBUF1 CMP0CN1 SBUF1 0xD9 PCA0MD CLOUT0
0x9A - SPI0FCN0 0xDA PCA0CPM0 UART1PCF
0x9B CMP0CN0 SPI0FCN1 0xDB PCA0CPM1 -
0x9C PCA0CLR - 0xDC PCA0CPM2 -
0x9D CMP0MD UART1FCN0 0xDD CRC0IN - CRC0IN
0x9E PCA0CENT UART1LIN 0xDE CRC0DAT - CRC0DAT
0x9F CMP0MX - 0xDF ADC0PWR SPI0PCF
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