Silicon Laboratories EFM8SB2 Reference Manual
EFM8 Sleepy Bee Family
EFM8SB2 Reference Manual
The EFM8SB2, part of the Sleepy Bee family of MCUs, is the
world’s most energy friendly 8-bit microcontrollers with a comprehensive feature set in small packages.
These devices offer lowest power consumption by combining innovative low energy techniques and short wakeup times from energy saving modes into small packages, making
them well-suited for any battery operated applications. With an efficient 8051 core, 6-bit
current reference, and precision analog, the EFM8SB2 family is also optimal for embedded applications.
EFM8SB2 applications include the following:
• Hand-held devices
Industrial controls
•
CIP-51 8051 Core
Flash Program
Memory
(up to 64 KB)
Core / Memory Clock Management
(25 MHz)
RAM Memory
(4352 bytes)
• Battery-operated consumer electronics
•
Sensor interfaces
External
Oscillator
Debug Interface
with C2
External 32 kHz
RTC Oscillator
Low Power 20
MHz RC
Oscillator
High Frequency
24.5 MHz RC
Oscillator
ENERGY FRIENDLY FEATURES
• Lowest MCU sleep current with supply
brownout detection (50 nA)
•
Lowest MCU active current with these
features (170 μA / MHz at 24.5 MHz clock
rate)
• Lowest MCU sleep current using internal
RTC operating and supply brownout
detection (<300 nA)
• Ultra-fast wake up for digital and analog
peripherals (< 2 μs)
• Integrated low drop out (LDO) voltage
regulator to maintain ultra-low active
current at all voltages
Energy Management
Internal LDO
Regulator
Brown-Out Detector
Power-On Reset
8-bit SFR bus
Serial Interfaces Timers and Triggers Analog Interfaces
UART
2
I
C / SMBus
Lowest power mode with peripheral operational:
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2 x SPI
IdleNormal Suspend Sleep
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
Timers
0/1/2/3
Watchdog
Timer
PCA/PWM
Real Time
Clock
ADC
Comparator 1
Internal Current Reference
Comparator 0
Internal Voltage
Reference
SecurityI/O Ports
16/32-bit CRC
1. System Overview
1.1 Introduction
EFM8SB2 Reference Manual
System Overview
C2CK/RSTb
VDD
GND
XTAL3
XTAL4
Power On
Reset/PMU
Debug /
Programming
Hardware
C2D
Power Net
Analog
Power
Wake
Reset
XTAL1
XTAL2
CIP-51 8051 Controller
Core
64/32/16 KB ISP Flash
Program Memory
256 Byte SRAM
4096 Byte XRAM
VREG
Digital
Power
System Clock
Configuration
Precision
24.5 MHz
Oscillator
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
RTC
Oscillator
SYSCLK
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 3
Priority
PCA/WDT
SMBus
SPI 0,1
CRC
Crossbar Control
Crossbar
Decoder
External Memory Interface
Control
Address
Data
Analog Peripherals
VREF
External
VREF
10-bit
300ksps
ADC
AMUX
VDD
VREF
Temp
Sensor
GND
Internal
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Comparators
+
+
-
-
6-bit
IREF
P0.n
P1.n
P2.n
IREF0
Figure 1.1. Detailed EFM8SB2 Block Diagram
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EFM8SB2 Reference Manual
System Overview
1.2 Power
internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
All
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 1.1. Power Modes
Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational — —
Idle • Core halted
•
All peripherals clocked and fully operational
Set IDLE bit in PCON0 Any interrupt
• Code resumes execution on wake event
Suspend • Core and digital peripherals halted
•
Internal oscillators disabled
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0 or LPOSC0
2.
Set SUSPEND bit in
PMU0CF
• RTC0 Alarm Event
• RTC0 Fail Event
• Port Match Event
• Comparator 0 Rising
Edge
Sleep • Most internal power nets shut down
•
Select circuits remain powered
• Pins retain state
• All RAM and SFRs retain state
• Code resumes execution on wake event
1. Disable unused analog peripherals
2.
Set SLEEP bit in
PMU0CF
• RTC0 Alarm Event
• RTC0 Fail Event
• Port Match Event
• Comparator 0 Rising
Edge
1.3 I/O
Digital
and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.6 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7.
• Up to 24 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each pin.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
1.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 20 MHz low power oscillator divided by 8.
• Provides clock to core and peripherals.
• 20 MHz low power oscillator (LPOSC0), accurate to +/- 10% over supply and temperature corners.
• 24.5 MHz internal oscillator (HFOSC0), accurate to +/- 2% over supply and temperature corners.
• External RTC 32 kHz crystal.
• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK).
• Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
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EFM8SB2 Reference Manual
System Overview
1.5 Counters/Timers and PWM
Real Time Clock (RTC0)
RTC is an ultra low power, 36 hour 32-bit independent time-keeping Real Time Clock with alarm. The RTC has a dedicated 32 kHz
The
oscillator. No external resistor or loading capacitors are required, and a missing clock detector features alerts the system if the external
crystal fails. The on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of crystals.
The RTC module includes the following features:
• Up to 36 hours (32-bit) of independent time keeping.
• Support for external 32 kHz crystal or internal self-oscillate mode.
• Internal crystal loading capacitors with 16 levels.
• Operation in the lowest power mode and across the full supported voltage range.
• Alarm and oscillator failure events to wake from the lowest power mode or reset the device.
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
• 16-bit time base.
• Programmable clock divisor and clock source selection.
• Up to six independently-configurable channels
• 8, 9, 10, 11 and 16-bit PWM modes (edge-aligned operation).
• Frequency output mode.
• Capture on rising, falling or any edge.
• Compare function for arbitrary waveform generation.
• Software timer (internal compare) mode.
• Integrated watchdog timer.
Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2 and Timer 3 are 16-bit timers including the following features:
• Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• Comparator 0 or RTC0 capture (Timer 2)
• Comparator 1 or EXTCLK/8 capture (Timer 3)
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System Overview
Watchdog Timer (WDT0)
device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU
The
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software. The state of the RSTb pin is unaffected by this reset.
The Watchdog Timer integrated in the PCA0 peripheral has the following features:
• Programmable timeout interval
• Runs from the selected PCA clock source
• Automatically enabled after any system reset
1.6 Communications and Other Digital Peripherals
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
• Asynchronous transmissions and receptions
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 8- or 9-bit data
• Automatic start and stop generation
Serial Peripheral Interface (SPI0 and SPI1)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
The SPI module includes the following features:
• Supports 3- or 4-wire operation in master or slave modes.
• Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode.
• Support for four clock phase and polarity options.
• 8-bit dedicated clock clock rate generator.
• Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
• Support for master, slave, and multi-master modes.
• Hardware synchronization and arbitration for multi-master mode.
• Clock low extending (clock stretching) to interface with faster masters.
• Hardware support for 7-bit slave and general call address recognition.
• Firmware support for 10-bit slave address decoding.
• Ability to inhibit all slave states.
• Programmable data setup/hold times.
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System Overview
External Memory Interface (EMIF0)
External Memory Interface (EMIF) enables access of off-chip memories and memory-mapped devices connected to the GPIO
The
ports. The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in
either 8-bit or 16-bit formats.
• Supports multiplexed memory access.
• Four external memory modes:
• Internal only.
• Split mode without bank select.
• Split mode with bank select.
• External only
• Configurable ALE (address latch enable) timing.
• Configurable address setup and hold times.
• Configurable write and read pulse widths.
16/32-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data
and posts the result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC
the flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module includes the following features:
• Support for CCITT-16 polynomial (0x1021).
• Support for CRC-32 polynomial (0x04C11DB7).
• Byte-level bit reversal.
• Automatic CRC of flash contents on one or more 1024-byte blocks.
• Initial seed selection of 0x0000/0x00000000 or 0xFFFF/0xFFFFFFFF.
1.7 Analog
Programmable Current Reference (IREF0)
The programmable current reference (IREF0) module enables current source or sink with two output current settings: Low Power Mode
and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 µA steps) and the maximum current output in
High Current Mode is 504 µA (8 µA steps).
The IREF module includes the following features:
• Capable of sourcing or sinking current in programmable steps.
• Two operational modes: Low Power Mode and High Current Mode.
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System Overview
10-Bit Analog-to-Digital Converter (ADC0)
ADC is a successive-approximation-register (SAR) ADC with 10- and 8-bit modes, integrated track-and hold and a programmable
The
window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure
different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external reference
sources.
• Up to 22 external inputs.
• Single-ended 10-bit mode.
• Supports an output update rate of 300 ksps samples per second.
• Operation in low power modes at lower conversion speeds.
• Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.
• Output data window comparator allows automatic range checking.
• Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time.
• Conversion complete and window compare interrupts supported.
• Flexible output data formatting.
• Includes an internal 1.65 V fast-settling reference and support for external reference.
• Integrated temperature sensor.
Low Current Comparators (CMP0, CMP1)
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator module includes the following features:
• Up to 12 external positive inputs.
• Up to 11 external negative inputs.
• Additional input options:
• Capacitive Sense Comparator output.
• VDD.
• VDD divided by 2.
• Internal connection to LDO output.
• Direct connection to GND.
• Synchronous and asynchronous outputs can be routed to pins via crossbar.
• Programmable hysteresis between 0 and +/-20 mV.
• Programmable response time.
• Interrupts generated on rising, falling, or both edges.
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System Overview
1.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
The core halts program execution.
•
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include the following:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• RTC0 alarm or oscillator failure
1.9 Debugging
The EFM8SB2 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
1.10 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed.
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EFM8SB2 Reference Manual
Memory Organization
2. Memory Organization
2.1 Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory
spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different
instruction types. Program memory consists of a non-volatile storage area that may be used for either program code or non-volatile
data storage. The data memory, consisting of "internal" and "external" data space, is implemented as RAM, and may be used only for
data storage. Program execution is not supported from the data memory space.
2.2 Program Memory
The CIP-51 core has a 64 KB program memory space. The product family implements some of this program memory space as in-system, re-programmable flash memory. Flash security is implemented by a user-programmable location in the flash block and provides
read, write, and erase protection. All addresses not specified in the device memory map are reserved and may not be used for code or
data storage.
MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the devices, the MOVX instruction is
normally used to read and write on-chip XRAM, but can be re-configured to write and erase on-chip flash memory space. MOVC instructions are always used to read flash memory, while MOVX write instructions are used to erase and write flash. This flash access
feature provides a mechanism for the product to update program code and use the program memory space for non-volatile data storage.
2.3 Data Memory
The RAM space on the chip includes both an "internal" RAM area which is accessed with MOV instructions, and an on-chip "external"
RAM area which is accessed using MOVX instructions. Total RAM varies, based on the specific device. The device memory map has
more details about the specific amount of RAM available in each area for the different device variants.
Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower
128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit
locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the
Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when
accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper
128 bytes of data memory.
General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each
bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in
the program status word (PSW) register, RS0 and RS1, select the active register bank. This allows fast context switching when entering
subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
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Memory Organization
Bit Addressable Locations
addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also ac-
In
cessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address
0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished
from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B
is the bit position within the byte. For example, the instruction:
Mov C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
Stack
A
programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer
(SP) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which
is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a
location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes.
External RAM
On devices with more than 256 bytes of on-chip RAM, the additional RAM is mapped into the external data memory space (XRAM).
Addresses in XRAM area accessed using the external move (MOVX) instructions.
Note: The 16-bit MOVX write instruction is also used for writing and erasing the flash memory. More details may be found in the flash
memory section.
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2.4 Memory Map
EFM8SB2 Reference Manual
Memory Organization
0xFFFF
Reserved
0xFBFF Lock Byte
0xFBFE
Security Page
1024 Bytes
0xF800
0x0000
63 KB Flash
(63 x 1024 Byte pages)
0x03FF
0x0000
Figure 2.1. Flash Memory Map — 64 KB Devices
Scratchpad
1024 Bytes
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0xFFFF
Reserved
0x7FFF Lock Byte
0x7FFE
Security Page
1024 Bytes
0x7C00
EFM8SB2 Reference Manual
Memory Organization
0x0000
32 KB Flash
(32 x 1024 Byte pages)
0x03FF
0x0000
Figure 2.2. Flash Memory Map — 32 KB Devices
Scratchpad
1024 Bytes
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0xFFFF
Reserved
0x3FFF Lock Byte
0x3FFE
Security Page
1024 Bytes
0x3C00
EFM8SB2 Reference Manual
Memory Organization
0x0000
16 KB Flash
(16 x 1024 Byte pages)
0x03FF
0x0000
Figure 2.3. Flash Memory Map — 16 KB Devices
On-Chip RAM
Accessed with MOV Instructions as Indicated
0xFF
Upper 128 Bytes
RAM
(Indirect Access)
Special Function
Registers
(Direct Access)
0x80
0x7F
Lower 128 Bytes RAM
(Direct or Indirect Access)
0x30
0x2F
0x20
0x1F
0x00
General-Purpose Register Banks
Bit-Addressable
Scratchpad
1024 Bytes
Figure 2.4. Direct / Indirect RAM Memory
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0xFFFF
0x1000
0x0FFF
0x0000
EFM8SB2 Reference Manual
Memory Organization
On-Chip XRAM
Accessed with MOVX Instructions
Shadow XRAM
Duplicates 0x0000-0x0FFF
On 4096 B boundaries
XRAM
4096 Bytes
Figure 2.5. XRAM Memory
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EFM8SB2 Reference Manual
Special Function Registers
3. Special Function Registers
3.1 Special Function Register Access
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control
and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addi-
tion of new functionality while retaining compatibility with the MCS-51 ™ instruction set.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs
with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs
are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an
indeterminate effect and should be avoided.
SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory address space. The SFR
memory space has 256 pages. In this way, each memory location from 0x80 to 0xFF can access up to 256 SFRs. The EFM8SB2
devices utilize multiple SFR pages. All of the common 8051 SFRs are available on all pages. Certain SFRs are only available on a
subset of pages. SFR pages are selected using the SFRPAGE register. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
The SFRPAGE register only needs to be changed in the case that the SFR to be accessed does not exist on the currently-selected
page. See the SFR memory map for details on the locations of each SFR. It is good practice inside of interrupt service routines to save
the current SFRPAGE at the beginning of the ISR and restore this value at the end.
Interrupts and SFR Paging
In any system which changes the SFRPAGE while interrupts are active, it is good practice to save the current SFRPAGE value upon
ISR entry, and then restore the SFRPAGE before exiting the ISR. This ensures that SFRPAGE will remain at the desired setting when
returning from the ISR.
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Special Function Registers
3.2 Special Function Register Memory Map
Table 3.1. Special Function Registers by Address
Address SFR Page Address SFR Page
(*bit-addressable) 0x00 0x0F (*bit-addressable) 0x00 0x0F
0x80* P0 0xC0* SMB0CN0 -
0x81 SP 0xC1 SMB0CF -
0x82 DPL 0xC2 SMB0DAT -
0x83 DPH 0xC3 ADC0GTL -
0x84 SPI1CFG - 0xC4 ADC0GTH -
0x85 SPI1CKR TOFFL 0xC5 ADC0LTL -
0x86 SPI1DAT TOFFH 0xC6 ADC0LTH -
0x87 PCON0 0xC7 P0MASK -
0x88* TCON - 0xC8* TMR2CN0 -
0x89 TMOD - 0xC9 REG0CN -
0x8A TL0 - 0xCA TMR2RLL -
0x8B TL1 - 0xCB TMR2RLH -
0x8C TH0 - 0xCC TMR2L -
0x8D TH1 - 0xCD TMR2H -
0x8E CKCON0 - 0xCE PCA0CPM5 -
0x8F PSCTL - 0xCF P1MAT -
0x90* P1 0xD0* PSW
0x91 TMR3CN0 CRC0DAT 0xD1 REF0CN -
0x92 TMR3RLL CRC0CN0 0xD2 PCA0CPL5 -
0x93 TMR3RLH CRC0IN 0xD3 PCA0CPH5 -
0x94 TMR3L - 0xD4 P0SKIP -
0x95 TMR3H CRC0FLIP 0xD5 P1SKIP -
0x96 - CRC0AUTO 0xD6 P2SKIP -
0x97 - CRC0CNT 0xD7 P0MAT -
0x98* SCON0 - 0xD8* PCA0CN0 -
0x99 SBUF0 - 0xD9 PCA0MD -
0x9A CMP1CN0 - 0xDA PCA0CPM0 -
0x9B CMP0CN0 - 0xDB PCA0CPM1 -
0x9C CMP1MD - 0xDC PCA0CPM2 -
0x9D CMP0MD - 0xDD PCA0CPM3 -
0x9E CMP1MX - 0xDE PCA0CPM4 -
0x9F CMP0MX - 0xDF PCA0PWM -
0xA0* P2 0xE0* ACC
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Special Function Registers
Address SFR Page Address SFR Page
(*bit-addressable) 0x00 0x0F (*bit-addressable) 0x00 0x0F
0xA1 SPI0CFG - 0xE1 XBR0 -
0xA2 SPI0CKR - 0xE2 XBR1 -
0xA3 SPI0DAT - 0xE3 XBR2 -
0xA4 P0MDOUT P0DRV 0xE4 IT01CF -
0xA5 P1MDOUT P1DRV 0xE5 -
0xA6 P2MDOUT P2DRV 0xE6 EIE1
0xA7 SFRPAGE 0xE7 EIE2
0xA8* IE 0xE8* ADC0CN0 -
0xA9 CLKSEL 0xE9 PCA0CPL1 -
0xAA EMI0CN - 0xEA PCA0CPH1 -
0xAB EMI0CF - 0xEB PCA0CPL2 -
0xAC RTC0ADR - 0xEC PCA0CPH2 -
0xAD RTC0DAT - 0xED PCA0CPL3 -
0xAE RTC0KEY - 0xEE PCA0CPH3 -
0xAF EMI0TC - 0xEF RSTSRC -
0xB0* SPI1CN0 - 0xF0* B
0xB1 XOSC0CN - 0xF1 P0MDIN -
0xB2 HFO0CN - 0xF2 P1MDIN -
0xB3 HFO0CAL - 0xF3 P2MDIN -
0xB4 - 0xF4 SMB0ADR -
0xB5 PMU0CF - 0xF5 SMB0ADM -
0xB6 FLSCL - 0xF6 EIP1
0xB7 FLKEY - 0xF7 EIP2
0xB8* IP 0xF8* SPI0CN0 -
0xB9 IREF0CN0 - 0xF9 PCA0L -
0xBA ADC0AC ADC0PWR 0xFA PCA0H -
0xBB ADC0MX - 0xFB PCA0CPL0 -
0xBC ADC0CF - 0xFC PCA0CPH0 -
0xBD ADC0L ADC0TK 0xFD PCA0CPL4 -
0xBE ADC0H - 0xFE PCA0CPH4 -
0xBF P1MASK - 0xFF VDM0CN -
Table 3.2. Special Function Registers by Name
Register Address SFR Pages Description
ACC 0xE0 ALL Accumulator
ADC0AC 0xBA 0x00 ADC0 Accumulator Configuration
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Register Address SFR Pages Description
ADC0CF 0xBC 0x00 ADC0 Configuration
ADC0CN0 0xE8 0x00 ADC0 Control 0
ADC0GTH 0xC4 0x00 ADC0 Greater-Than High Byte
ADC0GTL 0xC3 0x00 ADC0 Greater-Than Low Byte
ADC0H 0xBE 0x00 ADC0 Data Word High Byte
ADC0L 0xBD 0x00 ADC0 Data Word Low Byte
ADC0LTH 0xC6 0x00 ADC0 Less-Than High Byte
ADC0LTL 0xC5 0x00 ADC0 Less-Than Low Byte
ADC0MX 0xBB 0x00 ADC0 Multiplexer Selection
ADC0PWR 0xBA 0x0F ADC0 Power Control
ADC0TK 0xBD 0x0F ADC0 Burst Mode Track Time
B 0xF0 ALL B Register
CKCON0 0x8E 0x00 Clock Control 0
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Special Function Registers
CLKSEL 0xA9 ALL Clock Select
CMP0CN0 0x9B 0x00 Comparator 0 Control 0
CMP0MD 0x9D 0x00 Comparator 0 Mode
CMP0MX 0x9F 0x00 Comparator 0 Multiplexer Selection
CMP1CN0 0x9A 0x00 Comparator 1 Control 0
CMP1MD 0x9C 0x00 Comparator 1 Mode
CMP1MX 0x9E 0x00 Comparator 1 Multiplexer Selection
CRC0AUTO 0x96 0x0F CRC0 Automatic Control
CRC0CN0 0x92 0x0F CRC0 Control 0
CRC0CNT 0x97 0x0F CRC0 Automatic Flash Sector Count
CRC0DAT 0x91 0x0F CRC0 Data Output
CRC0FLIP 0x95 0x0F CRC0 Bit Flip
CRC0IN 0x93 0x0F CRC0 Data Input
DPH 0x83 ALL Data Pointer High
DPL 0x82 ALL Data Pointer Low
EIE1 0xE6 ALL Extended Interrupt Enable 1
EIE2 0xE7 ALL Extended Interrupt Enable 2
EIP1 0xF6 ALL Extended Interrupt Priority 1
EIP2 0xF7 ALL Extended Interrupt Priority 2
EMI0CF 0xAB 0x00 External Memory Configuration
EMI0CN 0xAA 0x00 External Memory Interface Control
EMI0TC 0xAF 0x00 External Memory Timing Control
FLKEY 0xB7 0x00 Flash Lock and Key
FLSCL 0xB6 0x00 Flash Scale
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Register Address SFR Pages Description
HFO0CAL 0xB3 0x00 High Frequency Oscillator Calibration
HFO0CN 0xB2 0x00 High Frequency Oscillator Control
IE 0xA8 ALL Interrupt Enable
IP 0xB8 ALL Interrupt Priority
IREF0CN0 0xB9 0x00 Current Reference Control 0
IT01CF 0xE4 0x00 INT0/INT1 Configuration
P0 0x80 ALL Port 0 Pin Latch
P0DRV 0xA4 0x0F Port 0 Drive Strength
P0MASK 0xC7 0x00 Port 0 Mask
P0MAT 0xD7 0x00 Port 0 Match
P0MDIN 0xF1 0x00 Port 0 Input Mode
P0MDOUT 0xA4 0x00 Port 0 Output Mode
P0SKIP 0xD4 0x00 Port 0 Skip
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Special Function Registers
P1 0x90 ALL Port 1 Pin Latch
P1DRV 0xA5 0x0F Port 1 Drive Strength
P1MASK 0xBF 0x00 Port 1 Mask
P1MAT 0xCF 0x00 Port 1 Match
P1MDIN 0xF2 0x00 Port 1 Input Mode
P1MDOUT 0xA5 0x00 Port 1 Output Mode
P1SKIP 0xD5 0x00 Port 1 Skip
P2 0xA0 ALL Port 2 Pin Latch
P2DRV 0xA6 0x0F Port 2 Drive Strength
P2MDIN 0xF3 0x00 Port 2 Input Mode
P2MDOUT 0xA6 0x00 Port 2 Output Mode
P2SKIP 0xD6 0x00 Port 2 Skip
PCA0CN0 0xD8 0x00 PCA Control 0
PCA0CPH0 0xFC 0x00 PCA Channel 0 Capture Module High Byte
PCA0CPH1 0xEA 0x00 PCA Channel 1 Capture Module High Byte
PCA0CPH2 0xEC 0x00 PCA Channel 2 Capture Module High Byte
PCA0CPH3 0xEE 0x00 PCA Channel 3 Capture Module High Byte
PCA0CPH4 0xFE 0x00 PCA Channel 4 Capture Module High Byte
PCA0CPH5 0xD3 0x00 PCA Channel 5 Capture Module High Byte
PCA0CPL0 0xFB 0x00 PCA Channel 0 Capture Module Low Byte
PCA0CPL1 0xE9 0x00 PCA Channel 1 Capture Module Low Byte
PCA0CPL2 0xEB 0x00 PCA Channel 2 Capture Module Low Byte
PCA0CPL3 0xED 0x00 PCA Channel 3 Capture Module Low Byte
PCA0CPL4 0xFD 0x00 PCA Channel 4 Capture Module Low Byte
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Special Function Registers
Register Address SFR Pages Description
PCA0CPL5 0xD2 0x00 PCA Channel 5 Capture Module Low Byte
PCA0CPM0 0xDA 0x00 PCA Channel 0 Capture/Compare Mode
PCA0CPM1 0xDB 0x00 PCA Channel 1 Capture/Compare Mode
PCA0CPM2 0xDC 0x00 PCA Channel 2 Capture/Compare Mode
PCA0CPM3 0xDD 0x00 PCA Channel 3 Capture/Compare Mode
PCA0CPM4 0xDE 0x00 PCA Channel 4 Capture/Compare Mode
PCA0CPM5 0xCE 0x00 PCA Channel 5 Capture/Compare Mode
PCA0H 0xFA 0x00 PCA Counter/Timer High Byte
PCA0L 0xF9 0x00 PCA Counter/Timer Low Byte
PCA0MD 0xD9 0x00 PCA Mode
PCA0PWM 0xDF 0x00 PCA PWM Configuration
PCON0 0x87 ALL Power Control 0
PMU0CF 0xB5 0x00 Power Management Unit Configuration
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PSCTL 0x8F 0x00 Program Store Control
PSW 0xD0 ALL Program Status Word
REF0CN 0xD1 0x00 Voltage Reference Control
REG0CN 0xC9 0x00 Voltage Regulator Control
RSTSRC 0xEF 0x00 Reset Source
RTC0ADR 0xAC 0x00 RTC Address
RTC0DAT 0xAD 0x00 RTC Data
RTC0KEY 0xAE 0x00 RTC Lock and Key
SBUF0 0x99 0x00 UART0 Serial Port Data Buffer
SCON0 0x98 0x00 UART0 Serial Port Control
SFRPAGE 0xA7 ALL SFR Page
SMB0ADM 0xF5 0x00 SMBus 0 Slave Address Mask
SMB0ADR 0xF4 0x00 SMBus 0 Slave Address
SMB0CF 0xC1 0x00 SMBus 0 Configuration
SMB0CN0 0xC0 0x00 SMBus 0 Control
SMB0DAT 0xC2 0x00 SMBus 0 Data
SP 0x81 ALL Stack Pointer
SPI0CFG 0xA1 0x00 SPI0 Configuration
SPI0CKR 0xA2 0x00 SPI0 Clock Rate
SPI0CN0 0xF8 0x00 SPI0 Control
SPI0DAT 0xA3 0x00 SPI0 Data
SPI1CFG 0x84 0x00 SPI1 Configuration
SPI1CKR 0x85 0x00 SPI1 Clock Rate
SPI1CN0 0xB0 0x00 SPI1 Control
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Register Address SFR Pages Description
SPI1DAT 0x86 0x00 SPI1 Data
TCON 0x88 0x00 Timer 0/1 Control
TH0 0x8C 0x00 Timer 0 High Byte
TH1 0x8D 0x00 Timer 1 High Byte
TL0 0x8A 0x00 Timer 0 Low Byte
TL1 0x8B 0x00 Timer 1 Low Byte
TMOD 0x89 0x00 Timer 0/1 Mode
TMR2CN0 0xC8 0x00 Timer 2 Control 0
TMR2H 0xCD 0x00 Timer 2 High Byte
TMR2L 0xCC 0x00 Timer 2 Low Byte
TMR2RLH 0xCB 0x00 Timer 2 Reload High Byte
TMR2RLL 0xCA 0x00 Timer 2 Reload Low Byte
TMR3CN0 0x91 0x00 Timer 3 Control 0
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Special Function Registers
TMR3H 0x95 0x00 Timer 3 High Byte
TMR3L 0x94 0x00 Timer 3 Low Byte
TMR3RLH 0x93 0x00 Timer 3 Reload High Byte
TMR3RLL 0x92 0x00 Timer 3 Reload Low Byte
TOFFH 0x86 0x0F Temperature Sensor Offset High
TOFFL 0x85 0x0F Temperature Sensor Offset Low
VDM0CN 0xFF 0x00 VDD Supply Monitor Control
XBR0 0xE1 0x00 Port I/O Crossbar 0
XBR1 0xE2 0x00 Port I/O Crossbar 1
XBR2 0xE3 0x00 Port I/O Crossbar 2
XOSC0CN 0xB1 0x00 External Oscillator Control
3.3 SFR Access Control Registers
3.3.1 SFRPAGE: SFR Page
Bit 7 6 5 4 3 2 1 0
Name SFRPAGE
Access RW
Reset 0x00
SFR Page = ALL; SFR Address: 0xA7
Bit Name Reset Access Description
7:0 SFRPAGE 0x00 RW SFR Page.
Specifies the SFR Page used when reading, writing, or modifying special function registers.
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Flash Memory
4. Flash Memory
4.1 Introduction
On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The flash memory is organized in
1024-byte pages. It can be erased and written through the C2 interface or from firmware by overloading the MOVX instruction. Any
individual byte in flash memory must only be written once between page erase operations.
0xFFFF
Reserved
0xFBFF Lock Byte
0xFBFE
Security Page
1024 Bytes
0xF800
0x0000
63 KB Flash
(63 x 1024 Byte pages)
0x03FF
0x0000
Figure 4.1. Flash Memory Map — 64 KB Devices
Scratchpad
1024 Bytes
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0xFFFF
Reserved
0x7FFF Lock Byte
0x7FFE
Security Page
1024 Bytes
0x7C00
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Flash Memory
0x0000
32 KB Flash
(32 x 1024 Byte pages)
0x03FF
0x0000
Figure 4.2. Flash Memory Map — 32 KB Devices
Scratchpad
1024 Bytes
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0xFFFF
Reserved
0x3FFF Lock Byte
0x3FFE
Security Page
1024 Bytes
0x3C00
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Flash Memory
16 KB Flash
(16 x 1024 Byte pages)
0x0000
Figure 4.3. Flash Memory Map — 16 KB Devices
4.2 Features
The flash memory has the following features:
Up to 64 KB organized in 1024-byte sectors.
•
• In-system programmable from user firmware.
• Security lock to prevent unwanted read/write/erase access.
• 1024 bytes of non-volatile data storage in the Scratchpad.
0x03FF
0x0000
Scratchpad
1024 Bytes
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4.3 Functional Description
4.3.1 Security Options
CIP-51 provides security options to protect the flash memory from inadvertent modification by software as well as to prevent the
The
viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program
Store Erase Enable (bit PSEE in register PSCTL) bits protect the flash memory from accidental modification by software. PSWE must
be explicitly set to 1 before software can modify the flash memory; both PSWE and PSEE must be set to 1 before software can erase
flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the
C2 interface.
A Security Lock Byte located in flash user space offers protection of the flash program memory from access (reads, writes, or erases)
by unprotected code or the C2 interface. See the specific device memory map for the location of the security byte. The flash security
mechanism allows the user to lock "n" flash pages, starting at page 0, where "n" is the 1s complement number represented by the
Security Lock Byte.
Note: The page containing the flash Security Lock Byte is unlocked when no other flash pages are locked (all bits of the Lock Byte are
1) and locked when any other flash pages are locked (any bit of the Lock Byte is 0).
Table 4.1. Security Byte Decoding
Security Lock Byte 111111101b
1s Complement 00000010b
Flash Pages Locked 3 (First two flash pages + Lock Byte Page)
The level of flash security depends on the flash access method. The three flash access methods that can be restricted are reads,
writes,
and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked
pages.
Table 4.2. Flash Security Summary—Firmware Permissions
Permissions according to the area firmware is executing from:
Target Area for Read / Write / Erase Unlocked User
Page
Locked User Page Unlocked Data
Page
Locked Data Page
Any Unlocked Page [R] [W] [E] [R] [W] [E] [R] [W] [E] [R] [W] [E]
Locked Page (except security page) reset [R] [W] [E] reset [R] [W] [E]
Locked Security Page reset [R] [W] reset [R] [W]
Reserved Area reset reset reset reset
[R] = Read permitted
[W] = Write permitted
[E] = Erase permitted
reset = Flash error reset triggered
n/a = Not applicable
Table 4.3. Flash Security Summary—C2 Permissions
Target Area for Read / Write / Erase Permissions from C2 interface
Any Unlocked Page [R] [W] [E]
Any Locked Page Device Erase Only
Reserved Area None
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Target Area for Read / Write / Erase Permissions from C2 interface
[R] = Read permitted
[W] = Write permitted
[E] = Erase permitted
Device Erase Only = No read, write, or individual page erase is allowed. Must erase entire flash space.
None = Read, write and erase are not permitted
4.3.2 Programming the Flash Memory
Writes
to flash memory clear bits from logic 1 to logic 0 and can be performed on single byte locations. Flash erasures set bits back to
logic 1 and occur only on full pages. The write and erase operations are automatically timed by hardware for proper execution; data
polling to determine the end of the write/erase operation is not required. Code execution is stalled during a flash write/erase operation.
The simplest means of programming the flash memory is through the C2 interface using programming tools provided by Silicon Labs or
a third party vendor. Firmware may also be loaded into the device to implement code-loader functions or allow non-volatile data storage. To ensure the integrity of flash contents, it is strongly recommended that the on-chip supply monitor be enabled in any system that
includes code that writes and/or erases flash memory from software.
4.3.2.1 Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The FLKEY register must be written with the correct key codes, in sequence, before flash operations may be performed. The key codes are 0xA5 and 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order or the wrong codes are written, flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a flash write or erase is attempted
before the key codes have been written properly. The flash lock resets after each write or erase; the key codes must be written again
before another flash write or erase operation can be performed.
4.3.2.2 Flash Page Erase Procedure
The flash memory is erased one page at a time by firmware using the MOVX write instruction with the address targeted to any byte
within the page. Before erasing a page of flash memory, flash write and erase operations must be enabled by setting the PSWE and
PSEE bits in the PSCTL register to logic 1 (this directs the MOVX writes to target flash memory and enables page erasure) and writing
the flash key codes in sequence to the FLKEY register. The PSWE and PSEE bits remain set until cleared by firmware.
Erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire page, perform the following steps:
1. Disable interrupts (recommended).
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSEE bit (register PSCTL).
5. Set the PSWE bit (register PSCTL).
6. Using the MOVX instruction, write a data byte to any location within the page to be erased.
7. Clear the PSWE and PSEE bits.
4.3.2.3 Flash Byte Write Procedure
The flash memory is written by firmware using the MOVX write instruction with the address and data byte to be programmed provided
as normal operands in DPTR and A. Before writing to flash memory using MOVX, flash write operations must be enabled by setting the
PSWE bit in the PSCTL register to logic 1 (this directs the MOVX writes to target flash memory) and writing the flash key codes in
sequence to the FLKEY register. The PSWE bit remains set until cleared by firmware. A write to flash memory can clear bits to logic 0
but cannot set them. A byte location to be programmed should be erased (already set to 0xFF) before a new value is written.
To write a byte of flash, perform the following steps:
1. Disable interrupts (recommended).
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSWE bit (register PSCTL).
5. Clear the PSEE bit (register PSCTL).
6. Using the MOVX instruction, write a single data byte to the desired location within the desired page.
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7. Clear the PSWE bit.
4.3.3 Flash Write and Erase Precautions
system which contains routines which write or erase flash memory from software involves some risk that the write or erase routines
Any
will execute unintentionally if the CPU is operating outside its specified operating range of supply voltage, system clock frequency or
temperature. This accidental execution of flash modifying code can result in alteration of flash memory contents causing a system failure that is only recoverable by re-flashing the code in the device.
To help prevent the accidental modification of flash by firmware, hardware restricts flash writes and erasures when the supply monitor is
not active and selected as a reset source. As the monitor is enabled and selected as a reset source by default, it is recommended that
systems writing or erasing flash simply maintain the default state.
The following sections provide general guidelines for any system which contains routines which write or erase flash from code. Additional flash recommendations and example code can be found in AN201: Writing to Flash From Firmware, available from the Silicon
Laboratories website.
Voltage Supply Maintenance and the Supply Monitor
• If the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to
ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded.
• Make certain that the minimum supply rise time specification is met. If the system cannot meet this rise time specification, then add
an external supply brownout circuit to the RSTb pin of the device that holds the device in reset until the voltage supply reaches the
lower limit, and re-asserts RSTb if the supply drops below the low supply limit.
• Do not disable the supply monitor. If the supply monitor must be disabled in the system, firmware should be added to the startup
routine to enable the on-chip supply monitor and enable the supply monitor as a reset source as early in code as possible. This
should be the first set of instructions executed after the reset vector. For C-based systems, this may involve modifying the startup
code added by the C compiler. See your compiler documentation for more details. Make certain that there are no delays in software
between enabling the supply monitor and enabling the supply monitor as a reset source.
Note: The supply monitor must be enabled and enabled as a reset source when writing or erasing flash memory. A flash error reset
will occur if either condition is not met.
• As an added precaution if the supply monitor is ever disabled, explicitly enable the supply monitor and enable the supply monitor as
a reset source inside the functions that write and erase flash memory. The supply monitor enable instructions should be placed just
after the instruction to set PSWE to a 1, but before the flash write or erase operation instruction.
• Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and explicitly do not use the
bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
• Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check are initialization code which
enables other reset sources, such as the Missing Clock Detector or Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this.
PSWE Maintenance
• Reduce the number of places in code where the PSWE bit (in register PSCTL) is set to a 1. There should be exactly one routine in
code that sets PSWE to a 1 to write flash bytes and one routine in code that sets PSWE and PSEE both to a 1 to erase flash pages.
• Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates and loop variable maintenance
outside the "PSWE = 1;... PSWE = 0;" area.
• Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been reset to 0. Any interrupts posted
during the flash write or erase operation will be serviced in priority order after the flash operation has been completed and interrupts
have been re-enabled by software.
• Make certain that the flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas.
• Add address bounds checking to the routines that write or erase flash memory to ensure that a routine called with an illegal address
does not result in modification of the flash.
System Clock
• If operating from an external crystal-based source, be advised that crystal performance is susceptible to electrical interference and is
sensitive to layout and to changes in temperature. If the system is operating in an electrically noisy environment, use the internal
oscillator or use an external CMOS clock.
• If operating from the external oscillator, switch to the internal oscillator during flash write or erase operations. The external oscillator
can continue to run, and the CPU can switch back to the external oscillator after the flash operation has completed.
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4.3.4 Minimizing Flash Read Current
The flash memory is responsible for a substantial portion of the total digital supply current when the device is executing code. Below are
suggestions to minimize flash read current.
Use low power modes while waiting for an interrupt, rather than polling the interrupt flag.
1.
2. Disable the one-shot timer.
3. Reduce the number of toggling address lines for short code loops.
Using Low Power Modes
To reduce flash read current, use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the interrupt flag. Idle
mode is particularly well-suited for use in implementing short pauses, since the wake-up time is no more than three system clock cycles. See the Power Management chapter for details on the various low-power operating modes.
Disabling the One-Shot Timer
The flash has a one-shot timer that saves power when operating at system clock frequencies of 10 MHz or less. The one-shot timer
generates a minimum-duration enable signal for the flash sense amps on each clock cycle in which the flash memory is accessed. This
allows the flash to remain in a low power state for the remainder of the long clock cycle.
At clock frequencies above 10 MHz, the system clock cycle becomes short enough that the one-shot timer no longer provides a power
benefit. Disabling the one-shot timer at higher frequencies reduces power consumption. The one-shot is enabled by default, and it can
be disabled (bypassed) by setting the BYPASS bit in the FLSCL register. To reenable the one-shot, clear the BYPASS bit to logic 0.
Reduce Toggling Lines in Loops
Flash read current depends on the number of address lines that toggle between sequential flash read operations. In most cases, the
difference in power is relatively small (on the order of 5%).
The flash memory is organized in rows of 128 bytes. A substantial current increase can be detected when the read address jumps from
one row in the flash memory to another. Consider a 3-cycle loop (e.g., SJMP $, or while(1);) which straddles a flash row boundary. The
flash address jumps from one row to another on two of every three clock cycles. This can result in a current increase of up 30% when
compared to the same 3-cycle loop contained entirely within a single row.
To minimize the power consumption of small loops, it is best to locate them within a single row, if possible. To check if a loop is contained within a flash row, divide the starting address of the first instruction in the loop by 128. If the remainder (result of modulo operation) plus the length of the loop is less than 127, then the loop fits inside a single flash row. Otherwise, the loop will be straddling two
adjacent flash rows. If a loop executes in 20 or more clock cycles, then the transitions from one row to another will occur on relatively
few clock cycles, and any resulting increase in operating current will be negligible.
4.3.5 Scratchpad
An additional scratchpad area is available for non-volatile data storage. It is accessible at addresses 0x0000 to 0x03FF when the SFLE
bit is set to 1. The scratchpad area cannot be used for code execution. The scratchpad is locked when all other flash pages are locked,
and it is erased when a Flash Device Erase command is performed.
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4.4 Flash Control Registers
4.4.1 PSCTL: Program Store Control
Bit 7 6 5 4 3 2 1 0
Name Reserved SFLE PSEE PSWE
Access R RW RW RW
Reset 0x00 0 0 0
SFR Page = 0x0; SFR Address: 0x8F
Bit Name Reset Access Description
7:3 Reserved Must write reset value.
2 SFLE 0 RW Scratchpad Flash Memory Access Enable.
When this bit is set, flash MOVC reads and MOVX writes from user software are directed to the Scratchpad flash sector.
Flash accesses outside the address range 0x0000-0x01FF should not be attempted and may yield undefined results when
SFLE is set to 1.
Value Name Description
0 SCRATCHPAD_DISA-
Flash access from user software directed to the Program/Data Flash sector.
BLED
1 SCRATCHPAD_ENA-
Flash access from user software directed to the Scratchpad sector.
BLED
1 PSEE 0 RW Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of flash program memory to be erased. If this bit is logic 1
and
flash writes are enabled (PSWE is logic 1), a write to flash memory using the MOVX instruction will erase the entire
page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter.
Value Name Description
0 ERASE_DISABLED Flash program memory erasure disabled.
1 ERASE_ENABLED Flash program memory erasure enabled.
0 PSWE 0 RW Program Store Write Enable.
Setting this bit allows writing a byte of data to the flash program memory using the MOVX write instruction. The flash location should be erased before writing data.
Value Name Description
0 WRITE_DISABLED Writes to flash program memory disabled.
1 WRITE_ENABLED Writes to flash program memory enabled; the MOVX write instruction targets flash
memory.
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EFM8SB2 Reference Manual
Flash Memory
4.4.2 FLKEY: Flash Lock and Key
Bit 7 6 5 4 3 2 1 0
Name FLKEY
Access RW
Reset 0x00
SFR Page = 0x0; SFR Address: 0xB7
Bit Name Reset Access Description
7:0 FLKEY 0x00 RW Flash Lock and Key Register.
Write:
This
register provides a lock and key function for flash erasures and writes. Flash writes and erases are enabled by writing
0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or
erase is complete. If any writes to FLKEY are performed incorrectly, or if a flash write or erase operation is attempted while
these operations are disabled, the flash will be permanently locked from writes or erasures until the next device reset. If an
application never writes to flash, it can intentionally lock the flash by writing a non-0xA5 value to FLKEY from firmware.
Read:
When read, bits 1-0 indicate the current flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases are disabled until the next reset.
4.4.3 FLSCL: Flash Scale
Bit 7 6 5 4 3 2 1 0
Name Reserved BYPASS Reserved
Access R RW R
Reset 0 0 0x00
SFR Page = 0x0; SFR Address: 0xB6
Bit Name Reset Access Description
7 Reserved Must write reset value.
6 BYPASS 0 RW Flash Read Timing One-Shot Bypass.
Value Name Description
0 ONE_SHOT The one-shot determines the flash read time. This setting should be used for op-
erating frequencies less than 14 MHz.
1 SYSCLK The system clock determines the flash read time. This setting should be used for
frequencies greater than 14 MHz.
5:0 Reserved Must write reset value.
When changing the BYPASS bit from 1 to 0, the third opcode byte fetched from program memory is indeterminate. Therefore, the
operation which clears the BYPASS bit should be immediately followed by a benign 3-byte instruction whose third byte is a don't care.
An
example of such an instruction is a 3-byte MOV that targets the CRC0FLIP register. When programming in C, the dummy value
written to CRC0FLIP should be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction.
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