Silicon Laboratories CP2120, CP2120-EK User Manual

CP2120-EK

CP2120 EVALUATION KIT USER’S GUIDE

1. Kit Contents

The CP2120 Evaluation Kit contains a CP2120 evaluation board and a power supply. The following supporting
documents can be downloaded from www.silabs.com:

 CP2120 Data Sheet
 AN311: CP2120 Porting Guide

2. CP2120 Hardware Interface

The evaluation board is connected to a SPI master and to SMBus devices as shown in Figure 1.

1. Connect the SPI Master’s SPI bus lines to the CP2120. If The CP2120 is the only SPI slave device on the
SPI bus, then the CS pin can be tied low.

2. Connect the CP2120’s INT pin to a port pin of the SPI Master.

3. Connect the CP2120 to SMBus devices through the SMBus lines.

Please refer to "4. Evaluation Board" on page 2 for more information about these steps.

SMBus

Device

SPI Bus

MOSI

SCK

CS

SPI Master CP2120

MISO

INT

SMBus

SDA

SCL

SMBus

Device

SMBus

Device

Figure 1. System Connections

3. CP2120 Operation

Once connected as shown in Figure 1, the SPI Master issues commands to the CP2120 across the SPI bus. The
CP2120 responds to commands by initiating an SMBus transfer with SMBus slave devices, reading from or writing
to internal registers, or interfacing with general purpose input/output (I/O) port pins. When an SMBus transaction
completes, the CP2120 pulls the INT pin low, which signals the SPI Master that the command has been processed.

Rev. 0.1 9/06 Copyright © 2006 by Silicon Laboratories CP2120-EK

CP2120-EK

4. Evaluation Board

The CP2120 evaluation board comes with a CP2120 device pre-installed for system evaluation and development.
Numerous I/O connections are provided to facilitate prototyping using the evaluation board. Refer to Figure 2 for
the locations of the various I/O connectors.

J1 Power Connector

J2 SPI Master Interface

J3 SMBus Interface

J4 MISO-MOSI Connector

J6 SMBus SDA Pullup Connector

J7 SMBus SCL Pullup Connector

J9 LED Connector

J10 General Purpose I/O Interface

POWER

J1

J2

J4

J9

D7 D0D1D2D3D4D5D6

SA-TB51PCB

SILICON LABORATORIES

Figure 2. CP2120 Evaluation Board

J6

J7

J3

J10

2 Rev. 0.1

CP2120-EK

4.1. J2—SPI Master Interface

Connector J2 provides the SPI Master access to the CP2120 SPI, control, and reset lines. Table 1 shows the
pinout of the J2 header.

Table 1. Pinout for J2

Pin 1 SPI Bus—SCLK

Pin 2 SPI Bus—MISO

Pin 3 SPI Bus—MOSI

Pin 4 SPI Bus—CS

Pin 5 INT

Pin 6 Not Used

Pin 7 RST

Pin 8 GND

Pin 9 Not Used

Pin 10 Not Used

4.2. J3—SMBus Interface

Connector J3 provides the CP2120 access to the SMBus. Table 2 shows the pinout of the J3 header.

Note: All pins labeled SCL are tied together, and all pins labeled SDA are tied together. Multiple connections to SCL and SDA

signals are provided to allow multiple devices to connect to the evaluation board.

Table 2. Pinout for J3

Pin 1 SMBus—SCL

Pin 2 SMBus—SDA

Pin 3 SMBus—SCL

Pin 4 SMBus—SDA

Pin 5 SMBus—SCL

Pin 6 SMBus—SDA

Pin 7 SMBus—SCL

Pin 8 SMBus—SDA

Pin 9 GND

Pin 10 GND

Rev. 0.1 3