Silicon Laboratories C8051F320, C8051F321 Technical data
C8051F320/1
Full Speed USB, 16k ISP FLASH MCU Family
ANALOG PERIPHERALS
- 10-Bit ADC
• Up to 200 ksps
• Up to 17 or 13 External Single-Ended or Differential
Inputs
• VREF from External Pin, Internal Reference, or VDD
• Built-in Temperature Sensor
• External Conversion Start Input
- Two Comparators
- Internal Voltage Reference
- POR/Brown-Out Detector
USB FUNCTION CONTROLLER
- USB Specification 2.0 Compliant
- Full Speed (12 Mbps) or Low Speed (1.5 Mbps)
Operation
- Integrated Clock Recovery; No External Crystal
Required for Full Speed or Low Speed
- Supports Eight Flexible Endpoints
- 1k Byte USB Buffer Memory
- Integrated Transceiver; No External Resistors Required
ON-CHIP DEBUG
- On-Chip Debug Circuitry Facilitates Full Speed,
Non-Intrusive In-System Debug (No Emulator
Required!)
- Provides Breakpoints, Single Stepping,
Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using
ICE-Chips, Target Pods, and Sockets
VOLTAGE REGULATOR INPUT: 4.0V TO 5.25V
HIGH SPEED 8051 µC Core
- Pipelined Instruction Architecture; Executes 70% of
Instructions in 1 or 2
System Clocks
- Up to 25 MIPS Throughput with 25 MHz Clock
- Expanded Interrupt Handler
MEMORY
- 2304 Bytes Internal RAM (1k + 256 + 1k USB FIFO)
- 16k Bytes FLASH; In-system programmable in 512-byte
Sectors
DIGITAL PERIPHERALS
- 25/21 Port I/O; All 5 V tolerant with High Sink Current
- Hardware Enhanced SPI™, Enhanced UART, and
SMBus™ Serial Ports
- Four General Purpose 16-Bit Counter/Timers
- 16-Bit Programmable Counter Array (PCA) with Five
Capture/Compare Modules
- Real Time Clock Mode using External Clock Source and
PCA or Timer
CLOCK SOURCES
- Internal Oscillator: 0.25% Accuracy with Clock
Recovery enabled. Supports all USB and UART Modes
- External Oscillator: Crystal, RC, C, or Clock (1 or 2 Pin
Modes)
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Strategies
PACKAGES
- 32-pin LQFP (C8051F320)
- 28-pin MLP (C8051F321)
TEMPERATURE RANGE: -40°C TO +85°C
ANALOG
PERIPHERALS
A
M
U
X
TEMP
SENSOR
10-bit
200ksps
ADC
PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16KB
ISP FLASH
16
INTERRUPTS
+
-
+
-
VREGVREF
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
Timer 0
Timer 1
Timer 2
Timer 3
DIGITAL I/O
UART
SPI
SMBus
PCA
CROSSBAR
USB Controller /
Transceiver
2304 B
SRAM
POR
Port 0
Port 1
Port 2
Port 3
WDT
Preliminary Rev. 1.1 12/03 Copyright © 2003 by Silicon Laboratories C8051F320/1-DS11
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
C8051F320/1
Notes
2 Rev. 1.1
C8051F320/1
TABLE OF CONTENTS
1. SYSTEM OVERVIEW .........................................................................................................17
1.1. CIP-51™ Microcontroller Core ......................................................................................20
1.1.1. Fully 8051 Compatible ..........................................................................................20
1.1.2. Improved Throughput ............................................................................................20
1.1.3. Additional Features................................................................................................21
1.2. On-Chip Memory ............................................................................................................22
1.3. Universal Serial Bus Controller.......................................................................................23
1.4. Voltage Regulator............................................................................................................23
1.5. On-Chip Debug Circuitry ................................................................................................24
1.6. Programmable Digital I/O and Crossbar .........................................................................25
1.7. Serial Ports.......................................................................................................................25
1.8. Programmable Counter Array .........................................................................................26
1.9. 10-Bit Analog to Digital Converter.................................................................................27
1.10.Comparators ....................................................................................................................28
2. ABSOLUTE MAXIMUM RATINGS..................................................................................29
3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................30
4. PINOUT AND PACKAGE DEFINITIONS........................................................................31
5. 10-BIT ADC (ADC0) .............................................................................................................39
5.1. Analog Multiplexer .........................................................................................................40
5.2. Temperature Sensor.........................................................................................................41
5.3. Modes of Operation.........................................................................................................42
5.3.1. Starting a Conversion.............................................................................................42
5.3.2. Tracking Modes .....................................................................................................43
5.3.3. Settling Time Requirements ..................................................................................44
5.4. Programmable Window Detector ....................................................................................50
5.4.1. Window Detector In Single-Ended Mode .............................................................52
5.4.2. Window Detector In Differential Mode.................................................................53
6. VOLTAGE REFERENCE....................................................................................................55
7. COMPARATORS ................................................................................................................57
8. VOLTAGE REGULATOR (REG0) ....................................................................................67
8.1. Regulator Mode Selection ...............................................................................................68
8.2. VBUS Detection..............................................................................................................69
9. CIP-51 MICROCONTROLLER .........................................................................................73
9.1. Instruction Set..................................................................................................................75
9.1.1. Instruction and CPU Timing..................................................................................75
9.1.2. MOVX Instruction and Program Memory.............................................................75
9.2. Memory Organization .....................................................................................................79
9.2.1. Program Memory...................................................................................................79
9.2.2. Data Memory .........................................................................................................80
9.2.3. General Purpose Registers .....................................................................................80
9.2.4. Bit Addressable Locations .....................................................................................80
9.2.5. Stack ...................................................................................................................80
9.2.6. Special Function Registers.....................................................................................81
Rev. 1.1 3
C8051F320/1
9.2.7. Register Descriptions.............................................................................................84
9.3. Interrupt Handler .............................................................................................................87
9.3.1. MCU Interrupt Sources and Vectors .....................................................................87
9.3.2. External Interrupts .................................................................................................88
9.3.3. Interrupt Priorities..................................................................................................88
9.3.4. Interrupt Latency....................................................................................................88
9.3.5. Interrupt Register Descriptions..............................................................................90
9.4. Power Management Modes .............................................................................................96
9.4.1. Idle Mode...............................................................................................................96
9.4.2. Stop Mode..............................................................................................................96
10. RESET SOURCES ..............................................................................................................99
10.1.Power-On Reset.............................................................................................................100
10.2.Power-Fail Reset / VDD Monitor..................................................................................101
10.3.External Reset................................................................................................................102
10.4.Missing Clock Detector Reset .......................................................................................102
10.5.Comparator0 Reset ........................................................................................................102
10.6.PCA Watchdog Timer Reset .........................................................................................102
10.7.FLASH Error Reset .......................................................................................................102
10.8.Software Reset...............................................................................................................103
10.9.USB Reset .....................................................................................................................103
11. FLASH MEMORY ............................................................................................................107
11.1.Programming The FLASH Memory .............................................................................107
11.1.1. FLASH Lock and Key Functions ........................................................................107
11.1.2. FLASH Erase Procedure......................................................................................107
11.1.3. FLASH Write Procedure .....................................................................................108
11.2.Non-volatile Data Storage .............................................................................................109
11.3.Security Options ............................................................................................................109
12. EXTERNAL RAM .............................................................................................................113
12.1.Accessing User XRAM .................................................................................................113
12.2.Accessing USB FIFO Space..........................................................................................114
13. OSCILLATORS...................................................................................................................117
13.1.Programmable Internal Oscillator .................................................................................117
13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices .........................118
13.1.2. Internal Oscillator Suspend Mode .......................................................................118
13.2.External Oscillator Drive Circuit...................................................................................120
13.2.1. Clocking Timers Directly Through the External Oscillator ................................120
13.2.2. External Crystal Example ....................................................................................120
13.2.3. External RC Example ..........................................................................................121
13.2.4. External Capacitor Example ................................................................................121
13.3.4x Clock Multiplier .......................................................................................................123
13.4.System and USB Clock Selection .................................................................................124
13.4.1. System Clock Selection .......................................................................................124
13.4.2. USB Clock Selection ...........................................................................................124
14. PORT INPUT/OUTPUT ...................................................................................................127
14.1.Priority Crossbar Decoder .............................................................................................129
4 Rev. 1.1
C8051F320/1
14.2.Port I/O Initialization.....................................................................................................131
14.3.General Purpose Port I/O...............................................................................................134
15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ....................................................143
15.1.Endpoint Addressing .....................................................................................................144
15.2.USB Transceiver ...........................................................................................................144
15.3.USB Register Access.....................................................................................................146
15.4.USB Clock Configuration .............................................................................................150
15.5.FIFO Management.........................................................................................................151
15.5.1. FIFO Split Mode..................................................................................................151
15.5.2. FIFO Double Buffering .......................................................................................151
15.5.3. FIFO Access ........................................................................................................152
15.6.Function Addressing......................................................................................................153
15.7.Function Configuration and Control .............................................................................154
15.8.Interrupts .......................................................................................................................157
15.9.The Serial Interface Engine ...........................................................................................161
15.10.Endpoint0.....................................................................................................................161
15.10.1.Endpoint0 SETUP Transactions .........................................................................162
15.10.2.Endpoint0 IN Transactions .................................................................................162
15.10.3.Endpoint0 OUT Transactions .............................................................................163
15.11.Configuring Endpoints1-3 ...........................................................................................166
15.12.Controlling Endpoints1-3 IN .......................................................................................166
15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode ...........................................................166
15.12.2.Endpoints1-3 IN Isochronous Mode...................................................................167
15.13.Controlling Endpoints1-3 OUT ...................................................................................170
15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode .......................................................170
15.13.2.Endpoints1-3 OUT Isochronous Mode...............................................................170
16. SMBUS..................................................................................................................................175
16.1.Supporting Documents ..................................................................................................176
16.2.SMBus Configuration....................................................................................................176
16.3.SMBus Operation ..........................................................................................................177
16.3.1. Arbitration............................................................................................................177
16.3.2. Clock Low Extension...........................................................................................178
16.3.3. SCL Low Timeout ...............................................................................................178
16.3.4. SCL High (SMBus Free) Timeout.......................................................................178
16.4.Using the SMBus...........................................................................................................179
16.4.1. SMBus Configuration Register............................................................................180
16.4.2. SMB0CN Control Register..................................................................................183
16.4.3. Data Register........................................................................................................186
16.5.SMBus Transfer Modes.................................................................................................187
16.5.1. Master Transmitter Mode ....................................................................................187
16.5.2. Master Receiver Mode.........................................................................................188
16.5.3. Slave Receiver Mode ...........................................................................................189
16.5.4. Slave Transmitter Mode.......................................................................................190
16.6.SMBus Status Decoding................................................................................................191
17. UART0 ..................................................................................................................................193
Rev. 1.1 5
C8051F320/1
17.1.Enhanced Baud Rate Generation...................................................................................194
17.2.Operational Modes ........................................................................................................195
17.2.1. 8-Bit UART .........................................................................................................195
17.2.2. 9-Bit UART .........................................................................................................196
17.3.Multiprocessor Communications...................................................................................197
18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................203
18.1.Signal Descriptions........................................................................................................204
18.1.1. Master Out, Slave In (MOSI) ..............................................................................204
18.1.2. Master In, Slave Out (MISO) ..............................................................................204
18.1.3. Serial Clock (SCK) ..............................................................................................204
18.1.4. Slave Select (NSS)...............................................................................................204
18.2.SPI0 Master Mode Operation ........................................................................................205
18.3.SPI0 Slave Mode Operation ..........................................................................................207
18.4.SPI0 Interrupt Sources...................................................................................................207
18.5.Serial Clock Timing ......................................................................................................208
18.6.SPI Special Function Registers .....................................................................................210
19. TIMERS ...............................................................................................................................217
19.1.Timer 0 and Timer 1......................................................................................................217
19.1.1. Mode 0: 13-bit Counter/Timer.............................................................................217
19.1.2. Mode 1: 16-bit Counter/Timer.............................................................................218
19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload.................................................219
19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................220
19.2.Timer 2 .......................................................................................................................225
19.2.1. 16-bit Timer with Auto-Reload ...........................................................................225
19.2.2. 8-bit Timers with Auto-Reload............................................................................226
19.2.3. USB Start-of-Frame Capture ...............................................................................227
19.3.Timer 3 .......................................................................................................................230
19.3.1. 16-bit Timer with Auto-Reload ...........................................................................230
19.3.2. 8-bit Timers with Auto-Reload............................................................................231
19.3.3. USB Start-of-Frame Capture ...............................................................................232
20. PROGRAMMABLE COUNTER ARRAY (PCA0) .........................................................235
20.1.PCA Counter/Timer.......................................................................................................236
20.2.Capture/Compare Modules............................................................................................237
20.2.1. Edge-triggered Capture Mode .............................................................................238
20.2.2. Software Timer (Compare) Mode........................................................................239
20.2.3. High Speed Output Mode ....................................................................................240
20.2.4. Frequency Output Mode ......................................................................................241
20.2.5. 8-Bit Pulse Width Modulator Mode ....................................................................242
20.2.6. 16-Bit Pulse Width Modulator Mode ..................................................................244
20.3.Watchdog Timer Mode..................................................................................................246
20.3.1. Watchdog Timer Operation .................................................................................246
20.3.2. Watchdog Timer Usage .......................................................................................247
20.4.Register Descriptions for PCA ......................................................................................248
21. C2 INTERFACE ..................................................................................................................253
21.1.C2 Interface Registers ...................................................................................................253
6 Rev. 1.1
C8051F320/1
21.2.C2 Pin Sharing...............................................................................................................255
Rev. 1.1 7
C8051F320/1
Notes
8 Rev. 1.1
C8051F320/1
LIST OF FIGURES AND TABLES
1. SYSTEM OVERVIEW ........................................................................................................17
Table 1.1. Product Selection Guide......................................................................................17
Figure 1.1. C8051F320 Block Diagram.................................................................................18
Figure 1.2. C8051F321 Block Diagram.................................................................................19
Figure 1.3. Comparison of Peak MCU Execution Speeds.....................................................20
Figure 1.4. On-Chip Clock and Reset....................................................................................21
Figure 1.5. On-Board Memory Map ......................................................................................22
Figure 1.6. USB Controller Block Diagram ..........................................................................23
Figure 1.7. Development/In-System Debug Diagram ...........................................................24
Figure 1.8. Digital Crossbar Diagram....................................................................................25
Figure 1.9. PCA Block Diagram............................................................................................26
Figure 1.10. PCA Block Diagram............................................................................................26
Figure 1.11. 10-Bit ADC Block Diagram................................................................................27
Figure 1.12. Comparator0 Block Diagram ..............................................................................28
2. ABSOLUTE MAXIMUM RATINGS .................................................................................29
Table 2.1. Absolute Maximum Ratings*..............................................................................29
3. GLOBAL DC ELECTRICAL CHARACTERISTICS .....................................................30
Table 3.1. Global DC Electrical Characteristics...................................................................30
4. PINOUT AND PACKAGE DEFINITIONS .......................................................................31
Table 4.1. Pin Definitions for the C8051F320/1 ..................................................................31
Figure 4.1. LQFP-32 Pinout Diagram (Top View)................................................................33
Figure 4.2. LQFP-32 Package Diagram.................................................................................34
Table 4.2. LQFP-32 Package Dimensions............................................................................34
Figure 4.3. MLP-28 Pinout Diagram (Top View) .................................................................35
Figure 4.4. MLP-28 Package Drawing ..................................................................................36
Table 4.3. MLP-28 Package Dimensions .............................................................................36
Figure 4.5. Typical MLP-28 Landing Diagram .....................................................................37
Figure 4.6. Typical MLP-28 Solder Mask.............................................................................38
5. 10-BIT ADC (ADC0) ............................................................................................................39
Figure 5.1. ADC0 Functional Block Diagram.......................................................................39
Figure 5.2. Typical Temperature Sensor Transfer Function..................................................41
Figure 5.3. 10-Bit ADC Track and Conversion Example Timing.........................................43
Figure 5.4. ADC0 Equivalent Input Circuits .........................................................................44
Figure 5.5. AMX0P: AMUX0 Positive Channel Select Register..........................................45
Figure 5.6. AMX0N: AMUX0 Negative Channel Select Register........................................46
Figure 5.7. ADC0CF: ADC0 Configuration Register ...........................................................47
Figure 5.8. ADC0H: ADC0 Data Word MSB Register.........................................................47
Figure 5.9. ADC0L: ADC0 Data Word LSB Register ..........................................................48
Figure 5.10. ADC0CN: ADC0 Control Register.....................................................................49
Figure 5.11. ADC0GTH: ADC0 Greater-Than Data High Byte Register...............................50
Figure 5.12. ADC0GTL: ADC0 Greater-Than Data Low Byte Register................................50
Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte Register....................................51
Figure 5.14. ADC0LTL: ADC0 Less-Than Data Low Byte Register .....................................51
Rev. 1.1 9
C8051F320/1
Figure 5.15. ADC Window Compare Example: Right-Justified Single-Ended Data..............52
Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data................52
Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data.................53
Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ...................53
Table 5.1. ADC0 Electrical Characteristics..........................................................................54
6. VOLTAGE REFERENCE ...................................................................................................55
Figure 6.1. Voltage Reference Functional Block Diagram....................................................55
Figure 6.2. REF0CN: Reference Control Register ................................................................56
Table 6.1. Voltage Reference Electrical Characteristics ......................................................56
7. COMPARATORS ...............................................................................................................57
Figure 7.1. Comparator0 Functional Block Diagram ............................................................57
Figure 7.2. Comparator1 Functional Block Diagram ............................................................58
Figure 7.3. Comparator Hysteresis Plot.................................................................................59
Figure 7.4. CPT0CN: Comparator0 Control Register ...........................................................60
Figure 7.5. CPT0MX: Comparator0 MUX Selection Register..............................................61
Figure 7.6. CPT0MD: Comparator0 Mode Selection Register..............................................62
Figure 7.7. CPT1CN: Comparator1 Control Register ...........................................................63
Figure 7.8. CPT1MX: Comparator1 MUX Selection Register..............................................64
Figure 7.9. CPT1MD: Comparator1 Mode Selection Register..............................................65
Table 7.1. Comparator Electrical Characteristics.................................................................66
8. VOLTAGE REGULATOR (REG0) ...................................................................................67
Table 8.1. Voltage Regulator Electrical Specifications........................................................69
Figure 8.1. REG0 Configuration: USB Bus-Powered ...........................................................70
Figure 8.2. REG0 Configuration: USB Self-Powered...........................................................70
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled..........................71
Figure 8.4. REG0 Configuration: No USB Connection ........................................................71
Figure 8.5. REG0CN: Voltage Regulator Control.................................................................72
9. CIP-51 MICROCONTROLLER ........................................................................................73
Figure 9.1. CIP-51 Block Diagram ........................................................................................73
Table 9.1. CIP-51 Instruction Set Summary.........................................................................75
Figure 9.2. Memory Map .......................................................................................................79
Table 9.2. Special Function Register (SFR) Memory Map..................................................81
Table 9.3. Special Function Registers ..................................................................................81
Figure 9.3. DPL: Data Pointer Low Byte ..............................................................................84
Figure 9.4. DPH: Data Pointer High Byte .............................................................................84
Figure 9.5. SP: Stack Pointer .................................................................................................85
Figure 9.6. PSW: Program Status Word ................................................................................85
Figure 9.7. ACC: Accumulator..............................................................................................86
Figure 9.8. B: B Register .......................................................................................................86
Table 9.4. Interrupt Summary...............................................................................................89
Figure 9.9. IE: Interrupt Enable .............................................................................................90
Figure 9.10. IP: Interrupt Priority ............................................................................................91
Figure 9.11. EIE1: Extended Interrupt Enable 1 .....................................................................92
Figure 9.12. EIP1: Extended Interrupt Priority 1.....................................................................93
Figure 9.13. EIE2: Extended Interrupt Enable 2 .....................................................................94
10 Rev. 1.1
C8051F320/1
Figure 9.14. EIP2: Extended Interrupt Priority 2.....................................................................94
Figure 9.15. IT01CF: INT0/INT1 Configuration Register ......................................................95
Figure 9.16. PCON: Power Control Register ..........................................................................97
10. RESET SOURCES .............................................................................................................99
Figure 10.1. Reset Sources ......................................................................................................99
Figure 10.2. Power-On and VDD Monitor Reset Timing .....................................................100
Figure 10.3. VDM0CN: VDD Monitor Control ....................................................................101
Figure 10.4. RSTSRC: Reset Source Register.......................................................................104
Table 10.1. Reset Electrical Characteristics .........................................................................105
11. FLASH MEMORY ...........................................................................................................107
Table 11.1. FLASH Electrical Characteristics .....................................................................108
Figure 11.1. FLASH Program Memory Map and Security Byte...........................................110
Figure 11.2. PSCTL: Program Store R/W Control................................................................110
Figure 11.3. FLKEY: FLASH Lock and Key Register .........................................................111
Figure 11.4. FLSCL: FLASH Scale Register ........................................................................111
12. EXTERNAL RAM ............................................................................................................113
Figure 12.1. External Ram Memory Map..............................................................................113
Figure 12.2. XRAM Memory Map Expanded View .............................................................114
Figure 12.3. EMI0CN: External Memory Interface Control .................................................115
13. OSCILLATORS ..................................................................................................................117
Figure 13.1. Oscillator Diagram ............................................................................................117
Figure 13.2. OSCICN: Internal Oscillator Control Register .................................................119
Figure 13.3. OSCICL: Internal Oscillator Calibration Register ............................................119
Figure 13.4. OSCXCN: External Oscillator Control Register...............................................122
Figure 13.5. CLKMUL: Clock Multiplier Control Register..................................................123
Table 13.1. Typical USB Full Speed Clock Settings ...........................................................124
Table 13.2. Typical USB Low Speed Clock Settings...........................................................124
Figure 13.6. CLKSEL: Clock Select Register .......................................................................125
Table 13.3. Internal Oscillator Electrical Characteristics.....................................................126
14. PORT INPUT/OUTPUT ..................................................................................................127
Figure 14.1. Port I/O Functional Block Diagram ..................................................................127
Figure 14.2. Port I/O Cell Block Diagram.............................................................................128
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped .............................................129
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ......................................130
Figure 14.5. XBR0: Port I/O Crossbar Register 0 .................................................................132
Figure 14.6. XBR1: Port I/O Crossbar Register 1 .................................................................133
Figure 14.7. P0: Port0 Register..............................................................................................135
Figure 14.8. P0MDIN: Port0 Input Mode Register ...............................................................135
Figure 14.9. P0MDOUT: Port0 Output Mode Register.........................................................136
Figure 14.10. P0SKIP: Port0 Skip Register...........................................................................136
Figure 14.11. P1: Port1 Register............................................................................................137
Figure 14.12. P1MDIN: Port1 Input Mode Register .............................................................137
Figure 14.13. P1MDOUT: Port1 Output Mode Register.......................................................138
Figure 14.14. P1SKIP: Port1 Skip Register...........................................................................138
Figure 14.15. P2: Port2 Register............................................................................................139
Rev. 1.1 11
C8051F320/1
Figure 14.16. P2MDIN: Port2 Input Mode Register .............................................................139
Figure 14.17. P2MDOUT: Port2 Output Mode Register.......................................................140
Figure 14.18. P2SKIP: Port2 Skip Register...........................................................................140
Figure 14.19. P3: Port3 Register............................................................................................141
Figure 14.20. P3MDIN: Port3 Input Mode Register .............................................................141
Figure 14.21. P3MDOUT: Port3 Output Mode Register.......................................................142
Table 14.1. Port I/O DC Electrical Characteristics ..............................................................142
15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ...................................................143
Figure 15.1. USB0 Block Diagram........................................................................................143
Table 15.1. Endpoint Addressing Scheme............................................................................144
Figure 15.2. USB0XCN: USB0 Transceiver Control............................................................145
Figure 15.3. USB0 Register Access Scheme.........................................................................146
Figure 15.4. USB0ADR: USB0 Indirect Address Register ...................................................147
Figure 15.5. USB0DAT: USB0 Data Register ......................................................................148
Figure 15.6. INDEX: USB0 Endpoint Index (USB Register) ...............................................148
Table 15.2. USB0 Controller Registers................................................................................149
Figure 15.7. CLKREC: Clock Recovery Control (USB Register) ........................................150
Figure 15.8. USB FIFO Allocation........................................................................................151
Table 15.3. FIFO Configurations .........................................................................................152
Figure 15.9. FIFOn: USB0 Endpoint FIFO Access (USB Registers) ...................................152
Figure 15.10. FADDR: USB0 Function Address (USB Register) ........................................153
Figure 15.11. POWER: USB0 Power (USB Register) ..........................................................155
Figure 15.12. FRAMEL: USB0 Frame Number Low (USB Register) .................................156
Figure 15.13. FRAMEH: USB0 Frame Number High (USB Register) ................................156
Figure 15.14. IN1INT: USB0 IN Endpoint Interrupt (USB Register)...................................157
Figure 15.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register).............................158
Figure 15.16. CMINT: USB0 Common Interrupt (USB Register)........................................159
Figure 15.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) .........................160
Figure 15.18. OUT1IE: USB0 Out Endpoint Interrupt Enable (USB Register)....................160
Figure 15.19. CMIE: USB0 Common Interrupt Enable (USB Register) ..............................161
Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register) ........................................164
Figure 15.21. E0CNT: USB0 Endpoint 0 Data Count (USB Register).................................165
Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register) ...............168
Figure 15.23. EINCSRH: USB0 IN Endpoint Control Low Byte (USB Register) ...............169
Figure 15.24. EOUTCSRL: USB0 OUT Endpoint Control High Byte (USB Register) .......171
Figure 15.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) .......172
Figure 15.26. EOUTCNTL: USB0 OUT Endpoint Count Low (USB Register) ..................172
Figure 15.27. EOUTCNTH: USB0 OUT Endpoint Count High (USB Register) .................172
Table 15.4. USB Transceiver Electrical Characteristics ......................................................173
16. SMBUS .................................................................................................................................175
Figure 16.1. SMBus Block Diagram .....................................................................................175
Figure 16.2. Typical SMBus Configuration ..........................................................................176
Figure 16.3. SMBus Transaction ...........................................................................................177
Table 16.1. SMBus Clock Source Selection.........................................................................180
Figure 16.4. Typical SMBus SCL Generation.......................................................................181
12 Rev. 1.1
C8051F320/1
Table 16.2. Minimum SDA Setup and Hold Times .............................................................181
Figure 16.5. SMB0CF: SMBus Clock/Configuration Register .............................................182
Figure 16.6. SMB0CN: SMBus Control Register .................................................................184
Table 16.3. Sources for Hardware Changes to SMB0CN ....................................................185
Figure 16.7. SMB0DAT: SMBus Data Register ...................................................................186
Figure 16.8. Typical Master Transmitter Sequence...............................................................187
Figure 16.9. Typical Master Receiver Sequence ...................................................................188
Figure 16.10. Typical Slave Receiver Sequence ...................................................................189
Figure 16.11. Typical Slave Transmitter Sequence...............................................................190
Table 16.4. SMBus Status Decoding....................................................................................191
17. UART0 .................................................................................................................................193
Figure 17.1. UART0 Block Diagram.....................................................................................193
Figure 17.2. UART0 Baud Rate Logic ..................................................................................194
Figure 17.3. UART Interconnect Diagram ............................................................................195
Figure 17.4. 8-Bit UART Timing Diagram ...........................................................................195
Figure 17.5. 9-Bit UART Timing Diagram ...........................................................................196
Figure 17.6. UART Multi-Processor Mode Interconnect Diagram .......................................197
Figure 17.7. SCON0: Serial Port 0 Control Register.............................................................198
Figure 17.8. SBUF0: Serial (UART0) Port Data Buffer Register .........................................199
Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ...........200
Table 17.2. Timer Settings for Standard Baud Rates Using an External Oscillator.............200
Table 17.3. Timer Settings for Standard Baud Rates Using an External Oscillator.............201
Table 17.4. Timer Settings for Standard Baud Rates Using an External Oscillator.............201
Table 17.5. Timer Settings for Standard Baud Rates Using an External Oscillator.............202
Table 17.6. Timer Settings for Standard Baud Rates Using an External Oscillator.............202
18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) ........................................203
Figure 18.1. SPI Block Diagram............................................................................................203
Figure 18.2. Multiple-Master Mode Connection Diagram ....................................................206
Figure 18.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ...206
Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ....206
Figure 18.5. Master Mode Data/Clock Timing......................................................................208
Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................................209
Figure 18.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................................209
Figure 18.8. SPI0CFG: SPI0 Configuration Register............................................................210
Figure 18.9. SPI0CN: SPI0 Control Register ........................................................................211
Figure 18.10. SPI0CKR: SPI0 Clock Rate Register..............................................................212
Figure 18.11. SPI0DAT: SPI0 Data Register ........................................................................213
Figure 18.12. SPI Master Timing (CKPHA = 0)...................................................................214
Figure 18.13. SPI Master Timing (CKPHA = 1)...................................................................214
Figure 18.14. SPI Slave Timing (CKPHA = 0) .....................................................................215
Figure 18.15. SPI Slave Timing (CKPHA = 1) .....................................................................215
Table 18.1. SPI Slave Timing Parameters............................................................................216
19. TIMERS ..............................................................................................................................217
Figure 19.1. T0 Mode 0 Block Diagram................................................................................218
Figure 19.2. T0 Mode 2 Block Diagram................................................................................219
Rev. 1.1 13
C8051F320/1
Figure 19.3. T0 Mode 3 Block Diagram................................................................................220
Figure 19.4. TCON: Timer Control Register.........................................................................221
Figure 19.5. TMOD: Timer Mode Register...........................................................................222
Figure 19.6. CKCON: Clock Control Register......................................................................223
Figure 19.7. TL0: Timer 0 Low Byte ....................................................................................224
Figure 19.8. TL1: Timer 1 Low Byte ....................................................................................224
Figure 19.9. TH0: Timer 0 High Byte ...................................................................................224
Figure 19.10. TH1: Timer 1 High Byte .................................................................................224
Figure 19.11. Timer 2 16-Bit Mode Block Diagram .............................................................225
Figure 19.12. Timer 2 8-Bit Mode Block Diagram ...............................................................226
Figure 19.13. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’) ................................................227
Figure 19.14. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’) ................................................227
Figure 19.15. TMR2CN: Timer 2 Control Register ..............................................................228
Figure 19.16. TMR2RLL: Timer 2 Reload Register Low Byte ............................................229
Figure 19.17. TMR2RLH: Timer 2 Reload Register High Byte ...........................................229
Figure 19.18. TMR2L: Timer 2 Low Byte ............................................................................229
Figure 19.19. TMR2H Timer 2 High Byte ............................................................................229
Figure 19.20. Timer 3 16-Bit Mode Block Diagram .............................................................230
Figure 19.21. Timer 3 8-Bit Mode Block Diagram ...............................................................231
Figure 19.22. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’) ................................................232
Figure 19.23. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’) ................................................232
Figure 19.24. TMR3CN: Timer 3 Control Register ..............................................................233
Figure 19.25. TMR3RLL: Timer 3 Reload Register Low Byte ............................................234
Figure 19.26. TMR3RLH: Timer 3 Reload Register High Byte ...........................................234
Figure 19.27. TMR3L: Timer 3 Low Byte ............................................................................234
Figure 19.28. TMR3H Timer 3 High Byte ............................................................................234
20. PROGRAMMABLE COUNTER ARRAY (PCA0) ........................................................235
Figure 20.1. PCA Block Diagram..........................................................................................235
Figure 20.2. PCA Counter/Timer Block Diagram.................................................................236
Table 20.1. PCA Timebase Input Options............................................................................236
Figure 20.3. PCA Interrupt Block Diagram...........................................................................237
Table 20.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..................237
Figure 20.4. PCA Capture Mode Diagram ............................................................................238
Figure 20.5. PCA Software Timer Mode Diagram................................................................239
Figure 20.6. PCA High Speed Output Mode Diagram ..........................................................240
Figure 20.7. PCA Frequency Output Mode...........................................................................241
Figure 20.8. PCA 8-Bit PWM Mode Diagram ......................................................................243
Figure 20.9. PCA 16-Bit PWM Mode ...................................................................................244
Figure 20.10. PCA Module 4 with Watchdog Timer Enabled ..............................................246
Table 20.3. Watchdog Timer Timeout Intervals† ................................................................247
Figure 20.11. PCA0CN: PCA Control Register ....................................................................248
Figure 20.12. PCA0MD: PCA Mode Register ......................................................................249
Figure 20.13. PCA0CPMn: PCA Capture/Compare Mode Registers ...................................250
Figure 20.14. PCA0L: PCA Counter/Timer Low Byte .........................................................251
Figure 20.15. PCA0H: PCA Counter/Timer High Byte ........................................................251
14 Rev. 1.1
C8051F320/1
Figure 20.16. PCA0CPLn: PCA Capture Module Low Byte ................................................252
Figure 20.17. PCA0CPHn: PCA Capture Module High Byte...............................................252
21. C2 INTERFACE .................................................................................................................253
Figure 21.1. C2ADD: C2 Address Register ..........................................................................253
Figure 21.2. DEVICEID: C2 Device ID Register .................................................................253
Figure 21.3. REVID: C2 Revision ID Register .....................................................................254
Figure 21.4. FPCTL: C2 FLASH Programming Control Register ........................................254
Figure 21.5. FPDAT: C2 FLASH Programming Data Register ............................................254
Figure 21.6. Typical C2 Pin Sharing .....................................................................................255
Rev. 1.1 15
C8051F320/1
Notes
16 Rev. 1.1
C8051F320/1
1. SYSTEM OVERVIEW
C8051F320/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed
below. Refer to
• High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and
1k
FIFO RAM
• Supply Voltage Regulator (5V-to-3V)
• True 10-bit 200 ksps 17-channel single-ended/differential ADC with analog multiplexer
• On-chip Voltage Reference and Temperature Sensor
• On-chip Voltage Comparators (2)
• Precision programmable 12 MHz internal oscillator and 4x clock multiplier
• 16k bytes of on-chip FLASH memory
• 2304 total bytes of on-chip RAM (256 + 1k + 1k USB FIFO)
•SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
• Four general-purpose 16-bit timers
• Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer function
• On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
• 25/21 Port I/O (5V tolerant)
Tabl e 1.1 for specific product feature selection.
With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F320/1 devices are truly stand-alone System-on-a-Chip solutions. The FLASH memory can be reprogrammed
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software
has complete control of all peripherals, and may individually shut down any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full
speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports
inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands.
All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be
shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7 V-t o- 3. 6 V operation over the industrial temperature range (-40°C to +85°C). (Note
that 3.0
to 5
V-t o- 3. 6 V is required for USB communication.) The Port I/O and /RST pins are tolerant of input signals up
V. C8051F320/1 are available in a 32-pin LQFP or a 28-pin MLP package.
Tab le 1.1. Product Selection Guide
C
2
MIPS (Peak)
FLASH Memory
C8051F320 25 16k 2304 3 3 3 3 3 3 4 3 25 3 3 3 2 LQFP-32
C8051F321 25 16k 2304 3 3 3 3 3 3 4 3 21 3 3 3 2 MLP-28
RAM
Calibrated Internal Oscillator
USB
Supply Voltage Regulator
SMBus/I
Enhanced SPI
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
10-bit 200ksps ADC
Temperature Sensor
Voltage Reference
Rev. 1.1 17
Analog Comparators
Package
C8051F320/1
Figure 1.1. C8051F320 Block Diagram
REGIN
VDD
GND
/RST/C2CK
VBUS
D+
D-
Analog/Digital
C2D
XTAL1 XTAL2
External
Oscillator
Circuit
12MHz
Internal
Oscillator
Clock
Recovery
5.0V
Power
IN
Regulator
POR
Voltage
OUT
Debug HW
Brown-
Out
x4 2
2
1,2,3,4
USB
Transceiver
Enable
USB Clock
Controller
1K byte USB
System
USB
SRAM
Reset
Clock
8
0
5
1
C
o
SFR Bus
r
e
16kbyte
FLASH
256 byte
SRAM
1K byte
XRAM
VREF
VDD
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
Port 2
Latch
Port 3
Latch
VREF
10-bit
200ksps
ADC
P
0
D
r
v
C
P
R
1
O
S
D
S
r
B
v
A
R
P
2
D
r
v
P
3
D
r
v
CP0
+
-
CP1
+
-
Temp
A
AIN0-AIN16
M
VDD
U
X
VREF
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
18 Rev. 1.1
Figure 1.2. C8051F321 Block Diagram
C8051F320/1
REGIN
VDD
GND
/RST/C2CK
VBUS
D+
D-
Analog/Digital
C2D
XTAL1 XTAL2
External
Oscillator
Circuit
12MHz
Internal
Oscillator
Clock
Recovery
5.0V
Power
IN
Regulator
POR
Voltage
OUT
Debug HW
Brown-
Out
x4 2
2
1,2,3,4
USB
Transceiver
Enable
USB Clock
Controller
1K byte USB
System
USB
SRAM
Reset
Clock
8
0
5
1
C
o
SFR Bus
r
e
16kbyte
FLASH
256 byte
SRAM
1K byte
XRAM
VREF
VDD
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
Port 2
Latch
Port 3
Latch
VREF
10-bit
200ksps
ADC
P
0
D
r
v
C
P
R
1
O
S
D
S
r
B
v
A
R
P
2
D
r
v
P
3
D
r
v
CP0
+
-
CP1
+
-
Temp
A
AIN0-AIN11
M
VDD
U
X
VREF
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P3.0/C2D
Rev. 1.1 19
C8051F320/1
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F320/1 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers,
a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 2304
128
byte Special Function Register (SFR) address space, and 25/21 I/O pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe
cute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in
one or two system clock cycles, with only four instructions taking more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each
execution time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
bytes of on-chip RAM,
-
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.3. Comparison of Peak MCU Execution Speeds
25
20
15
MIPS
10
5
Silicon Labs
CIP-51
(25MHz clk)
20 Rev. 1.1
Microchip
PIC17C75x
(33MHz clk)
Philips
80C51
(33MHz clk)
ADuC812
8051
(16MHz clk)
C8051F320/1
1.1.3. Additional Features
The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051),
allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less
intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when build
ing multi-tasking, real-time systems.
Nine reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power
supply voltage drops below V
transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an errant FLASH read/write protection circuit. Each reset source except for the
POR, Reset Input Pin, or FLASH error may be disabled by the user in software. The WDT may be permanently
enabled in software after a power-on reset during MCU initialization.
The internal oscillator is factory calibrated to 12 MHz ±1.5%, and the internal oscillator period may be user programmed in ~0.25% increments. A clock recovery mechanism allows the internal oscillator to be used with the 4x
Clock Multiplier as the USB clock source in Full Speed mode; the internal oscillator can also be used as the USB
clock source in Low Speed mode. External oscillators may also be used with the 4x Clock Multiplier. An external
oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS
clock source to generate the system clock. The system clock may be configured to use the internal oscillator, external
oscillator, or the Clock Multiplier output divided by 2. If desired, the system clock source may be switched on-the-fly
between oscillator sources. An external oscillator can be extremely useful in low power applications, allowing the
MCU to run from a slow (power saving) external clock source, while periodically switching to the internal oscillator
as needed.
as given in Table 10.1 on page 105), the USB controller (USB bus reset or a VBUS
RST
-
XTAL1
XTAL2
Internal
Oscillator
Clock
Multiplier
External
Oscillator
Drive
Px.x
Px.x
Figure 1.4. On-Chip Clock and Reset
VDD
Supply
Monitor
Enable
+
-
Power On
Reset
Software Reset (SW RSF)
Errant
FLASH
Operation
Controller
System
Clock
Clock Select
Comparator 0
+
-
Missing
Clock
Detector
(one-
shot)
EN
MCD
Enable
Microcontroller
Extended Interrupt
C0RSEF
CIP-51
Core
Handler
PCA
WDT
EN
WDT
Enable
System Reset
'0'
USB
(wired-OR)
Enable
Reset
Funnel
VBUS
Transition
/RST
Rev. 1.1 21
C8051F320/1
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the
upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indi
rect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes
can be byte addressable or bit addressable.
Program memory consists of 16k bytes of FLASH. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. See Figure 1.5 for the MCU system memory map.
Figure 1.5. On-Board Memory Map
PROGRAM/DATA MEMORY
(FLASH)
0x3E00
0x3DFF
RESERVED
16K FLASH
(In-Syste m
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
(Direct and Indirect
Bit Addressable
General Purpose
DATA MEMORY (RAM)
Only)
Addressing)
Registers
(Direct Addressing Only)
Special Fun c t ion
Register's
Lower 128 RAM
(Direct and Indirect
Addressing)
-
0x0000
0xFFFF
0x0800
0x07FF
0x0400
0x03FF
0x0000
EXTERNAL DATA ADDRESS SPACE
Same 2048 bytes as from
0x0000 to 0x07FF, wrapped
on 2K-byte boundaries
USB FIFOs
1024 Bytes
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
22 Rev. 1.1
C8051F320/1
1.3. Universal Serial Bus Controller
The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated
transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional control endpoint
(Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).
A 1k block of XRAM is used as dedicated USB FIFO space. This FIFO space is distributed among Endpoints0-3;
Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum FIFO size is
512 bytes (Endpoint3).
USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery circuitry
allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the USB clock
source. An external oscillator source can also be used with the 4x Clock Multiplier to generate the USB clock. The
CPU clock source is independent of the USB clock.
The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the software-selected
speed setting (Full or Low Speed).
Figure 1.6. USB Controller Block Diagram
Transceiver Serial Interface Engine (SIE)
VDD
D+
D-
1.4. Voltage Regulator
Data
Transfer
Control
Endpoint0
IN/OUT
Endpoint1
Endpoint2
Endpoint3
IN OUT
IN OUT
IN OUT
USB FIFOs
(1k RAM)
USB
Control,
Status, and
Interrupt
Registers
CIP-51 Core
C8051F320/1 devices include a 5 V- to -3 V voltage regulator (REG0). When enabled, the REG0 output appears on
the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software.
Rev. 1.1 23
C8051F320/1
1.5. On-Chip Debug Circuitry
The C8051F320/1 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full
speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the
digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the
USB, ADC, and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to
keep them synchronized.
The C8051F310DK development kit provides all the hardware and software necessary to develop application code
and perform in-circuit debugging with the C8051F320/1 MCUs. The kit includes software with a developer's studio
and debugger, an integrated 8051 assembler, and an RS-232 to C2 serial adapter. It also has a target application board
with the associated MCU installed and prototyping area, plus the RS-232 and C2 cables, and wall-mount power sup
ply. The Development Kit requires a Windows 95/98/NT/ME/2000 computer with one available RS-232 serial port.
As shown in
Serial Adapter to the user's application board, picking up the two C2 pins and VDD and GND. The Serial Adapter
takes its power from the application board. For applications where there is not sufficient power available from the tar
get board, the provided power supply can be connected directly to the Serial Adapter.
Figure 1.7, the PC is connected via RS-232 to the Serial Adapter. A six-inch ribbon cable connects the
-
-
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard
MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon
Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals.
Figure 1.7. Development/In-System Debug Diagram
Silicon Labs Integrated
Development Environment
WINDOWS 95/ 9 8/NT/ME/2000
RS-232
Serial
Adapter
C2 (x2), VDD, GND
VDD GND
TARGET PCB
C8051F320
24 Rev. 1.1
C8051F320/1
1.6. Programmable Digital I/O and Crossbar
C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321 devices include
21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like
typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin.
Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups”
that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.8). On-chip
counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the
exact mix of general purpose Port I/O and digital resources needed for the particular application.
Highest
Priority
Lowest
Priority
Figure 1.8. Digital Crossbar Diagram
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Priority
Decoder
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0)
2
P0
4
2
2
2
6
2
8
8
8
8
Digital
Crossbar
8
I/O
Cells
P1
8
I/O
Cells
P2
8
I/O
Cells
P3
1
I/O
Cells
Note: P2.4-P2.7 only available
on the C8051F320
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
UART
SPI
SMBus
CP0
Outputs
CP1
Outputs
SYSCLK
(Internal Digital Signals)
PCA
T0, T1
P0
P1
P2
(Port Latches)
P3
1.7. Serial Ports
The C8051F320/1 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
Rev. 1.1 25
C8051F320/1
1.8. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose
counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programmable capture/com
pare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock
divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock
source divided by 8. The external clock source selection is useful for real-time clock functionality, where the PCA is
clocked by an external source while the internal oscillator drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software
Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally, Capture/Compare
Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4 is configured and enabled
in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the
Digital Crossbar.
Figure 1.9. PCA Block Diagram
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
-
Capture/Compare
Module 0
ECI
CEX0
Capture/Compare
Module 1
CEX1
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
CEX3
Capture/Compare
Module 4 / WDT
CEX4
Crossbar
Port I/O
26 Rev. 1.1
C8051F320/1
1.9. 10-Bit Analog to Digital Converter
The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multiplexer. With
a maximum throughput of 200
includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available
as ADC inputs; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are avail
able as ADC inputs. User firmware may shut down the ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a periodic signal
(timer overflows), or external HW signals. Conversion completions are indicated by a status bit and an interrupt (if
enabled). The resulting 10-bit data word is latched into the ADC data SFRs upon completion of a conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either
within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not
interrupt the controller unless the converted data is within/outside the specified range.
Analog Multiplexer
P1.0
ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. The ADC system
Figure 1.10. 10-Bit ADC Block Diagram
-
P2.4-2.7
available on
C8051F320
Temp
Sensor
P2.4-2.7
available on
C8051F320
P1.7
P2.0
P2.7
P3.0
VDD
P1.0
P1.7
P2.0
P2.7
P3.0
VREF
GND
19-to-1
AMUX
19-to-1
AMUX
Configuration, Control, and Data Registers
(+)
10-Bit
SAR
(-)
ADC
End of
Conversion
Interrupt
Start
Conversion
16
Window Compare
000 AD0BUSY (W)
Timer 0 Overflow
001
Timer 2 Overflow
010
011
Timer 1 Overflow
100
CNVSTR Input
Timer 3 Overflow
101
ADC Data
Registers
Window
Logic
Compare
Interrupt
Rev. 1.1 27
C8051F320/1
1.10. Comparators
C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user
software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be
routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time
is programmable, allowing the user to select between high-speed and low-power modes. Positive and negative hyster
esis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may
be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Comparator0 block diagram.
Figure 1.11. Comparator0 Block Diagram
CP0EN
CP0OUT
CMX0N1
CMX0N0
CPT0MX
CMX0P1
CMX0P0
P1.0
P1.4
P2.0
P2.4
P1.1
P1.5
P2.1
P2.5
CP0RIF
CP0FIF
CP0HYP1
CPT0CN
CP0HYP0
CP0HYN1
CP0HYN0
CP0 +
CP0 -
VDD
Rising-edge
+
-
GND
Reset
Decision
Tree
SET
D
(SYNCHRONIZER)
SET
D
Q
Q
CLR
CLR
Q
Q
Figure 1.11 shows the
Interrupt
CP0
Falling-edge
Interrupt
Logic
Crossbar
CP0
CP0
CP0RIE
CP0FIE
CP0
CP0A
-
CP0RIE
Note: P2.4 and P2.5 available
only on C8051F320
CP0FIE
CPT0MD
CP0MD1
CP0MD0
28 Rev. 1.1
2. ABSOLUTE MAXIMUM RATINGS
C8051F320/1
Tab le 2.1. Absolute Maximum Ratings
PARAMETER CONDITIONS MIN TYP MAX UNITS
Ambient temperature under bias -55 125 °C
Storage Temperature -65 150 °C
Voltage on any Port I/O Pin or /RST with respect
to GND
Voltage on VDD with respect to GND -0.3 4.2 V
Maximum Total current through VDD and GND 500 mA
Maximum output current sunk by /RST or any
Port pin
*
Note: stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
*
-0.3 5.8 V
100 mA
Rev. 1.1 29
C8051F320/1
3. GLOBAL DC ELECTRICAL CHARACTERISTICS
Tab le 3.1. Global DC Electrical Characteristics
-40°C to +85°C, 25 MHz System Clock unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Supply Voltage (Note 1) 2.7 3.3 3.6 V
Digital Supply Current with CPU
active
Digital Supply Current with CPU
active and USB active (Full or Low
Speed)
Digital Supply Current with CPU
inactive (not accessing FLASH)
Digital Supply Current (suspend
mode or shutdown mode)
Digital Supply RAM Data Retention Voltage
SYSCLK (System Clock) (Note 2) 0 25 MHz
T
(SYSCLK High Time) 18 ns
SYSH
(SYSCLK Low Time) 18 ns
T
SYSL
Specified Operating Temperature
Range
VDD=3.3V, Clock=24MHz
VDD=3.3V, Clock=1MHz
VDD=3.3V, Clock=32kHz
VDD=3.3V, Clock=24MHz
VDD=3.3V, Clock=6MHz
VDD=3.3V, Clock=24MHz
VDD=3.3V, Clock=1MHz
VDD=3.3V, Clock=32kHz
Oscillator not running < 0.1 µA
-40 +85 °C
10
0.6
30
TBD
TBD
5
0.3
14
1.5 V
mA
mA
µA
mA
mA
mA
mA
µA
Note 1: USB Requires 3.0 V Minimum Supply Voltage.
Note 2: SYSCLK must be at least 32 kHz to enable debugging.
30 Rev. 1.1
Loading...