Silicon Laboratories C8051F310, C8051F311, C8051F312, C8051F313, C8051F314 Technical data
...
C8051F310/1/2/3/4/5
8/16 kB ISP FLASH MCU Family
Analog Peripherals
- 10-Bit ADC (C8051F310/1/2/3 only)
• Up to 200 ksps
• Up to 21 or 17 external single-ended or differential
inputs
• VREF from external pin or V
DD
• Built-in temperature sensor
• External conversion start input
- Comparators
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
(Comparator0)
• Low current (< 0.5 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug
(no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-Chips, target pods, and sockets
- Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 5 mA at 25 MHz;
11 µA at 32 kHz
- Typical stop mode current: 0.1 µA
- Temperature range: –40 to +85 °C
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 1280 bytes internal data RAM (1024 + 256)
- 16 kB (C8051F310/1) or 8 kB (C8051F312/3/4/5)
Flash; In-system programmable in 512-byte sectors
Digital Peripherals
- 29/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART, SMBus™, and SPI™
serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five
capture/compare modules
- Real time clock capability using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
- 32-pin LQFP (C8051F310/2/4)
- 28-pin MLP (C8051F311/3/5)
ANALOG
PERIPHERALS
A
M
U
X
TEMP
SENSOR
C8051F310/1/2/3 only
10-bit
200ksps
ADC
+
+
-
VOLTAGE
COMPARATORS
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CROSSBAR
Port 0
Port 1
Port 2
Port 3
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB/8 kB
ISP FLASH
14
INTERRUPTS
Rev. 1.5 10/04 Copyright © 2004 by Silicon Laboratories C8051F310/1/2/3/4/5
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
1280 B
SRAM
POR
WDT
C8051F310/1/2/3/4/5
Notes
2 Rev. 1.5
C8051F310/1/2/3/4/5
Table Of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 25
1.1.1. Fully 8051 Compatible.............................................................................. 25
1.1.2. Improved Throughput............................................................................... 25
1.1.3. Additional Features .................................................................................. 26
1.2. On-Chip Memory............................................................................................... 27
1.3. On-Chip Debug Circuitry................................................................................... 28
1.4. Programmable Digital I/O and Crossbar ........................................................... 29
1.5. Serial Ports ....................................................................................................... 30
1.6. Programmable Counter Array ........................................................................... 30
1.7. 10-Bit Analog to Digital Converter..................................................................... 31
1.8. Comparators ..................................................................................................... 32
2. Absolute Maximum Ratings .................................................................................. 33
3. Global DC Electrical Characteristics .................................................................... 34
4. Pinout and Package Definitions............................................................................ 35
5. 10-Bit ADC (ADC0, C8051F310/1/2/3 only) ........................................................... 43
5.1. Analog Multiplexer ............................................................................................ 44
5.2. Temperature Sensor ......................................................................................... 45
5.3. Modes of Operation .......................................................................................... 47
5.3.1. Starting a Conversion............................................................................... 47
5.3.2. Tracking Modes........................................................................................ 48
5.3.3. Settling Time Requirements..................................................................... 49
5.4. Programmable Window Detector ...................................................................... 54
5.4.1. Window Detector In Single-Ended Mode ................................................. 56
5.4.2. Window Detector In Differential Mode...................................................... 57
6. Voltage Reference (C8051F310/1/2/3 only)........................................................... 59
7. Comparators ........................................................................................................... 61
8. CIP-51 Microcontroller .......................................................................................... 71
8.1. Instruction Set ................................................................................................... 73
8.1.1. Instruction and CPU Timing ..................................................................... 73
8.1.2. MOVX Instruction and Program Memory ................................................. 73
8.2. Memory Organization........................................................................................ 77
8.2.1. Program Memory...................................................................................... 77
8.2.2. Data Memory............................................................................................ 78
8.2.3. General Purpose Registers ...................................................................... 78
8.2.4. Bit Addressable Locations........................................................................ 78
8.2.5. Stack ....................................................................................................... 78
8.2.6. Special Function Registers....................................................................... 79
8.2.7. Register Descriptions ............................................................................... 82
8.3. Interrupt Handler ............................................................................................... 86
8.3.1. MCU Interrupt Sources and Vectors ........................................................ 86
8.3.2. External Interrupts.................................................................................... 87
8.3.3. Interrupt Priorities ..................................................................................... 87
Rev. 1.5 3
C8051F310/1/2/3/4/5
8.3.4. Interrupt Latency ...................................................................................... 87
8.3.5. Interrupt Register Descriptions................................................................. 89
8.4. Power Management Modes .............................................................................. 94
8.4.1. Idle Mode.................................................................................................. 94
8.4.2. Stop Mode................................................................................................ 95
9. Reset Sources......................................................................................................... 97
9.1. Power-On Reset ............................................................................................... 98
9.2. Power-Fail Reset / VDD Monitor....................................................................... 99
9.3. External Reset ................................................................................................ 100
9.4. Missing Clock Detector Reset......................................................................... 100
9.5. Comparator0 Reset......................................................................................... 100
9.6. PCA Watchdog Timer Reset........................................................................... 100
9.7. Flash Error Reset............................................................................................ 100
9.8. Software Reset ............................................................................................... 101
10.Flash Memory ..................................................................................................... 103
10.1.Programming The Flash Memory ................................................................... 103
10.1.1.Flash Lock and Key Functions ............................................................... 103
10.1.2.Flash Erase Procedure .......................................................................... 103
10.1.3.Flash Write Procedure ........................................................................... 104
10.2.Non-volatile Data Storage .............................................................................. 105
10.3.Security Options ............................................................................................. 105
11.External RAM ........................................................................................................ 109
12.Oscillators ............................................................................................................. 111
12.1.Programmable Internal Oscillator ................................................................... 111
12.2.External Oscillator Drive Circuit...................................................................... 114
12.3.System Clock Selection.................................................................................. 114
12.4.External Crystal Example ............................................................................... 116
12.5.External RC Example ..................................................................................... 117
12.6.External Capacitor Example ........................................................................... 117
13.Port Input/Output ................................................................................................ 119
13.1.Priority Crossbar Decoder .............................................................................. 121
13.2.Port I/O Initialization ....................................................................................... 123
13.3.General Purpose Port I/O ............................................................................... 126
14.SMBus ................................................................................................................... 135
14.1.Supporting Documents................................................................................... 136
14.2.SMBus Configuration...................................................................................... 136
14.3.SMBus Operation ........................................................................................... 137
14.3.1.Arbitration............................................................................................... 137
14.3.2.Clock Low Extension.............................................................................. 138
14.3.3.SCL Low Timeout................................................................................... 138
14.3.4.SCL High (SMBus Free) Timeout .......................................................... 138
14.4.Using the SMBus............................................................................................ 139
14.4.1.SMBus Configuration Register............................................................... 140
14.4.2.SMB0CN Control Register ..................................................................... 143
14.4.3.Data Register ......................................................................................... 146
4 Rev. 1.5
C8051F310/1/2/3/4/5
14.5.SMBus Transfer Modes.................................................................................. 147
14.5.1.Master Transmitter Mode ....................................................................... 147
14.5.2.Master Receiver Mode........................................................................... 148
14.5.3.Slave Receiver Mode............................................................................. 149
14.5.4.Slave Transmitter Mode ......................................................................... 150
14.6.SMBus Status Decoding................................................................................. 151
15.UART0.................................................................................................................... 153
15.1.Enhanced Baud Rate Generation................................................................... 154
15.2.Operational Modes ......................................................................................... 155
15.2.1.8-Bit UART............................................................................................. 155
15.2.2.9-Bit UART............................................................................................. 156
15.3.Multiprocessor Communications .................................................................... 157
16.Enhanced Serial Peripheral Interface (SPI0)...................................................... 163
16.1.Signal Descriptions......................................................................................... 164
16.1.1.Master Out, Slave In (MOSI).................................................................. 164
16.1.2.Master In, Slave Out (MISO).................................................................. 164
16.1.3.Serial Clock (SCK) ................................................................................. 164
16.1.4.Slave Select (NSS) ................................................................................ 164
16.2.SPI0 Master Mode Operation ......................................................................... 165
16.3.SPI0 Slave Mode Operation ........................................................................... 167
16.4.SPI0 Interrupt Sources ................................................................................... 167
16.5.Serial Clock Timing......................................................................................... 168
16.6.SPI Special Function Registers...................................................................... 170
17.Timers ................................................................................................................... 177
17.1.Timer 0 and Timer 1 ....................................................................................... 177
17.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 177
17.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 179
17.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 179
17.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 180
17.2.Timer 2 .......................................................................................................... 185
17.2.1.16-bit Timer with Auto-Reload................................................................ 185
17.2.2.8-bit Timers with Auto-Reload................................................................ 186
17.3.Timer 3 .......................................................................................................... 189
17.3.1.16-bit Timer with Auto-Reload................................................................ 189
17.3.2.8-bit Timers with Auto-Reload................................................................ 190
18.Programmable Counter Array ............................................................................ 193
18.1.PCA Counter/Timer ........................................................................................ 194
18.2.Capture/Compare Modules ............................................................................ 195
18.2.1.Edge-triggered Capture Mode................................................................ 196
18.2.2.Software Timer (Compare) Mode........................................................... 197
18.2.3.High-Speed Output Mode ...................................................................... 198
18.2.4.Frequency Output Mode ........................................................................ 199
18.2.5.8-Bit Pulse Width Modulator Mode......................................................... 200
18.2.6.16-Bit Pulse Width Modulator Mode....................................................... 201
18.3.Watchdog Timer Mode ................................................................................... 202
Rev. 1.5 5
C8051F310/1/2/3/4/5
18.3.1.Watchdog Timer Operation .................................................................... 202
18.3.2.Watchdog Timer Usage ......................................................................... 203
18.4.Register Descriptions for PCA........................................................................ 205
19.Revision Specific Behavior ................................................................................. 211
19.1.Revision Identification..................................................................................... 211
19.2.Reset Behavior............................................................................................... 211
19.2.1.Weak Pullups on GPIO Pins .................................................................. 211
19.2.2.VDD Monitor and the RST Pin ............................................................... 211
19.3.PCA Counter .................................................................................................. 212
20.C2 Interface ........................................................................................................... 213
20.1.C2 Interface Registers.................................................................................... 213
20.2.C2 Pin Sharing ............................................................................................... 215
Document Change List............................................................................................. 216
Contact Information.................................................................................................. 218
6 Rev. 1.5
C8051F310/1/2/3/4/5
List of Figures
1. System Overview
Figure 1.1. C8051F310 Block Diagram .................................................................... 19
Figure 1.2. C8051F311 Block Diagram .................................................................... 20
Figure 1.3. C8051F312 Block Diagram .................................................................... 21
Figure 1.4. C8051F313 Block Diagram .................................................................... 22
Figure 1.5. C8051F314 Block Diagram .................................................................... 23
Figure 1.6. C8051F315 Block Diagram .................................................................... 24
Figure 1.7. Comparison of Peak MCU Execution Speeds ....................................... 25
Figure 1.8. On-Chip Clock and Reset ...................................................................... 26
Figure 1.9. On-Board Memory Map.......................................................................... 27
Figure 1.10. Development/In-System Debug Diagram............................................. 28
Figure 1.11. Digital Crossbar Diagram ..................................................................... 29
Figure 1.12. PCA Block Diagram.............................................................................. 30
Figure 1.13. 10-Bit ADC Block Diagram................................................................... 31
Figure 1.14. Comparator0 Block Diagram ................................................................ 32
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 37
Figure 4.2. LQFP-32 Package Diagram ................................................................... 38
Figure 4.3. MLP-28 Pinout Diagram (Top View) ...................................................... 39
Figure 4.4. MLP-28 Package Drawing ..................................................................... 40
Figure 4.5. Typical MLP-28 Landing Diagram .......................................................... 41
Figure 4.6. MLP-28 Solder Paste Recommendation ................................................ 42
5. 10-Bit ADC (ADC0, C8051F310/1/2/3 only)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 43
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 45
Figure 5.3. Temperature Sensor Error with 1-Point Calibration ............................... 46
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing .............................. 48
Figure 5.5. ADC0 Equivalent Input Circuits .............................................................. 49
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data ... 56
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 56
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ....... 57
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data.......... 57
6. Voltage Reference (C8051F310/1/2/3 only)
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 59
7. Comparators
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 61
Figure 7.2. Comparator1 Functional Block Diagram ................................................ 62
Figure 7.3. Comparator Hysteresis Plot ................................................................... 63
8. CIP-51 Microcontroller
Figure 8.1. CIP-51 Block Diagram............................................................................ 71
Figure 8.2. Memory Map .......................................................................................... 77
Rev. 1.5 7
C8051F310/1/2/3/4/5
9. Reset Sources
Figure 9.1. Reset Sources........................................................................................ 97
Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 98
10.Flash Memory
Figure 10.1. Flash Program Memory Map.............................................................. 105
11.External RAM
12.Oscillators
Figure 12.1. Oscillator Diagram.............................................................................. 111
Figure 12.2. 32.768 kHz External Crystal Example................................................ 116
13.Port Input/Output
Figure 13.1. Port I/O Functional Block Diagram ..................................................... 119
Figure 13.2. Port I/O Cell Block Diagram ............................................................... 120
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped ............................... 121
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 122
14.SMBus
Figure 14.1. SMBus Block Diagram ....................................................................... 135
Figure 14.2. Typical SMBus Configuration ............................................................. 136
Figure 14.3. SMBus Transaction ............................................................................ 137
Figure 14.4. Typical SMBus SCL Generation......................................................... 141
Figure 14.5. Typical Master Transmitter Sequence................................................ 147
Figure 14.6. Typical Master Receiver Sequence.................................................... 148
Figure 14.7. Typical Slave Receiver Sequence...................................................... 149
Figure 14.8. Typical Slave Transmitter Sequence.................................................. 150
15.UART0
Figure 15.1. UART0 Block Diagram ....................................................................... 153
Figure 15.2. UART0 Baud Rate Logic .................................................................... 154
Figure 15.3. UART Interconnect Diagram .............................................................. 155
Figure 15.4. 8-Bit UART Timing Diagram............................................................... 155
Figure 15.5. 9-Bit UART Timing Diagram............................................................... 156
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram .......................... 157
16.Enhanced Serial Peripheral Interface (SPI0)
Figure 16.1. SPI Block Diagram ............................................................................. 163
Figure 16.2. Multiple-Master Mode Connection Diagram ....................................... 166
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 166
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 166
Figure 16.5. Master Mode Data/Clock Timing ........................................................ 168
Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 169
Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 169
Figure 16.8. SPI Master Timing (CKPHA = 0)........................................................ 173
Figure 16.9. SPI Master Timing (CKPHA = 1)........................................................ 173
Figure 16.10. SPI Slave Timing (CKPHA = 0)........................................................ 174
Figure 16.11. SPI Slave Timing (CKPHA = 1)........................................................ 174
17.Timers
Figure 17.1. T0 Mode 0 Block Diagram.................................................................. 178
Figure 17.2. T0 Mode 2 Block Diagram.................................................................. 179
8 Rev. 1.5
C8051F310/1/2/3/4/5
Figure 17.3. T0 Mode 3 Block Diagram.................................................................. 180
Figure 17.4. Timer 2 16-Bit Mode Block Diagram .................................................. 185
Figure 17.5. Timer 2 8-Bit Mode Block Diagram .................................................... 186
Figure 17.6. Timer 3 16-Bit Mode Block Diagram .................................................. 189
Figure 17.7. Timer 3 8-Bit Mode Block Diagram .................................................... 190
18.Programmable Counter Array
Figure 18.1. PCA Block Diagram............................................................................ 193
Figure 18.2. PCA Counter/Timer Block Diagram.................................................... 194
Figure 18.3. PCA Interrupt Block Diagram ............................................................. 195
Figure 18.4. PCA Capture Mode Diagram.............................................................. 196
Figure 18.5. PCA Software Timer Mode Diagram .................................................. 197
Figure 18.6. PCA High Speed Output Mode Diagram............................................ 198
Figure 18.7. PCA Frequency Output Mode ............................................................ 199
Figure 18.8. PCA 8-Bit PWM Mode Diagram ......................................................... 200
Figure 18.9. PCA 16-Bit PWM Mode...................................................................... 201
Figure 18.10. PCA Module 4 with Watchdog Timer Enabled ................................. 202
19.Revision Specific Behavior
Figure 19.1. Reading Package Marking ................................................................. 211
20.C2 Interface
Figure 20.1. Typical C2 Pin Sharing....................................................................... 215
Rev. 1.5 9
C8051F310/1/2/3/4/5
Notes
10 Rev. 1.5
C8051F310/1/2/3/4/5
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 18
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 33
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics ....................................................... 34
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F31x .......................................................... 35
Table 4.2. LQFP-32 Package Dimensions .............................................................. 38
Table 4.3. MLP-28 Package Dimensions ................................................................ 40
5. 10-Bit ADC (ADC0, C8051F310/1/2/3 only)
Table 5.1. ADC0 Electrical Characteristics .............................................................. 58
6. Voltage Reference (C8051F310/1/2/3 only)
Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 60
7. Comparators
Table 7.1. Comparator Electrical Characteristics .................................................... 70
8. CIP-51 Microcontroller
Table 8.1. CIP-51 Instruction Set Summary ............................................................ 73
Table 8.2. Special Function Register (SFR) Memory Map ...................................... 79
Table 8.3. Special Function Registers ..................................................................... 80
Table 8.4. Interrupt Summary .................................................................................. 88
9. Reset Sources
Table 9.1. Reset Electrical Characteristics ............................................................ 102
10.Flash Memory
Table 10.1. Flash Electrical Characteristics .......................................................... 104
11.External RAM
12.Oscillators
Table 12.1. Internal Oscillator Electrical Characteristics ....................................... 113
13.Port Input/Output
Table 13.1. Port I/O DC Electrical Characteristics ................................................. 133
14.SMBus
Table 14.1. SMBus Clock Source Selection .......................................................... 140
Table 14.2. Minimum SDA Setup and Hold Times ................................................ 141
Table 14.3. Sources for Hardware Changes to SMB0CN ..................................... 145
Table 14.4. SMBus Status Decoding ..................................................................... 151
15.UART0
Table 15.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator 160
Table 15.2. Timer Settings for Standard Baud Rates Using an External
25 MHz Oscillator ............................................................................... 160
Table 15.3. Timer Settings for Standard Baud Rates Using an External
22.1184 MHz Oscillator ...................................................................... 161
Rev. 1.5 11
C8051F310/1/2/3/4/5
Table 15.4. Timer Settings for Standard Baud Rates Using an External
18.432 MHz Oscillator ........................................................................ 161
Table 15.5. Timer Settings for Standard Baud Rates Using an External
11.0592 MHz Oscillator ...................................................................... 162
Table 15.6. Timer Settings for Standard Baud Rates Using an External
3.6864 MHz Oscillator ........................................................................ 162
16.Enhanced Serial Peripheral Interface (SPI0)
Table 16.1. SPI Slave Timing Parameters ............................................................ 175
17.Timers
18.Programmable Counter Array
Table 18.1. PCA Timebase Input Options ............................................................. 194
Table 18.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 195
Table 18.3. Watchdog Timer Timeout Intervals ..................................................... 204
19.Revision Specific Behavior
20.C2 Interface
12 Rev. 1.5
C8051F310/1/2/3/4/5
List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 51
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 54
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 54
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 55
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 55
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 65
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 66
SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SFR Definition 8.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 8.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 8.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 8.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SFR Definition 8.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 8.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 9.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SFR Definition 10.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 10.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 10.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 11.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 109
SFR Definition 12.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 112
SFR Definition 12.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 12.3. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SFR Definition 12.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 115
SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 124
SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 125
SFR Definition 13.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SFR Definition 13.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Rev. 1.5 13
C8051F310/1/2/3/4/5
SFR Definition 13.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Definition 13.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Definition 13.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SFR Definition 13.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SFR Definition 13.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 129
SFR Definition 13.10. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SFR Definition 13.11. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SFR Definition 13.12. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SFR Definition 13.13. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 130
SFR Definition 13.14. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 13.15. P3: Port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 13.16. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 13.17. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 142
SFR Definition 14.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SFR Definition 14.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 159
SFR Definition 16.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 170
SFR Definition 16.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 16.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 17.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
SFR Definition 17.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SFR Definition 17.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
SFR Definition 17.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 17.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 17.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 17.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 17.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
SFR Definition 17.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 188
SFR Definition 17.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 188
SFR Definition 17.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
SFR Definition 17.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
SFR Definition 17.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
SFR Definition 17.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 192
SFR Definition 17.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 192
SFR Definition 17.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SFR Definition 17.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SFR Definition 18.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
SFR Definition 18.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
SFR Definition 18.3. PCA0CPMn: PCA Capture/Compare Mode Registers . . . . . . . 207
SFR Definition 18.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 208
SFR Definition 18.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 208
SFR Definition 18.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 208
14 Rev. 1.5
C8051F310/1/2/3/4/5
SFR Definition 18.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 209
C2 Register Definition 20.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
C2 Register Definition 20.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 213
C2 Register Definition 20.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 214
C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 214
C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 214
Rev. 1.5 15
C8051F310/1/2/3/4/5
Notes
16 Rev. 1.5
C8051F310/1/2/3/4/5
1. System Overview
C8051F31x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are
listed below. Refer to
• High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 10-bit 200 ksps 25-channel single-ended/differential ADC with analog multiplexer
(C8051F310/1/2/3)
• Precision programmable 25 MHz internal oscillator
• 16 kB (C8051F310/1) or 8 kB (C8051F312/3/4/5) of on-chip Flash memory
• 1280 bytes of on-chip RAM
• SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
• Four general-purpose 16-bit timers
• Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
• On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
• On-chip Voltage Comparators (2)
• 29/25 Port I/O (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F31x devices
are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-cir
cuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
Tab le 1.1 for specific product feature selection.
-
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system programming
and debugging without occupying package pins.
Each device is specified for 2.7-to-3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/O and
LQFP or a 28-pin MLP package.
RST pins are tolerant of input signals up to 5 V. The C8051F31x are available in a 32-pin
Rev. 1.5 17
C8051F310/1/2/3/4/5
Table 1.1. Product Selection Guide
MIPS (Peak)
Flash Memory
C8051F310 25 16 1280 3 3 3 3 4 3 29 3 3 2 LQFP-32
C8051F311 25 16 1280 3 3 3 3 4 3 25 3 3 2 MLP-28
C8051F312 25 8 1280 3 3 3 3 4 3 29 3 3 2 LQFP-32
C8051F313 25 8 1280 3 3 3 3 4 3 25 3 3 2 MLP-28
RAM
Calibrated Internal Oscillator
SMBus/I2C
Enhanced SPI
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
10-bit 200ksps ADC
Temperature Sensor
Analog Comparators
Package
C8051F314 25 8 1280 3 3 3 3 4 3 29 2 LQFP-32
C8051F315 25 8 1280 3 3 3 3 4 3 25 2 MLP-28
18 Rev. 1.5
C8051F310/1/2/3/4/5
VDD
GND
/RST/C2CK
Analog/Digital
Power
C2D
XTAL1
XTAL2
POR
External
Oscillator
Circuit
2%
Internal
Oscillator
Debug HW
Brown-
Out
Reset
System Clock
8
0
5
1
C
o
SFR Bus
r
e
16kbyte
FLASH
256 byte
SRAM
1K byte
SRAM
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
PCA/
WDT
SMBus
Port 2
Latch
Port 3
Latch
VDD
10-bit
200ksps
ADC
RTC
SPI
VREF
P
0
D
r
v
C
P
R
1
O
S
D
S
r
B
v
A
R
P
2
D
r
v
P
3
D
r
v
CP0
+
-
CP1
+
-
Temp
A
AIN0-AIN20
M
U
X
VDD
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
Figure 1.1. C8051F310 Block Diagram
Rev. 1.5 19
C8051F310/1/2/3/4/5
VDD
GND
/RST/C2CK
Analog/Digital
Power
C2D
XTAL1
XTAL2
POR
External
Oscillator
Circuit
2%
Internal
Oscillator
Debug HW
Brown-
Out
Reset
System Clock
8
0
5
1
C
o
SFR Bus
r
e
16kbyte
FLASH
256 byte
SRAM
1K byte
SRAM
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
SMBus
Port 2
Latch
Port 3
Latch
VDD
10-bit
200ksps
ADC
RTC
PCA/
WDT
SPI
VREF
P
0
D
r
v
C
P
R
1
O
S
D
S
r
B
v
A
R
P
2
D
r
v
P
3
D
r
v
CP0
+
-
CP1
+
-
Temp
A
AIN0-AIN20
M
U
X
VDD
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Figure 1.2. C8051F311 Block Diagram
20 Rev. 1.5
C8051F310/1/2/3/4/5
VDD
GND
/RST/C2CK
Analog/Digital
Power
C2D
XTAL1
XTAL2
POR
External
Oscillator
Circuit
2%
Internal
Oscillator
Debug HW
Brown-
Out
Reset
System Clock
8
0
5
1
C
o
SFR Bus
r
e
8 kB
FLASH
256 byte
SRAM
1K byte
SRAM
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
Port 2
Latch
Port 3
Latch
VDD
10-bit
200ksps
ADC
SPI
VREF
CP0
CP1
Temp
VDD
+
-
+
-
A
M
U
X
C
R
O
S
S
B
A
R
AIN0-AIN20
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
Figure 1.3. C8051F312 Block Diagram
Rev. 1.5 21
C8051F310/1/2/3/4/5
VDD
GND
/RST/C2CK
Analog/Digital
Power
C2D
XTAL1
XTAL2
POR
External
Oscillator
Circuit
2%
Internal
Oscillator
Debug HW
Brown-
Out
Reset
System Clock
8
0
5
1
C
o
SFR Bus
r
e
8 kB
FLASH
256 byte
SRAM
1K byte
SRAM
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
Port 2
Latch
Port 3
Latch
VDD
10-bit
200ksps
ADC
SPI
VREF
CP0
CP1
Temp
VDD
C
R
O
S
S
B
A
R
+
-
+
-
A
M
U
X
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
AIN0-AIN20
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Figure 1.4. C8051F313 Block Diagram
22 Rev. 1.5
C8051F310/1/2/3/4/5
VDD
GND
/RST/C2CK
Analog/Digital
Power
C2D
XTAL1
XTAL2
POR
External
Oscillator
Circuit
2%
Internal
Oscillator
Debug HW
Brown-
Out
Reset
8
0
5
1
8 kB
FLASH
256 byte
SRAM
1K byte
SRAM
C
System Clock
o
SFR Bus
r
e
Figure 1.5. C8051F314 Block Diagram
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
Port 2
Latch
Port 3
Latch
P
0
D
r
v
C
P
R
1
O
S
D
S
r
B
v
A
R
P
2
D
r
v
P
3
D
r
v
CP0
+
-
CP1
+
-
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
Rev. 1.5 23
C8051F310/1/2/3/4/5
VDD
GND
/RST/C2CK
Analog/Digital
Power
C2D
XTAL1
XTAL2
POR
External
Oscillator
Circuit
2%
Internal
Oscillator
Debug HW
Brown-
Out
Reset
System Clock
8
0
5
1
C
o
SFR Bus
r
e
8 kB
FLASH
256 byte
SRAM
1K byte
SRAM
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
Port 2
Latch
Port 3
Latch
P
0
D
r
v
C
P
R
1
O
S
D
S
r
B
v
A
R
P
2
D
r
v
P
3
D
r
v
CP0
+
-
CP1
+
-
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Figure 1.6. C8051F315 Block Diagram
24 Rev. 1.5
C8051F310/1/2/3/4/5
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F31x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used
to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including
four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI
port, 1280
pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 29/25 I/O
MHz. By contrast, the CIP-51 core exe-
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.7
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.
25
20
15
MIPS
10
5
Silicon Labs
CIP-51
(25 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Philips
80C51
(33 MHz clk)
ADuC812
8051
(16 MHz clk)
Figure 1.7. Comparison of Peak MCU Execution Speeds
Rev. 1.5 25
C8051F310/1/2/3/4/5
1.1.3. Additional Features
The C8051F31x SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below V
Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external
reset pin, and an errant Flash read/write protection circuit. Each reset source except for the POR, Reset
Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled
in software after a power-on reset during MCU initialization.
The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also
included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate
the system clock. If desired, the system clock source may be switched on-the-fly between the internal and
external oscillator circuits. An external oscillator can be extremely useful in low power applications, allow
ing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the
fast internal oscillator as needed.
as given in Ta bl e 9.1 on page 102), a Watchdog Timer, a
RST
-
XTAL1
XTAL2
Internal
Oscillator
External
Oscillator
Drive
Px.x
Px.x
VDD
Supply
Monitor
Comparator 0
+
-
System
Clock
Clock Select
C0RSEF
Missing
Clock
Detector
(one-
shot)
EN
MCD
Enable
CIP-51
Microcontroller
PCA
WDT
EN
WDT
Enable
+
-
System Reset
Enable
(Software Reset)
SWRSF
'0'
Core
Extended Interrupt
Handler
Figure 1.8. On-Chip Clock and Reset
Power On
Reset
Operation
Errant
FLASH
(wired-OR)
Reset
Funnel
/RST
26 Rev. 1.5
C8051F310/1/2/3/4/5
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 8 or 16 kB of Flash. This memory may be reprogrammed in-system in 512
byte sectors, and requires no special off-chip programming voltage. See
memory map.
Figure 1.9 for the MCU system
PROGRAM/DATA MEMORY
(Flash)
C8051F310/1
0x3E00
0x3DFF
0x0000
0x2000
0x1FFF
RESERVED
16 kB Flash
(In-System
Programmable in 512
Byte Sectors)
C8051F312/3/4/5
RESERVED
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1 kB boundaries
0x0000
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
Figure 1.9. On-Board Memory Map
0x0400
0x03FF
0x0000
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
Rev. 1.5 27
C8051F310/1/2/3/4/5
1.3. On-Chip Debug Circuitry
The C8051F31x devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them synchronized.
The C8051F310DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F31x MCUs. The kit includes software with a
developer's studio and debugger, an integrated 8051 assembler, a serial adapter, a target application
board with the associated MCU installed, and the required cables and wall-mount power supply. The Serial
Adapter takes its power from the application board. For applications where there is not sufficient power
available from the target board, the provided power supply can be connected directly to the Serial Adapter.
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to
standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
Silicon Laboratories Integrated
Development Environment
WINDOWS 95 or later
Serial
Adapter
C2 (x2), VDD, GND
VDD GND
C8051F31x
TARGET PCB
Figure 1.10. Development/In-System Debug Diagram
28 Rev. 1.5
C8051F310/1/2/3/4/5
1.4. Programmable Digital I/O and Crossbar
C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port);
C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port). The
C8051F31x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config
ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for
push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be globally
disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.11).
On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the
controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This
allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the
particular application.
-
Highest
Priority
Lowest
Priority
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Priority
Decoder
UART
SPI
SMBus
CP0
Outputs
CP1
Outputs
SYSCLK
(Internal Digital Signals)
PCA
T0, T1
P0
(P0.0-P0.7)
P1
(P1.0-P1.7)
P2
P3
(P2.0-P2.3)
(P2.4-P2.7)
(P3.0-P3.4)
(Port Latches)
2
4
2
2
2
6
2
8
8
4
4
5
Digital
Crossbar
8
8
4
P0
I/O
Cells
P1
I/O
Cells
P2
84
I/O
Cells
P3
5
I/O
Cells
Note: P3.1-P3.4 only available
on the C8051F310/2/4
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
Figure 1.11. Digital Crossbar Diagram
Rev. 1.5 29
C8051F310/1/2/3/4/5
1.5. Serial Ports
The C8051F31x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.6. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8. The external clock source selection is useful for real-time
clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the
system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
ECI
CEX0
PCA
CLOCK
MUX
Capture/Compare
Module 1
CEX1
16-Bit Counter/Timer
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
CEX3
Capture/Compare
Module 4 / WDT
CEX4
Crossbar
Port I/O
Figure 1.12. PCA Block Diagram
30 Rev. 1.5
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