Silicon Laboratories C8051F2xx User Manual

C8051F2xx

Mixed Signal 8 kB ISP Flash MCU Family

Analog Peripherals

- SAR ADC

• 12-bit resolution ('F206)

• 8-bit resolution ('F220/1/6)

• ±1/4 LSB INL (8-bit) and ±2 LSB INL (12-bit)

• Up to 100 ksps

• Up to 32 channel input multiplexer; each port

I/O pin can be an ADC input

- Two Comparators

• 16 programmable hysteresis states

• Configurable to generate interrupts or reset

- V

monitor and brown-out detector

DD

On-Chip JTAG Debug

- On-chip debug circuitry facilitates full speed,

non-intrusive in-system debug (No emulator
required)

- Provides breakpoints, single-stepping, watchpoints,

stack monitor

- Inspect/modify memory and registers

- Superior performance to emulation systems using

ICE-chips, target pods, and sockets

- Complete, low cost development kit

High Speed

- 8051 mC Core

- Pipelined Instruction Architecture; Executes 70% of

Instructions in 1 or 2 System Clocks

- Up to 25MIPS Throughput with 25MHz Clock

- Expanded Interrupt Handler

Memory

- 256 bytes internal data RAM

- 1024 bytes XRAM (available on 'F206/226/236)

- 8 kB Flash; In-system programmable in 512 byte

sectors

Digital Peripherals

- Four byte wide Port I/O; All are 5 V tolerant

- Hardware UART and SPI bus

- 3 general purpose 16-bit counter/timers

- Dedicated watch-dog timer

- Bi-directional reset

- System clock: internal programmable oscillator,

external crystal, external RC, or external clock

Supply Voltage 2.7 to 3.6 V

- Typical operating current: 10 mA @ 25 MHz

- Multiple power saving sleep and shutdown modes

(48-Pin TQFP and 32-Pin LQFP Version
Available)
Temperature Range: –40 to +85 °C

ANALOG PERIPHERALS

+

-

SAR

ADC

PGA

AMUX

+

-

VOLTAGE

COMPARATORS

DIGITAL I/O

SPI Bus

UART

Timer 0

Timer 1

Timer 2

Digital MUX

Port 0Port 1

Port 2Port 3

HIGH-SPEED CONTROLLER CORE

8051 CPU

(25MIPS)

8K x 8

ISP FLASH

CLOCK

CIRCUIT

1280 x 8

SRAM

JTAG

22 INTERRUPTS

Rev. 1.6 3/05 Copyright © 2005 by Silicon Laboratories C8051F2xx

EMULATION

CIRCUITRY

SANITY

CONTROL

C8051F2xx

NOTES:

2 Rev. 1.6

C8051F2xx

Table of Contents

1. System Overview.................................................................................................... 11

1.1. CIP-51TM Microcontroller Core ........................................................................ 15

1.1.1. Fully 8051 Compatible.............................................................................. 15

1.1.2. Improved Throughput............................................................................... 15

1.1.3. Additional Features .................................................................................. 16

1.2. On-Board Memory ............................................................................................ 17

1.3. JTAG ............................................................................................................ 18

1.4. Digital/Analog Configurable I/O......................................................................... 19

1.5. Serial Ports ....................................................................................................... 20

1.6. Analog to Digital Converter ............................................................................... 20

1.7. Comparators ..................................................................................................... 21

2. Absolute Maximum Ratings .................................................................................. 23

3. Global DC Electrical Characteristics .................................................................... 24

4. Pinout and Package Definitions............................................................................ 25

5. ADC (8-Bit, C8051F220/1/6 Only)........................................................................... 32

5.1. Analog Multiplexer and PGA............................................................................. 32

5.2. ADC Modes of Operation.................................................................................. 33

5.3. ADC Programmable Window Detector ............................................................. 37

6. ADC (12-Bit, C8051F206 Only)............................................................................... 40

6.1. Analog Multiplexer and PGA............................................................................. 40

6.2. ADC Modes of Operation.................................................................................. 41

6.3. ADC Programmable Window Detector ............................................................. 46

7. Voltage Reference (C8051F206/220/221/226) ....................................................... 50

8. Comparators ........................................................................................................... 52

9. CIP-51 Microcontroller ........................................................................................... 58

9.1. Instruction Set ................................................................................................... 60

9.1.1. Instruction and CPU Timing ..................................................................... 60

9.1.2. MOVX Instruction and Program Memory ................................................. 60

9.2. Memory Organization........................................................................................ 65

9.2.1. Program Memory...................................................................................... 65

9.2.2. Data Memory............................................................................................ 65

9.2.3. General Purpose Registers ...................................................................... 66

9.2.4. Bit Addressable Locations........................................................................ 66

9.2.5. Stack ....................................................................................................... 67

9.3. Special Function Registers ............................................................................... 68

9.3.1. Register Descriptions ............................................................................... 71

9.4. Interrupt Handler ............................................................................................... 74

9.4.1. MCU Interrupt Sources and Vectors ........................................................ 74

9.4.2. External Interrupts.................................................................................... 74

9.4.3. Software Controlled Interrupts.................................................................. 74

9.4.4. Interrupt Priorities ..................................................................................... 76

9.4.5. Interrupt Latency ...................................................................................... 76

9.4.6. Interrupt Register Descriptions................................................................. 77

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C8051F2xx

9.5. Power Management Modes .............................................................................. 83

9.5.1. Idle Mode.................................................................................................. 83

9.5.2. Stop Mode................................................................................................ 83

10.Flash Memory ......................................................................................................... 85

10.1.Programming The Flash Memory ..................................................................... 85

10.2.Security Options ............................................................................................... 86

11.On-Chip XRAM (C8051F206/226/236).................................................................... 90

12.Reset Sources......................................................................................................... 91

12.1.Power-on Reset................................................................................................ 92

12.2.Software Forced Reset..................................................................................... 92

12.3.Power-fail Reset ............................................................................................... 92

12.4.External Reset.................................................................................................. 93

12.5.Missing Clock Detector Reset .......................................................................... 93

12.6.Comparator 0 Reset ......................................................................................... 93

12.7.Watchdog Timer Reset..................................................................................... 93

12.7.1.Watchdog Usage...................................................................................... 93

13.Oscillator ................................................................................................................. 97

13.1.External Crystal Example ............................................................................... 100

13.2.External RC Example ..................................................................................... 100

13.3.External Capacitor Example ........................................................................... 100

14.Port Input/Output.................................................................................................. 101

14.1.Port I/O Initialization ....................................................................................... 101

14.2.General Purpose Port I/O ............................................................................... 105

15.Serial Peripheral Interface Bus ........................................................................... 110

15.1.Signal Descriptions......................................................................................... 111

15.1.1.Master Out, Slave In .............................................................................. 111

15.1.2.Master In, Slave Out .............................................................................. 111

15.1.3.Serial Clock ............................................................................................ 111

15.1.4.Slave Select ........................................................................................... 111

15.2.Serial Clock Timing......................................................................................... 113

15.3.SPI Special Function Registers...................................................................... 113

16.UART...................................................................................................................... 117

16.1.UART Operational Modes .............................................................................. 118

16.1.1.Mode 0: Synchronous Mode .................................................................. 118

16.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 119

16.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 121

16.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 121

16.2.Multiprocessor Communications .................................................................... 122

17.Timers.................................................................................................................... 125

17.1.Timer 0 and Timer 1 ....................................................................................... 125

17.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 125

17.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 126

17.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 127

17.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 128

4 Rev. 1.6

C8051F2xx

17.2.Timer 2 .......................................................................................................... 133

17.2.1.Mode 0: 16-bit Counter/Timer with Capture........................................... 134

17.2.2.Mode 1: 16-bit Counter/Timer with Auto-Reload.................................... 135

17.2.3.Mode 2: Baud Rate Generator............................................................... 136

18.JTAG ...................................................................................................................... 139

18.1.Flash Programming Commands..................................................................... 140

18.2.Boundary Scan Bypass and ID Code ............................................................. 143

18.2.1.BYPASS Instruction ............................................................................... 143

18.2.2.IDCODE Instruction................................................................................ 143

18.3.Debug Support ............................................................................................... 143

Contact Information.................................................................................................. 144

Rev. 1.6 5

C8051F2xx

NOTES:

6 Rev. 1.6

C8051F2xx

List of Figures and Tables

1. System Overview

Table 1.1. Product Selection Guide ........................................................................ 11

Figure 1.1. C8051F206, C8051F220 and C8051F226 Block Diagram (48 TQFP) .. 12

Figure 1.2. C8051F221 Block Diagram (32 LQFP) .................................................. 13

Figure 1.3. C8051F230 and C8051F236 Block Diagram (48 TQFP) ....................... 14

Figure 1.4. C8051F231 Block Diagram (32 LQFP) .................................................. 15

Figure 1.5. Comparison of Peak MCU Throughputs ................................................ 16

Figure 1.6. Comparison of Peak MCU Throughputs ................................................ 17

Figure 1.7. On-Board Memory Map.......................................................................... 18

Figure 1.8. Degub Environment Diagram ................................................................. 19

Figure 1.9. Port I/O Functional Block Diagram......................................................... 20

Figure 1.10. ADC Diagram ....................................................................................... 21

Figure 1.11. Comparator Diagram............................................................................ 22

2. Absolute Maximum Ratings

Table 2.1. Absolute Maximum Ratings*.................................................................. 23

3. Global DC Electrical Characteristics

Table 3.1. Global DC Electrical Characteristics ...................................................... 24

4. Pinout and Package Definitions

Table 4.1. Pin Definitions ........................................................................................ 25

Figure 4.1. TQFP-48 Pin Diagram............................................................................ 28

Figure 4.2. LQFP-32 Pin Diagram ............................................................................ 29

Figure 4.3. TQFP-48 Package Drawing ................................................................... 30

Figure 4.4. LQFP-32 Package Drawing ................................................................... 31

5. ADC (8-Bit, C8051F220/1/6 Only)

Figure 5.1. 8-Bit ADC Functional Block Diagram ..................................................... 32

Figure 5.2. 12-Bit ADC Track and Conversion Example Timing .............................. 33

Figure 5.3. 8-Bit ADC Window Interrupt Examples .................................................. 38

Table 5.1. 8-Bit ADC Electrical Characteristics....................................................... 39

6. ADC (12-Bit, C8051F206 Only)

Figure 6.1. 12-Bit ADC Functional Block Diagram ................................................... 40

Figure 6.2. 12-Bit ADC Track and Conversion Example Timing .............................. 41

Figure 6.3. 12-Bit ADC Window Interrupt Examples, Right Justified Data ............... 47

Figure 6.4. 12-Bit ADC Window Interrupt Examples, Left Justified Data ................. 48

Table 6.1. 12-Bit ADC Electrical Characteristics (C8015F206 only)....................... 49

7. Voltage Reference (C8051F206/220/221/226)

Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 50

Table 7.1. Reference Electrical Characteristics ...................................................... 51

8. Comparators

Figure 8.1. Comparator Functional Block Diagram .................................................. 53

Figure 8.2. Comparator Hysteresis Plot ................................................................... 54

Table 8.1. Comparator Electrical Characteristics.................................................... 57

9. CIP-51 Microcontroller

Figure 9.1. CIP-51 Block Diagram............................................................................ 58

Rev. 1.6 7

C8051F2xx

Table 9.1. CIP-51 Instruction Set Summary............................................................ 60

Figure 9.2. Memory Map .......................................................................................... 66

Table 9.2. Special Function Register Memory Map ................................................ 68

Table 9.3. Special Function Registers .................................................................... 69

Table 9.4. Interrupt Summary ................................................................................. 75

10.Flash Memory

Table 10.1. Flash Memory Electrical Characteristics ............................................... 86

Figure 10.1. Flash Program Memory Security Bytes................................................ 87

11.On-Chip XRAM (C8051F206/226/236)

12.Reset Sources

Figure 12.1. Reset Sources Diagram ....................................................................... 91

Figure 12.2. VDD Monitor Timing Diagram .............................................................. 92

Table 12.1. VDD Monitor Electrical Characteristics.................................................. 96

13.Oscillator

Figure 13.1. Oscillator Diagram................................................................................ 97

Table 13.1. Internal Oscillator Electrical Characteristics .......................................... 98

14.Port Input/Output

Figure 14.1. Port I/O Functional Block Diagram ..................................................... 102

Figure 14.2. Port I/O Cell Block Diagram ............................................................... 102

Table 14.1. Port I/O DC Electrical Characteristics.................................................. 109

15.Serial Peripheral Interface Bus

Figure 15.1. SPI Block Diagram ............................................................................. 110

Figure 15.2. SPI Block Diagram ............................................................................. 111

Figure 15.3. Full Duplex Operation......................................................................... 112

Figure 15.4. Full Duplex Operation......................................................................... 113

16.UART

Figure 16.1. UART Block Diagram ......................................................................... 117

Table 16.1. UART Modes ....................................................................................... 118

Figure 16.2. UART Mode 0 Interconnect................................................................ 118

Figure 16.3. UART Mode 0 Timing Diagram .......................................................... 118

Figure 16.4. UART Mode 1 Timing Diagram .......................................................... 119

Figure 16.5. UART Modes 1, 2, and 3 Interconnect Diagram ................................ 120

Figure 16.6. UART Modes 2 and 3 Timing Diagram .............................................. 121

Figure 16.7. UART Multi-Processor Mode Interconnect Diagram .......................... 122

Table 16.2. Oscillator Frequencies for Standard Baud Rates ................................ 122

17.Timers

Figure 17.1. T0 Mode 0 Block Diagram.................................................................. 126

Figure 17.2. T0 Mode 2 Block Diagram.................................................................. 127

Figure 17.3. T0 Mode 3 Block Diagram.................................................................. 128

Figure 17.4. T2 Mode 0 Block Diagram.................................................................. 134

Figure 17.5. T2 Mode 1 Block Diagram.................................................................. 135

Figure 17.6. T2 Mode 2 Block Diagram.................................................................. 136

18.JTAG

8 Rev. 1.6

C8051F2xx

List of Registers

SFR Definition 5.1. AMX0SL: AMUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SFR Definition 5.2. ADC0CF: ADC Configuration Register . . . . . . . . . . . . . . . . . . . . . 35

SFR Definition 5.3. ADC0CN: ADC Control (C8051F220/1/6 and C8051F206) . . . . . . 36

SFR Definition 5.4. ADC0H: ADC Data Word (‘F220/1/6 and ‘F206) . . . . . . . . . . . . . 37

SFR Definition 5.5. ADC0GTH: ADC Greater-Than Data (‘F220/1/6 and ‘F206) . . . . . 37

SFR Definition 5.6. ADC0LTH: ADC Less-Than Data Byte (‘F220/1/6 and ‘F206) . . . . 37

SFR Definition 6.1. AMX0SL: AMUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SFR Definition 6.2. ADC0CF: ADC Configuration (‘F220/1/6 and ‘F206) . . . . . . . . . . . 43

SFR Definition 6.3. ADC0CN: ADC Control (‘F220/1/6 and ‘F206) . . . . . . . . . . . . . . . 44

SFR Definition 6.4. ADC0H: ADC Data Word MSB (C8051F206) . . . . . . . . . . . . . . . . 45

SFR Definition 6.5. ADC0L: ADC Data Word LSB (C8051F206) . . . . . . . . . . . . . . . . 45

SFR Definition 6.6. ADC0GTH: ADC Greater-Than Data High Byte (C8051F206) . . . 46

SFR Definition 6.7. ADC0GTL: ADC Greater-Than Data Low Byte (C8051F206) . . . . 46

SFR Definition 6.8. ADC0LTH: ADC Less-Than Data High Byte (C8051F206) . . . . . . 46

SFR Definition 6.9. ADC0LTL: ADC Less-Than Data Low Byte (C8051F206) . . . . . . . 47

SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SFR Definition 8.1. CPT0CN: Comparator 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SFR Definition 8.2. CPT1CN: Comparator 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 56

SFR Definition 9.1. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

SFR Definition 9.2. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

SFR Definition 9.3. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

SFR Definition 9.7. SWCINT: Software Controlled Interrupt Register . . . . . . . . . . . . . 75

SFR Definition 9.8. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

SFR Definition 9.9. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SFR Definition 9.10. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . 79

SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 80

SFR Definition 9.12. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 81

SFR Definition 9.13. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 82

SFR Definition 9.14. PCON: Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 84

SFR Definition 10.1. PSCTL: Program Store RW Control . . . . . . . . . . . . . . . . . . . . . . 88

SFR Definition 10.2. FLSCL: Flash Memory Timing Prescaler . . . . . . . . . . . . . . . . . . . 89

SFR Definition 10.3. FLACL: Flash Access Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

SFR Definition 11.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . . 90

SFR Definition 12.1. WDTCN: Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . 94

SFR Definition 12.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

SFR Definition 13.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 98

SFR Definition 13.2. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . . 99

SFR Definition 14.1. PRT0MX: Port I/O MUX Register 0 . . . . . . . . . . . . . . . . . . . . . . 103

SFR Definition 14.2. PRT1MX: Port I/O MUX Register 1 . . . . . . . . . . . . . . . . . . . . . . 104

SFR Definition 14.3. PRT2MX: Port I/O MUX Register 2 . . . . . . . . . . . . . . . . . . . . . . 104

Rev. 1.6 9

C8051F2xx

SFR Definition 14.4. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

SFR Definition 14.5. PRT0CF: Port0 Configuration Register . . . . . . . . . . . . . . . . . . . 105

SFR Definition 14.6. P0MODE: Port0 Digital/Analog Input Mode . . . . . . . . . . . . . . . . 106

SFR Definition 14.7. P1: Port1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

SFR Definition 14.8. PRT1CF: Port1 Configuration Register . . . . . . . . . . . . . . . . . . . 106

SFR Definition 14.9. P1MODE: Port1 Digital/Analog Input Mode . . . . . . . . . . . . . . . . 107

SFR Definition 14.10. P2: Port2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

SFR Definition 14.11. PRT2CF: Port2 Configuration Register . . . . . . . . . . . . . . . . . . 107

SFR Definition 14.12. P2MODE: Port2 Digital/Analog Input Mode . . . . . . . . . . . . . . . 108

SFR Definition 14.13. P3: Port3 Register* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

SFR Definition 14.14. PRT3CF: Port3 Configuration Register* . . . . . . . . . . . . . . . . . 108

SFR Definition 14.15. P3MODE: Port3 Digital/Analog Input Mode* . . . . . . . . . . . . . . 109

SFR Definition 15.1. SPI0CFG: SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

SFR Definition 15.2. SPI0CN: SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

SFR Definition 15.3. SPI0CKR: SPI Clock Rate Register . . . . . . . . . . . . . . . . . . . . . . 116

SFR Definition 15.4. SPI0DAT: SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

SFR Definition 16.1. SBUF: Serial (UART) Data Buffer . . . . . . . . . . . . . . . . . . . . . . . 123

SFR Definition 16.2. SCON: Serial Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

SFR Definition 17.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

SFR Definition 17.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

SFR Definition 17.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

SFR Definition 17.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

SFR Definition 17.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

SFR Definition 17.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

SFR Definition 17.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

SFR Definition 17.8. T2CON: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

SFR Definition 17.9. RCAP2L: Timer 2 Capture Register Low Byte . . . . . . . . . . . . . . 138

SFR Definition 17.10. RCAP2H: Timer 2 Capture Register High Byte . . . . . . . . . . . . 138

SFR Definition 17.11. TL2: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

SFR Definition 17.12. TH2: Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

JTAG Register Definition 18.1. IR: JTAG Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 139

JTAG Register Definition 18.2. FLASHCON: JTAG Flash Control . . . . . . . . . . . . . . . 141

JTAG Register Definition 18.3. FLASHADR: JTAG Flash Address . . . . . . . . . . . . . . 141

JTAG Register Definition 18.4. FLASHDAT: JTAG Flash Data . . . . . . . . . . . . . . . . . 142

JTAG Register Definition 18.5. FLASHSCL: JTAG Flash Scale . . . . . . . . . . . . . . . . . 142

JTAG Register Definition 18.6. DEVICEID: JTAG Device ID . . . . . . . . . . . . . . . . . . . 143

10 Rev. 1.6

C8051F2xx

1. System Overview

The C8051F2xx is a family of fully integrated, mixed-signal System on a Chip MCU's available with a true
12-bit ('F206) multi-channel ADC, 8-bit multi-channel ADC ('F220/1/6 and 'F206), or without an ADC
('F230/1/6). Each model features an 8051-compatible microcontroller core with 8
There are also UART and SPI serial interfaces implemented in hardware (not "bit-banged" in user soft
ware). Products in this family feature 22 or 32 general purpose I/O pins, some of which can be used for
assigned digital peripheral interface. Any pins may be configured for use as analog input to the analog-to­digital converter ('F220/1/6 and 'F206 only). (See the Product Selection Guide in
erence of each MCUs' feature set.)

Other features include an on-board VDD monitor, WDT, and clock oscillator. On-board Flash memory can

be reprogrammed in-circuit, and may also be used for non-volatile data storage. Integrated peripherals
can also individually shut down any or all of the peripherals to conserve power. All parts have 256 bytes of
SRAM. Also, an additional 1024 bytes of RAM is available in the 'F206/226/236.

On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debug using the production MCU installed in the final application. This debug system supports inspection
and modification of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt
commands. All analog and digital peripherals are fully functional when emulating using JTAG.

kB of Flash memory.

-

Table 1.1 for a quick ref-

Each MCU is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C) and
is available in the 48-pin TFQP and 32-pin LFQP. The Port I/Os are tolerant for input signals up to 5

V.

Table 1.1. Product Selection Guide

MIPS (Peak)

Flash Memory

C8051F206 25 8 k 1280

C8051F220 25 8 k 256

C8051F221 25 8 k 256

C8051F226 25 8 k 1280

C8051F230 25 8 k 256

C8051F231 25 8 k 256

C8051F236 25 8 k 1280

RAM

SPI

3 3
3 3
3 3
3 3
3 3
3 3
3 3

UART

Timers (16-bit)

Digital Port I/O’s

ADC Resolution (bits)

ADC Max Speed (ksps)

ADC Inputs

Voltage Comparators

3 32 12 100 32 2 48TQFP

3 32 8 100 32 2 48TQFP

3 22 8 100 22 2 32LQFP

3 32 8 100 32 2 48TQFP

3 32 — — — 2 48TQFP

3 22 — — — 2 32LQFP

3 32 — — — 2 48TQFP

Package

Rev. 1.6 11

C8051F2xx

VDD
VDD

GND

GND

TCK
TMS
TDI
TDO

/RST

VDDMONEN

XTAL1
XTAL2

Digital Power

JTAG
Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

NC

NC

NC

Emulation HW

Reset

System Clock

8
0
5
1

C
o

r

e

(Available in
'F206/F226)

8kbyte
FLASH

256 byte

SRAM

SFR Bus

Clock & Reset
Configuration

1024 Byte

XRAM

ADC

Config. &

Control

Port I/O Mode

& Config.

Port 0
Latch

UART

Timer 0

Timer 1

Timer 2

Port 1
Latch

CP0

CP1

Comparator

Config.

Port 2
Latch

SPI

Port Mux

Control

Port 3
Latch

P0.0/TX

P

P
0

M
U
X

P

CP0+

CP0-

CP1+

CP1-

VREF

VREF

1

M
U
X

P
2

M
U
X

A
M

AIN0-AIN31

U

X

CP0

CP1

VDD

SAR
ADC

P0.1/RX

0

P0.2//INT0
P0.3//INT1
P0.4/T0

D

P0.5/T1

r

P0.6/T2

v

P0.7/T2EX

P1.0/CP0+

P

P1.1/CP0-

1

P1.2/CP0
P1.3/CP1+
P1.4/CP1-

D

P1.5/CP1

r

P1.6/SYSCLK

v

P1.7

P2.0/SCK

P

P2.1/MISO

2

P2.2/MOSI
P2.3/NSS
P2.4

D

P2.5

r

P2.6

v

P2.7

P3.0

P

P3.1

3

P3.2
P3.3
P3.4

D

P3.5

r

P3.6

v

P3.7

VREF

Figure 1.1. C8051F206, C8051F220 and C8051F226 Block Diagram (48 TQFP)

12 Rev. 1.6

VDD

GND

TCK
TMS
TDI
TDO

/RST

XTAL1
XTAL2

Digital Power

JTAG
Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

Emulation HW

Reset

System Clock

8
0
5
1

C
o

r

e

8kbyte

FLASH

256 byte

SRAM

SFR Bus

Clock & Reset

Configuration

CP0

CP1

ADC

Config. &

Control

Port I/O Mode

& Config.

Port 0
Latch

UART

Timer 0

Timer 1

Timer 2

Port 1
Latch

CP0

CP1

Comparator

Config.

Port 2
Latch

SPI

Port Mux

Control

Port 3
Latch

VDD

SAR
ADC

CP0+

CP0-

CP1+

CP1-

VREF

C8051F2xx

AIN0-AIN21

P
0

D

r

v

P
1

D

r

v

P
2

D

r

v

VREF

P
0

M
U
X

P
1

M
U
X

P
2

M
U
X

A
M
U
X

P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX

P1.0/CP0+
P1.1/CP0­P1.2/CP0
P1.3/CP1+
P1.4/CP1­P1.5/CP1
P1.6/SYSCLK
P1.7

P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5

VREF

Figure 1.2. C8051F221 Block Diagram (32 LQFP)

Rev. 1.6 13

C8051F2xx

Digital Power

VDD

GND

GND

TCK
TMS
TDI
TDO

/RST

MONEN

XTAL1
XTAL2

NC

NC

NC

NC

NC

JTAG
Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

Emulation HW

Reset

System Clock

8
0
5
1

C
o

r

e

(Available in

8kbyte
FLASH

256 byte

SRAM

SFR Bus

Clock & Reset
Configuration

1024 Byte

XRAM

'F236)

Port I/O Mode

& Config.

Port 0
Latch

UART

Timer 0

Timer 1

Timer 2

Port 1
Latch

CP0

CP1

Comparator

Config.

Port 2
Latch

SPI

Port Mux

Control

Port 3
Latch

P0.0/TX

P

P
0

M
U
X

P

CP0+

CP0-

CP1+

CP1-

1

M
U
X

P

2

M
U
X

CP0

CP1

P0.1/RX

0

P0.2//INT0
P0.3//INT1
P0.4/T0

D

P0.5/T1

r

P0.6/T2

v

P0.7/T2EX

P1.0/CP0+

P

P1.1/CP0-

1

P1.2/CP0
P1.3/CP1+
P1.4/CP1-

D

P1.5/CP1

r

P1.6/SYSCLK

v

P1.7

P2.0/SCK

P

P2.1/MISO

2

P2.2/MOSI
P2.3/NSS
P2.4

D

P2.5

r

P2.6

v

P2.7

P3.0

P

P3.1

3

P3.2
P3.3
P3.4

D

P3.5

r

P3.6

v

P3.7

Figure 1.3. C8051F230 and C8051F236 Block Diagram (48 TQFP)

14 Rev. 1.6

/RST

XTAL1
XTAL2

VDD

GND

TCK
TMS
TDI
TDO

C8051F2xx

Port I/O Mode

Digital Power

Reset

8
0
5
1

C
o

r
e

8kbyte

FLASH

256 byte

SRAM

SFR Bus

Clock & Reset
Configuration

JTAG

Emulation HW

Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

NC

System Clock

& Config.

Port 0

Latch

UART

Timer 0

Timer 1

Timer 2

Port 1

Latch

CP0

CP1

Comparator

Config.

Port 2

Latch

SPI

Port Mux

Control

Port 3

Latch

P0.0/TX

P

P
0

M
U
X

P

CP0+

CP0-

CP1+

CP1-

1

M
U
X

P
2

M
U
X

CP0

CP1

P0.1/RX

0

P0.2//INT0
P0.3//INT1
P0.4/T0

D

P0.5/T1

r

P0.6/T2

v

P0.7/T2EX

P1.0/CP0+

P

P1.1/CP0-

1

P1.2/CP0
P1.3/CP1+
P1.4/CP1-

D

P1.5/CP1

r

P1.6/SYSCLK

v

P1.7

P2.0/SCK

P

P2.1/MISO

2

P2.2/MOSI
P2.3/NSS
P2.4

D

P2.5

r

v

Figure 1.4. C8051F231 Block Diagram (32 LQFP)

1.1. CIP-51TM Microcontroller Core

1.1.1. Fully 8051 Compatible

The C8051F206, C8051F220/1/6 and C8051F230/1/6 utilize Silcon Labs’ proprietary CIP-51 microcontrol-

ler core. The CIP-51 is fully compatible with the MCS-51TM instruction set. Standard 803x/805x assem­blers and compilers can be used to develop software. The core contains the peripherals included with a
standard 8052, including three 16-bit counter/timers, a full-duplex UART, 256 bytes of internal RAM, an
optional 1024 bytes of XRAM, 128 byte Special Function Register (SFR) address space, and four byte­wide I/O Ports.

1.1.2. Improved Throughput

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan­dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12
70% of its instructions in one or two system clock cycles, with only four instructions taking more than four
system clock cycles.

The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to
execute them is as follows:

MHz. By contrast, the CIP-51 core executes

Instructions 26 50 5 14 7 3 1 2 1

Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8

Rev. 1.6 15

C8051F2xx

With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5
shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system
clocks.

25

20

15

MIPS

10

5

Silicon Labs

CIP-51

(25 MHz clk)

Microchip

PIC17C75x

(33 MHz clk)

Philips

80C51

(33 MHz clk)

ADuC812

8051

(16 MHz clk)

Figure 1.5. Comparison of Peak MCU Throughputs

1.1.3. Additional Features

The C8051F206, C8051F220/1/6 and C8051F230/1/6 have several key enhancements both inside and
outside the CIP-51 core to improve overall performance and ease of use in end applications.

The extended interrupt handler provides 22 interrupt sources into the CIP-51 (as opposed to 7 for the stan­dard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. (An interrupt
driven system requires less intervention by the MCU, giving it more effective throughput.) The extra inter
rupt sources are very useful when building multi-tasking, real-time systems.

There are up to six reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing

clock detector, a voltage level detection from Comparator 0, a forced software reset, and an external reset
pin. The

reset to be output on the

(digital 1). The user may disable each reset source except for the

software. The watchdog timer may be permanently enabled in software after a power-on reset during
MCU initialization.

RST pin is bi-directional, accommodating an external reset, or allowing the internally generated

RST pin. The on-board VDD monitor is enabled by pulling the MONEN pin high

V

monitor and Reset Input Pin from

DD

-

The MCU has an internal, stand-alone clock generator that is used by default as the system clock after
reset. If desired, the clock source may be switched "on the fly" to the external oscillator, which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) exter
nal crystal source, while periodically switching to the fast (up to 16MHz) internal oscillator as needed.

16 Rev. 1.6

-

C8051F2xx

System

Clock

Comparator 0

+

-

Missing

Clock

Detector

EN

MCD

Enable

CP0+

CP0- C0RSEF

Figure 1.6. Comparison of Peak MCU Throughputs

WDT

EN

Enable

WDT

PRE

WDT

VDD

Strobe

CIP-51

MonEn

Supply
Monitor

+

-

SWRSF

(Software Reset)

System Reset

Supply

Reset

Timeout

(wired-OR)

Reset
Funnel

/RST

Core

1.2. On-Board Memory

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. An optional 1024 bytes of XRAM is available on the 'F206,
'F226 and 'F236. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
addressing accesses the 128-byte SFR address space. The lower 128 bytes of RAM are accessible via
direct or indirect addressing. The first 32 bytes are addressable as four banks of general purpose regis
ters, and the next 16 bytes can be byte addressable or bit addressable.

The MCU's program memory consists of 8 k + 128 bytes of Flash. This memory may be reprogrammed in­system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from
addresses 0x1E00 to 0x1FFF are reserved for factory use. There is also a user programmable 128-byte
sector at address 0x2000 to 0x207F, which may be useful as a table for storing software constants, nonvol
atile configuration information, or as additional program space. See Figure 1.7 for the MCU system mem­ory map.

-

-

Rev. 1.6 17

C8051F2xx

0x207F

0x2000

0x1FFF

0x1E00

0x1DFF

0x0000

PROGRAM MEMORY

128 Byte ISP FLASH

RESERVED

FLASH

(In-System

Programmable in 512

Byte Sectors)

0xFF

0x80
0x7F

0x30

0x2F

0x20

0x1F

0x00

0x3FF

0x000

DATA MEMORY

Upper 128 RAM

(Indirect Addressing

Only)

(Direct and Indirect

Addressing)

Bit Addressable

General Purpose

Registers

1024 Byte

XRAM

Special Function

Register's

(Direct Addressing Only)

Lower 128 RAM
(Direct and Indirect
Addressing)

Mapped into

External Data Memory

Space

(C8051F226/236/206 only)

Figure 1.7. On-Board Memory Map

1.3. JTAG

The C8051F2xx have on-chip JTAG and debug logic that provide non-intrusive, full speed, in-circuit debug
using the production part installed in the end application using the four-pin JTAG I/F. The C8051F2xxDK is
a development kit with all the hardware and software necessary to develop application code and perform
in-circuit debug with the C8051F2xx. The kit includes software with a developer's studio and debugger, an
integrated 8051 assembler, and an RS-232 to JTAG interface module referred to as the EC. It also has a
target application board with a C8051F2xx installed and large prototyping area, plus the RS-232 and JTAG
cables, and wall-mount power supply. The Development Kit requires a Windows OS (Windows 95 or later)
computer with one available RS-232 serial port. As shown in
to the EC. A six-inch ribbon cable connects the EC to the user's application board, picking up the four

JTAG pins and

20

mA at 2.7–3.6 V. For applications where there is not sufficient power available from the target board,

V

and GND. The EC takes its power from the application board. It requires roughly

DD

the provided power supply can be connected directly to the EC.

This is a vastly superior configuration for developing and debugging embedded applications compared to
standard MCU Emulators, which use on-board "ICE Chips" and target cables and require the MCU in the
application board to be socketed. Silicon Labs' debug environment both increases ease of use, and pre
serves the performance of the precision analog peripherals.

Figure 1.8, the PC is connected via RS-232

-

18 Rev. 1.6

WINDOWS OS

Silicon Labs Integrated

Development Environment

RS-232

JTAG (x4), VDD, GND

SERIAL

ADAPTER

C8051F2xx

VDD GND

C8051

F2XX

TARGET PCB

Figure 1.8. Degub Environment Diagram

1.4. Digital/Analog Configurable I/O

The standard 8051 Ports (0, 1, 2, and 3) are available on the device. The ports behave like standard 8051
ports with a few enhancements.

Each port pin can be configured as either a push-pull or open-drain output. Any input that is configured as
an analog input will have its corresponding weak pull-up turned off.

Digital resources (timers, SPI, UART, system clock, and comparators) are routed to corresponding I/O pins
by configuring the port multiplexer. Port multiplexers are programmed by setting bits in SFR's (please see
Section 14). Any of the 32 external port pins may be configured as either analog inputs or digital I/O (See
Figure 1.9), so effectively, all port pins are dual function.

Rev. 1.6 19

C8051F2xx

T0,T1,T2

Timers

UART

External

INT0 & INT1

Comparators

0 & 1

SYSCLK

SPI

ADC

A
M
U
X

PRTnMX

Registers

Port

0

MUX

Port

1

MUX

Port

2

MUX

PRTnCF &

PnMODE
registers

Port0 I/O Cell

Port1 I/O Cell

Port2 I/O Cell

Port3 I/O Cell

External

pins

P0.0/TX
P0.1/RX
P0.2/INT0
P0.3/INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX

P1.0/CP0+
P1.1/CP0­P1.2/CP0
P1.3/CP1+
P1.4/CP1­P1.5/CP1
P1.6/SYSCLK
P1.7

P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Any port pin may be

configured via software as an

analog input to the ADC

Figure 1.9. Port I/O Functional Block Diagram

1.5. Serial Ports

The C8051F206, C8051F220/1/6 and C8051F230/1/6 include a Full-Duplex UART and SPI Bus. Each of
the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus
requiring very little intervention by the CPU. The serial buses do not have to "share" resources such as
timers, interrupts, or Port I/O, so both of the serial buses may be used simultaneously. (You may use
Timer1, Timer 2, or SYSCLK to generate baud rates for UART).

1.6. Analog to Digital Converter

The C8051F220/1/6 has an on-chip 8-bit SAR ADC and the C8051F206 has a 12-bit SAR ADC with a pro­grammable gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 8-bit with an INL of

V

±1/4 LSB, and or 12-bit accuracy with ±2 LSB. The voltage reference can be the power supply (

an external reference voltage (VREF). Also, the system controller can place the ADC into a power-saving
shutdown mode when not in use. A programmable gain amplifier follows the analog multiplexer. The gain
can be set in software from 0.5 to 16 in powers of 2.

Conversions can be initiated in two ways; a software command or an overflow on Timer 2. This flexibility
allows the start of conversion to be triggered by software events, or convert continuously. A completed
conversion causes an interrupt, or a status bit can be polled in software to determine the end of conver
sion. The resulting 8-bit data word is latched into an SFR upon completion of a conversion.

DD

), or

-

20 Rev. 1.6

C8051F2xx

ADC data is continuously monitored by a programmable window detector, which interrupts the CPU when
data is within the user-programmed window. This allows the ADC to monitor key system voltages in back
ground mode, without the use of CPU resources.

VREF

-

AIN0

AIN1

AIN0-31 are port 0-3

pins -- any external

port pin may be configured as

an analog input

(only 22 input port pins on

'F221)

AIN31

32-to-1

. . .

AMUX

X

Figure 1.10. ADC Diagram

Programmable

Gain Amp

+

-

GND

Control & Data

SFR's

VDD

100ksps

SAR

ADC

SFR Bus

1.7. Comparators

The MCU's have two on-chip voltage comparators. The inputs of the comparators are available at pack­age pins as illustrated in Figure 1.11. Each comparator's hysteresis is software programmable via special
function registers (SFR's). Both voltage level and positive/negative going symmetry can be easily pro­grammed by the user. Additionally, comparator interrupts can be implemented on either rising or falling­edge output transitions. Please see

8.‘Comparators” on page 52 for details.

Rev. 1.6 21

C8051F2xx

P1.2

P1.5

P1.0

P1.1

P1.3

P1.4

CP0

CP1

+

Port1

MUX

CP0

-

+

CP1

-

CP0

CP1

SFR's

(Data

and

Cntrl)

Figure 1.11. Comparator Diagram

CIP-51

and

Interrupt

Handler

22 Rev. 1.6

2. Absolute Maximum Ratings

C8051F2xx

Table 2.1. Absolute Maximum Ratings

Parameter Conditions Min Typ Max Units

Ambient Temperature under Bias –55 — 125 °C

Storage Temperature –65 — 150 °C

Voltage on any Pin (except V
respect to DGND

Voltage on any Port I/O Pin or RST
DGND

Voltage on V

Total Power Dissipation — 1.0 800 W

Maximum Output Current Sunk by any Port pin — — 200 mA

Maximum Output Current Sunk by any other I/O pin — — 25 mA

Maximum Output Current Sourced by any Port pin — — 200 mA

Maximum Output Current Sourced by any other I/O pin — — 25 mA

*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

with respect to DGND –0.3 4.2 V

DD

and Port I/O) with

DD

pins with respect to

*

–0.3 — VDD +

0.3

–0.3 — 5.8 V

V

Rev. 1.6 23

C8051F2xx

3. Global DC Electrical Characteristics

Table 3.1. Global DC Electrical Characteristics

–40 to +85 °C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Analog Supply Voltage

V

supply current with ADC and

DD

1

comparators active, and CPU
active

V

supply current with ADC and

DD

comparators active, and CPU inac­tive (Idle Mode)

V

supply current with ADC and

DD

comparators inactive, and CPU
active

Digital Supply Current with CPU
inactive (Idle Mode)

Digital Supply Current (Stop Mode),
V

monitor enabled

DD

Digital Supply Current (Stop Mode),

monitor disabled

V

DD

Digital Supply RAM Data Retention
Voltage

2.7 3.0 3.6 V

Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz

Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz

Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz

Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz

—13

1.5

300

—9

1.8

275

—12.5

1.0
25

—8.5

1.4
25

—mA

mA

µA

—mA

mA

µA

—mA

mA

µA

—mA

mA

µA

Oscillator not running — 10 — µA

Oscillator not running — 0.1 — µA

—1.5— V

Specified Operating Temperature

–40 — +85 °C

Range

SYSCLK (system clock

frequency)

2

0

—

25 MHz

Tsysl (SYSCLK low time) 18 — — ns

Tsysh (SYSCLK high time) 18 — — ns

Notes:

1. Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.

2. SYSCLK must be at least 32 kHz to enable debugging.

24 Rev. 1.6

C8051F2xx

4. Pinout and Package Definitions

Table 4.1. Pin Definitions

‘F206,

F220,

Name

226,
230,

236

48-Pin 32-Pin

V

DD

11,31 8 Digital Voltage Supply.

GND 5,6,8,

13,32

MONEN 12 D In Monitor Enable (on 48 pin package ONLY). Enables reset volt-

TCK 25 17 D In JTAG Test Clock with internal pull-up.

TMS 26 18 D In JTAG Test-Mode Select with internal pull-up.

TDI 28 20 D In JTAG Test Data Input with internal pull-up. TDI is latched on a

TDO 27 19 D Out JTAG Test Data Output. Data is shifted out on TDO on the falling

XTAL1 9 6 A In Crystal Input. This pin is the return for the internal oscillator cir-

XTAL2 10 7 A Out Crystal Output. This pin is the excitation driver for a crystal or

RST

14 10 D I/O Chip Reset. Open-drain output of internal Voltage Supply moni-

VREF 7 5 A I/O Voltage Reference. When configured as an input, this pin is the

CP0+ 4 4 A In Comparator 0 Non-Inverting Input.

CP0- 3 3 A In Comparator 0 Inverting Input.

CP0 2 2 D Out Comparator 0 Output

CP1+ 1 1 A In Comparator 1 Non-Inverting Input.

CP1- 48 32 A In Comparator 1 Inverting Input.

CP1 47 31 D Out Comparator 1 Output

P0.0/TX 40 28 D I/O

P0.1/RX 39 27 D I/O

P0.2/INT0 38 26 D I/O

‘F221,

231

Type Description

9 Ground. (Note: Pins 5,6, and 8 on the 48-pin package are not

connected (NC), but it is recommended that they be connected to

ground.)

age monitor function when pulled high (logic “1”).

rising edge of TCK.

edge of TCK. TDO output is a tri-state driver.

cuit for a crystal or ceramic resonator. For a precision internal

clock, connect a crystal or ceramic resonator from XTAL1 to

XTAL2. If overdriven by an external CMOS clock, this becomes

the system clock.

ceramic resonator.

tor. Is driven low when VDD is < 2.7V and MONEN=1, or when a

‘1’is written to PORSF. An external source can force a system

reset by driving this pin low.

voltage reference for the ADC. Otherwise, V

will be the refer-

DD

ence. NOTE: this pin is Not Connected (NC) on ‘F230/1/6.

Port0 Bit0. (See the Port I/O Sub-System section for complete

A In

description).

Port0 Bit1. (See the Port I/O Sub-System section for complete

A In

description).

Port0 Bit2. (See the Port I/O Sub-System section for complete

A In

description).

Rev. 1.6 25

C8051F2xx

Table 4.1. Pin Definitions (Continued)

‘F206,

F220,

Name

226,
230,

236

48-Pin 32-Pin

P0.3/INT1 37 25 D I/O

P0.4/T0 36 24 D I/O

P0.5/T1 35 23 D I/O

P0.6/T2 34 22 D I/O

P0.7/T2EX 33 21 D I/O

P1.0/CP0+ 4 4 D I/O

P1.1/CP0- 3 3 D I/O

P1.2/CP0 2 2 D I/O

P1.3/CP1+ 1 1 D I/O

P1.4/CP1- 48 32 D I/O

P1.5/CP1 47 31 D I/O

P1.6/SYSCLK 46 30 D I/O

P1.7 45 29 D I/O

P2.0/SCK 24 16 D I/O

P2.1/MISO 23 15 D I/O

P2.2/MOSI 22 14 D I/O

P2.3/NSS 21 13 D I/O

P2.4 15 11 D I/O

P2.5 16 12 D I/O

P2.6 17 D I/O

‘F221,

231

Type Description

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

A In

Port0 Bit3. (See the Port I/O Sub-System section for complete

description).

Port0 Bit4. (See the Port I/O Sub-System section for complete

description).

Port0 Bit5. (See the Port I/O Sub-System section for complete

description).

Port0 Bit6. (See the Port I/O Sub-System section for complete

description).

Port0 Bit7. (See the Port I/O Sub-System section for complete

description).

Port1 Bit0. (See the Port I/O Sub-System section for complete

description).

Port1 Bit1. (See the Port I/O Sub-System section for complete

description).

Port1 Bit2. (See the Port I/O Sub-System section for complete

description).

Port1 Bit3. (See the Port I/O Sub-System section for complete

description).

Port1 Bit4. (See the Port I/O Sub-System section for complete

description).

Port1 Bit5. (See the Port I/O Sub-System section for complete

description).

Port1 Bit6. (See the Port I/O Sub-System section for complete

description).

Port1 Bit7. (See the Port I/O Sub-System section for complete

description).

Port2 Bit0. (See the Port I/O Sub-System section for complete

description).

Port2 Bit1. (See the Port I/O Sub-System section for complete

description).

Port2 Bit2. (See the Port I/O Sub-System section for complete

description).

Port2 Bit3. (See the Port I/O Sub-System section for complete

description).

Port2 Bit4. (See the Port I/O Sub-System section for complete

description).

Port2 Bit5. (See the Port I/O Sub-System section for complete

description).

Port2 Bit6. (See the Port I/O Sub-System section for complete

description).

26 Rev. 1.6

Table 4.1. Pin Definitions (Continued)

‘F206,

F220,

Name

226,
230,

236

48-Pin 32-Pin

P2.7 18 D I/O

P3.0 44 D I/O

P3.1 43 D I/O

P3.2 42 D I/O

P3.3 41 D I/O

P3.4 30 D I/O

P3.5 29 D I/O

P3.6 20 D I/O

P3.7 19 D I/O

‘F221,

231

Type Description

A In

A In

A In

A In

A In

A In

A In

A In

A In

C8051F2xx

Port2 Bit7. (See the Port I/O Sub-System section for complete

description).

Port3 Bit0. (See the Port I/O Sub-System section for complete

description).

Port3 Bit1. (See the Port I/O Sub-System section for complete

description).

Port3 Bit2. (See the Port I/O Sub-System section for complete

description).

Port3 Bit3. (See the Port I/O Sub-System section for complete

description).

Port3 Bit4. (See the Port I/O Sub-System section for complete

description).

Port3 Bit5. (See the Port I/O Sub-System section for complete

description).

Port3 Bit6. (See the Port I/O Sub-System section for complete

description).

Port3 Bit7. (See the Port I/O Sub-System section for complete

description).

Rev. 1.6 27

C8051F2xx

P1.4/CP1-

48

P0.2/INT0

P3.1

P3.2

P3.0

44

43

P3.3

42

41

P0.1/RX

P0.0/TX

40

39

46

P1.6/SYSCLK

P1.7

45

P1.5/CP1

47

P0.3/INT1

38

37

P1.3/CP1+

P1.2/CP0

P1.1/CP0-

P1.0/CP0+

NC

NC

VREF*

NC

XTAL1

XTAL2

VDD

MONEN

1

2

3

4

5

6

7

8

9

10

11

12

C8051F220/6
C8051F230/6

C8051F206

*Pin 7 is a No Connect on

36

35

34

33

32

31

30

29

28

27

26

25

P0.4/T0

P0.5/T1

P0.6/T2

P0.7/T2EX

GND

VDD

P3.4

P3.5

TDI

TDO

TMS

TCK

'F230/6

13

14

15

16

17

18

19

20

21

22

23

24

P2.5

P2.4

/RST

GND

P2.6

P3.7

P2.7

P3.6

P2.3/NSS

P2.2/MOSI

P2.0/SCK

P2.1/MISO

Figure 4.1. TQFP-48 Pin Diagram

28 Rev. 1.6

P1.4/CP1-

32

P1.5/CP1

31

P1.6/SYSCLK

30

P1.7

29

P0.0/TX

28

P0.1/RX

27

P0.2/INT0

26

C8051F2xx

P0.3/INT1

25

P1.3/CP1+

P1.2/CP0

P1.1/CP0-

P1.0/CP0+

VREF*

XTAL1

XTAL2

VDD

1

2

3

4

5

C8051F221
C8051F231

6

7

8

*Pin 5 is a No Connect

24

23

22

21

20

19

18

17

P0.4/T0

P0.5/T1

P0.6/T2

P0.7/T2EX

TDI

TDO

TM
S

TCK

(NC) on 'F231

9

10

11

12

13

14

15

16

P2.5

GND

P2.4

RESTB

P2.3/NSS

P2.2/MOSI

P2.0/SCK

P2.1/MISO

Figure 4.2. LQFP-32 Pin Diagram

Rev. 1.6 29

C8051F2xx

48

PIN 1

IDENTIFIER

A2

D

D1

E1

E

1

e

A

A

A1

A2

b

D

D1

e

E

MIN

(mm)

-

0.05

0.95

0.17

-

-

-

-

NOM

(mm)

-

-

1.00

0.22

9.00

7.00

0.50

9.00

MAX

(mm)

1.20

0.15

1.05

0.27

-

-

-

-

A1

E1

b

Figure 4.3. TQFP-48 Package Drawing

-

7.00

-

30 Rev. 1.6

D

C8051F2xx

32

PIN 1

IDENTIFIER

A2

A

A1

A2

b

D

D1

e

E

E1

MIN

(mm)

0.05

1.35

0.30

D1

E1

1

E

A

A1

NOM
(mm)

-

1.40

0.37

-

9.00

-

7.00

-

0.80

-

9.00

-

7.00

MAX

(mm)

-

1.60

-

0.15

1.45

0.45

-

-

-

-

-

eb

Figure 4.4. LQFP-32 Package Drawing

Rev. 1.6 31

C8051F2xx

5. ADC (8-Bit, C8051F220/1/6 Only)

Description

The ADC subsystem for the C8051F220/1/6 consists of configurable analog multiplexer (AMUX), a pro­grammable gain amplifier (PGA), and a 100ksps, 8-bit successive-approximation-register ADC with inte­grated track-and-hold and programmable window detector (see Figure 5.1). The AMUX, PGA, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Func­tion Register's shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, SFR Definition 5.3) is set to 1. The ADC sub­system is in low power shutdown when this bit is 0.

ADC0LTHADC0GTH

AIN0-31 are port 0-3

pins -- any external

port pin may be configured as an

analog input

16

VDD VREF

Dig

Comp

ADWINT

AIN0

32-to-1

. . .

AIN31

AMUX

X

AMXEN

PRTSL0

PRTSL1

AMX0SL

GND

PINSL2

+

-

PINSL0

PINSL1

Figure 5.1. 8-Bit ADC Functional Block Diagram

5.1. Analog Multiplexer and PGA

ADCEN

VDD

GND

ADCSC0

ADCSC1

ADCSC2

ADC0CF

SAR

ADC

AMPGN0

AMPGN1

AMPGN2

VDD

8-Bit

ADCEN

ADCTM

ADCINT

ADC0CN

SYSCLK

REF

ADC0H

8

ADLJST

ADWINT

ADSTM0

ADSTM1

ADBUSY

8

Conversion Start

T2 OV

A

D

B

U

S

w

)

(

Y

Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See

SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0-1), and then the pin in the selected port (bits PINSL0-2) to be the analog
input.

The table in ?? shows AMUX functionality by channel for each possible configuration. The PGA amplifies
the AMUX output signal by an amount determined by the states of the AMPGN2-0 bits in the ADC Config
uration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed for gains of 0.5, 1,
2, 4, 8 or 16. It defaults to a gain of 1 on reset.

32 Rev. 1.6

-

C8051F2xx

5.2. ADC Modes of Operation

The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the
system clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of
1,2,4,8, or 16 are supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust
conversion speed to accommodate different system clock speeds.

A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:

1. Writing a 1 to the ADBUSY bit of ADC0CN;

2. A Timer 2 overflow (i.e., timed continuous conversions).

Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed "on­demand". During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete.
The falling edge of ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the
ADC0CN register. Note: When conversions are performed "on-demand", the ADCINT flag, not ADBUSY,
should be polled to determine when the conversion has completed. Converted data is available in the ADC
data word register, ADC0H.

The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC
input is continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of
two different low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in
ADC0CN):

1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;

2. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.

Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.

A. ADC Timing for External Trigger Source

CNVSTR

(ADSTM[1:0]=10)

12345678910111213141516

SAR Clocks

ADCTM=1

ADCTM=0

Low Power or

Convert

Track Convert Low Power Mode

Track Or Convert

Convert Track

B. ADC Timing for Internal Trigger Sources

Timer2, Timer3 Overflow;

Write 1 to ADBUSY

(ADSTM[1:0]=00, 01, 11)

SAR Clocks

ADCTM=1

SAR Clocks

Low Power or

1234567891011121314151617 18 19

Convert

Track Convert Low Power Mode

12345678910111213141516

ADCTM=0

Track or Convert

Convert Track

Figure 5.2. 12-Bit ADC Track and Conversion Example Timing

Rev. 1.6 33

C8051F2xx

SFR Definition 5.1. AMX0SL: AMUX Channel Select

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - AMXEN PRTSL1 PRTSL0 PINSL2 PINSL1 PINSL0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits 7–6: UNUSED. Read = 00b; Write = don't care
Bit 5: AMXEN enable

0: AMXEN disabled and port pins are unavailable for analog use.
1: AMXEN enabled to use/select port pins for analog use.

Bits 4–3: PRTSL1–0: Port Select Bits*.

00: Port0 select to configure pin for analog input from this port.
01: Port1 select to configure pin for analog input from this port.
10: Port2 select to configure pin for analog input from this port.
11: Port3 select to configure pin for analog input from this port.

Bits 2–0:PINSL2–0: Pin Select Bits

000: Pin 0 of selected port (above) to be used for analog input.
001: Pin 1 of selected port (above) to be used for analog input.
010: Pin 2 of selected port (above) to be used for analog input.
011: Pin 3 of selected port (above) to be used for analog input.
100: Pin 4 of selected port (above) to be used for analog input.
101: Pin 5 of selected port (above) to be used for analog input.
110: Pin 6 of selected port (above) to be used for analog input.
111: Pin 7 of selected port (above) to be used for analog input.

00000000

0xBB

* Selecting a port for analog input does NOT default all pins of that port as analog input. After select-

ing a port for analog input, a pin must be selected using pin select bits (PINSL2–0). For example,
after setting the AMXEN to ‘1’, setting PRTSL1–0 to “11”, and setting PINSL2–0 to “100” P3.4 is
configured as analog input. All other Port 3 pins remain as GPIO pins. Also note that in order to use
a port pin as analog input, its input mode should be set to

analog. Please see section 14.2.

34 Rev. 1.6

C8051F2xx

SFR Definition 5.2. ADC0CF: ADC Configuration Register

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ADCSC2 ADCSC1 ADCSC0 - - AMPGN2 AMPGN1 AMPGN0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits7–5: ADCSC2–0: ADC SAR Conversion Clock Period Bits

000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks

NOTE: SAR conversion clock should be less than or equal to 2MHz.

Bits4–3: UNUSED. Read = 00b; Write = don’t care
Bits2–0: AMPGN2–0: ADC Internal Amplifier Gain

000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5

01100000

0xBC

Rev. 1.6 35

C8051F2xx

SFR Definition 5.3. ADC0CN: ADC Control (C8051F220/1/6 and C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ADCEN ADCTM ADCINT ADBUSY ADSTM1 ADSTM0 ADWINT ADLJST

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable) 0xE8

Bit7: ADCEN: ADC Enable Bit

0: ADC Disabled. ADC is in low power shutdown.
1: ADC Enabled. ADC is active and ready for data conversions.

Bit6: ADCTM: ADC Track Mode Bit

0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits

ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: RESERVED
10: RESERVED
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks

Bit5: ADCINT: ADC Conversion Complete Interrupt Flag (cleared by software).

0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion

Bit4: ADBUSY: ADC Busy Bit

Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b

Bits3–2: ADSTM1–0: ADC Start of Conversion Mode Bits

00: ADC conversion started upon a write of 1 to ADBUSY
01: RESERVED
10: RESERVED
11: ADC conversions initiated on overflows of Timer 2

Bit1: ADWINT: ADC Window Compare Interrupt Flag

0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred

Bit0: ADLJST: ADC Left Justify Data Bit (Used on C8051F206 only)

0: Data in ADC0H:ADC0L registers are right justified.
1: Data in ADC0H:ADC0L registers are left justified.

00000000

36 Rev. 1.6

C8051F2xx

SFR Definition 5.4. ADC0H: ADC Data Word (‘F220/1/6 and ‘F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

MSB LSB

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits7–0: ADC Data Word Bits

EXAMPLE: ADC Data Word Conversion Map

AIN – GND(Volts) ADC0H

REF x (255/256) 0xFF

REF x ½ 0x80

REF x (127/256) 0x7F

00x00

5.3. ADC Programmable Window Detector

00000000

0xBF

The ADC programmable window detector is very useful in many applications. It continuously compares
the ADC output to user-programmed limits and notifies the system when an out-of-band condition is
detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth
while delivering faster system response times. The window detector interrupt flag (ADWINT in ADC0CN)
can also be used in polled mode. The high and low bytes of the reference words are loaded into the ADC
Greater-Than and ADC Less-Than registers (ADC0GTH and ADC0LTH).

SFR Definition 5.5. ADC0GTH: ADC Greater-Than Data (‘F220/1/6 and ‘F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC5

Bits7–0:
The high byte of the ADC Greater-Than Data Word.

SFR Definition 5.6. ADC0LTH: ADC Less-Than Data Byte (‘F220/1/6 and ‘F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC7

Bits7–0:
The high byte of the ADC Less-Than Data Word.

Rev. 1.6 37

C8051F2xx

Input Voltage

(Analog Input - GND)

REF x (255/256)

REF x (32/256)

REF x (16/256)

0

ADC Data

Word

0xFF

0x21

0x20

0x1F

0x11

0x10

0x0F

0x00

ADWINT
not affected

ADC0LTH

ADWINT=1

ADC0GTH

ADWINT
not affected

Given:
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH = 0x20, ADC0GTH = 0x10.

An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x20 and > 0x10.

Input Voltage

(Analog Input - GND)

REF x (255/256)

REF x (32/256)

REF x (16/256)

0

ADC Data

Word

0xFF

0x21

0x20

0x1F

0x11

0x10

0x0F

0x00

ADWINT=1

ADC0GTH

ADWINT
not affected

ADC0LTH

ADWINT=1

Given:

AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH = 0x10, ADC0GTH = 0x20.

An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x10 or > 0x20.

Figure 5.3. 8-Bit ADC Window Interrupt Examples

38 Rev. 1.6

C8051F2xx

Table 5.1. 8-Bit ADC Electrical Characteristics

VDD = 3.0 V, VREF = 2.40 V, PGA Gain = 1, –40 to +85 ×C unless otherwise specified.

Parameter Conditions Min Typ Max Units

DC Accuracy

Resolution — 8 — bits

Integral Nonlinearity — — ±1/2 LSB

Differential Nonlinearity Guaranteed Monotonic — — ±1/2 LSB

Offset Error ±2 — ±1/2 LSB

Gain Error ±2 — ±1/2 LSB

Offset Temperature Coefficient ±0.25 — ppm/°C

Dynamic Performance (10 kHz sine-wave input, 0 to –1 dB of full scale, 100 ksps)

Signal-to-Noise Plus Distortion 49.5 — — dB

Total Harmonic Distortion

Spurious-Free Dynamic Range — –65 — dB

Conversion Rate

Conversion Time in SAR Clocks 16 — — clocks

SAR Clock Frequency — 2.5 MHz

Track/Hold Acquisition Time 1.5 — — µs

Throughput Rate — — 100 ksps

Analog Inputs

Input Voltage Range 0 —

Input Capacitance — 10 — pF

Power Specifications

Power Supply Current Operating Mode, 100 ksps — 0.45 1.0 mA

Power Supply Current in Shutdown — 0.1 1 µA

Power Supply Rejection — ±0.3 — mV/V

Up to the 5th harmonic

–60 –65 — dB

V

DD

V

Rev. 1.6 39

C8051F2xx

6. ADC (12-Bit, C8051F206 Only)

Description

The ADC subsystem for the C8051F206 consists of configurable analog multiplexer (AMUX), a program­mable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector (see Figure 6.1). The AMUX, PGA, Data Conversion
Modes, and Window Detector are all configurable under software control via the Special Function Regis
ter's shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the
ADCEN bit in the ADC Control register (ADC0CN, Figure 6.5) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0.

-

AIN0-31 are port 0-3

pins -- any external

port pin may be configured

as an analog input

AIN0

AIN31

. . .

32-to-1

AMUX

X

AMXEN

PRTSL0

PRTSL1

AMX0SL

GND

PINSL2

ADC0GTLADC0GTH

VDD

ADCEN

VDD

ADC0LTLADC0LTH

VDD VREF

SYSCLK

24

REF

ADC0L

12

Dig

Comp

ADWINT

12-Bit

+

SAR

-

ADC

GND

PINSL0

PINSL1

ADCSC1

ADCSC2

ADC0CF

ADCSC0

AMPGN2

ADCEN

ADCTM

ADCINT

ADSTM1

AMPGN0

AMPGN1

ADBUSY

ADC0CN

12

ADC0H

Conversion Start

T2 OV

A

D

B

U

S

w

)

Y

(

ADLJST

ADWINT

ADSTM0

Figure 6.1. 12-Bit ADC Functional Block Diagram

6.1. Analog Multiplexer and PGA

Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See
port is to be used (bits PRTSL0–1), and then the pin in the selected port (bits PINSL0–2) to be the analog
input.

The PGA amplifies the AMUX output signal by an amount determined by the states of the AMPGN2–0 bits
in the ADC Configuration register, ADC0CF (
for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain of 1 on reset.

40 Rev. 1.6

SFR Definition 5.1). When the AMUX is enabled, the user selects which

SFR Definition 5.2). The PGA can be software-programmed

C8051F2xx

e

6.2. ADC Modes of Operation

The ADC has a maximum conversion speed of 100 ksps. The ADC conversion clock is derived from the
system clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of 1,
2, 4, 8, or 16 are supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust
conversion speed to accommodate different system clock speeds.

A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:

1. Writing a 1 to the ADBUSY bit of ADC0CN;

2. A Timer 2 overflow (i.e. timed continuous conversions).

Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed "on­demand". During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete.
The falling edge of ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the
ADC0CN register. Note: When conversions are performed "on-demand", the ADCINT flag, not ADBUSY,
should be polled to determine when the conversion has completed. Converted data is available in the ADC
data word register, ADC0H.

The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC
input is continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of
two different low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in
ADC0CN):

1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;

2. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.

Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.

A. ADC Timing for External Trigger Sourc

CNVSTR

(ADSTM[1:0]=10)

SAR Clocks

ADCTM=1

ADCTM=0

Timer2, Timer3 Overflow;

Write 1 to ADBUSY

(ADSTM[1:0]=00, 01, 11)

SAR Clocks

ADCTM=1 Track Convert Low Power Mode

SAR Clocks

Low Power or

Convert

Track Or Convert

B. ADC Timing for Internal Trigger Sources

1234567891011121314151617 18 19

Low Power or

Convert

12345678910111213141516

12345678910111213141516

Track Convert Low Power Mode

Convert Track

ADCTM=0

Track or Convert

Convert Track

Figure 6.2. 12-Bit ADC Track and Conversion Example Timing

Rev. 1.6 41

C8051F2xx

SFR Definition 6.1. AMX0SL: AMUX Channel Select

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - AMXEN PRTSL1 PRTSL0 PINSL2 PINSL1 PINSL0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits 7–6: UNUSED. Read = 00b; Write = don’t care
Bit 5: AMXEN enable

0: AMXEN disabled and port pins are unavailable for analog use.
1: AMXEN enabled to use/select port pins for analog use.

Bits 4–3: PRTSL1–0: Port Select Bits*.

00: Port0 select to configure pin for analog input from this port.
01: Port1 select to configure pin for analog input from this port.

10: Port2 select to configure pin for analog input from this port.

11: Port3 select to configure pin for analog input from this port.

Bits 2–0:PINSL2–0: Pin Select Bits

000: Pin 0 of selected port (above) to be used for analog input.
001: Pin 1 of selected port (above) to be used for analog input.
010: Pin 2 of selected port (above) to be used for analog input.
011: Pin 3 of selected port (above) to be used for analog input.
100: Pin 4 of selected port (above) to be used for analog input.
101: Pin 5 of selected port (above) to be used for analog input.
110: Pin 6 of selected port (above) to be used for analog input.
111: Pin 7 of selected port (above) to be used for analog input.

00000000

0xBB

* Selecting a port for analog input does NOT default all pins of that port as analog input. After select-

ing a port for analog input, a pin must be selected using pin select bits (PINSL2–0). For example,
after setting the AMXEN to ‘1’, setting PRTSL1–0 to “11”, and setting PINSL2–0 to “100” P3.4 is
configured as analog input. All other Port 3 pins remain as GPIO pins. Also note that in order to use
a port pin as analog input, its input mode should be set to

analog. Please see section 14.2.

42 Rev. 1.6

C8051F2xx

SFR Definition 6.2. ADC0CF: ADC Configuration (‘F220/1/6 and ‘F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ADCSC2 ADCSC1 ADCSC0 - - AMPGN2 AMPGN1 AMPGN0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits7–5: ADCSC2–0: ADC SAR Conversion Clock Period Bits

000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks

NOTE: SAR conversion clock should be less than or equal to 2MHz.
Bits4–3: UNUSED. Read = 00b; Write = don't care
Bits2–0: AMPGN2–0: ADC Internal Amplifier Gain

000: Gain = 1

001: Gain = 2

010: Gain = 4

011: Gain = 8

10x: Gain = 16

1x: Gain = 0.5

01100000

0xBC

Rev. 1.6 43

C8051F2xx

SFR Definition 6.3. ADC0CN: ADC Control (‘F220/1/6 and ‘F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ADCEN ADCTM ADCINT ADBUSY ADSTM1 ADSTM0 ADWINT ADLJST

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable) 0xE8

Bit7: ADCEN: ADC Enable Bit

0: ADC Disabled. ADC is in low power shutdown.

1: ADC Enabled. ADC is active and ready for data conversions.
Bit6: ADCTM: ADC Track Mode Bit

0: When the ADC is enabled, tracking is continuous unless a conversion is in process

1: Tracking Defined by ADSTM1–0 bits

ADSTM1–0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: RESERVED
10: RESERVED
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks

Bit5: ADCINT: ADC Conversion Complete Interrupt Flag (cleared by software).

0: ADC has not completed a data conversion since the last time this flag was cleared

1: ADC has completed a data conversion
Bit4: ADBUSY: ADC Busy Bit

Read

0: ADC Conversion complete or no valid data has been converted since a reset. The falling

edge of ADBUSY generates an interrupt when enabled.

1: ADC Busy converting data

Write

0: No effect

1: Starts ADC Conversion if ADSTM1–0 = 00b
Bits3–2: ADSTM1–0: ADC Start of Conversion Mode Bits

00: ADC conversion started upon a write of 1 to ADBUSY

01: RESERVED

10: RESERVED

11: ADC conversions initiated on overflows of Timer 2
Bit1: ADWINT: ADC Window Compare Interrupt Flag

0: ADC Window Comparison Data match has not occurred

1: ADC Window Comparison Data match occurred
Bit0: ADLJST: ADC Left Justify Data Bit

0: Data in ADC0H:ADC0L registers are right justified.

1: Data in ADC0H:ADC0L registers are left justified.

00000000

44 Rev. 1.6

C8051F2xx

SFR Definition 6.4. ADC0H: ADC Data Word MSB (C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xBF

Bits7–0: ADC Data Word Bits

For ADLJST = 1: Upper 8-bits of the 12-bit ADC Data Word.

For ADLJST = 0: Bits7–4 are the sign extension of Bit3. Bits 3–0 are the upper 4-bits of the

12-bit ADC Data Word.

SFR Definition 6.5. ADC0L: ADC Data Word LSB (C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xBE

Bits7–0: ADC Data Word Bits

For ADLJST = 1: Bits7–4 are the lower 4-bits of the 12-bit ADC Data Word. Bits3–0 will

always read 0.

For ADLJST = 0: Bits7–0 are the lower 8-bits of the 12-bit ADC Data Word.

NOTE: Resulting 12-bit ADC Data Word appears in the ADC Data Word Registers as follows:
ADC0H[3:0]:ADC0L[7:0], if ADLJST = 0
(ADC0H[7:4] will be sign extension of ADC0H.3 if a differential reading, otherwise = 0000b)

ADC0H[7:0]:ADC0L[7:4], if ADLJST = 1
(ADC0L[3:0] = 0000b)

EXAMPLE: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode

(AMX0CF=0x00, AMX0SL=0x00)

AIN0 – AGND (Volts)

ADC0H:ADC0L

(ADLJST = 0)

ADC0H:ADC0L

(ADLJST = 1)

REF x (4095/4096) 0x0FFF 0xFFF0

REF x ½ 0x0800 0x8000

REF x (2047/4096) 0x07FF 0x7FF0

0 0x0000 0x0000

Rev. 1.6 45

C8051F2xx

6.3. ADC Programmable Window Detector

The ADC programmable window detector is very useful in many applications. It continuously compares
the ADC output to user-programmed limits and notifies the system when an out-of-band condition is
detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth
while delivering faster system response times. The window detector interrupt flag (ADWINT in ADC0CN)
can also be used in polled mode. The high and low bytes of the reference words are loaded into the ADC
Greater-Than and ADC Less-Than registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL).
Figure 6.3 and Figure 6.4 show example comparisons for reference. Notice that the window detector flag
can be asserted when the measured data is inside or outside the user-programmed limits, depending on
the programming of the ADC0GTx and ADC0LTx registers.

SFR Definition 6.6. ADC0GTH: ADC Greater-Than Data High Byte (C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC5

Bits7–0:
The high byte of the ADC Greater-Than Data Word.

SFR Definition 6.7. ADC0GTL: ADC Greater-Than Data Low Byte (C8051F206)

R/WR/WR/WR/WR/WR/WR/WR/WReset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC4

Bits7–0:
The low byte of the ADC Greater-Than Data Word.

Definition: ADC Greater-Than Data Word = ADC0GTH:ADC0GTL

SFR Definition 6.8. ADC0LTH: ADC Less-Than Data High Byte (C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC4

Bits7–0:
The high byte of the ADC Less-Than Data Word.

46 Rev. 1.6

C8051F2xx

SFR Definition 6.9. ADC0LTL: ADC Less-Than Data Low Byte (C8051F206)

R/WR/WR/WR/WR/WR/WR/WR/WReset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC4

Bits7–0:
These bits are the low byte of the ADC Less-Than Data Word.

Definition:
ADC Less-Than Data Word = ADC0LTH:ADC0LTL

Input Voltage

(Analog Input - GND)

REF x (4095/4096)

REF x (512/4096)

REF x (256/4096)

0

Given:

AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0200,
ADC0GTH:ADC0GTL = 0x0100.

An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x0200 and >
0x0100.

ADC Data

Word

0x0FFF

0x0201

0x0200

0x01FF

0x0101

0x0100

0x00FF

0x0000

(Analog Input - GND)

ADWINT
not affected

ADC0LTH:ADC0LTL

ADWINT=1

ADC0GTH:ADC0GTL

ADWINT
not affected

Given:

AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0x0200.

An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x0100 or >
0x0200.

Input Voltage

REF x (4095/4096)

REF x (512/4096)

REF x (256/4096)

0

ADC Data

Word

0x0FFF

0x0201

0x0200

0x01FF

0x0101

0x0100

0x00FF

0x0000

ADWINT=1

ADC0GTH:ADC0GTL

ADWINT
not affected

ADC0LTH:ADC0LTL

ADWINT=1

Figure 6.3. 12-Bit ADC Window Interrupt Examples, Right Justified Data

Rev. 1.6 47

C8051F2xx

Input Voltage

(AD0 - AGND)

REF x (4095/4096)

REF x (512/4096)

REF x (256/4096)

0

Given:

AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x2000,
ADC0GTH:ADC0GTL = 0x1000.

ADC Data

Word

0xFFF0

0x2010

0x2000

0x1FF0

0x1010

0x1000

0x0FF0

0x0000

ADWINT
not affected

ADC0LTH:ADC0LTL

ADWINT=1

ADC0GTH:ADC0GTL

ADWINT
not affected

Given:

AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0x2000.

Input Voltage

(AD0 - AGND)

REF x (4095/4096)

REF x (512/4096)

REF x (256/4096)

0

ADC Data

Word

0xFFF0

0x2010

0x2000

0x1FF0

0x1010

0x1000

0x0FF0

0x0000

ADWINT=1

ADC0GTH:ADC0GTL

ADWINT
not affected

ADC0LTH:ADC0LTL

ADWINT=1

An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x2000 and >
0x1000.

Figure 6.4. 12-Bit ADC Window Interrupt Examples, Left Justified Data

An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x1000 or >
0x2000.

48 Rev. 1.6

C8051F2xx

Table 6.1. 12-Bit ADC Electrical Characteristics (C8015F206 only)

VDD = 3.0 V, VREF = 2.40 V (REFBE=0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.

Parameter Conditions Min Typ Max Units

DC Accuracy

Resolution 12 bits

Integral Nonlinearity — ±1 ±2 LSB

Differential Nonlinearity Guaranteed Monotonic — — ±2 LSB

Offset Error ±20 ±5 — LSB

Full Scale Error Differential mode — — –20±10 LSB

Offset Temperature Coefficient — ±0.25 — ppm/°C

Dynamic Performance (10 kHz sine-wave input, 0 to –1 dB of full scale, 100 ksps)

Signal-to-Noise Plus Distortion 63 66 — dB

Total Harmonic Distortion

Spurious-Free Dynamic Range 60 76 — dB

Conversion Rate

Conversion Time in SAR Clocks 16 — — clocks

SAR Clock Frequency — — 2.0 MHz

Track/Hold Acquisition Time 1.5 — — µs

Throughput Rate — — 100 ksps

Analog Inputs

Voltage Conversion Range 0 — VREF V

Input Voltage Any pin (in Analog Input Mode) GND —

Input Capacitance — 10 — pF

Power Specifications

Power Supply Current
(VDD supplied to ADC)

Power Supply Rejection — ±0.3 — mV/V

Up to the 5th harmonic

Operating Mode, 100 ksps — 0.45 1.0 mA

–60 –72 — dB

V

DD

V

Rev. 1.6 49

C8051F2xx

7. Voltage Reference (C8051F206/220/221/226)

The voltage reference circuit selects between an externally connected reference and the power supply
voltage (V

An external reference can be connected to the VREF pin and selected by setting the REF0CN special
function register per

may also be selected using REF0CN per SFR Definition 7.1. The electrical specifications for the Voltage
Reference are given in Ta bl e 7.1.

). (See Figure 7.1).

DD

Figure 7.1. The external reference supply must be between VDD – 0.3 V and 1 V. V

Vdd

Vref (external)

DD

To ADC Ref

REF0CN[1:0]

2

Set REF0CN to:

00: Use external Vref
11: Use Vdd

Figure 7.1. Voltage Reference Functional Block Diagram

SFR Definition 7.1. REF0CN: Reference Control

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - - - - - REFSL1 REFSL0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits7–2: UNUSED. Read = 00000b; Write = don't care

Bit1–0: REFSL1– REFSL0: Voltage reference selection.

Bits control which reference is selected.

00: External VREF source is selected.

01: Reserved.

10: Reserved.

11: V

selected as VREF source.

DD

00000000

0xD1

50 Rev. 1.6

Table 7.1. Reference Electrical Characteristics

VDD = 3.0 V, Temperature –40 to +85 ×C

C8051F2xx

External Reference ([REFSL1: REFSL0] = 00), V

Input Voltage Range 1.00 —

Input Current — 0.1 10 µA

Input Resistance 100 — — MΩ

REF

= 2.4 V)

Min Typ Max Units

(VDD) – 0.3 V

V

Rev. 1.6 51

C8051F2xx

8. Comparators

The MCU has two on-board voltage comparators as shown in Figure 8.1. The inputs of each Comparator
are available at the package pins. The output of each comparator is optionally available at port1 by config­uring (see Section 14). When assigned to package pins, each comparator output can be programmed to
operate in open drain or push-pull modes (see section 14.2).

The hysteresis of each comparator is software-programmable via its respective Comparator Control Regis­ter (CPT0CN, CPT1CN). The user can program both the amount of hysteresis voltage (referred to the
input voltage) and the positive-going and negative-going symmetry of this hysteresis around the threshold
voltage. The output of the comparator can be polled in software, or can be used as an interrupt source.
Each comparator can be individually enabled or disabled (shutdown). When disabled, the comparator out
put (if assigned to a Port I/O pin via the Port1 MUX) defaults to the logic low state and its interrupt capabil­ity is suspended. Comparator inputs can be externally driven from –0.25 V to (VDD) + 0.25 V without

damage or upset.

The Comparator 0 hysteresis is programmed using bits 3–0 in the Comparator 0 Control Register CPT0CN
(shown in
the CP0HYN bits. As shown in Figure 8.2, settings of 10, 4 or 2 mV of negative hysteresis can be pro­grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.

SFR Definition 8.1). The amount of negative hysteresis voltage is determined by the settings of

-

Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter­rupt enable and priority control, see Section 9.4). The CP0FIF flag is set upon a Comparator 0 falling-edge
interrupt, and the CP0RIF flag is set upon the Comparator 0 rising-edge interrupt. Once set, these bits
remain set until cleared by the user software. The Output State of Comparator 0 can be obtained at any
time by reading the CP0OUT bit. Comparator 0 is enabled by setting the CP0EN bit, and is disabled by
clearing this bit. Note there is a 20
Comparator 0 can also be programmed as a reset source. For details, see Section 11. The operation of
Comparator 1 is identical to that of Comparator 0, except the Comparator 1 is controlled by the CPT1CN
Register (
plete electrical specifications for the Comparators are given in Ta bl e 8.1.

SFR Definition 8.2). Also, Comparator 1 can not be programmed as a reset source. The com-

mS power on time between setting CP0EN and the output stabilizing.

52 Rev. 1.6

P1.0/CP0+

P1.1/CP0-

P1.3/CP1+

P1.4/CP1-

CPT0CN

CPT1CN

CP0EN

CP0OUT

CP0RIF

CP0FIF

CP0HYP1

CP0HYP0

CP0HYN1

CP0HYN0

CP1EN

CP1OUT

CP1RIF

CP1FIF

CP1HYP1

CP1HYP0

CP1HYN1

CP1HYN0

C8051F2xx

AV+

Reset

Decision

Tree

External Pin

MUX

MUX

P1.2/CP0

External Pin

P1.5/CP1

+

Synchronizer

-

AGND

AV+

+

Synchronizer

-

AGND

PORT1

Interrupt

Handler

PORT1

Interrupt

Handler

Figure 8.1. Comparator Functional Block Diagram

Rev. 1.6 53

C8051F2xx

VIN+

VIN-

Positive Hyst eresis Volt age

(Programmed with CP0HYSP Bits)

INPUTS

OUTPUT

CP0+

CP0-

+

CP0

_

CIRCUIT CONFIGURATION

VIN-

VIN+

VOH

VOL

Positive Hysteresis

Disabled

Maximum

Positive Hysteresis

OUT

Negative Hysteresis

Disabled

Negative Hysteresis Voltage

(Programmed by CP0HYSN Bits)

Maximum

Negative Hysteresis

Figure 8.2. Comparator Hysteresis Plot

54 Rev. 1.6

C8051F2xx

SFR Definition 8.1. CPT0CN: Comparator 0 Control

R/W R R/W R/W R/W R/W R/W R/W Reset Value

CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: CP0EN: Comparator 0 Enable Bit

0: Comparator 0 Disabled.

1: Comparator 0 Enabled.
Bit6: CP0OUT: Comparator 0 Output State Flag

0: Voltage on CP0+ < CP0–

1: Voltage on CP0+ > CP0–
Bit5: CP0RIF: Comparator 0 Rising-Edge Interrupt Flag

0: No Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared

1: Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared
Bit4: CP0FIF: Comparator 0 Falling-Edge Interrupt Flag

0: No Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared

1: Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared
Bit3–2: CP0HYP1–0: Comparator 0 Positive Hysteresis Control Bits

00: Positive Hysteresis Disabled

01: Positive Hysteresis = 2 mV

10: Positive Hysteresis = 4 mV

11: Positive Hysteresis = 10 mV
Bit1–0: CP0HYN1–0: Comparator 0 Negative Hysteresis Control Bits

00: Negative Hysteresis Disabled

01: Negative Hysteresis = 2 mV

10: Negative Hysteresis = 4 mV

11: Negative Hysteresis = 10 mV

00000000

0x9E

Rev. 1.6 55

C8051F2xx

SFR Definition 8.2. CPT1CN: Comparator 1 Control

R/W R R/W R/W R/W R/W R/W R/W Reset Value

CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: CP1EN: Comparator 1 Enable Bit

0: Comparator 1 Disabled.

1: Comparator 1 Enabled.
Bit6: CP1OUT: Comparator 1 Output State Flag

0: Voltage on CP1+ < CP1–

1: Voltage on CP1+ > CP1–
Bit5: CP1RIF: Comparator 1 Rising-Edge Interrupt Flag

0: No Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared

1: Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared
Bit4: CP1FIF: Comparator 1 Falling-Edge Interrupt Flag

0: No Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared

1: Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared
Bit3–2: CP1HYP1–0: Comparator 1 Positive Hysteresis Control Bits

00: Positive Hysteresis Disabled

01: Positive Hysteresis = 2 mV

10: Positive Hysteresis = 4 mV

11: Positive Hysteresis = 10 mV
Bit1–0: CP1HYN1–0: Comparator 1 Negative Hysteresis Control Bits

00: Negative Hysteresis Disabled

01: Negative Hysteresis = 2 mV

10: Negative Hysteresis = 4 mV

11: Negative Hysteresis = 10 mV

00000000

0x9F

56 Rev. 1.6

C8051F2xx

Table 8.1. Comparator Electrical Characteristics

VDD = 3.0 V, –40 to +85 ×C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Response Time1* (CP+) – (CP–) = 100 mV — 4 — µs

Response Time2* (CP+) – (CP–) = 10 mV — 12 — µs

Common Mode Rejection
Ratio

Positive Hysteresis1 CPnHYP1-0 = 00 — 0 1 mV

Positive Hysteresis2 CPnHYP1-0 = 01 2 4.5 7 mV

Positive Hysteresis3 CPnHYP1-0 = 10 4 9 15 mV

Positive Hysteresis4 CPnHYP1-0 = 11 10 17 25 mV

Negative Hysteresis1 CPnHYN1-0 = 00 — 0 1 mV

Negative Hysteresis2 CPnHYN1-0 = 01 2 4.5 7 mV

Negative Hysteresis3 CPnHYN1-0 = 10 4 9 15 mV

Negative Hysteresis4 CPnHYN1-0 = 11 10 17 25 mV

Inverting or Non-inverting
Input Voltage Range

Input Capacitance — 7 — pF

Input Bias Current –5 0.001 +5 nA

Input Offset Voltage –10 — +10 mV

POWER SUPPLY

— 1.5 4 mV/V

–0.25 —

(VDD)

+ 0.25

V

Power-up Time CPnEN from 0 to 1 — 20 — µs

Power Supply Rejection — 0.1 1 mV/V

Supply Current

*Note: CPnHYP1-0 = CPnHYN1-0 = 00.

Operating Mode
(each comparator) at DC

Rev. 1.6 57

— 1.5 4 µA

C8051F2xx

9. CIP-51 Microcontroller

General Description

The MCU’s system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the

MCS-51
ware. The MCU has a superset of all the peripherals included with a standard 8051. Included are three
16-bit counter/timers (see description in Section 17), a full-duplex UART (see description in Section 16),
256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section 9.3),
and four byte-wide I/O Ports (see description in Section 14). The CIP-51 also includes on-chip debug
hardware (see description in Section 18), and interfaces directly with the MCU’s analog and digital sub
systems providing a complete data acquisition or control-system solution in a single integrated circuit.

Features

The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see
The CIP-51 includes the following features:

TM

instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-

Figure 9.1 for a block diagram).

-

• Fully Compatible with MCS-51 Instruction Set

• 25 MIPS Peak Throughput with 25 MHz Clock

• 0 to 25 MHz Clock Frequency

• 256 Bytes of Internal RAM

• Optional 1024 Bytes of XRAM

• 8 kB Flash Program Memory

ACCUMULATOR

DATA BUS

PROGRAM COUNTER (PC)

CONTROL

RESET

CLOCK

STOP

IDLE

D8

PSW

D8

DATA POINTER

PC INCREMENTER

PRGM. ADDRESS REG.

LOGIC

POWER CONTROL

D8

TMP1 TMP2

ALU

D8

BUFFER

PIPELINE

REGISTER

• Four Byte-Wide I/O Ports

• Extended Interrupt Handler

• Reset Input

• Power Management Modes

• On-chip Debug Circuitry

• Program and Data Memory Security

DATA BUS

D8

DATA BUS

D8

D8

DATA BUS

D8

B REGISTER

ADDRESS

REGISTER

D8

INTERFACE

D8

A16

INTERFACE

D8

INTERRUPT
INTERFACE

D8

D8

SRAM

D8

SFR

BUS

MEMORY

D8

STACK POINTER

SRAM

(256 X 8)

D8

SFR_ADDRESS

SFR_CONTROL

SFR_WRITE_DATA

SFR_READ_DATA

MEM_ADDRESS

MEM_CONTROL

MEM_WRITE_DATA

MEM_READ_DATA

SYSTEM_IRQs

EMULATION_IRQ

Figure 9.1. CIP-51 Block Diagram

58 Rev. 1.6

C8051F2xx

Performance

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan­dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.

With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. The CIP-51 has
a total of 109 instructions. The number of instructions versus the system clock cycles required to execute
them is as follows:

Instructions 26 50 5 14 7 3 1 2 1

Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8

Programming and Debugging Support

A JTAG-based serial interface is provided for in-system programming of the Flash program memory and
communication with on-chip debug support logic. The re-programmable Flash can also be read and
changed a single byte at a time by the application software using the MOVC and MOVX instructions. This
feature allows program memory to be used for non-volatile data storage as well as updating program code
under software control.

The on-chip debug support circuitry facilitates full speed in-circuit debugging, allowing the setting of hard­ware breakpoints and watchpoints, starting, stopping and single stepping through program execution
(including interrupt service routines), examination of the program’s call stack, and reading/writing the con
tents of registers and memory. This method of on-chip debugging is completely non-intrusive and non­invasive, requiring no RAM, Stack, timers, or other on-chip resources.

The CIP-51 is supported by development tools from Silicon Laboratories and third party vendors. Silicon
Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger
and programmer. The IDE’s debugger and programmer interface to the CIP-51 via its JTAG interface to
provide fast and efficient in-system device programming and debugging. Third party macro assemblers
and C compilers are also available.

-

Rev. 1.6 59

C8051F2xx

9.1. Instruction Set

The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc­tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan
dard 8051.

9.1.1. Instruction and CPU Timing

In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.

Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken.
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.

9.1.2. MOVX Instruction and Program Memory

Table 9.1 is the

-

The MOVX instruction is typically used to access external data memory. The CIP-51 does not support
external data or program memory. In the CIP-51, the MOVX instruction accesses the on-chip program
memory space implemented as re-programmable Flash memory and the 1024 bytes of XRAM (optionally
available on ‘F226/236 and ‘F206). This feature provides a mechanism for the CIP-51 to update program
code and use the program memory space for non-volatile data storage. Refer to Section 10 (Flash Mem
ory) and Section 11 (External RAM) for further details.

Table 9.1. CIP-51 Instruction Set Summary

Mnemonic Description Bytes

Arithmetic Operations

ADD A,Rn Add register to A 1 1

ADD A,direct Add direct byte to A 2 2

ADD A,@Ri Add indirect RAM to A 1 2

ADD A,#data Add immediate to A 2 2

ADDC A,Rn Add register to A with carry 1 1

ADDC A,direct Add direct byte to A with carry 2 2

ADDC A,@Ri Add indirect RAM to A with carry 1 2

ADDC A,#data Add immediate to A with carry 2 2

SUBB A,Rn Subtract register from A with borrow 1 1

SUBB A,direct Subtract direct byte from A with borrow 2 2

SUBB A,@Ri Subtract indirect RAM from A with borrow 1 2

SUBB A,#data Subtract immediate from A with borrow 2 2

INC A Increment A 1 1

INC Rn Increment register 1 1

INC direct Increment direct byte 2 2

Clock

Cycles

-

60 Rev. 1.6

C8051F2xx

Table 9.1. CIP-51 Instruction Set Summary (Continued)

Mnemonic Description Bytes

INC @Ri Increment indirect RAM 1 2

DEC A Decrement A 1 1

DEC Rn Decrement register 1 1

DEC direct Decrement direct byte 2 2

DEC @Ri Decrement indirect RAM 1 2

INC DPTR Increment Data Pointer 1 1

MUL AB Multiply A and B 1 4

DIV AB Divide A by B 1 8

DA A Decimal Adjust A 1 1

Logical Operations

ANL A,Rn AND Register to A 1 1

ANL A,direct AND direct byte to A 2 2

ANL A,@Ri AND indirect RAM to A 1 2

ANL A,#data AND immediate to A 2 2

ANL direct,A AND A to direct byte 2 2

ANL direct,#data AND immediate to direct byte 3 3

ORL A,Rn OR Register to A 1 1

ORL A,direct OR direct byte to A 2 2

ORL A,@Ri OR indirect RAM to A 1 2

ORL A,#data OR immediate to A 2 2

ORL direct,A OR A to direct byte 2 2

ORL direct,#data OR immediate to direct byte 3 3

XRL A,Rn Exclusive-OR Register to A 1 1

XRL A,direct Exclusive-OR direct byte to A 2 2

XRL A,@Ri Exclusive-OR indirect RAM to A 1 2

XRL A,#data Exclusive-OR immediate to A 2 2

XRL direct,A Exclusive-OR A to direct byte 2 2

XRL direct,#data Exclusive-OR immediate to direct byte 3 3

CLR A Clear A 1 1

CPL A Complement A 1 1

RL A Rotate A left 1 1

RLC A Rotate A left through carry 1 1

RR A Rotate A right 1 1

RRC A Rotate A right through carry 1 1

SWAP A Swap nibbles of A 1 1

Data Transfer

MOV A,Rn Move register to A 1 1

MOV A,direct Move direct byte to A 2 2

MOV A,@Ri Move indirect RAM to A 1 2

Clock

Cycles

Rev. 1.6 61

C8051F2xx

Table 9.1. CIP-51 Instruction Set Summary (Continued)

Mnemonic Description Bytes

MOV A,#data Move immediate to A 2 2

MOV Rn,A Move A to register 1 1

MOV Rn,direct Move direct byte to register 2 2

MOV Rn,#data Move immediate to register 2 2

MOV direct,A Move A to direct byte 2 2

MOV direct,Rn Move register to direct byte 2 2

MOV direct,direct Move direct byte to direct 3 3

MOV direct,@Ri Move indirect RAM to direct byte 2 2

MOV direct,#data Move immediate to direct byte 3 3

MOV @Ri,A Move A to indirect RAM 1 2

MOV @Ri,direct Move direct byte to indirect RAM 2 2

MOV @Ri,#data Move immediate to indirect RAM 2 2

MOV DPTR,#data16 Load data pointer with 16-bit constant 3 3

MOVC A,@A+DPTR Move code byte relative DPTR to A 1 3

MOVC A,@A+PC Move code byte relative PC to A 1 3

MOVX A,@Ri Move external data (8-bit address) to A 1 3

MOVX @Ri,A Move A to external data (8-bit address) 1 3

MOVX A,@DPTR Move external data (16-bit address) to A 1 3

MOVX @DPTR,A Move A to external data (16-bit address) 1 3

PUSH direct Push direct byte onto stack 2 2

POP direct Pop direct byte from stack 2 2

XCH A,Rn Exchange register with A 1 1

XCH A,direct Exchange direct byte with A 2 2

XCH A,@Ri Exchange indirect RAM with A 1 2

XCHD A,@Ri Exchange low nibble of indirect RAM with A 1 2

Boolean Manipulation

CLR C Clear carry 1 1

CLR bit Clear direct bit 2 2

SETB C Set carry 1 1

SETB bit Set direct bit 2 2

CPL C Complement carry 1 1

CPL bit Complement direct bit 2 2

ANL C,bit AND direct bit to carry 2 2

ANL C,/bit AND complement of direct bit to carry 2 2

ORL C,bit OR direct bit to carry 2 2

ORL C,/bit OR complement of direct bit to carry 2 2

MOV C,bit Move direct bit to carry 2 2

MOV bit,C Move carry to direct bit 2 2

JC rel Jump if carry is set 2 2/3

Clock

Cycles

62 Rev. 1.6

C8051F2xx

Table 9.1. CIP-51 Instruction Set Summary (Continued)

Mnemonic Description Bytes

JNC rel Jump if carry not set 2 2/3

JB bit,rel Jump if direct bit is set 3 3/4

JNB bit,rel Jump if direct bit is not set 3 3/4

JBC bit,rel Jump if direct bit is set and clear bit 3 3/4

Program Branching

ACALL addr11 Absolute subroutine call 2 3

LCALL addr16 Long subroutine call 3 4

RET Return from subroutine 1 5

RETI Return from interrupt 1 5

AJMP addr11 Absolute jump 2 3

LJMP addr16 Long jump 3 4

SJMP rel Short jump (relative address) 2 3

JMP @A+DPTR Jump indirect relative to DPTR 1 3

JZ rel Jump if A equals zero 2 2/3

JNZ rel Jump if A does not equal zero 2 2/3

CJNE A,direct,rel Compare direct byte to A and jump if not equal 3 3/4

CJNE A,#data,rel Compare immediate to A and jump if not equal 3 3/4

CJNE Rn,#data,rel Compare immediate to register and jump if not equal 3 3/4

CJNE @Ri,#data,rel Compare immediate to indirect and jump if not equal 3 4/5

DJNZ Rn,rel Decrement register and jump if not zero 2 2/3

DJNZ direct,rel Decrement direct byte and jump if not zero 3 3/4

NOP No operation 1 1

Clock

Cycles

Rev. 1.6 63

C8051F2xx

Notes on Registers, Operands and Addressing Modes:

Rn - Register R0–R7 of the currently selected register bank.

@Ri - Data RAM location addressed indirectly through register R0–R1

rel - 8-bit, signed (two’s compliment) offset relative to the first byte of the following instruction. Used by

SJMP and all conditional jumps.

direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–

0x7F) or an SFR (0x80–0xFF).

#data - 8-bit constant

#data 16 - 16-bit constant

bit - Direct-addressed bit in Data RAM or SFR.

addr 11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the

same 2

kB page of program memory as the first byte of the following instruction.

addr 16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere

within the 8

There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.

kB program memory space.

64 Rev. 1.6

C8051F2xx

9.2. Memory Organization

The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. There are 256 bytes of internal data
memory and 8
memory organization is shown in

9.2.1. Program Memory

The CIP-51 has a 8 kB program memory space. The MCU implements 8320 bytes of this program mem­ory space as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses
0x0000 to 0x207F. Note: 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for factory use and
are not available for user program storage.

Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro
vides a mechanism for the CIP-51 to update program code and use the program memory space for non­volatile data storage. Refer to Section 10 Flash Memory for further details.

9.2.2. Data Memory

kB of internal program memory address space implemented within the CIP-51. The CIP-51

Figure 9.2.

-

The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers and memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct bit addressing mode.

The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F will
access the upper 128 bytes of data memory.
CIP-51.

Additionally, the C8051F206/226/236 feature 1024 Bytes of RAM mapped in the external data memory
space. All address locations may be accessed using the MOVX instruction. (Please see Section 11).

Figure 9.2 illustrates the data memory organization of the

Rev. 1.6 65

C8051F2xx

0x207F

0x2000

0x1FFF

0x1E00

0x1DFF

0x0000

PROGRAM MEMORY

128 Byte ISP FLASH

RESERVED

FLASH

(In-System

Programmable in 512

Byte Sectors)

0xFF

0x80

0x7F

0x30

0x2F

0x20

0x1F

0x00

0x3FF

0x000

DATA MEMORY

Upper 128 RAM

(Indirect Addressing

Only)

(Direct and Indirect

Addressing)

Bit Addressable

General Purpose

Registers

1024 Byte

XRAM

Special Function

Register's

(Direct Addressing Only)

Lower 128 RAM
(Direct and Indirect
Addressing)

Mapped into

External Data Memory

Space

(C8051F226/236/206 only)

Figure 9.2. Memory Map

9.2.3. General Purpose Registers

The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen­eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in
fast context switching when entering subroutines and interrupt service routines. Indirect addressing
modes use registers R0 and R1 as index registers.

9.2.4. Bit Addressable Locations

In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access
by the type of instruction used (bit source or destination operands as opposed to a byte source or destina
tion).

The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:

MOV C, 22h.3

SFR Definition 9.4). This allows

-

moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the user Carry flag.

66 Rev. 1.6

C8051F2xx

9.2.5. Stack

A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig­nated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.

The MCU also has built-in hardware for a stack record. The stack record is a 32-bit shift register, where
each Push or increment SP pushes one record bit onto the register, and each Call pushes two record bits
onto the register. (A Pop or decrement SP pops one record bit, and a Return pops two record bits, also.)
The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can
notify the emulator software even with the MCU running full-speed debug.

Rev. 1.6 67

C8051F2xx

9.3. Special Function Registers

The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set.
mented in the CIP-51 System Controller.

The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit­addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indetermi
nate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in
Ta bl e 9.3, for a detailed description of each register.

Table 9.2. Special Function Register Memory Map

F8 SPI0CN WDTCN

F0 B P0MODE P1MODE P2MODE

E8

ADC0CN

1

P3MODE

E0 ACC PRT0MX PRT1MX PRT2MX EIE1 EIE2
D8
D0 PSW REF0CN
C8 T2CON RCAP2L RCAP2H TL2 TH2

C0

B8 IP

AMX0SL1ADC0CF

ADC0GTL4ADC0GTH1ADC0LTL4ADC0LTH

B0 P3 OSCXCN OSCICN FLSCL FLACL

A8 IE SWCINT

A0 P2 PRT0CF PRT1CF PRT2CF PRT3CF

98 SCON SBUF SPI0CFG SPI0DAT SPI0CKR CPT0CN CPT1CN

90 P1

88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL

80 P0 SP DPL DPH PCON

0(8)

Bit Addressable

1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)

2

1

Ta bl e 9.3 lists the SFRs imple-

EIP1 EIP2

RSTSRC

ADC0L

4

ADC0H

EMI0CN

1

3

-

1

Notes:

1. C8051F230/1/6 Do not have these registers.

2. C8051F221/231 Does not have this register (32 pin package).

3. On the C8051F206 and C8051F226/236 only.

4. On the C8051F206 only (12-bit ADC)

68 Rev. 1.6

C8051F2xx

Table 9.3. Special Function Registers

SFR’s are listed in alphabetical order.

Address Register Description Page No.

0xE0 ACC Accumulator 73

0xBC ADC0CF ADC Configuration 35

0xE8 ADC0CN ADC Control 36

0xC5

0xC4

0xBF

0xBE

0xC7

0xCE

ADC0GTH

ADC0GTL

ADC0H

ADC0L

ADC0LTH

ADC0LTL

0xBB AMX0SL ADC MUX Channel Selection 34

0xF0 B B Register 73

0x8E CKCON Clock Control 131

0x9E CPT0CN Comparator 0 Control 55

0x9F CPT1CN Comparator 1 Control 56

0x83 DPH Data Pointer (High Byte) 71

0x82 DPL Data Pointer (Low Byte) 71

0xE6 EIE1 Extended Interrupt Enable 1 79

0xE7 EIE2 Extended Interrupt Enable 2 80

0xF6 EIP1 External Interrupt Priority 1 81

0xF7 EIP2 External Interrupt Priority 2 82

0xAF

EMI0CN

0xB7 FLACL Flash Memory Read Limit 89

0xB6 FLSCL Flash Memory Timing Prescaler 89

0xA8 IE Interrupt Enable 77

0xB8 IP Interrupt Priority Control 78

0xB2 OSCICN Internal Oscillator Control 98

0xB1 OSCXCN External Oscillator Control 99

0x80 P0 Port 0 Latch 105

0x90 P1 Port 1 Latch 106

0xA0 P2 Port 2 Latch 107

0xB0 P3 Port 3 Latch 108

0xF1 P0MODE Port0 Digital/Analog Output Mode 106

0xF2 P1MODE Port1 Digital/Analog Output Mode 107

0xF3 P2MODE Port2 Digital/Analog Output Mode 108

0xF4

P3MODE

0x87 PCON Power Control 84

1

4

1

4

1

4

3

2

ADC Greater-Than Data Word (High Byte) 37

ADC Greater-Than Data Word (Low Byte) 46

ADC Data Word (High Byte) 37

ADC Data Word (Low Byte) 45

ADC Less-Than Data Word (High Byte) 46

ADC Less-Than Data Word (Low Byte) 47

External Memory Interface Control 90

Port3 Digital/Analog Output Mode 109

Rev. 1.6 69

C8051F2xx

Table 9.3. Special Function Registers (Continued)

SFR’s are listed in alphabetical order.

Address Register Description Page No.

0xA4 PRT0CF Port 0 Configuration 105

0xA5 PRT1CF Port 1 Configuration 106

0xA6 PRT2CF Port 2 Configuration 107

0xA7 PRT3CF Port 3 Configuration 108

0xE1 PRT0MX Port 0 Multiplexer I/O Configuration 103

0xE2 PRT1MX Port 1 Multiplexer I/O Configuration 104

0xE3 PRT2MX Port 2 Multiplexer I/O Configuration 104

0x8F PSCTL Program Store RW Control 88

0xD0 PSW Program Status Word 72

0xCB RCAP2H Counter/Timer 2 Capture (High Byte) 138

0xCA RCAP2L Counter/Timer 2 Capture (Low Byte) 138

0xD1 REF0CN Voltage Reference Control Register 50

0xEF RSTSRC Reset Source Register 95

0x99 SBUF Serial Data Buffer (UART) 123

0x98 SCON Serial Port Control (UART) 124

0x81 SP Stack Pointer 71

0x9A SPI0CFG Serial Peripheral Interface Configuration 114

0x9D SPI0CKR SPI Clock Rate 116

0xF8 SPI0CN SPI Bus Control 115

0x9B SPI0DAT SPI Port 1Data 116

0xAD SWCINT Software Controlled Interrupt Register 75

0xC8 T2CON Counter/Timer 2 Control 137

0x88 TCON Counter/Timer Control 129

0x8C TH0 Counter/Timer 0 Data Word (High Byte) 132

0x8D TH1 Counter/Timer 1 Data Word (High Byte) 132

0xCD TH2 Counter/Timer 2 Data Word (High Byte) 138

0x8A TL0 Counter/Timer 0 Data Word (Low Byte) 132

0x8B TL1 Counter/Timer 1 Data Word (Low Byte) 132

0xCC TL2 Counter/Timer 2 Data Word (Low Byte) 138

0x89 TMOD Counter/Timer Mode 130

0xFF WDTCN Watchdog Timer Control 94

0x84–86, 0x91–97, 0x9C, 0xA1–A3, 0xA9–
AC, 0xAE, 0xB3–B5, 0xB9–BA, 0xBD–
BE,0xC0–C4, 0xC6,0xCE–CF,0xD2–
DF,0xE9–EE,0xF5,0xF9–FE

Reserved

Notes:

1. C8051F230/1/6 Do not have these registers.

2. C8051F221/231 Does not have this register (32 pin package).

3. On the C8051F206 and C8051F226/236 only.

4. On the C8051F206 only (12-bit ADC)

70 Rev. 1.6

C8051F2xx

9.3.1. Register Descriptions

Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved
bits should be set to logic 0. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic 0, selecting the feature’s default state. Detailed descrip
tions of the remaining SFRs are included in the sections of the datasheet associated with their correspond­ing system function.

SFR Definition 9.1. SP: Stack Pointer

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0x81

Bits 7–0: SP: Stack Pointer.

The stack pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.

-

SFR Definition 9.2. DPL: Data Pointer Low Byte

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits 7–0: DPL: Data Pointer Low.

The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.

SFR Definition 9.3. DPH: Data Pointer High Byte

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits 7–0: DPH: Data Pointer High.

The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.

0x81

0x81

Rev. 1.6 71

C8051F2xx

SFR Definition 9.4. PSW: Program Status Word

R/W R/W R/W R/W R/W R/W R/W R Reset Value

CY AC F0 RS1 RS0 OV F1 PARITY

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit

addressable)

Bit7: CY: Carry Flag.

This bit is set when the last arithmetic operation results in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.

Bit6: AC: Auxiliary Carry Flag.

This bit is set when the last arithmetic operation results in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.

00000000

0xD0

Bit5: F0: User Flag 0.

This is a bit-addressable, general-purpose flag for use under software control.

Bits4–3: RS1–RS0: Register Bank Select.

These bits select which register bank is used during register accesses.

RS1 RS0 Register Bank Address

0 0 0 0x00–0x07

0 1 1 0x08–0x0F

1 0 2 0x10–0x17

1 1 3 0x18–0x1F

Note: Any instruction which changes the RS1–RS0 bits must not be immediately followed by
the “MOV Rn, A” instruction.

Bit2: OV: Overflow Flag.

This bit is set to 1 under the following circumstances:

•An ADD, ADDC, or SUBB instruction causes a sign-change overflow.

•A MUL instruction results in an overflow (result is greater than 255).

•A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.

Bit1: F1: User Flag 1.

This is a bit-addressable, general purpose flag for use under software control.

Bit0: PARITY: Parity Flag.

This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.

72 Rev. 1.6

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SFR Definition 9.5. ACC: Accumulator

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable) 0xE0

Bits 7–0: ACC: Accumulator

This register is the accumulator for arithmetic operations.

SFR Definition 9.6. B: B Register

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable) 0xF0

00000000

00000000

Bits 7–0: B: B Register

This register serves as a second accumulator for certain arithmetic operations.

Rev. 1.6 73

C8051F2xx

9.4. Interrupt Handler

The CIP-51 includes an extended interrupt system supporting up to 22 interrupt sources with two priority
levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated inter
rupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt con­dition, the associated interrupt-pending flag is set to logic 1.

If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an
RETI instruction, which returns program execution to the next instruction that would have been executed if
the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by
the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1
regardless of the interrupt's enable/disable state.)

Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE2). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 dis
ables all interrupt sources regardless of the individual interrupt-enable settings.

Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.

-

-

-

9.4.1. MCU Interrupt Sources and Vectors

The MCU allocates 9 interrupt sources to on-chip peripherals. Software can simulate an interrupt by set­ting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be
generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. The
MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in
Ta bl e 9.4. Refer to the datasheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).

9.4.2. External Interrupts

The two external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or
active-low edge-sensitive inputs depending on the setting of IT0 (TCON.0) and IT1 (TCON.2). IE0
(TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts,
respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin.
The external interrupt source must hold the input active until the interrupt request is recognized. It must
then deactivate the interrupt request before execution of the ISR completes or another interrupt request
will be generated.

9.4.3. Software Controlled Interrupts

The C8051F2xx family of devices features four Software Controlled Interrupts controlled by flags located in
the Software Controlled Interrupt Flag Register (SWCINT). See
written to a Software-Controlled Interrupt Flag, the CIP-51 will jump to an associated interrupt service vec­tor (see Ta bl e 9.4, “Interrupt Summary,” on page 75). These interrupt flags must be cleared by software.

SFR Definition 9.7. When a logic '1' is

74 Rev. 1.6

C8051F2xx

SFR Definition 9.7. SWCINT: Software Controlled Interrupt Register

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

SCI3 SCI2 SCI1 SCI0 - - - -

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: SCI3: Software Controlled Interrupt 3 Bit.

If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI3 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.

Bit6: SCI2: Software Controlled Interrupt 2 Bit.

If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI2 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.

Bit5: SCI1: Software Controlled Interrupt 1 Bit.

If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI1 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.

Bit4: SCI0: Software Controlled Interrupt 0 Bit.

If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI0 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.

Bits3–0: UNUSED. Read = 0000b, Write = don't care.

00000000

0xAD

Table 9.4. Interrupt Summary

Interrupt Source

Reset 0x0000 To p None Always enabled

External Interrupt 0 (/INT0) 0x0003 0 IE0 (TCON.1) EX0 (IE.0)

Timer 0 Overflow 0x000B 1 TF0 (TCON.5) ET0 (IE.1)

External Interrupt 1 (/INT1) 0x0013 2 IE1 (TCON.3) EX1 (IE.2)

Timer 1 Overflow 0x001B 3 TF1 (TCON.7) ET1 (IE.3)

Serial Port (UART) 0x0023 4

Timer 2 Overflow (or EXF2) 0x002B 5 TF2 (T2CON.7) ET2 (IE.5)

Serial Peripheral Interface 0x0033 6

ADC0 Window Comparison 0x0043 8 ADWINT (ADC0CN.2) EWADC0 (EIE1.2)

Comparator 0 Falling Edge 0x0053 10 CP0FIF (CPT0CN.4) ECP0F (EIE1.4)

Comparator 0 Rising Edge 0x005B 11 CP0RIF (CPT0CN.5) ECP0R (EIE1.5)

Comparator 1 Falling Edge 0x0063 12 CP1FIF (CPT1CN.4) ECP1F (EIE1.6)

Comparator 1 Rising Edge 0x006B 13 CP1RIF (CPT1CN.5) ECP1R (EIE1.7)

Interrupt

Vector

Priority

Order

Interrupt-Pending Flag Enable

RI (SCON.0)
TI (SCON.1)

SPIF (SPI0STA.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)

ES (IE.4)

ESPI0 (EIE1.0)

Rev. 1.6 75

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Table 9.4. Interrupt Summary (Continued)

Interrupt Source

ADC0 End of Conversion 0x007B 15 ADCINT (ADC0CN.5) EADC0 (EIE2.1)

Software Controlled Interrupt 0 0x0083 16 SCI0 (SWCINT.4) ESCI0 (EIE2.2)

Software Controlled Interrupt 1 0x008B 17 SCI1 (SWCINT.5) ESCI1 (EIE2.3)

Software Controlled Interrupt 2 0x0093 18 SCI2 (SWCINT.6) ESCI2 (EIE2.4)

Software Controlled Interrupt 3 0x009B 19 SCI3 (SWCINT.7) ESCI3 (EIE2.5)

Unused Interrupt Location 0x00A3 20 None Reserved (EIE2.6)

External Crystal OSC Ready 0x00AB 21 XTLVLD (OSCXCN.7) EXVLD (EIE2.7)

Interrupt

Vector

Priority

Order

Interrupt-Pending Flag Enable

9.4.4. Interrupt Priorities

Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior­ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP–EIP2) used to configure its
priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate.

9.4.5. Interrupt Latency

Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. NOTE: If a
Flash write or erase is performed, the MCU is stalled during the operation and interrupts will not be ser
viced until the operation is complete. If the CPU is executing an ISR for an interrupt with equal or higher
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and fol
lowing instruction.

-

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9.4.6. Interrupt Register Descriptions

The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to
the datasheet section associated with a particular on-chip peripheral for information regarding valid inter
rupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).

SFR Definition 9.8. IE: Interrupt Enable

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

EA - ET2 ES ET1 EX1 ET0 EX0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable) 0xA8

Bit7: EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-

tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.

Bit6: UNUSED. Read = 0, Write = don't care.

00000000

-

Bit5: ET2: Enable Timer 2 Interrupt.

This bit sets the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7)

Bit4: ES: Enable Serial Port (UART) Interrupt.

This bit sets the masking of the Serial Port (UART) interrupt.
0: Disable all UART interrupts.
1: Enable interrupt requests generated by the R1 flag (SCON.0) or T1 flag (SCON.1).

Bit3: ET1: Enable Timer 1 Interrupt.

This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupts.
1: Enable interrupt requests generated by the TF1 flag (TCON.7).

Bit2: EX1: Enable External Interrupt 1.

This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.

Bit1: ET0: Enable Timer 0 Interrupt.

This bit sets the masking of the Timer 0 interrupt.

0: Disable all Timer 0 interrupts.

1: Enable interrupt requests generated by the TF0 flag (TCON.5).

Bit0: EX0: Enable External Interrupt 0.

This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.

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C8051F2xx

SFR Definition 9.9. IP: Interrupt Priority

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - PT2 PS PT1 PX1 PT0 PX0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable) 0xB8

Bits7–6: UNUSED. Read = 00b, Write = don't care.

Bit5: PT2 Timer 2 Interrupt Priority Control.

This bit sets the priority of the Timer 2 interrupts.
0: Timer 2 interrupts set to low priority level.
1: Timer 2 interrupts set to high priority level.

Bit4: PS: Serial Port (UART) Interrupt Priority Control.

This bit sets the priority of the Serial Port (UART) interrupts.
0: UART interrupts set to low priority level.
1: UART interrupts set to high priority level.

Bit3: PT1: Timer 1 Interrupt Priority Control.

This bit sets the priority of the Timer 1 interrupts.
0: Timer 1 interrupts set to low priority level.
1: Timer 1 interrupts set to high priority level.

00000000

Bit2: PX1: External Interrupt 1 Priority Control.

This bit sets the priority of the External Interrupt 1 interrupts.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.

Bit1: PT0: Timer 0 Interrupt Priority Control.

This bit sets the priority of the Timer 0 interrupts.
0: Timer 0 interrupts set to low priority level.
1: Timer 0 interrupt set to high priority level.

Bit0: PX0: External Interrupt 0 Priority Control.

This bit sets the priority of the External Interrupt 0 interrupts.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.

78 Rev. 1.6

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SFR Definition 9.10. EIE1: Extended Interrupt Enable 1

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ECP1R ECP1F ECP0R ECP0F - EWADC0 - ESPI0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: ECP1R: Enable Comparator 1 (CP1) Rising Edge Interrupt.

This bit sets the masking of the CP1 interrupt.
0: Disable CP1 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP1RIF flag (CPT1CN.3).

Bit6: ECP1F: Enable Comparator 1 (CP1) Falling Edge Interrupt.

This bit sets the masking of the CP1 interrupt.
0: Disable CP1 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP1FIF flag (CPT1CN.4).

Bit5: ECP0R: Enable Comparator 0 (CP0) Rising Edge Interrupt.

This bit sets the masking of the CP0 interrupt.
0: Disable CP0 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP0RIF flag (CPT0CN.3).

00000000

0xE6

Bit4: ECP0F: Enable Comparator 0 (CP0) Falling Edge Interrupt.

This bit sets the masking of the CP0 interrupt.
0: Disable CP0 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP0FIF flag (CPT0CN.4).

Bit3: Reserved. Read = 0, Write = don't care.

Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt.

This bit sets the masking of ADC0 window compare interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable Interrupt requests generated by ADC0 Window Comparisons.

Bit1: Reserved. Read = 0, Write = don't care.

Bit0: ESPI0: Enable Serial Peripheral Interface 0 Interrupt.

This bit sets the masking of SPI0 interrupt.
0: Disable all SPI0 interrupts.
1: Enable Interrupt requests generated by SPI0.

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C8051F2xx

SFR Definition 9.11. EIE2: Extended Interrupt Enable 2

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

EXVLD - ESCI3 ESCI2 ESCI1 ESCI0 EADC0 -

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt.

This bit sets the masking of the XTLVLD interrupt.
0: Disable all XTLVLD interrupts.
1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7)

Bit6: Reserved. Must write 0. Reads 0.

Bit5: ESCI3: Enable Software Controlled Interrupt 3.

This bit sets the masking of Software Controlled Interrupt 3.
0: Disable Software Controlled Interrupt 3.
1: Enable interrupt requests generated setting the Software Controlled Interrupt Bit 3.

Bit4: ESCI2: Enable Software Controlled Interrupt 2.

This bit sets the masking of Software Controlled Interrupt 2.
0: Disable Software Controlled Interrupt 2.
1: Enable interrupt requests generated setting the Software Controlled Interrupt Bit 2.

00000000

0xE7

Bit3: ESCI1: Enable Software Controlled Interrupt 1.

This bit sets the masking of Software Controlled Interrupt 1.
0: Disable Software Controlled Interrupt 1.
1: Enable interrupt requests generated setting the Software Controlled Interrupt Bit 1.

Bit2: ESCI0: Enable Software Controlled Interrupt 0.

This bit sets the masking of Software Controlled Interrupt 0.
0: Disable Software Controlled Interrupt 0.
1: Enable interrupt requests generated setting the Software Controlled Interrupt Bit 0.

Bit1: EADC0: Enable ADC0 End of Conversion Interrupt.

This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt.
1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.

Bit0: Reserved. Read = 0, Write = don't care.

80 Rev. 1.6

C8051F2xx

SFR Definition 9.12. EIP1: Extended Interrupt Priority 1

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

PCP1R PCP1F PCP0R PCP0F - PWADC0 - PSPI0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: PCP1R: Comparator 1 (CP1) Rising Interrupt Priority Control.

This bit sets the priority of the CP1 interrupt.
0: CP1 rising interrupt set to low priority level.
1: CP1 rising interrupt set to high priority level.

Bit6: PCP1F: Comparator 1 (CP1) Falling Interrupt Priority Control.

This bit sets the priority of the CP1 interrupt.
0: CP1 falling interrupt set to low priority level.
1: CP1 falling interrupt set to high priority level.

Bit5: PCP0R: Comparator 0 (CP0) Rising Interrupt Priority Control.

This bit sets the priority of the CP0 interrupt.
0: CP0 rising interrupt set to low priority level.
1: CP0 rising interrupt set to high priority level.

00000000

0xF6

Bit4: PCP0F: Comparator 0 (CP0) Falling Interrupt Priority Control.

This bit sets the priority of the CP0 interrupt.
0: CP0 falling interrupt set to low priority level.
1: CP0 falling interrupt set to high priority level.

Bit3: Reserved. Read = 0, Write = don't care.

Bit2: PWADC0: Analog-to-Digital Converter 0 window compare (ADC0) Interrupt Priority Control.

This bit sets the priority of the ADC0 window compare interrupt.
0: ADC0 window compare interrupt set to low priority level.
1: ADC0 window compare interrupt set to high priority level.

Bit1: UNUSED. Read = 0, Write = don't care.

Bit0: PSPI0: Serial Peripheral Interface 0 Interrupt Priority Control.

This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.

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C8051F2xx

SFR Definition 9.13. EIP2: Extended Interrupt Priority 2

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

PXVLD - PSCI3 PSCI2 PSCI1 PSCI0 PADC0 -

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control.

This bit sets the priority of the XTLVLD interrupt.
0: XTLVLD interrupt set to low priority level.
1: XTLVLD interrupt set to high priority level.

Bit6: Reserved. Must write 0. Reads 0.

Bit5: PSCI3: Software Controlled Interrupt 3 Priority Control.

This bit sets the priority of the Software Controlled Interrupt 3.
0: External Interrupt 7 set to low priority level.
1: External Interrupt 7 set to high priority level.

Bit4: PSCI2: Software Controlled Interrupt 2 Priority Control.

This bit sets the priority of the Software Controlled Interrupt 2.
0: Software Controlled Interrupt 2 set to low priority level.
1: Software Controlled Interrupt 2 set to high priority level.

00000000

0xF7

Bit3: PSCI1: Software Controlled Interrupt 1 Priority Control.

This bit sets the priority of the Software Controlled Interrupt 1.
0: Software Controlled Interrupt 1 set to low priority level.
1: Software Controlled Interrupt 1 set to high priority level.

Bit2: PSCI0: Software Controlled Interrupt 0 Priority Control.

This bit sets the priority of the Software Controlled Interrupt 0.
0: Software Controlled Interrupt 0 set to low priority level.
1: Software Controlled Interrupt 0 set to high priority level.

Bit1: PADC0: ADC End of Conversion Interrupt Priority Control.

This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority level.
1: ADC0 End of Conversion interrupt set to high priority level.

Bit0: Reserved. Read = 0, Write = don't care.

82 Rev. 1.6

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9.5. Power Management Modes

The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is
halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is
stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock
frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes
the least power.
CIP-51’s power management modes.

Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and put into low power mode. Turning
off the active oscillator saves even more power, but requires a reset to restart the MCU.

9.5.1. Idle Mode

Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes. All internal registers and memory maintain their original
data. All analog and digital peripherals can remain active during Idle mode.

Idle mode is terminated when an enabled interrupt or RST is asserted. The assertion of an enabled inter­rupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU will resume operation.
The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt
(RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is
terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins pro
gram execution at address 0x0000.

SFR Definition 9.14 describes the Power Control Register (PCON) used to control the

-

Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Any instructions that set the IDLE bit should be followed by an instruction
that has 2 or more op-code bytes, for example:

// in ‘C’:
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction

; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON ; ... followed by a 3-cycle dummy instruction

If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode.
This feature protects the system from an unintended permanent shutdown in the event of an inadvertent
write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to
entering the Idle mode if the WDT was initially configured to allow this operation. This provides the oppor
tunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for
an external stimulus to wake up the system. Refer to Section 12.7 Watchdog Timer for more information
on the use and configuration of the WDT.

9.5.2. Stop Mode

Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc­tion that sets the bit completes. In Stop mode, the CPU and oscillators are stopped, effectively shutting

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C8051F2xx

down all digital peripherals. Each analog peripheral must be shut down individually prior to entering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.

If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD
timeout of 100

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

SMOD GF4 GF3 GF2 GF1 GF0 STOP IDLE

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: SMOD: Serial Port Baud Rate Doubler Enable.

Bits6–2: GF4–GF0: General Purpose Flags 4–0.

µsec.

SFR Definition 9.14. PCON: Power Control Register

00000000

0x87

0: Serial Port baud rate is that defined by Serial Port Mode in SCON.
1: Serial Port baud rate is double that defined by Serial Port Mode in SCON.

These are general purpose flags for use under software control.

Bit1: STOP: Stop Mode Select.

Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: Goes into power down mode. (Turns off internal oscillator).

Bit0: IDLE: Idle Mode Select.

Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)

84 Rev. 1.6

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10. Flash Memory

This MCU includes 8 k + 128 bytes of on-chip, re-programmable Flash memory for program code and non­volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through
the JTAG interface or by software using the MOVX instruction. Once cleared to 0, a Flash bit must be
erased to set it back to 1. The bytes would typically be erased (set to 0xFF) before being reprogrammed.
The write and erase operations are automatically timed by hardware for proper execution. Data polling to
determine the end of the write/erase operation is not required. The Flash memory is designed to withstand
at least 20,000 write/erase cycles. Refer to
ory.

10.1. Programming The Flash Memory

The simplest means of programming the Flash memory is through the JTAG interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-ini
tialized device. For details on the JTAG commands to program Flash memory, see Section 18.1.

The Flash memory can be programmed by software using the MOVX instruction with the address and data
byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, flash
write operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic

1. Writing to Flash remains enabled until the PSWE bit is cleared by software.

Table 10.1 for the electrical characteristics of the Flash mem-

-

To ensure the contents of the Flash contents, it is strongly recommended that the on-chip VDD monitor be
enabled (by tieing the MONEN pin 'high') in any application that writes and/or erases Flash memory from

software.

Writes to Flash memory can clear bits but cannot set them. Only an erase operation can set bits in Flash.
The byte location to be programmed must be erased before a new value can be written. The 8kbyte Flash
memory is organized in 512-byte sectors. The erase operation applies to an entire sector (setting all bytes
in the sector to 0xFF). Setting the PSEE Program Store Erase Enable bit (PSCTL.1) and PSWE Program
Store Write Enable bit (PSCTL.0) to logic 1 and then using the MOVX command to write a data byte to any
byte location within the sector will erase an entire 512-byte sector. The data byte written can be of any
value because it is not actually written to the Flash. Flash erasure remains enabled until the PSEE bit is
cleared by software. The following sequence illustrates the algorithm for programming the Flash memory
by software:

1. Disable interrupts.

2. Enable Flash Memory write/erase in FLSCL Register using FLASCL bits.

3. Set PSEE (PSCTL.1) to enable Flash sector erase.

4. Set PSWE (PSCTL.0) to enable Flash writes.

5. Use MOVX to write a data byte to any location within the 512-byte sector to be erased.

6. Clear PSEE to disable Flash sector erase.

7. Use MOVX to write a data byte to the desired byte location within the erased 512-byte sector.
Repeat until finished. (Any number of bytes can be written from a single byte to and entire
sector.)

8. Clear the PSWE bit to disable Flash writes.

Write/Erase timing is automatically controlled by hardware based on the prescaler value held in the Flash
Memory Timing Prescaler register (FLSCL). The 4-bit prescaler value FLASCL determines the time inter
val for write/erase operations. The FLASCL value required for a given system clock is shown in SFR Defi­nition 10.2, along with the formula used to derive the FLASCL values. When FLASCL is set to 1111b, the

Rev. 1.6 85

-

C8051F2xx

write/erase operations are disabled. Note that code execution in the 8051 is stalled while the Flash is
being programmed or erased.

Table 10.1. Flash Memory Electrical Characteristics

VDD = 2.7 to 3.6 V, –40 to +85 ×C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Endurance 20 k 100 k — Erase/Wr

Erase/Write Cycle Time — 10 — ms

Non-volatile Data Storage

The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
instruction and read using the MOVC instruction.

The MCU incorporates an additional 128-byte sector of Flash memory located at 0x2000 – 0x207F. This
sector can be used for program code or data storage. However, its smaller sector size makes it particularly
well suited as general purpose, non-volatile scratchpad memory. Even though Flash memory can be writ
ten a single byte at a time, an entire sector must be erased first. In order to change a single byte of a multi­byte data set, the data must be moved to temporary storage. Next, the sector is erased, the data set
updated and the data set returned to the original sector. The 128-byte sector-size facilitates updating data
without wasting program memory space by allowing the use of internal data RAM for temporary storage. (A
normal 512-byte sector is too large to be stored in the 256-byte internal data memory.)

-

10.2. Security Options

The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft­ware as well as prevent the viewing of proprietary program code and constants. The Program Store Write
Enable (PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from
accidental modification by software. These bits must be explicitly set to logic 1 before software can modify
the Flash memory. Additional security features prevent proprietary program code and data constants from
being read or altered across the JTAG interface or by software running on the system controller.

A set of security lock bytes stored at 0x1DFE and 0x1DFF protect the Flash program memory from being
read or altered across the JTAG interface. Each bit in a security lock-byte protects one 1
ory. Clearing a bit to logic 0 in a Read lock byte prevents the corresponding block of Flash memory from
being read across the JTAG interface. Clearing a bit in the Write/Erase lock byte protects the block from
JTAG erasures and/or writes. The Read lock byte is at location 0x1DFF. The Write/Erase lock byte is
located at 0x1DFE.
sector containing the lock byte cannot be erased by software. Writing to the reserved area should not be
performed.

Figure 10.1 shows the location and bit definitions of the security bytes. The 512-byte

kB block of mem-

86 Rev. 1.6

C8051F2xx

(This Block locked only if all

other blocks are locked)

Reserved

Read Lock Byte

Write/Erase Lock Byte

Program Memory

Space

Software Read Limit

0x207F
0x2000
0x1FFF

0x1E00

0x1DFF

0x1DF
E
0x1DFD

0x0000

Read and Write/Erase Security Bits.
(Bit 7 is MSB.)

Bit Memory Block

7
6
5
4
3
2
1
0

Flash Read Lock Byte
Bits7–0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.)

0: Read operations are locked (disabled) for corresponding block across the JTAG inter­face.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG inter-

face.
Flash Write/Erase Lock Byte
Bits7–0: Each bit locks a corresponding block of memory.

0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG

interface.

1: Write/Erase operations are unlocked (enabled) for corresponding block across the

JTAG interface.
Flash Access Limit Register (FLACL)

The content of this register is used as the high byte of the 16-bit software read limit

address. The 16-bit read limit address value is calculated as 0xNN00 where NN is

replaced by content of this register on reset. Software running at or above this address is

prohibited from using the MOVX and MOVC instructions to read, write, or erase, locations

below this address. Any attempts to read locations below this limit will return the value

0x00.

0x1C00 - 0x1DFD

0x1800 - 0x1BFF
0x1400 - 0x17FF
0x1000 - 0x13FF

0x0C00 - 0x0FFF

0x0800 - 0x0BFF
0x0400 - 0x07FF
0x0000 - 0x03FF

Figure 10.1. Flash Program Memory Security Bytes

The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the
block containing the security bytes. This allows additional blocks to be protected after the block containing
the security bytes has been locked. However, the only means of removing a lock once set is to erase the
entire program memory space by performing a JTAG erase operation. NOTE: Erasing the Flash memory
block containing the security bytes will automatically initiate erasure of the entire program memory space
(except for the reserved area). This erasure can only be performed via the JTAG. If a non-security byte in
the 0x1C00–0x1DFF page is written to in order to perform an erasure of that page, then that page including
the security bytes will be erased.

Rev. 1.6 87

C8051F2xx

The Flash Access Limit security feature protects proprietary program code and data from being read by
software running on the CIP-51. This feature provides support for OEMs that wish to program the MCU
with proprietary value-added firmware before distribution. The value-added firmware can be protected
while allowing additional code to be programmed in remaining program memory space later.

The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program
memory space. The first is an upper partition consisting of all the program memory locations at or above
the SRL address, and the second is a lower partition consisting of all the program memory locations start
ing at 0x0000 up to (but excluding) the SRL address. Software in the upper partition can execute code in
the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruc
tion. (Executing a MOVC instruction from the upper partition with a source address in the lower partition
will always return a data value of 0x00.) Software running in the lower partition can access locations in
both the upper and lower partition without restriction.

The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value­added firmware via the reset vector. Once the value-added firmware completes its initial execution, it
branches to a predetermined location in the upper partition. If entry points are published, software running
in the upper partition may execute program code in the lower partition, but it cannot read the contents of
the lower partition. Parameters may be passed to the program code running in the lower partition either
through the typical method of placing them on the stack or in registers before the call or by placing them in
prescribed memory locations in the upper partition.

-

-

The SRL address is specified using the contents of the Flash Access Register. The 16-bit SRL address is
calculated as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be
located on 256-byte boundaries anywhere in program memory space. However, the 512-byte erase sector
size essentially requires that a 512 boundary be used. The contents of a non-initialized SRL security byte
is 0x00, thereby setting the SRL address to 0x0000 and allowing read access to all locations in program
memory space by default.

SFR Definition 10.1. PSCTL: Program Store RW Control

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

------PSEE PSWE

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits7–2: UNUSED. Read = 000000b, Write = don't care.

Bit1: PSEE: Program Store Erase Enable.

Setting this bit allows an entire page of the Flash program memory to be erased (provided
the PSWE bit is set to '1'). After setting this bit, a write to Flash memory using the MOVX
instruction will erase the entire page that contains the location addressed by the MOVX
instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.

00000000

0x8F

Bit0: PSWE: Program Store Write Enable.

Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
instruction. The location must be erased before writing data.
0: Write to Flash program memory disabled.
1: Write to Flash program memory enabled.

88 Rev. 1.6

C8051F2xx

SFR Definition 10.2. FLSCL: Flash Memory Timing Prescaler

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

FOSE FRAE - - FLASCL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: FOSE: Flash One-Shot Timer Enable

0: Flash One-shot timer disabled.
1: Flash One-shot timer enabled

Bit6: FRAE: Flash Read Always Enable

0: Flash reads per one-shot timer

1: Flash always in read mode
Bits5–4: UNUSED. Read = 00b, Write = don't care.
Bits3–0: FLASCL: Flash Memory Timing Prescaler.

This register specifies the prescaler value for a given system clock required to generate the

correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash

write/erase operations are disabled.

0000: System Clock < 50 kHz

0001: 50 kHz <

0010: 100 kHz <

0011: 200 kHz <

0100: 400 kHz <

0101: 800 kHz <

0110: 1.6 MHz <

0111: 3.2 MHz <

1000: 6.4 MHz <

1001: 12.8 MHz <

1010: 25.6 MHz <

System Clock < 100 kHz

System Clock < 200 kHz

System Clock < 400 kHz

System Clock < 800 kHz
System Clock < 1.6 MHz
System Clock < 3.2 MHz

System Clock < 6.4 MHz

System Clock < 12.8 MHz

System Clock < 25.6 MHz

System Clock < 51.2 MHz*
1011, 1100, 1101, 1110: Reserved Values
1111: Flash Memory Write/Erase Disabled

10001111

0xB6

The prescaler value is the smallest value satisfying the following equation:
FLASCL > log2(System Clock / 50kHz)

*For test purposes. The C8051F2xx is not guaranteed to operate over 25 MHz.

SFR Definition 10.3. FLACL: Flash Access Limit

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bits 7–0: FLACL: Flash Memory Access Limit.

This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. Any
subsequent writes are ignored until the next reset.

Rev. 1.6 89

0xB7

C8051F2xx

11. On-Chip XRAM (C8051F206/226/236)

The C8051F206/226/236 features 1024 Bytes of RAM mapped into the external data memory space. All
address locations may be accessed using the external move instruction (MOVX) and the data pointer
(DPTR), or using indirect MOVX addressing mode. If the MOVX instruction is used with an 8-bit operand
(such as @R1), then the high byte is the External Memory Interface Control Register (EMI0CN, shown in
SFR Definition 11.1). Addressing using 8 bits will map to one of four 256-byte pages, and these pages are
selected by setting the PGSEL bits in the EMI0CN register.

NOTE: The MOVX instruction is also used for write to the Flash memory. Please see section 10 for
details. The MOVX instruction will access XRAM by default.

For any of the addressing modes, the upper 6 bits of the 16-bit external data memory address word are
"don't cares". As a result, the 1024-byte RAM is mapped modulo style ("wrap around") over the entire 64k
of possible address values. For example, the XRAM byte at address 0x0000 is also at address 0x0400,
0x0800, 0x0C00, 0x1000, etc. This feature is useful when doing a linear memory fill, as the address
pointer does not have to be reset when reaching the RAM block boundary.

SFR Definition 11.1. EMI0CN: External Memory Interface Control

RRRRRRR/WR/WReset Value

------PGSEL1PGSEL0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

00000000

0xAF

Bits7–2: Not Used -read only 000000b
Bits1–0: XRAM Page Select Bits PGSEL[1:0]

The XRAM Page Select bits provide the high byte of the 16-bit external memory address
when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. The
upper 6 bits are "don't cares", so the 1k address blocks are repeated modulo over the entire
data memory address space.
00:0x000 – 0x0FF
01:0x100 – 0x1FF
10:0x200 – 0x2FF
11:0x300 – 0x3FF

90 Rev. 1.6

C8051F2xx

12. Reset Sources

The reset circuitry of the MCU allows the controller to be easily placed in a predefined default condition.
On entry to this reset state, the CIP-51 halts program execution, forces the external port pins to a known
state and initializes the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the
program counter (PC) is reset, and program execution starts at location 0x0000.

All of the SFRs are reset to predefined values. The reset values of the SFR bits are defined in the SFR
detailed descriptions. The contents of internal data memory are not changed during a reset and any previ
ously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost
even though the data on the stack are not altered.

The I/O port latches are reset to 0xFF (all logic ones), activating internal weak pull-ups which take the
external I/O pins to a high state. The weak pull-ups are enabled during and after the reset. If the source of
reset is from the V

reset timeout.

V

DD

On exit from the reset state, the MCU uses the internal oscillator running at 2MHz as the system clock by
default. Refer to Section 13 for information on selecting and configuring the system clock source. The
Watchdog Timer is enabled using its longest timeout interval. (Section 12.7 details the use of the Watch
dog Timer.) Once the system clock source is stable, program execution begins at location 0x0000.

Monitor or writing a '1' to the PORSF bit, the RST pin is driven low until the end of the

DD

-

-

There are six sources for putting the MCU into the reset state: power-on/power-fail (VDD monitor), external
RST pin, software commanded, Comparator 0, Missing Clock Detector, and Watchdog Timer. Each reset

source is described below:

CP0+

CP0-

System

Clock

Comparator 0

+

-

Missing

Clock

Detector

EN

MCD

Enable

C0RSEF

VDD

WDT

PRE

EN

WDT

WDT

Enable

Strobe

CIP-51

MonEn

Supply
Monitor

+

-

SWRSF

(Software Reset)

System Reset

Supply

Reset

Timeout

(wired-OR)

Reset
Funnel

/RST

Core

Figure 12.1. Reset Sources Diagram

Rev. 1.6 91

C8051F2xx

12.1. Power-on Reset

The CIP-51 incorporates a power supply monitor that holds the MCU in the reset state until VDD rises
above the VRST level during power-up. (See

the Electrical Characteristics of the power supply monitor circuit.) The RST pin is asserted (low) until the
end of the 100msec V

packages, the V

DD

Monitor timeout in order to allow the VDD supply to become stable. On 48-pin

DD

monitor is enabled by pulling the MONEN pin high and is disabled by pulling the
MONEN pin low. The MONEN pin should never be left floating. On 32-pin packages, the V
always enabled and cannot be disabled.

On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other
reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF
flag to determine if a power-up was the cause of reset. The content of internal data memory should be
assumed to be undefined after a power-on reset.

12.2. Software Forced Reset

Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 12.1.

Figure 12.2 for timing diagram, and refer to Ta b le 12.1 for

monitor is

DD

volts

2.70

2.55

2.0

1.0

Logic HIGH

Logic LOW

/RST

V

RST

D

D

V

t

100ms 100ms

Figure 12.2. VDD Monitor Timing Diagram

12.3. Power-fail Reset

When the VDD monitor is enabled, the MONEN pin (not on C8051F221/F231 32 pin parts) is "pulled high",
and power-down transition or power irregularity causes V
will drive the

RST pin low and return the CIP-51 to the reset state (see Figure 12.2). When VDD returns to

a level above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on
reset. Note that even though internal data memory contents are not altered by the power-fail reset, it is
impossible to determine if V

dropped below the level required for data retention. If the PORSF flag is

DD

set, the data may no longer be valid.

to drop below VRST, the power supply monitor

DD

92 Rev. 1.6

C8051F2xx

12.4. External Reset

The external RST pin provides a means for external circuitry to force the CIP-51 into a reset state. Assert­ing an active-low signal on the RST pin will cause the CIP-51 to enter the reset state. Although there is a
weak pull-up, it may be desirable to provide an external pull-up and/or decoupling of the
erroneous noise-induced resets. The CIP-51 will remain in reset until at least 12 clock cycles after the
active-low
The

RST signal is removed. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.

RST pin is 5 V tolerant.

12.5. Missing Clock Detector Reset

The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If
the system clock goes away for more than 100msec, the one-shot will time out and generate a reset. After
a Missing Clock Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset
source; otherwise, this bit reads 0. The state of the
MSCLKE bit in the OSCICN register (see

SFR Definition 13.1) enables the Missing Clock Detector.

RST pin is unaffected by this reset. Setting the

12.6. Comparator 0 Reset

Comparator 0 can be configured as a reset input by writing a 1 to the C0RSEF flag (RSTSRC.5). Compar­ator 0 should be enabled using CPT0CN.7 (see SFR Definition 8.1) prior to writing to C0RSEF to prevent
any turn-on chatter on the output from generating an unwanted reset. When configured as a reset, if the
non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the MCU is put
into the reset state. After a Comparator 0 Reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Com
parator 0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.

RST pin to avoid

-

12.7. Watchdog Timer Reset

The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. The WDT will
force the MCU into the reset state when the watchdog timer overflows. To prevent the reset, the WDT
must be restarted by application software before the overflow occurs. If the system experiences a soft
ware/hardware malfunction preventing the software from restarting the WDT, the WDT will overflow and
cause a reset. This should prevent the system from running out of control.

The WDT is automatically enabled and started with the default maximum time interval on exit from all
resets. If desired, the WDT can be disabled by system software or locked 'on' to prevent accidental dis
abling. Once locked, the WDT cannot be disabled until the next system reset. The state of the RST pin is
unaffected by this reset.

12.7.1. Watchdog Usage

The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the
period between specific writes to its control register. If this period exceeds the programmed limit, a WDT
reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently
enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN)
shown in

Enable/Reset WDT

The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica­tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer
overflow. The WDT is enabled and reset as a result of any system reset.

SFR Definition 12.1.

-

-

Rev. 1.6 93

C8051F2xx

Disable WDT

Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT.

CLR EA ; disable all interrupts
MOV WDTCN,#0DEh ; disable watchdog timer
MOV WDTCN,#0ADh ;
SETB EA ; re-enable interrupts

The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is
ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.

Disable WDT Lockout

Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored
until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications alays
intending to use the watchdog should write 0xFF to WDTCN in their initialization code.

Setting WDT Interval

WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:

3+WDTCN[2:0]

4

x T

SYSCLK

, (where T

SYSCLK

is the system clock period).

For a 2.0 MHz system clock, this provides an interval range of 32msec to 524msec. WDTCN.7 must be
written as 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] is
111b after a system reset.

SFR Definition 12.1. WDTCN: Watchdog Timer Control

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

xxxxx111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xFF

Bits7–0: WDT Control

Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.

Bit4: Watchdog Status Bit (when Read)

Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active

Bits2–0: Watchdog Timeout Interval Bits

The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits,
WDTCN.7 must be set to 0.

94 Rev. 1.6

C8051F2xx

SFR Definition 12.2. RSTSRC: Reset Source

R R/W R/W R R R/W R Reset Value

- C0RSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(Note: Do not use read-modify-write operations on this register.)

Bit7: RESERVED.
Bit6: Not Used. Read only 0b.
Bit5: C0RSEF: Comparator 0 Reset Enable and Flag

Write
0: Comparator 0 is not a reset source
1: Comparator 0 is a reset source (active low)
Read
Note: The value read from C0RSEF is not defined if Comparator 0 has not been enabled as
a reset source.
0: Source of prior reset was not from Comparator 0
1: Source of prior reset was from Comparator 0

Bit4: SWRSF: Software Reset Force and Flag

Write
0: No Effect
1: Forces an internal reset. RST

Read

0: Prior reset source was not from write to the SWRSF bit.
1: Prior reset source was from write to the SWRSF bit.

Bit3: WDTRSF: Watchdog Timer Reset Flag (Read only)

0: Source of prior reset was not from WDT timeout.
1: Source of prior reset was from WDT timeout.

Bit2: MCDRSF: Missing Clock Detector Flag (Read only)

0: Source of prior reset was not from Missing Clock Detector timeout.
1: Source of prior reset was from Missing Clock Detector timeout.

Bit1: PORSF: Power-On Reset Force and Flag

Write
0: No effect
1: Forces a Power-On Reset. RST

Read

0: Source of prior reset was not from POR.
1: Source of prior reset was from POR.

Bit0: PINRSF: HW Pin Reset Flag

0: Source of prior reset was not from RST
1: Source of prior reset was from RST

pin is not affected.

is driven low.

pin.

pin.

xxxxxxxx

0xEF

Rev. 1.6 95

C8051F2xx

Table 12.1. VDD Monitor Electrical Characteristics

–40 to +85 ×C unless otherwise specified.

Parameter Conditions Min Ty p Max Units

RST Output Low Voltage

RST Input High Voltage

RST Input Low Voltage — —

RST Input Leakage Current RST = 0.0 V — — 50 µA

VDD for RST Output Valid

Reset Threshold (Vrst) 2.40 2.55 2.70 V

Reset Time Delay

Missing Clock Detector
Timeout

IOL = 8.5 mA, VDD = 2.7 to 3.6 V

RST rising edge after crossing reset
threshold

Time from last system clock to reset
generation

— — 0.6 V

0.8 x
V

DD

1.0 — — V

80 100 120 ms

100 220 500 µs

— — V

0.2 x
V

DD

V

96 Rev. 1.6

C8051F2xx

13. Oscillator

The MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate
the system clock. The MCU boots from the internal oscillator after any reset. This internal oscillator can
be enabled/disabled and its frequency can be set using the Internal Oscillator Control Register (OSCICN)
as shown in

Both oscillators are disabled when the RST pin is held low. The MCU can run from the internal oscillator
permanently, or it can switch to the external oscillator if desired using CLKSL bit in the OSCICN Register.
The external oscillator requires an external resonator, crystal, capacitor, or RC network connected to the
XTAL1/XTAL2 pins (see
the OSCXCN register. An external CMOS clock can also provide the system clock by driving the XTAL1
pin. The XTAL1 and XTAL2 pins are NOT 5

SFR Definition 13.1. The internal oscillator's electrical specifications are given in Ta bl e 13.1.

Figure 13.1). The oscillator circuit must be configured for one of these sources in

V tolerant.

OSCICN

IFCN1

MSCLKE

IFRDY

CLKSL

IOSCEN

IFCN0

opt. 4

opt. 3

XTAL1

XTAL2

opt. 2

VDD

opt. 1

XTAL1XTAL1

XTAL1

XTAL2

Figure 13.1. Oscillator Diagram

Internal Clock

Generator

Input

Circuit

XTLVLD

XOSCMD2

XOSCMD1

OSCXCN

EN

OSC

XFCN2

XFCN1

XOSCMD0

SYSCLK

XFCN0

Rev. 1.6 97

C8051F2xx

SFR Definition 13.1. OSCICN: Internal Oscillator Control

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

MSCLKE - - IFRDY CLKSL IOSCEN IFCN1 IFCN0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: MSCLKE: Missing Clock Enable Bit

0: Missing Clock Detector Disabled

1: Missing Clock Detector Enabled; triggers a reset if a missing clock is detected
Bits6–5: UNUSED. Read = 00b, Write = don't care
Bit4: IFRDY: Internal Oscillator Frequency Ready Flag

0: Internal Oscillator Frequency not running at speed specified by the IFCN bits.

1: Internal Oscillator Frequency running at speed specified by the IFCN bits.
Bit3: CLKSL: System Clock Source Select Bit

0: Uses Internal Oscillator as System Clock.

1: Uses External Oscillator as System Clock.
Bit2: IOSCEN: Internal Oscillator Enable Bit

0: Internal Oscillator Disabled

1: Internal Oscillator Enabled
Bits1–0: IFCN1-0: Internal Oscillator Frequency Control Bits

00: Internal Oscillator typical frequency is 2 MHz.

01: Internal Oscillator typical frequency is 4 MHz.

10: Internal Oscillator typical frequency is 8 MHz.

11: Internal Oscillator typical frequency is 16 MHz.

00000100

0xB2

Table 13.1. Internal Oscillator Electrical Characteristics

–40 to +85 ×C unless otherwise specified.

Parameter Conditions Min Ty p Max Units

Internal Oscillator Frequency OSCICN.[1:0] = 00

OSCICN.[1:0] = 01
OSCICN.[1:0] = 10
OSCICN.[1:0] = 11

Internal Oscillator Current Consumption OSCICN.2 = 1 — 200 — µA

Internal Oscillator Temperature Stability — 4 — ppm/°C

Internal Oscillator Power Supply (VDD)
Stability

1.5

3.0

6.0
12

— 6.4 — %/V

2.0

4.0

8.0
16

2.5

5.0
10
20

MHz

98 Rev. 1.6

C8051F2xx

SFR Definition 13.2. OSCXCN: External Oscillator Control

R R/W R/W R/W R/W R/W R/W R/W Reset Value

XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 - XFCN2 XFCN1 XFCN0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

Bit7: XTLVLD: Crystal Oscillator Valid Flag

(Valid only when XOSCMD = 1xx.)
0: Crystal Oscillator is unused or not yet stable
1: Crystal Oscillator is running and stable

Bits6–4: XOSCMD2–0: External Oscillator Mode Bits

00x: Off. XTAL1 pin is grounded internally.
010: System Clock from External CMOS Clock on XTAL1 pin.
011: System Clock from External CMOS Clock on XTAL1 pin divided by 2.
10x: RC/C Oscillator Mode with divide by 2 stage.
110: Crystal Oscillator Mode

111: Crystal Oscillator Mode with divide by 2 stage.
Bit3: RESERVED. Read = undefined, Write = don’t care
Bits2–0: XFCN2–0: External Oscillator Frequency Control Bits

000–111: see table below

00110000

0xB1

XFCN Crystal (XOSCMD = 11x) RC (XOSCMD = 10x) C (XOSCMD = 10x)

000 f

001 12.5 kHz < f

010 30.35 kHz < f

011 93.8 kHz < f

100 267 kHz < f

101 722 kHz < f

110 2.23 MHz < f

111 f > 6.74 MHz 1.6 MHz < f

≤ 12.5 kHz f ≤ 25 kHz K Factor = 0.44

≤ 30.3 kHz 25 kHz < f ≤ 50 kHz K Factor = 1.4

≤ 93.8 kHz 50 kHz < f ≤ 100 kHz K Factor = 4.4

≤ 26 7kHz 100 kHz < f ≤ 200 kHz K Factor = 13

≤ 722 kHz 200 kHz < f ≤ 400 kHz K Factor = 38

≤ 2.23 MHz 400 kHz < f ≤ 800 kHz K Factor = 100

≤ 6.74 MHz 800 kHz < f ≤ 1.6 MHz K Factor = 420

≤ 3.2 MHz K Factor = 1400

CRYSTAL MODE (Circuit from Figure 13.1, Option 1; XOSCMD = 11x)

Choose XFCN value to match the crystal frequency.

RC MODE (Circuit from Figure 13.1, Option 2; XOSCMD = 10x)

Choose oscillation frequency range where:

f = 1.23(103) / (R x C), where

f = frequency of oscillation in MHz

C = capacitor value in pF

R = Pull-up resistor value in k

Ω

C MODE (Circuit from Figure 13.1, Option 3; XOSCMD = 10x)

Choose K Factor (KF) for the oscillation frequency desired:

f = KF / (C x AV+), where

f = frequency of oscillation in MHz

C = capacitor value on XTAL1, XTAL2 pins in pF

V

= Power supply voltage on MCU in volts

DD

Rev. 1.6 99

C8051F2xx

13.1. External Crystal Example

If a crystal were used to generate the system clock for the MCU, the circuit would be as shown in
Figure 13.1, Option 1. For an ECS-110.5-20-4 crystal, the resonate frequency is 11.0592 MHz, the intrin­sic capacitance is 7 pF, and the ESR is 60 W. The compensation capacitors should be 33 pF each, and
the PWB parasitic capacitance is estimated to be 2
Control value (XFCN) from the Crystal column in the table in
should be 111b.

The Crystal Oscillator Valid Flag (XTLVLD in register OSCXCN) is set to logic 1 by hardware when the
external oscillator is running and stable. The XTLVLD detection circuit requires a startup time of at least
1ms between enabling the oscillator and checking the XTLVLD flag. Switching to the external oscillator
before 1ms can result in unpredictable behavior. The recommend procedure is:

1. Enable the external oscillator

2. Wait 1 ms

3. Poll for XTLVLD '0' ==> '1'

4. Switch to the external oscillator

Switching to the external oscillator before the crystal oscillator has stabilized could result in unpredictable
behavior.

NOTE: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close
as possible to the XTAL pins on the device, keeping the traces as short as possible and shielded with
ground plane from any other traces which could introduce noise or interference.

pF. The appropriate External Oscillator Frequency

SFR Definition 13.2 (OSCXCN Register)

13.2. External RC Example

If an external RC network were used to generate the system clock for the MCU, the circuit would be as
shown in
capacitor will increase the frequency drift due to the PWB parasitic capacitance. To determine the required
External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network
value to produce the desired frequency of oscillation. If the frequency desired is 100
and C = 50

Figure 13.1, Option 2. The capacitor must be no greater than 100 pF, but using a very small

kHz, let R = 246 kW

pF:

f = 1.23(103)/RC = 1.23(103) / [246 x 50] = 0.1 MHz = 100 kHz

XFCN ³ log2(f/25 kHz)
XFCN ³ log2(100 kHz/25 kHz) = log2(4)
XFCN ³ 2, or code 010

13.3. External Capacitor Example

If an external capacitor were used to generate the system clock for the MCU, the circuit would be as shown
in

Figure 13.1, Option 3. The capacitor must be no greater than 100 pF, but using a very small capacitor
will increase the frequency drift due to the PWB parasitic capacitance. To determine the required External
Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and
find the frequency of oscillation from the equations below. Assume V

f = KF / (C x VDD) = KF / (50 x 3)
f = KF / 150

If a frequency of roughly 90kHz is desired, select the K Factor from the table in SFR Definition 13.2 as KF
= 13:

= 3.0 V and C = 50 pF:

DD

f = 13 /150 = 0.087 MHz, or 87 kHz

Therefore, the XFCN value to use in this example is 011.

100 Rev. 1.6