Silicon Laboratories C8051F2xx User Manual
C8051F2xx
Mixed Signal 8 kB ISP Flash MCU Family
Analog Peripherals
- SAR ADC
• 12-bit resolution ('F206)
• 8-bit resolution ('F220/1/6)
• ±1/4 LSB INL (8-bit) and ±2 LSB INL (12-bit)
• Up to 100 ksps
• Up to 32 channel input multiplexer; each port
I/O pin can be an ADC input
- Two Comparators
• 16 programmable hysteresis states
• Configurable to generate interrupts or reset
- V
monitor and brown-out detector
DD
On-Chip JTAG Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (No emulator
required)
- Provides breakpoints, single-stepping, watchpoints,
stack monitor
- Inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Complete, low cost development kit
High Speed
- 8051 mC Core
- Pipelined Instruction Architecture; Executes 70% of
Instructions in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- Expanded Interrupt Handler
Memory
- 256 bytes internal data RAM
- 1024 bytes XRAM (available on 'F206/226/236)
- 8 kB Flash; In-system programmable in 512 byte
sectors
Digital Peripherals
- Four byte wide Port I/O; All are 5 V tolerant
- Hardware UART and SPI bus
- 3 general purpose 16-bit counter/timers
- Dedicated watch-dog timer
- Bi-directional reset
- System clock: internal programmable oscillator,
external crystal, external RC, or external clock
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 10 mA @ 25 MHz
- Multiple power saving sleep and shutdown modes
(48-Pin TQFP and 32-Pin LQFP Version
Available)
Temperature Range: –40 to +85 °C
ANALOG PERIPHERALS
+
-
SAR
ADC
PGA
AMUX
+
-
VOLTAGE
COMPARATORS
DIGITAL I/O
SPI Bus
UART
Timer 0
Timer 1
Timer 2
Digital MUX
Port 0Port 1
Port 2Port 3
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
8K x 8
ISP FLASH
CLOCK
CIRCUIT
1280 x 8
SRAM
JTAG
22 INTERRUPTS
Rev. 1.6 3/05 Copyright © 2005 by Silicon Laboratories C8051F2xx
EMULATION
CIRCUITRY
SANITY
CONTROL
C8051F2xx
NOTES:
2 Rev. 1.6
C8051F2xx
Table of Contents
1. System Overview.................................................................................................... 11
1.1. CIP-51TM Microcontroller Core ........................................................................ 15
1.1.1. Fully 8051 Compatible.............................................................................. 15
1.1.2. Improved Throughput............................................................................... 15
1.1.3. Additional Features .................................................................................. 16
1.2. On-Board Memory ............................................................................................ 17
1.3. JTAG ............................................................................................................ 18
1.4. Digital/Analog Configurable I/O......................................................................... 19
1.5. Serial Ports ....................................................................................................... 20
1.6. Analog to Digital Converter ............................................................................... 20
1.7. Comparators ..................................................................................................... 21
2. Absolute Maximum Ratings .................................................................................. 23
3. Global DC Electrical Characteristics .................................................................... 24
4. Pinout and Package Definitions............................................................................ 25
5. ADC (8-Bit, C8051F220/1/6 Only)........................................................................... 32
5.1. Analog Multiplexer and PGA............................................................................. 32
5.2. ADC Modes of Operation.................................................................................. 33
5.3. ADC Programmable Window Detector ............................................................. 37
6. ADC (12-Bit, C8051F206 Only)............................................................................... 40
6.1. Analog Multiplexer and PGA............................................................................. 40
6.2. ADC Modes of Operation.................................................................................. 41
6.3. ADC Programmable Window Detector ............................................................. 46
7. Voltage Reference (C8051F206/220/221/226) ....................................................... 50
8. Comparators ........................................................................................................... 52
9. CIP-51 Microcontroller ........................................................................................... 58
9.1. Instruction Set ................................................................................................... 60
9.1.1. Instruction and CPU Timing ..................................................................... 60
9.1.2. MOVX Instruction and Program Memory ................................................. 60
9.2. Memory Organization........................................................................................ 65
9.2.1. Program Memory...................................................................................... 65
9.2.2. Data Memory............................................................................................ 65
9.2.3. General Purpose Registers ...................................................................... 66
9.2.4. Bit Addressable Locations........................................................................ 66
9.2.5. Stack ....................................................................................................... 67
9.3. Special Function Registers ............................................................................... 68
9.3.1. Register Descriptions ............................................................................... 71
9.4. Interrupt Handler ............................................................................................... 74
9.4.1. MCU Interrupt Sources and Vectors ........................................................ 74
9.4.2. External Interrupts.................................................................................... 74
9.4.3. Software Controlled Interrupts.................................................................. 74
9.4.4. Interrupt Priorities ..................................................................................... 76
9.4.5. Interrupt Latency ...................................................................................... 76
9.4.6. Interrupt Register Descriptions................................................................. 77
Rev. 1.6 3
C8051F2xx
9.5. Power Management Modes .............................................................................. 83
9.5.1. Idle Mode.................................................................................................. 83
9.5.2. Stop Mode................................................................................................ 83
10.Flash Memory ......................................................................................................... 85
10.1.Programming The Flash Memory ..................................................................... 85
10.2.Security Options ............................................................................................... 86
11.On-Chip XRAM (C8051F206/226/236).................................................................... 90
12.Reset Sources......................................................................................................... 91
12.1.Power-on Reset................................................................................................ 92
12.2.Software Forced Reset..................................................................................... 92
12.3.Power-fail Reset ............................................................................................... 92
12.4.External Reset.................................................................................................. 93
12.5.Missing Clock Detector Reset .......................................................................... 93
12.6.Comparator 0 Reset ......................................................................................... 93
12.7.Watchdog Timer Reset..................................................................................... 93
12.7.1.Watchdog Usage...................................................................................... 93
13.Oscillator ................................................................................................................. 97
13.1.External Crystal Example ............................................................................... 100
13.2.External RC Example ..................................................................................... 100
13.3.External Capacitor Example ........................................................................... 100
14.Port Input/Output.................................................................................................. 101
14.1.Port I/O Initialization ....................................................................................... 101
14.2.General Purpose Port I/O ............................................................................... 105
15.Serial Peripheral Interface Bus ........................................................................... 110
15.1.Signal Descriptions......................................................................................... 111
15.1.1.Master Out, Slave In .............................................................................. 111
15.1.2.Master In, Slave Out .............................................................................. 111
15.1.3.Serial Clock ............................................................................................ 111
15.1.4.Slave Select ........................................................................................... 111
15.2.Serial Clock Timing......................................................................................... 113
15.3.SPI Special Function Registers...................................................................... 113
16.UART...................................................................................................................... 117
16.1.UART Operational Modes .............................................................................. 118
16.1.1.Mode 0: Synchronous Mode .................................................................. 118
16.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 119
16.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 121
16.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 121
16.2.Multiprocessor Communications .................................................................... 122
17.Timers.................................................................................................................... 125
17.1.Timer 0 and Timer 1 ....................................................................................... 125
17.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 125
17.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 126
17.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 127
17.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 128
4 Rev. 1.6
C8051F2xx
17.2.Timer 2 .......................................................................................................... 133
17.2.1.Mode 0: 16-bit Counter/Timer with Capture........................................... 134
17.2.2.Mode 1: 16-bit Counter/Timer with Auto-Reload.................................... 135
17.2.3.Mode 2: Baud Rate Generator............................................................... 136
18.JTAG ...................................................................................................................... 139
18.1.Flash Programming Commands..................................................................... 140
18.2.Boundary Scan Bypass and ID Code ............................................................. 143
18.2.1.BYPASS Instruction ............................................................................... 143
18.2.2.IDCODE Instruction................................................................................ 143
18.3.Debug Support ............................................................................................... 143
Contact Information.................................................................................................. 144
Rev. 1.6 5
C8051F2xx
NOTES:
6 Rev. 1.6
C8051F2xx
List of Figures and Tables
1. System Overview
Table 1.1. Product Selection Guide ........................................................................ 11
Figure 1.1. C8051F206, C8051F220 and C8051F226 Block Diagram (48 TQFP) .. 12
Figure 1.2. C8051F221 Block Diagram (32 LQFP) .................................................. 13
Figure 1.3. C8051F230 and C8051F236 Block Diagram (48 TQFP) ....................... 14
Figure 1.4. C8051F231 Block Diagram (32 LQFP) .................................................. 15
Figure 1.5. Comparison of Peak MCU Throughputs ................................................ 16
Figure 1.6. Comparison of Peak MCU Throughputs ................................................ 17
Figure 1.7. On-Board Memory Map.......................................................................... 18
Figure 1.8. Degub Environment Diagram ................................................................. 19
Figure 1.9. Port I/O Functional Block Diagram......................................................... 20
Figure 1.10. ADC Diagram ....................................................................................... 21
Figure 1.11. Comparator Diagram............................................................................ 22
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*.................................................................. 23
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics ...................................................... 24
4. Pinout and Package Definitions
Table 4.1. Pin Definitions ........................................................................................ 25
Figure 4.1. TQFP-48 Pin Diagram............................................................................ 28
Figure 4.2. LQFP-32 Pin Diagram ............................................................................ 29
Figure 4.3. TQFP-48 Package Drawing ................................................................... 30
Figure 4.4. LQFP-32 Package Drawing ................................................................... 31
5. ADC (8-Bit, C8051F220/1/6 Only)
Figure 5.1. 8-Bit ADC Functional Block Diagram ..................................................... 32
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing .............................. 33
Figure 5.3. 8-Bit ADC Window Interrupt Examples .................................................. 38
Table 5.1. 8-Bit ADC Electrical Characteristics....................................................... 39
6. ADC (12-Bit, C8051F206 Only)
Figure 6.1. 12-Bit ADC Functional Block Diagram ................................................... 40
Figure 6.2. 12-Bit ADC Track and Conversion Example Timing .............................. 41
Figure 6.3. 12-Bit ADC Window Interrupt Examples, Right Justified Data ............... 47
Figure 6.4. 12-Bit ADC Window Interrupt Examples, Left Justified Data ................. 48
Table 6.1. 12-Bit ADC Electrical Characteristics (C8015F206 only)....................... 49
7. Voltage Reference (C8051F206/220/221/226)
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 50
Table 7.1. Reference Electrical Characteristics ...................................................... 51
8. Comparators
Figure 8.1. Comparator Functional Block Diagram .................................................. 53
Figure 8.2. Comparator Hysteresis Plot ................................................................... 54
Table 8.1. Comparator Electrical Characteristics.................................................... 57
9. CIP-51 Microcontroller
Figure 9.1. CIP-51 Block Diagram............................................................................ 58
Rev. 1.6 7
C8051F2xx
Table 9.1. CIP-51 Instruction Set Summary............................................................ 60
Figure 9.2. Memory Map .......................................................................................... 66
Table 9.2. Special Function Register Memory Map ................................................ 68
Table 9.3. Special Function Registers .................................................................... 69
Table 9.4. Interrupt Summary ................................................................................. 75
10.Flash Memory
Table 10.1. Flash Memory Electrical Characteristics ............................................... 86
Figure 10.1. Flash Program Memory Security Bytes................................................ 87
11.On-Chip XRAM (C8051F206/226/236)
12.Reset Sources
Figure 12.1. Reset Sources Diagram ....................................................................... 91
Figure 12.2. VDD Monitor Timing Diagram .............................................................. 92
Table 12.1. VDD Monitor Electrical Characteristics.................................................. 96
13.Oscillator
Figure 13.1. Oscillator Diagram................................................................................ 97
Table 13.1. Internal Oscillator Electrical Characteristics .......................................... 98
14.Port Input/Output
Figure 14.1. Port I/O Functional Block Diagram ..................................................... 102
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 102
Table 14.1. Port I/O DC Electrical Characteristics.................................................. 109
15.Serial Peripheral Interface Bus
Figure 15.1. SPI Block Diagram ............................................................................. 110
Figure 15.2. SPI Block Diagram ............................................................................. 111
Figure 15.3. Full Duplex Operation......................................................................... 112
Figure 15.4. Full Duplex Operation......................................................................... 113
16.UART
Figure 16.1. UART Block Diagram ......................................................................... 117
Table 16.1. UART Modes ....................................................................................... 118
Figure 16.2. UART Mode 0 Interconnect................................................................ 118
Figure 16.3. UART Mode 0 Timing Diagram .......................................................... 118
Figure 16.4. UART Mode 1 Timing Diagram .......................................................... 119
Figure 16.5. UART Modes 1, 2, and 3 Interconnect Diagram ................................ 120
Figure 16.6. UART Modes 2 and 3 Timing Diagram .............................................. 121
Figure 16.7. UART Multi-Processor Mode Interconnect Diagram .......................... 122
Table 16.2. Oscillator Frequencies for Standard Baud Rates ................................ 122
17.Timers
Figure 17.1. T0 Mode 0 Block Diagram.................................................................. 126
Figure 17.2. T0 Mode 2 Block Diagram.................................................................. 127
Figure 17.3. T0 Mode 3 Block Diagram.................................................................. 128
Figure 17.4. T2 Mode 0 Block Diagram.................................................................. 134
Figure 17.5. T2 Mode 1 Block Diagram.................................................................. 135
Figure 17.6. T2 Mode 2 Block Diagram.................................................................. 136
18.JTAG
8 Rev. 1.6
C8051F2xx
List of Registers
SFR Definition 5.1. AMX0SL: AMUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SFR Definition 5.2. ADC0CF: ADC Configuration Register . . . . . . . . . . . . . . . . . . . . . 35
SFR Definition 5.3. ADC0CN: ADC Control (C8051F220/1/6 and C8051F206) . . . . . . 36
SFR Definition 5.4. ADC0H: ADC Data Word (‘F220/1/6 and ‘F206) . . . . . . . . . . . . . 37
SFR Definition 5.5. ADC0GTH: ADC Greater-Than Data (‘F220/1/6 and ‘F206) . . . . . 37
SFR Definition 5.6. ADC0LTH: ADC Less-Than Data Byte (‘F220/1/6 and ‘F206) . . . . 37
SFR Definition 6.1. AMX0SL: AMUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SFR Definition 6.2. ADC0CF: ADC Configuration (‘F220/1/6 and ‘F206) . . . . . . . . . . . 43
SFR Definition 6.3. ADC0CN: ADC Control (‘F220/1/6 and ‘F206) . . . . . . . . . . . . . . . 44
SFR Definition 6.4. ADC0H: ADC Data Word MSB (C8051F206) . . . . . . . . . . . . . . . . 45
SFR Definition 6.5. ADC0L: ADC Data Word LSB (C8051F206) . . . . . . . . . . . . . . . . 45
SFR Definition 6.6. ADC0GTH: ADC Greater-Than Data High Byte (C8051F206) . . . 46
SFR Definition 6.7. ADC0GTL: ADC Greater-Than Data Low Byte (C8051F206) . . . . 46
SFR Definition 6.8. ADC0LTH: ADC Less-Than Data High Byte (C8051F206) . . . . . . 46
SFR Definition 6.9. ADC0LTL: ADC Less-Than Data Low Byte (C8051F206) . . . . . . . 47
SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 8.1. CPT0CN: Comparator 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SFR Definition 8.2. CPT1CN: Comparator 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SFR Definition 9.1. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 9.2. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 9.3. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 9.7. SWCINT: Software Controlled Interrupt Register . . . . . . . . . . . . . 75
SFR Definition 9.8. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 9.9. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SFR Definition 9.10. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 80
SFR Definition 9.12. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 9.13. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 9.14. PCON: Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 10.1. PSCTL: Program Store RW Control . . . . . . . . . . . . . . . . . . . . . . 88
SFR Definition 10.2. FLSCL: Flash Memory Timing Prescaler . . . . . . . . . . . . . . . . . . . 89
SFR Definition 10.3. FLACL: Flash Access Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SFR Definition 11.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . . 90
SFR Definition 12.1. WDTCN: Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 12.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 13.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 13.2. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 14.1. PRT0MX: Port I/O MUX Register 0 . . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 14.2. PRT1MX: Port I/O MUX Register 1 . . . . . . . . . . . . . . . . . . . . . . 104
SFR Definition 14.3. PRT2MX: Port I/O MUX Register 2 . . . . . . . . . . . . . . . . . . . . . . 104
Rev. 1.6 9
C8051F2xx
SFR Definition 14.4. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 14.5. PRT0CF: Port0 Configuration Register . . . . . . . . . . . . . . . . . . . 105
SFR Definition 14.6. P0MODE: Port0 Digital/Analog Input Mode . . . . . . . . . . . . . . . . 106
SFR Definition 14.7. P1: Port1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SFR Definition 14.8. PRT1CF: Port1 Configuration Register . . . . . . . . . . . . . . . . . . . 106
SFR Definition 14.9. P1MODE: Port1 Digital/Analog Input Mode . . . . . . . . . . . . . . . . 107
SFR Definition 14.10. P2: Port2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 14.11. PRT2CF: Port2 Configuration Register . . . . . . . . . . . . . . . . . . 107
SFR Definition 14.12. P2MODE: Port2 Digital/Analog Input Mode . . . . . . . . . . . . . . . 108
SFR Definition 14.13. P3: Port3 Register* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 14.14. PRT3CF: Port3 Configuration Register* . . . . . . . . . . . . . . . . . 108
SFR Definition 14.15. P3MODE: Port3 Digital/Analog Input Mode* . . . . . . . . . . . . . . 109
SFR Definition 15.1. SPI0CFG: SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 15.2. SPI0CN: SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SFR Definition 15.3. SPI0CKR: SPI Clock Rate Register . . . . . . . . . . . . . . . . . . . . . . 116
SFR Definition 15.4. SPI0DAT: SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SFR Definition 16.1. SBUF: Serial (UART) Data Buffer . . . . . . . . . . . . . . . . . . . . . . . 123
SFR Definition 16.2. SCON: Serial Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SFR Definition 17.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SFR Definition 17.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SFR Definition 17.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 17.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 17.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 17.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 17.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 17.8. T2CON: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SFR Definition 17.9. RCAP2L: Timer 2 Capture Register Low Byte . . . . . . . . . . . . . . 138
SFR Definition 17.10. RCAP2H: Timer 2 Capture Register High Byte . . . . . . . . . . . . 138
SFR Definition 17.11. TL2: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SFR Definition 17.12. TH2: Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
JTAG Register Definition 18.1. IR: JTAG Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 139
JTAG Register Definition 18.2. FLASHCON: JTAG Flash Control . . . . . . . . . . . . . . . 141
JTAG Register Definition 18.3. FLASHADR: JTAG Flash Address . . . . . . . . . . . . . . 141
JTAG Register Definition 18.4. FLASHDAT: JTAG Flash Data . . . . . . . . . . . . . . . . . 142
JTAG Register Definition 18.5. FLASHSCL: JTAG Flash Scale . . . . . . . . . . . . . . . . . 142
JTAG Register Definition 18.6. DEVICEID: JTAG Device ID . . . . . . . . . . . . . . . . . . . 143
10 Rev. 1.6
C8051F2xx
1. System Overview
The C8051F2xx is a family of fully integrated, mixed-signal System on a Chip MCU's available with a true
12-bit ('F206) multi-channel ADC, 8-bit multi-channel ADC ('F220/1/6 and 'F206), or without an ADC
('F230/1/6). Each model features an 8051-compatible microcontroller core with 8
There are also UART and SPI serial interfaces implemented in hardware (not "bit-banged" in user soft
ware). Products in this family feature 22 or 32 general purpose I/O pins, some of which can be used for
assigned digital peripheral interface. Any pins may be configured for use as analog input to the analog-todigital converter ('F220/1/6 and 'F206 only). (See the Product Selection Guide in
erence of each MCUs' feature set.)
Other features include an on-board VDD monitor, WDT, and clock oscillator. On-board Flash memory can
be reprogrammed in-circuit, and may also be used for non-volatile data storage. Integrated peripherals
can also individually shut down any or all of the peripherals to conserve power. All parts have 256 bytes of
SRAM. Also, an additional 1024 bytes of RAM is available in the 'F206/226/236.
On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debug using the production MCU installed in the final application. This debug system supports inspection
and modification of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt
commands. All analog and digital peripherals are fully functional when emulating using JTAG.
kB of Flash memory.
-
Table 1.1 for a quick ref-
Each MCU is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C) and
is available in the 48-pin TFQP and 32-pin LFQP. The Port I/Os are tolerant for input signals up to 5
V.
Table 1.1. Product Selection Guide
MIPS (Peak)
Flash Memory
C8051F206 25 8 k 1280
C8051F220 25 8 k 256
C8051F221 25 8 k 256
C8051F226 25 8 k 1280
C8051F230 25 8 k 256
C8051F231 25 8 k 256
C8051F236 25 8 k 1280
RAM
SPI
3 3
3 3
3 3
3 3
3 3
3 3
3 3
UART
Timers (16-bit)
Digital Port I/O’s
ADC Resolution (bits)
ADC Max Speed (ksps)
ADC Inputs
Voltage Comparators
3 32 12 100 32 2 48TQFP
3 32 8 100 32 2 48TQFP
3 22 8 100 22 2 32LQFP
3 32 8 100 32 2 48TQFP
3 32 — — — 2 48TQFP
3 22 — — — 2 32LQFP
3 32 — — — 2 48TQFP
Package
Rev. 1.6 11
C8051F2xx
VDD
VDD
GND
GND
TCK
TMS
TDI
TDO
/RST
VDDMONEN
XTAL1
XTAL2
Digital Power
JTAG
Logic
VDD
Monitor,
WDT
External
Oscillator
Circuit
Internal
Oscillator
NC
NC
NC
Emulation HW
Reset
System Clock
8
0
5
1
C
o
r
e
(Available in
'F206/F226)
8kbyte
FLASH
256 byte
SRAM
SFR Bus
Clock & Reset
Configuration
1024 Byte
XRAM
ADC
Config. &
Control
Port I/O Mode
& Config.
Port 0
Latch
UART
Timer 0
Timer 1
Timer 2
Port 1
Latch
CP0
CP1
Comparator
Config.
Port 2
Latch
SPI
Port Mux
Control
Port 3
Latch
P0.0/TX
P
P
0
M
U
X
P
CP0+
CP0-
CP1+
CP1-
VREF
VREF
1
M
U
X
P
2
M
U
X
A
M
AIN0-AIN31
U
X
CP0
CP1
VDD
SAR
ADC
P0.1/RX
0
P0.2//INT0
P0.3//INT1
P0.4/T0
D
P0.5/T1
r
P0.6/T2
v
P0.7/T2EX
P1.0/CP0+
P
P1.1/CP0-
1
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
D
P1.5/CP1
r
P1.6/SYSCLK
v
P1.7
P2.0/SCK
P
P2.1/MISO
2
P2.2/MOSI
P2.3/NSS
P2.4
D
P2.5
r
P2.6
v
P2.7
P3.0
P
P3.1
3
P3.2
P3.3
P3.4
D
P3.5
r
P3.6
v
P3.7
VREF
Figure 1.1. C8051F206, C8051F220 and C8051F226 Block Diagram (48 TQFP)
12 Rev. 1.6
VDD
GND
TCK
TMS
TDI
TDO
/RST
XTAL1
XTAL2
Digital Power
JTAG
Logic
VDD
Monitor,
WDT
External
Oscillator
Circuit
Internal
Oscillator
Emulation HW
Reset
System Clock
8
0
5
1
C
o
r
e
8kbyte
FLASH
256 byte
SRAM
SFR Bus
Clock & Reset
Configuration
CP0
CP1
ADC
Config. &
Control
Port I/O Mode
& Config.
Port 0
Latch
UART
Timer 0
Timer 1
Timer 2
Port 1
Latch
CP0
CP1
Comparator
Config.
Port 2
Latch
SPI
Port Mux
Control
Port 3
Latch
VDD
SAR
ADC
CP0+
CP0-
CP1+
CP1-
VREF
C8051F2xx
AIN0-AIN21
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
VREF
P
0
M
U
X
P
1
M
U
X
P
2
M
U
X
A
M
U
X
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P1.0/CP0+
P1.1/CP0P1.2/CP0
P1.3/CP1+
P1.4/CP1P1.5/CP1
P1.6/SYSCLK
P1.7
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
VREF
Figure 1.2. C8051F221 Block Diagram (32 LQFP)
Rev. 1.6 13
C8051F2xx
Digital Power
VDD
GND
GND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
NC
NC
NC
NC
NC
JTAG
Logic
VDD
Monitor,
WDT
External
Oscillator
Circuit
Internal
Oscillator
Emulation HW
Reset
System Clock
8
0
5
1
C
o
r
e
(Available in
8kbyte
FLASH
256 byte
SRAM
SFR Bus
Clock & Reset
Configuration
1024 Byte
XRAM
'F236)
Port I/O Mode
& Config.
Port 0
Latch
UART
Timer 0
Timer 1
Timer 2
Port 1
Latch
CP0
CP1
Comparator
Config.
Port 2
Latch
SPI
Port Mux
Control
Port 3
Latch
P0.0/TX
P
P
0
M
U
X
P
CP0+
CP0-
CP1+
CP1-
1
M
U
X
P
2
M
U
X
CP0
CP1
P0.1/RX
0
P0.2//INT0
P0.3//INT1
P0.4/T0
D
P0.5/T1
r
P0.6/T2
v
P0.7/T2EX
P1.0/CP0+
P
P1.1/CP0-
1
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
D
P1.5/CP1
r
P1.6/SYSCLK
v
P1.7
P2.0/SCK
P
P2.1/MISO
2
P2.2/MOSI
P2.3/NSS
P2.4
D
P2.5
r
P2.6
v
P2.7
P3.0
P
P3.1
3
P3.2
P3.3
P3.4
D
P3.5
r
P3.6
v
P3.7
Figure 1.3. C8051F230 and C8051F236 Block Diagram (48 TQFP)
14 Rev. 1.6
/RST
XTAL1
XTAL2
VDD
GND
TCK
TMS
TDI
TDO
C8051F2xx
Port I/O Mode
Digital Power
Reset
8
0
5
1
C
o
r
e
8kbyte
FLASH
256 byte
SRAM
SFR Bus
Clock & Reset
Configuration
JTAG
Emulation HW
Logic
VDD
Monitor,
WDT
External
Oscillator
Circuit
Internal
Oscillator
NC
System Clock
& Config.
Port 0
Latch
UART
Timer 0
Timer 1
Timer 2
Port 1
Latch
CP0
CP1
Comparator
Config.
Port 2
Latch
SPI
Port Mux
Control
Port 3
Latch
P0.0/TX
P
P
0
M
U
X
P
CP0+
CP0-
CP1+
CP1-
1
M
U
X
P
2
M
U
X
CP0
CP1
P0.1/RX
0
P0.2//INT0
P0.3//INT1
P0.4/T0
D
P0.5/T1
r
P0.6/T2
v
P0.7/T2EX
P1.0/CP0+
P
P1.1/CP0-
1
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
D
P1.5/CP1
r
P1.6/SYSCLK
v
P1.7
P2.0/SCK
P
P2.1/MISO
2
P2.2/MOSI
P2.3/NSS
P2.4
D
P2.5
r
v
Figure 1.4. C8051F231 Block Diagram (32 LQFP)
1.1. CIP-51TM Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F206, C8051F220/1/6 and C8051F230/1/6 utilize Silcon Labs’ proprietary CIP-51 microcontrol-
ler core. The CIP-51 is fully compatible with the MCS-51TM instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The core contains the peripherals included with a
standard 8052, including three 16-bit counter/timers, a full-duplex UART, 256 bytes of internal RAM, an
optional 1024 bytes of XRAM, 128 byte Special Function Register (SFR) address space, and four bytewide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12
70% of its instructions in one or two system clock cycles, with only four instructions taking more than four
system clock cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to
execute them is as follows:
MHz. By contrast, the CIP-51 core executes
Instructions 26 50 5 14 7 3 1 2 1
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Rev. 1.6 15
C8051F2xx
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5
shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system
clocks.
25
20
15
MIPS
10
5
Silicon Labs
CIP-51
(25 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Philips
80C51
(33 MHz clk)
ADuC812
8051
(16 MHz clk)
Figure 1.5. Comparison of Peak MCU Throughputs
1.1.3. Additional Features
The C8051F206, C8051F220/1/6 and C8051F230/1/6 have several key enhancements both inside and
outside the CIP-51 core to improve overall performance and ease of use in end applications.
The extended interrupt handler provides 22 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. (An interrupt
driven system requires less intervention by the MCU, giving it more effective throughput.) The extra inter
rupt sources are very useful when building multi-tasking, real-time systems.
There are up to six reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing
clock detector, a voltage level detection from Comparator 0, a forced software reset, and an external reset
pin. The
reset to be output on the
(digital 1). The user may disable each reset source except for the
software. The watchdog timer may be permanently enabled in software after a power-on reset during
MCU initialization.
RST pin is bi-directional, accommodating an external reset, or allowing the internally generated
RST pin. The on-board VDD monitor is enabled by pulling the MONEN pin high
V
monitor and Reset Input Pin from
DD
-
The MCU has an internal, stand-alone clock generator that is used by default as the system clock after
reset. If desired, the clock source may be switched "on the fly" to the external oscillator, which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) exter
nal crystal source, while periodically switching to the fast (up to 16MHz) internal oscillator as needed.
16 Rev. 1.6
-
C8051F2xx
System
Clock
Comparator 0
+
-
Missing
Clock
Detector
EN
MCD
Enable
CP0+
CP0- C0RSEF
Figure 1.6. Comparison of Peak MCU Throughputs
WDT
EN
Enable
WDT
PRE
WDT
VDD
Strobe
CIP-51
MonEn
Supply
Monitor
+
-
SWRSF
(Software Reset)
System Reset
Supply
Reset
Timeout
(wired-OR)
Reset
Funnel
/RST
Core
1.2. On-Board Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. An optional 1024 bytes of XRAM is available on the 'F206,
'F226 and 'F236. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
addressing accesses the 128-byte SFR address space. The lower 128 bytes of RAM are accessible via
direct or indirect addressing. The first 32 bytes are addressable as four banks of general purpose regis
ters, and the next 16 bytes can be byte addressable or bit addressable.
The MCU's program memory consists of 8 k + 128 bytes of Flash. This memory may be reprogrammed insystem in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from
addresses 0x1E00 to 0x1FFF are reserved for factory use. There is also a user programmable 128-byte
sector at address 0x2000 to 0x207F, which may be useful as a table for storing software constants, nonvol
atile configuration information, or as additional program space. See Figure 1.7 for the MCU system memory map.
-
-
Rev. 1.6 17
C8051F2xx
0x207F
0x2000
0x1FFF
0x1E00
0x1DFF
0x0000
PROGRAM MEMORY
128 Byte ISP FLASH
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0x3FF
0x000
DATA MEMORY
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
1024 Byte
XRAM
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
Mapped into
External Data Memory
Space
(C8051F226/236/206 only)
Figure 1.7. On-Board Memory Map
1.3. JTAG
The C8051F2xx have on-chip JTAG and debug logic that provide non-intrusive, full speed, in-circuit debug
using the production part installed in the end application using the four-pin JTAG I/F. The C8051F2xxDK is
a development kit with all the hardware and software necessary to develop application code and perform
in-circuit debug with the C8051F2xx. The kit includes software with a developer's studio and debugger, an
integrated 8051 assembler, and an RS-232 to JTAG interface module referred to as the EC. It also has a
target application board with a C8051F2xx installed and large prototyping area, plus the RS-232 and JTAG
cables, and wall-mount power supply. The Development Kit requires a Windows OS (Windows 95 or later)
computer with one available RS-232 serial port. As shown in
to the EC. A six-inch ribbon cable connects the EC to the user's application board, picking up the four
JTAG pins and
20
mA at 2.7–3.6 V. For applications where there is not sufficient power available from the target board,
V
and GND. The EC takes its power from the application board. It requires roughly
DD
the provided power supply can be connected directly to the EC.
This is a vastly superior configuration for developing and debugging embedded applications compared to
standard MCU Emulators, which use on-board "ICE Chips" and target cables and require the MCU in the
application board to be socketed. Silicon Labs' debug environment both increases ease of use, and pre
serves the performance of the precision analog peripherals.
Figure 1.8, the PC is connected via RS-232
-
18 Rev. 1.6
WINDOWS OS
Silicon Labs Integrated
Development Environment
RS-232
JTAG (x4), VDD, GND
SERIAL
ADAPTER
C8051F2xx
VDD GND
C8051
F2XX
TARGET PCB
Figure 1.8. Degub Environment Diagram
1.4. Digital/Analog Configurable I/O
The standard 8051 Ports (0, 1, 2, and 3) are available on the device. The ports behave like standard 8051
ports with a few enhancements.
Each port pin can be configured as either a push-pull or open-drain output. Any input that is configured as
an analog input will have its corresponding weak pull-up turned off.
Digital resources (timers, SPI, UART, system clock, and comparators) are routed to corresponding I/O pins
by configuring the port multiplexer. Port multiplexers are programmed by setting bits in SFR's (please see
Section 14). Any of the 32 external port pins may be configured as either analog inputs or digital I/O (See
Figure 1.9), so effectively, all port pins are dual function.
Rev. 1.6 19
C8051F2xx
T0,T1,T2
Timers
UART
External
INT0 & INT1
Comparators
0 & 1
SYSCLK
SPI
ADC
A
M
U
X
PRTnMX
Registers
Port
0
MUX
Port
1
MUX
Port
2
MUX
PRTnCF &
PnMODE
registers
Port0 I/O Cell
Port1 I/O Cell
Port2 I/O Cell
Port3 I/O Cell
External
pins
P0.0/TX
P0.1/RX
P0.2/INT0
P0.3/INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P1.0/CP0+
P1.1/CP0P1.2/CP0
P1.3/CP1+
P1.4/CP1P1.5/CP1
P1.6/SYSCLK
P1.7
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Any port pin may be
configured via software as an
analog input to the ADC
Figure 1.9. Port I/O Functional Block Diagram
1.5. Serial Ports
The C8051F206, C8051F220/1/6 and C8051F230/1/6 include a Full-Duplex UART and SPI Bus. Each of
the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus
requiring very little intervention by the CPU. The serial buses do not have to "share" resources such as
timers, interrupts, or Port I/O, so both of the serial buses may be used simultaneously. (You may use
Timer1, Timer 2, or SYSCLK to generate baud rates for UART).
1.6. Analog to Digital Converter
The C8051F220/1/6 has an on-chip 8-bit SAR ADC and the C8051F206 has a 12-bit SAR ADC with a programmable gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 8-bit with an INL of
V
±1/4 LSB, and or 12-bit accuracy with ±2 LSB. The voltage reference can be the power supply (
an external reference voltage (VREF). Also, the system controller can place the ADC into a power-saving
shutdown mode when not in use. A programmable gain amplifier follows the analog multiplexer. The gain
can be set in software from 0.5 to 16 in powers of 2.
Conversions can be initiated in two ways; a software command or an overflow on Timer 2. This flexibility
allows the start of conversion to be triggered by software events, or convert continuously. A completed
conversion causes an interrupt, or a status bit can be polled in software to determine the end of conver
sion. The resulting 8-bit data word is latched into an SFR upon completion of a conversion.
DD
), or
-
20 Rev. 1.6
C8051F2xx
ADC data is continuously monitored by a programmable window detector, which interrupts the CPU when
data is within the user-programmed window. This allows the ADC to monitor key system voltages in back
ground mode, without the use of CPU resources.
VREF
-
AIN0
AIN1
AIN0-31 are port 0-3
pins -- any external
port pin may be configured as
an analog input
(only 22 input port pins on
'F221)
AIN31
32-to-1
. . .
AMUX
X
Figure 1.10. ADC Diagram
Programmable
Gain Amp
+
-
GND
Control & Data
SFR's
VDD
100ksps
SAR
ADC
SFR Bus
1.7. Comparators
The MCU's have two on-chip voltage comparators. The inputs of the comparators are available at package pins as illustrated in Figure 1.11. Each comparator's hysteresis is software programmable via special
function registers (SFR's). Both voltage level and positive/negative going symmetry can be easily programmed by the user. Additionally, comparator interrupts can be implemented on either rising or fallingedge output transitions. Please see
8.‘Comparators” on page 52 for details.
Rev. 1.6 21
C8051F2xx
P1.2
P1.5
P1.0
P1.1
P1.3
P1.4
CP0
CP1
+
Port1
MUX
CP0
-
+
CP1
-
CP0
CP1
SFR's
(Data
and
Cntrl)
Figure 1.11. Comparator Diagram
CIP-51
and
Interrupt
Handler
22 Rev. 1.6
2. Absolute Maximum Ratings
C8051F2xx
Table 2.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Ambient Temperature under Bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on any Pin (except V
respect to DGND
Voltage on any Port I/O Pin or RST
DGND
Voltage on V
Total Power Dissipation — 1.0 800 W
Maximum Output Current Sunk by any Port pin — — 200 mA
Maximum Output Current Sunk by any other I/O pin — — 25 mA
Maximum Output Current Sourced by any Port pin — — 200 mA
Maximum Output Current Sourced by any other I/O pin — — 25 mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
with respect to DGND –0.3 4.2 V
DD
and Port I/O) with
DD
pins with respect to
*
–0.3 — VDD +
0.3
–0.3 — 5.8 V
V
Rev. 1.6 23
C8051F2xx
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Analog Supply Voltage
V
supply current with ADC and
DD
1
comparators active, and CPU
active
V
supply current with ADC and
DD
comparators active, and CPU inactive (Idle Mode)
V
supply current with ADC and
DD
comparators inactive, and CPU
active
Digital Supply Current with CPU
inactive (Idle Mode)
Digital Supply Current (Stop Mode),
V
monitor enabled
DD
Digital Supply Current (Stop Mode),
monitor disabled
V
DD
Digital Supply RAM Data Retention
Voltage
2.7 3.0 3.6 V
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz
—13
1.5
300
—9
1.8
275
—12.5
1.0
25
—8.5
1.4
25
—mA
mA
µA
—mA
mA
µA
—mA
mA
µA
—mA
mA
µA
Oscillator not running — 10 — µA
Oscillator not running — 0.1 — µA
—1.5— V
Specified Operating Temperature
–40 — +85 °C
Range
SYSCLK (system clock
frequency)
2
0
—
25 MHz
Tsysl (SYSCLK low time) 18 — — ns
Tsysh (SYSCLK high time) 18 — — ns
Notes:
1. Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.
2. SYSCLK must be at least 32 kHz to enable debugging.
24 Rev. 1.6
C8051F2xx
4. Pinout and Package Definitions
Table 4.1. Pin Definitions
‘F206,
F220,
Name
226,
230,
236
48-Pin 32-Pin
V
DD
11,31 8 Digital Voltage Supply.
GND 5,6,8,
13,32
MONEN 12 D In Monitor Enable (on 48 pin package ONLY). Enables reset volt-
TCK 25 17 D In JTAG Test Clock with internal pull-up.
TMS 26 18 D In JTAG Test-Mode Select with internal pull-up.
TDI 28 20 D In JTAG Test Data Input with internal pull-up. TDI is latched on a
TDO 27 19 D Out JTAG Test Data Output. Data is shifted out on TDO on the falling
XTAL1 9 6 A In Crystal Input. This pin is the return for the internal oscillator cir-
XTAL2 10 7 A Out Crystal Output. This pin is the excitation driver for a crystal or
RST
14 10 D I/O Chip Reset. Open-drain output of internal Voltage Supply moni-
VREF 7 5 A I/O Voltage Reference. When configured as an input, this pin is the
CP0+ 4 4 A In Comparator 0 Non-Inverting Input.
CP0- 3 3 A In Comparator 0 Inverting Input.
CP0 2 2 D Out Comparator 0 Output
CP1+ 1 1 A In Comparator 1 Non-Inverting Input.
CP1- 48 32 A In Comparator 1 Inverting Input.
CP1 47 31 D Out Comparator 1 Output
P0.0/TX 40 28 D I/O
P0.1/RX 39 27 D I/O
P0.2/INT0 38 26 D I/O
‘F221,
231
Type Description
9 Ground. (Note: Pins 5,6, and 8 on the 48-pin package are not
connected (NC), but it is recommended that they be connected to
ground.)
age monitor function when pulled high (logic “1”).
rising edge of TCK.
edge of TCK. TDO output is a tri-state driver.
cuit for a crystal or ceramic resonator. For a precision internal
clock, connect a crystal or ceramic resonator from XTAL1 to
XTAL2. If overdriven by an external CMOS clock, this becomes
the system clock.
ceramic resonator.
tor. Is driven low when VDD is < 2.7V and MONEN=1, or when a
‘1’is written to PORSF. An external source can force a system
reset by driving this pin low.
voltage reference for the ADC. Otherwise, V
will be the refer-
DD
ence. NOTE: this pin is Not Connected (NC) on ‘F230/1/6.
Port0 Bit0. (See the Port I/O Sub-System section for complete
A In
description).
Port0 Bit1. (See the Port I/O Sub-System section for complete
A In
description).
Port0 Bit2. (See the Port I/O Sub-System section for complete
A In
description).
Rev. 1.6 25
C8051F2xx
Table 4.1. Pin Definitions (Continued)
‘F206,
F220,
Name
226,
230,
236
48-Pin 32-Pin
P0.3/INT1 37 25 D I/O
P0.4/T0 36 24 D I/O
P0.5/T1 35 23 D I/O
P0.6/T2 34 22 D I/O
P0.7/T2EX 33 21 D I/O
P1.0/CP0+ 4 4 D I/O
P1.1/CP0- 3 3 D I/O
P1.2/CP0 2 2 D I/O
P1.3/CP1+ 1 1 D I/O
P1.4/CP1- 48 32 D I/O
P1.5/CP1 47 31 D I/O
P1.6/SYSCLK 46 30 D I/O
P1.7 45 29 D I/O
P2.0/SCK 24 16 D I/O
P2.1/MISO 23 15 D I/O
P2.2/MOSI 22 14 D I/O
P2.3/NSS 21 13 D I/O
P2.4 15 11 D I/O
P2.5 16 12 D I/O
P2.6 17 D I/O
‘F221,
231
Type Description
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port0 Bit3. (See the Port I/O Sub-System section for complete
description).
Port0 Bit4. (See the Port I/O Sub-System section for complete
description).
Port0 Bit5. (See the Port I/O Sub-System section for complete
description).
Port0 Bit6. (See the Port I/O Sub-System section for complete
description).
Port0 Bit7. (See the Port I/O Sub-System section for complete
description).
Port1 Bit0. (See the Port I/O Sub-System section for complete
description).
Port1 Bit1. (See the Port I/O Sub-System section for complete
description).
Port1 Bit2. (See the Port I/O Sub-System section for complete
description).
Port1 Bit3. (See the Port I/O Sub-System section for complete
description).
Port1 Bit4. (See the Port I/O Sub-System section for complete
description).
Port1 Bit5. (See the Port I/O Sub-System section for complete
description).
Port1 Bit6. (See the Port I/O Sub-System section for complete
description).
Port1 Bit7. (See the Port I/O Sub-System section for complete
description).
Port2 Bit0. (See the Port I/O Sub-System section for complete
description).
Port2 Bit1. (See the Port I/O Sub-System section for complete
description).
Port2 Bit2. (See the Port I/O Sub-System section for complete
description).
Port2 Bit3. (See the Port I/O Sub-System section for complete
description).
Port2 Bit4. (See the Port I/O Sub-System section for complete
description).
Port2 Bit5. (See the Port I/O Sub-System section for complete
description).
Port2 Bit6. (See the Port I/O Sub-System section for complete
description).
26 Rev. 1.6
Table 4.1. Pin Definitions (Continued)
‘F206,
F220,
Name
226,
230,
236
48-Pin 32-Pin
P2.7 18 D I/O
P3.0 44 D I/O
P3.1 43 D I/O
P3.2 42 D I/O
P3.3 41 D I/O
P3.4 30 D I/O
P3.5 29 D I/O
P3.6 20 D I/O
P3.7 19 D I/O
‘F221,
231
Type Description
A In
A In
A In
A In
A In
A In
A In
A In
A In
C8051F2xx
Port2 Bit7. (See the Port I/O Sub-System section for complete
description).
Port3 Bit0. (See the Port I/O Sub-System section for complete
description).
Port3 Bit1. (See the Port I/O Sub-System section for complete
description).
Port3 Bit2. (See the Port I/O Sub-System section for complete
description).
Port3 Bit3. (See the Port I/O Sub-System section for complete
description).
Port3 Bit4. (See the Port I/O Sub-System section for complete
description).
Port3 Bit5. (See the Port I/O Sub-System section for complete
description).
Port3 Bit6. (See the Port I/O Sub-System section for complete
description).
Port3 Bit7. (See the Port I/O Sub-System section for complete
description).
Rev. 1.6 27
C8051F2xx
P1.4/CP1-
48
P0.2/INT0
P3.1
P3.2
P3.0
44
43
P3.3
42
41
P0.1/RX
P0.0/TX
40
39
46
P1.6/SYSCLK
P1.7
45
P1.5/CP1
47
P0.3/INT1
38
37
P1.3/CP1+
P1.2/CP0
P1.1/CP0-
P1.0/CP0+
NC
NC
VREF*
NC
XTAL1
XTAL2
VDD
MONEN
1
2
3
4
5
6
7
8
9
10
11
12
C8051F220/6
C8051F230/6
C8051F206
*Pin 7 is a No Connect on
36
35
34
33
32
31
30
29
28
27
26
25
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
GND
VDD
P3.4
P3.5
TDI
TDO
TMS
TCK
'F230/6
13
14
15
16
17
18
19
20
21
22
23
24
P2.5
P2.4
/RST
GND
P2.6
P3.7
P2.7
P3.6
P2.3/NSS
P2.2/MOSI
P2.0/SCK
P2.1/MISO
Figure 4.1. TQFP-48 Pin Diagram
28 Rev. 1.6
P1.4/CP1-
32
P1.5/CP1
31
P1.6/SYSCLK
30
P1.7
29
P0.0/TX
28
P0.1/RX
27
P0.2/INT0
26
C8051F2xx
P0.3/INT1
25
P1.3/CP1+
P1.2/CP0
P1.1/CP0-
P1.0/CP0+
VREF*
XTAL1
XTAL2
VDD
1
2
3
4
5
C8051F221
C8051F231
6
7
8
*Pin 5 is a No Connect
24
23
22
21
20
19
18
17
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
TDI
TDO
TM
S
TCK
(NC) on 'F231
9
10
11
12
13
14
15
16
P2.5
GND
P2.4
RESTB
P2.3/NSS
P2.2/MOSI
P2.0/SCK
P2.1/MISO
Figure 4.2. LQFP-32 Pin Diagram
Rev. 1.6 29
C8051F2xx
48
PIN 1
IDENTIFIER
A2
D
D1
E1
E
1
e
A
A
A1
A2
b
D
D1
e
E
MIN
(mm)
-
0.05
0.95
0.17
-
-
-
-
NOM
(mm)
-
-
1.00
0.22
9.00
7.00
0.50
9.00
MAX
(mm)
1.20
0.15
1.05
0.27
-
-
-
-
A1
E1
b
Figure 4.3. TQFP-48 Package Drawing
-
7.00
-
30 Rev. 1.6
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