Figure 9.8. B: B Register.................................................................................................................................64
The C8051F2xx is a family of fully integrated, mixed-signal System on a Chip MCU’s available with a true 8-bit
multi-channel ADC (‘F220/1/6 and ‘F206), or without an ADC (‘F230/1/6).Each model features an 8051compatible microcontroller core with 8kbytes of FLASH memory. There are also UART and SPI serial interfaces
implemented in hardware (not “bit-banged” in user software). Products in this family feature 22 or 32 general
Page 5CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
purpose I/O pins, some of which can be used for assigned digital peripheral interface. Any pins may be configured
for use as analog input to the analog-to-digital converter (‘F220/1/6 and ‘F206 only). (See the Product Selection
Guide in Table 1.1.1 for a quick reference of each MCUs’ feature set.)
Other features include an on-board VDD monitor, WDT, and clock oscillator. On-board FLASH memory can be
reprogrammed in-circuit, and may also be used for non-volatile data storage.Integrated peripherals can also
individually shut down any or all of the peripherals to conserve power. All parts have 256 bytes of SRAM. Also, an
additional 1024 bytes of RAM is available in the ‘F226/’F236.
On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit debug usingthe production MCU installed in the final application. This debug system supports inspection and modification of
memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and
digital peripherals are fully functional when emulating using JTAG.
Each MCU is specified for 2.7V to 3.6V operation over the industrial temperature range (-45C to +85C) and is
available in the 48-pin TFQP and 32-pin LFQP. The Port I/Os are tolerant for input signals up to 5V.
Table 1.1.1. Product Selection Guide
Part Number
C8051F206258k1280
C8051F220258k256
C8051F221258k256
C8051F226258k1280
C8051F230258k256
C8051F231258k256
C8051F236258k1280
MIPS (Peak)
FLASH Memory
RAM
√√
√√
√√
√√
√√
√√
√√
SPI
UART
Timers (16-bit)
Digital Port I/O’s
ADC Resolution (bits)
ADC Max Speed (ksps)
ADC Inputs
Voltage Comparators
3321210032248TQFP
332810032248TQFP
322810022232LQFP
332810032248TQFP
332---248TQFP
322---232LQFP
332---248TQFP
Package
Page 6CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
VDD
VDD
GND
GND
TCK
TMS
TDI
TDO
/RST
VDDMONEN
XTAL1
XTAL2
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 1.1. C8051F206, C8051F220 and C8051F226 Block Diagram (48 TQFP)
Page 10CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
1.1.CIP-51TMMicrocontroller Core
1.1.1.Fully 8051 Compatible
The C8051F206, C8051F220/1/6 and C8051F230/1/6 utilize Cygnal’s proprietary CIP-51 microcontroller core. The
CIP-51 is fully compatible with the MCS-51
used to develop software. The core contains the peripherals included with a standard 8052, including three 16-bit
counter/timers, a full-duplex UART, 256 bytes of internal RAM, an optional 1024 bytes of XRAM, 128 byte Special
Function Register (SFR) address space, and four byte-wide I/O Ports.
1.1.2.Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its instructions in
one or two system clock cycles, with only four instructions taking more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:
TM
instruction set. Standard 803x/805x assemblers and compilers can be
Instructions
Clocks to Execute
265051473121
122/333/444/558
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.5 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.5. Comparison of Peak MCU Throughputs
25
20
15
MIPS
10
5
Cygnal
CIP-51
(25MHz clk)
Microchip
PIC17C75x
(33MHz clk)
Philips
80C51
(33MHz clk)
ADuC812
8051
(16MHz clk)
Page 11CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
1.1.3.Additional Features
The C8051F206, C8051F220/1/6 and C8051F230/1/6 have several key enhancements both inside and outside the
CIP-51 core to improve overall performance and ease of use in end applications.
The extended interrupt handler provides 22 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051),
allowing the numerous analog and digital peripherals to interrupt the controller. (An interrupt driven system requires
less intervention by the MCU, giving it more effective throughput.) The extra interrupt sources are very useful when
building multi-tasking, real-time systems.
There are up to six reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock
detector, a voltage level detection from Comparator 0, a forced software reset, and an external reset pin. The /RST
pin is bi-directional, accommodating an external reset, or allowing the internally generated reset to be output on the
/RST pin. The on-board VDD monitor is enabled by pulling the MONEN pin high (digital 1). The user may disable
each reset source except for the VDD monitor and Reset Input Pin from software. The watchdog timer may be
permanently enabled in software after a power-on reset during MCU initialization.
The MCU has an internal, stand-alone clock generator that is used by default as the system clock after reset. If
desired, the clock source may be switched “on the fly” to the external oscillator, which can use a crystal, ceramic
resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low
power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically
switching to the fast (up to 16MHz) internal oscillator as needed.
CP0+
CP0-
System
Clock
Comparator 0
+
-
Missing
Clock
Detector
EN
MCD
Enable
Figure 1.6. On-Board Clock and Reset
C0RSEF
VDD
WDT
PRE
EN
WDT
WDT
Enable
Strobe
CIP-51
MonEn
Supply
Monitor
+
-
SWRSF
(Software Reset)
System Reset
Core
Supply
Reset
Timeout
(wired-OR)
Reset
Funnel
/RST
Page 12CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
1.2.On-Board Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with
the upper 128 bytes dual-mapped. An optional 1024 bytes of XRAM is available on the ‘F206, ‘F226 and ‘F236.
Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128byte SFR address space. The lower 128 bytes of RAM are accessible via direct or indirect addressing. The first 32
bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit
addressable.
The MCU’s program memory consists of 8k + 128 bytes of FLASH. This memory may be reprogrammed in-system
in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses 0x1E00 to
0x1FFF are reserved for factory use. There is also a user programmable 128-byte sector at address 0x2000 to
0x207F, which may be useful as a table for storing software constants, nonvolatile configuration information, or as
additional program space. See Figure 1.7 for the MCU system memory map.
Figure 1.7. On-Board Memory Map
0x207F
0x2000
0x1FFF
0x1E00
0x1DFF
0x0000
PROGRAM MEMORY
128 Byte ISP FLASH
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0x3FF
0x000
DATA MEMORY
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
1024 Byte
XRAM
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
Mapped into
External Data Memory
Space
(C8051F226/236/206 only)
Page 13CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
1.3.JTAG
The C8051F2xx have on-chip JTAG and debug logic that provide non-intrusive, full speed, in-circuit debug using
the production part installed in the end application using the four-pin JTAG I/F.The C8051F2xxDK is a
development kit with all the hardware and software necessary to develop application code and perform in-circuit
debug with the C8051F2xx. The kit includes software with a developer’s studio and debugger, an integrated 8051
assembler, and an RS-232 to JTAG interface module referred to as the EC. It also has a target application board
with a C8051F2xx installed and large prototyping area, plus the RS-232 and JTAG cables, and wall-mount power
supply. The Development Kit requires a Windows 9x, NT, or ME computer with one available RS-232 serial port.
As shown in Figure 1.8, the PC is connected via RS-232 to the EC. A six-inch ribbon cable connects the EC to the
user’s application board, picking up the four JTAG pins and VDD and GND. The EC takes its power from the
application board. It requires roughly 20mA at 2.7-3.6V. For applications where there is not sufficient power
available from the target board, the provided power supply can be connected directly to the EC.
This is a vastly superior configuration for developing and debugging embedded applications compared to standard
MCU Emulators, which use on-board “ICE Chips” and target cables and require the MCU in the application board to
be socketed. Cygnal’s debug environment both increases ease of use, and preserves the performance of the precision
analog peripherals.
Figure 1.8. Debug Environment Diagram
WINDOWS 95/98/NT/ME
CYGNAL Integrated
Development Environment
RS-232
EMULATION
CARTRIDGE
JTAG(x4),VDD,GND
VDD GND
C8051
F2XX
TARGET PCB
Page 14CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
1.4.Digital/Analog Configurable I/O
The standard 8051 Ports (0, 1, 2, and 3) are available on the device. The ports behave like standard 8051 ports with
a few enhancements.
Each port pin can be configured as either a push-pull or open-drain output. Any input that is configured as an analog
input will have its corresponding weak pull-up turned off.
Digital resources (timers, SPI, UART, system clock, and comparators) are routed to corresponding I/O pins by
configuring the port multiplexer. Port multiplexers are programmed by setting bits in SFR’s (please see Section 14).
Any of the 32 external port pins may be configured as either analog inputs or digital I/O (See Figure 1.9), so
effectively, all port pins are dual function.
The C8051F206, C8051F220/1/6 and C8051F230/1/6 include a Full-Duplex UART and SPI Bus. Each of the serial
buses is fully implemented in hardware and makes extensive use of the CIP-51’s interrupts, thus requiring very little
intervention by the CPU. The serial buses do not have to “share” resources such as timers, interrupts, or Port I/O, so
both of the serial buses may be used simultaneously. (You may use Timer1, Timer 2, or SYSCLK to generate baud
rates for UART).
Page 15CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
1.6.Analog to Digital Converter
The C8051F220/1/6 has an on-chip 8-bit SAR ADC and the C8051F206 has a 12-bit SAR ADC with a
programmable gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 8-bit with an INL of
±1/4 LSB, and or 12-bit accuracy with ±2 LSB. The voltage reference can be the power supply (VDD), or an
external reference voltage (VREF). Also, the system controller can place the ADC into a power-saving shutdown
mode when not in use. A programmable gain amplifier follows the analog multiplexer. The gain can be set in
software from 0.5 to 16 in powers of 2.
Conversions can be initiated in two ways; a software command or an overflow on Timer 2. This flexibility allows
the start of conversion to be triggered by software events, or convert continuously. A completed conversion causes
an interrupt, or a status bit can be polled in software to determine the end of conversion. The resulting 8-bit data
word is latched into an SFR upon completion of a conversion.
ADC data is continuously monitored by a programmable window detector, which interrupts the CPU when data is
within the user-programmed window. This allows the ADC to monitor key system voltages in background mode,
without the use of CPU resources.
Figure 1.10. ADC Diagram
VREF
AIN0
AIN1
AIN0-31 are port 0-3
pins -- any external
port pin may be configured as
an analog input
(only 22 input port pins on
'F221)
AIN31
...
32-to-1
AMUX
Programmable
Gain Amp
+
X
-
GND
Control & Data
SFR's
VDD
100ksps
SAR
ADC
SFR Bus
Page 16CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
1.7.Comparators
The MCU’s have two on-chip voltage comparators. The inputs of the comparators are available at package pins as
illustrated in Figure 1.11. Each comparator’s hysteresis is software programmable via special function registers
(SFR’s). Both voltage level and positive/negative going symmetry can be easily programmed by the user.
Additionally, comparator interrupts can be implemented on either rising or falling-edge output transitions. Please
see section 8 for details.
Figure 1.11. Comparator Diagram
P1.2
P1.5
P1.0
P1.1
P1.3
P1.4
CP0
CP1
+
CP0
-
+
CP1
-
Port1
MUX
CP0
CP1
SFR's
(Data
and
Cntrl)
CIP-51
and
Interrupt
Handler
Page 17CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
2.ABSOLUTE MAXIMUM RATINGS*
Ambient temperature under bias................................................................................................................. -55 to 125°C
Storage Temperature .................................................................................................................................. -65 to 150°C
Voltage on any Pin (except VDD and Port I/O) with respect to DGND ................................... -0.3V to (VDD + 0.3V)
Voltage on any Port I/O Pin or /RST with respect to DGND .................................................................... -0.3V to 5.8V
Voltage on VDD with respect to DGND ................................................................................................... -0.3V to 4.2V
Total Power Dissipation ......................................................................................................................................... 1.0W
Maximum output current sink by any Port pin .................................................................................................... 200mA
Maximum output current sink by any other I/O pin............................................................................................... 25mA
Maximum output current sourced by any Port pin............................................................................................... 200mA
Maximum output current sourced by any other I/O pin......................................................................................... 25mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
3.GLOBAL DC ELECTRICAL CHARACTERISTICS
-40°Cto+85°C unless otherwise specified.
PARAMETERCONDITIONSMINTYPMAXUNITS
Power supply voltage(Note 1)2.73.6V
VDD supply current with
ADC and comparators
active, and CPU active
VDD supply current with
ADC and comparators
active, and CPU inactive
(Idle Mode).
VDD supply current with
ADC and comparators
inactive, and CPU active
Digital Supply Current with
CPU inactive (Idle Mode)
Digital Supply Current (Stop
mode), VDD monitor
enabled.
Digital Supply Current (Stop
Mode), VDD monitor
disabled
Digital Supply RAM Data
Retention Voltage
Specified Operating
Temperature Range
Clock=25MHz
Clock=1MHz
Clock=32kHz
Clock=25MHz
Clock=1MHz
Clock=32kHz
Clock=25MHz
Clock=1MHz
Clock=32kHz
Clock=25MHz
Clock=1MHz
Clock=32kHz
Oscillator not running10
Oscillator not running0.1
-40+85
9.5
3.6
125
1.8
125
20
4.5
0.1
10
1.5V
mA
µA
5
9
1
mA
µA
mA
µA
mA
µA
µA
µA
°C
Note 1: Power Supply must be greater than 1V and the MONEN pin must be pulled high for VDD monitor to
operate.
Page 18CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
Ground. (Note: Pins 5,6, and 8 on the 48-pin package are not connected
(NC), but it is recommended that they be connected to ground.)
Monitor Enable (on 48 pin package ONLY). Enables reset voltage monitor
function when pulled high (logic “1”).
JTAG Test Clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of
TCK.
JTAG Test Data Output. Data is shifted out on TDO on the falling edge of
TCK. TDO output is a tri-state driver.
Crystal Input. This pin is the return for the internal oscillator circuit for a
crystal or ceramic resonator. For a precision internal clock, connect a crystal
or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external
CMOS clock, this becomes the system clock.
Crystal Output. This pin is the excitation driver for a crystal or ceramic
resonator.
Chip Reset. Open-drain output of internal Voltage Supply monitor. Is driven
low when VDD is < 2.7V and MONEN=1, or when a ‘1’is written to PORSF.
An external source can force a system reset by driving this pin low.
Voltage Reference. When configured as an input, this pin is the voltage
reference for the ADC. Otherwise, VDD will be the reference. NOTE: this
pin is Not Connected (NC) on ‘F230/1/6.
Comparator 0 Non-Inverting Input.
Comparator 0 Inverting Input.
Comparator 0 Output
Comparator 1 Non-Inverting Input.
Comparator 1 Inverting Input.
Comparator 1 Output
Port0 Bit0. (See the Port I/O Sub-System section for complete description).
Port0 Bit1. (See the Port I/O Sub-System section for complete description).
Port0 Bit2. (See the Port I/O Sub-System section for complete description).
Port0 Bit3. (See the Port I/O Sub-System section for complete description).
Port0 Bit4. (See the Port I/O Sub-System section for complete description).
Port0 Bit5. (See the Port I/O Sub-System section for complete description).
Port0 Bit6. (See the Port I/O Sub-System section for complete description).
Port0 Bit7. (See the Port I/O Sub-System section for complete description).
Port1 Bit0. (See the Port I/O Sub-System section for complete description).
Page 19CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
Port1 Bit1. (See the Port I/O Sub-System section for complete description).
Port1 Bit2. (See the Port I/O Sub-System section for complete description).
Port1 Bit3. (See the Port I/O Sub-System section for complete description).
Port1 Bit4. (See the Port I/O Sub-System section for complete description).
Port1 Bit5. (See the Port I/O Sub-System section for complete description).
Port1 Bit6. (See the Port I/O Sub-System section for complete description).
Port1 Bit7. (See the Port I/O Sub-System section for complete description).
Port2 Bit0. (See the Port I/O Sub-System section for complete description).
Port2 Bit1. (See the Port I/O Sub-System section for complete description).
Port2 Bit2. (See the Port I/O Sub-System section for complete description).
Port2 Bit3. (See the Port I/O Sub-System section for complete description).
Port2 Bit4. (See the Port I/O Sub-System section for complete description).
Port2 Bit5. (See the Port I/O Sub-System section for complete description).
Port2 Bit6. (See the Port I/O Sub-System section for complete description).
Port2 Bit7. (See the Port I/O Sub-System section for complete description).
Port3 Bit0. (See the Port I/O Sub-System section for complete description).
Port3 Bit1. (See the Port I/O Sub-System section for complete description).
Port3 Bit2. (See the Port I/O Sub-System section for complete description).
Port3 Bit3. (See the Port I/O Sub-System section for complete description).
Port3 Bit4. (See the Port I/O Sub-System section for complete description).
Port3 Bit5. (See the Port I/O Sub-System section for complete description).
Port3 Bit6. (See the Port I/O Sub-System section for complete description).
Port3 Bit7. (See the Port I/O Sub-System section for complete description).
C8051F206
C8051F220/1/6
Page 20CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
Figure 4.1 TQFP-48 Pin Diagram
P1.4/CP1-
P1.5/CP1
48
47
P1.7
P1.6/SYSCLK
46
45
P3.1
P3.0
44
P3.2
P3.3
43
42
41
C8051F206
C8051F220/1/6
P0.2/INT0
P0.1/RX
P0.0/TX
40
39
P0.3/INT1
38
37
P1.3/CP1+
P1.2/CP0
P1.1/CP0-
P1.0/CP0+
NC
NC
VREF*
NC
XTAL1
XTAL2
VDD
MONEN
1
2
3
4
5
6
7
8
9
10
11
12
C8051F220/6
C8051F230/6
C8051F206
*Pin 7 is a No Connect on
36
35
34
33
32
31
30
29
28
27
26
25
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
GND
VDD
P3.4
P3.5
TDI
TDO
TMS
TCK
'F230/6
13
14
15
16
17
18
19
20
21
22
23
24
P2.5
P2.4
/RST
GND
P2.6
P3.7
P2.7
P3.6
P2.3/NSS
P2.2/MOSI
P2.0/SCK
P2.1/MISO
Page 21CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
Figure 4.2 LQFP-32 Pin Diagram
P0.1/RX
P1.4/CP1-
32
P1.5/CP1
31
P1.6/SYSCLK
30
P1.7
29
P0.0/TX
28
27
P0.2/INT0
26
C8051F206
C8051F220/1/6
P0.3/INT1
25
P1.3/CP1+
P1.2/CP0
P1.1/CP0-
P1.0/CP0+
VREF*
XTAL1
XTAL2
VDD
1
2
3
4
5
6
7
8
9
GND
C8051F221
C8051F231
*Pin 5 is a No Connect
(NC) on 'F231
10
11
12
13
P2.5
P2.4
RESTB
P2.3/NSS
14
P2.2/MOSI
15
P2.1/MISO
16
P2.0/SCK
24
23
22
21
20
19
18
17
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
TDI
TDO
TMS
TCK
Page 22CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
Figure 4.3 TQFP-48 Package Drawing
C8051F206
C8051F220/1/6
48
PIN 1
IDENTIFIER
A2
D
D1
E1
E
1
e
A
A
A1
A2
b
D
D1
e
E
MIN
(mm)
-
0.05
0.95
0.17
-
-
-
-
NOM
(mm)
-
-
1.00
0.22
9.00
7.00
0.50
9.00
MAX
(mm)
1.20
0.15
1.05
0.27
-
-
-
-
E1
A1
b
-
7.00
-
Page 23CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
Figure 4.4 LQFP-32 Package Drawing
D
D1
A
A1
C8051F206
C8051F220/1/6
MIN
NOM
(mm)
0.05
(mm)
-
MAX
(mm)
-
1.60
-
0.15
32
PIN 1
IDENTIFIER
A2
E1
1
E
A
A1
A2
b
D
D1
e
E
E1
1.35
0.30
-
-
-
-
-
1.40
0.37
9.00
7.00
0.80
9.00
7.00
1.45
0.45
-
-
-
-
-
eb
Page 24CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
5.ADC (8-Bit, C8051F220/1/6 Only)
Description
The ADC subsystem for the C8051F220/1/6 consists of configurable analog multiplexer (AMUX), a programmable
gain amplifier (PGA), and a 100ksps, 8-bit successive-approximation-register ADC with integrated track-and-hold
and programmable window detector (see Figure 5.1). The AMUX, PGA, Data Conversion Modes, and Window
Detector are all configurable under software control via the Special Function Register’s shown in Figure 5.1. The
ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the ADCEN bit in the ADC Control register
(ADC0CN, Figure 5.5) is set to 1. The ADC subsystem is in low power shutdown when this bit is 0.
Figure 5.1. 8-Bit ADC Functional Block Diagram
AIN0-31 are port 0-3
pins -- any external
port pin may be configured as an
analog input
AIN0
AIN31
...
32-to-1
AMUX
X
AMXEN
PRTSL0
PRTSL1
AMX0SL
GND
PINSL2
+
ADCEN
VDD
VDD
8-Bit
SAR
ADC0LTHADC0GTH
VDDVREF
SYSCLK
REF
8
16
ADC0H
Dig
Comp
ADWINT
8
-
ADC
GND
PINSL0
PINSL1
ADCSC0
ADCSC1
ADCSC2
ADC0CF
AMPGN2
AMPGN1
AMPGN0
ADCEN
ADCTM
ADCINT
ADC0CN
ADBUSY
ADLJST
ADWINT
ADSTM0
ADSTM1
Conversion Start
T2 OV
S
Y
U
B
D
A
)
w
(
5.1.Analog Multiplexer and PGA
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the desired
analog input pin. (See Figure 5.3). When the AMUX is enabled, the user selects which port is to be used (bits
PRTSL0-1), and then the pin in the selected port (bits PINSL0-2) to be the analog input.
The table in shows AMUX functionality by channel for each possible configuration. The PGA amplifies the AMUX
output signal by an amount determined by the states of the AMPGN2-0 bits in the ADC Configuration register,
ADC0CF (Figure 5.4). The PGA can be software-programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain
of 1 on reset.
5.2.ADC Modes of Operation
The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the system
clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of 1,2,4,8, or 16 are
supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to
accommodate different system clock speeds.
Page 25CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the ADC0CN register.
Converted data is available in the ADC data word register, ADC0H.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of two different low
power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1.Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2.Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing
CNVSTR
(ADSTM[1:0]=10)
SAR Clocks
ADCTM=1
ADCTM=0
Timer2, Timer3 Overflow;
Write1toADBUSY
(ADSTM[1:0]=00, 01, 11)
SAR Clocks
ADCTM=1
SAR Clocks
ADCTM=0
A. ADC Timing for External Trigger Source
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Low Power or
Convert
TrackConvertLow Power Mode
Track Or Convert
ConvertTrack
B. ADC Timing for Internal Trigger Sources
1 2 3 4 5 6 7 8 9 1011121314151617 18 19
Low Power or
Convert
Track or Convert
TrackConvertLow Power Mode
1 2 3 4 5 6 7 8 9 10111213141516
ConvertTrack
Page 26CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
p
C8051F206
C8051F220/1/6
Figure 5.3. AMX0SL: AMUX Channel Select Register (C8051F220/1/6 and C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
--AMXENPRTSL1PRTSL0PINSL2PINSL1PINSL000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits 7-6: UNUSED. Read = 00b; Write = don’t care
Bit 5:AMXEN enable
0: AMXEN disabled and port pins are unavailable for analog use.
1: AMXEN enabled to use/select port pins for analog use.
Bits 4-3: PRTSL1-0: Port Select Bits*.
00: Port0 select to configure pin for analog input from this port.
01: Port1 select to configure pin for analog input from this port.
10: Port2 select to configure pin for analog input from this port.
11: Port3 select to configure pin for analog input from this port.
Bits 2-0:PINSL2-0: Pin Select Bits
000: Pin 0 of selected port (above) to be used for analog input.
001: Pin 1 of selected port (above) to be used for analog input.
010: Pin 2 of selected port (above) to be used for analog input.
011: Pin 3 of selected port (above) to be used for analog input.
100: Pin 4 of selected port (above) to be used for analog input.
101: Pin 5 of selected port (above) to be used for analog input.
110: Pin 6 of selected port (above) to be used for analog input.
111: Pin 7 of selected
ort(above)to be used for analoginput.
SFR Address:
0xBB
* Selecting a port for analog input does NOT default all pins of that port as analog input. After selecting a
port for analog input, a pin must be selected using pin select bits (PINSL2-0). For example, after setting the
AMXEN to ‘1’, setting PRTSL1-0 to “11”, and setting PINSL2-0 to “100” P3.4 is configured as analog input.
All other Port 3 pins remain as GPIO pins. Also note that in order to use a port pin as analog input, its input
mode should be set to analog. Please see section 14.2.
Page 27CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 5.4. ADC0CF: ADC Configuration Register (C8051F220/1/6 and C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
ADCSC2ADCSC1ADCSC0--AMPGN2AMPGN1AMPGN0
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits
000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks
NOTE: SAR conversion clock should be less than or equal to 2MHz.
Bits4-3: UNUSED. Read = 00b; Write = don’t care
Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
01100000
SFR Address:
0xBC
Page 28CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 5.5. ADC0CN: ADC Control Register (C8051F220/1/6 and C8051F206)
1: ADC Enabled. ADC is active and ready for data conversions.
Bit6:ADCTM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits
ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: RESERVED
10: RESERVED
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
Bit5:ADCINT: ADC Conversion Complete Interrupt Flag (cleared by software).
0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion
Bit4:ADBUSY: ADC Busy Bit
Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b
Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits
00: ADC conversion started upon a write of 1 to ADBUSY
01: RESERVED
10: RESERVED
11: ADC conversions initiated on overflows of Timer 2
Bit1:ADWINT: ADC Window Compare Interrupt Flag
0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred
Bit0:ADLJST: ADC Left Justify Data Bit (Used on C8051F206 only)
0: Data in ADC0H:ADC0L registers are right justified.
1: Data in ADC0H:ADC0L registers are left justified.
SFR Address:
0xE8
Page 29CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 5.6. ADC0H: ADC Data Word Register (C8051F220/1/6 and C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
MSBLSB00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0: ADC Data Word Bits
EXAMPLE: ADC Data Word Conversion Map
SFR Address:
0xBF
AIN – GND(Volts)
ADC0H
REF x (255/256)0xFF
REF x ½0x80
REF x (127/256)0x7F
00x00
5.3.ADC Programmable Window Detector
The ADC programmable window detector is very useful in many applications. It continuously compares the ADC
output to user-programmed limits and notifies the system when an out-of-band condition is detected.This is
especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled
mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than
registers (ADC0GTH and ADC0LTH).
Figure 5.7. ADC0GTH: ADC Greater-Than Data Register (C8051F220/1/6 and C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
11111111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0:
The high byte of the ADC Greater-Than Data Word.
SFR Address:
0xC5
Figure 5.8. ADC0LTH: ADC Less-Than Data Byte Register (C8051F220/1/6 and C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address:
0xC7
Bits7-0:
ThehighbyteoftheADCLess-ThanDataWord.
Page 30CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
Resolution8bits
Integral Nonlinearity
Differential NonlinearityGuaranteed Monotonic
Offset Error
Gain Error
Total Unadjusted Error
DYNAMIC PERFORMANCE (10kHz sine-wave input, 0 to –1dB of full scale, 100ksps)
Signal-to-Noise Plus
Distortion
Total Harmonic DistortionUp to the 5thharmonic-65dB
Spurious-Free Dynamic
Range
CONVERSION RATE
Throughput Rate100ksps
ANALOG INPUTS
Input Voltage Range0VDDV
Input Capacitance10pF
POWER SPECIFICATIONS
Power Supply CurrentOperating Mode, 100ksps1.0mA
Power Supply Current in
Shutdown
Power Supply Rejection
49.5dB
-65dB
0.11
±0.3
±1/4
±1/2
±1/2
±1/2
±1/2
LSB
LSB
LSB
LSB
LSB
µA
mV/V
Page 32CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
6.ADC (12-Bit, C8051F206 Only)
Description
The ADC subsystem for the C8051F206 consists of configurable analog multiplexer (AMUX), a programmable gain
amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and
programmable window detector (see Figure 6.1).The AMUX, PGA, Data Conversion Modes, and Window
Detector are all configurable under software control via the Special Function Register’s shown in Figure 6.1. The
ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the ADCEN bit in the ADC Control register
(ADC0CN, Figure 6.5) is set to 1. The ADC subsystem is in low power shutdown when this bit is 0.
Figure 6.1. 12-Bit ADC Functional Block Diagram
AIN0-31 are port 0-3
pins -- any external
port pin may be configured
as an analog input
AIN0
AIN31
...
32-to-1
AMUX
X
AMXEN
PRTSL0
PRTSL1
AMX0SL
GND
PINSL2
ADC0GTLADC0GTH
VDD
ADCEN
VDD
ADC0LTLADC0LTH
VDDVREF
SYSCLK
REF
24
ADC0L
Dig
Comp
ADWINT
12
12-Bit
+
SAR
-
12
ADC0H
ADC
GND
Conversion Start
T2 OV
S
Y
U
B
D
A
PINSL0
PINSL1
ADCSC0
ADCSC1
ADCSC2
ADC0CF
AMPGN2
AMPGN1
AMPGN0
ADCEN
ADCTM
ADCINT
ADC0CN
ADBUSY
ADLJST
ADWINT
ADSTM0
ADSTM1
)
w
(
6.1.Analog Multiplexer and PGA
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the desired
analog input pin. (See Figure 6.3). When the AMUX is enabled, the user selects which port is to be used (bits
PRTSL0-1), and then the pin in the selected port (bits PINSL0-2) to be the analog input.
The table in shows AMUX functionality by channel for each possible configuration. The PGA amplifies the AMUX
output signal by an amount determined by the states of the AMPGN2-0 bits in the ADC Configuration register,
ADC0CF (Figure 6.4). The PGA can be software-programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain
of 1 on reset.
6.2.ADC Modes of Operation
The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the system
clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of 1,2,4,8, or 16 are
supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to
accommodate different system clock speeds.
Page 33CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the ADC0CN register.
Converted data is available in the ADC data word register, ADC0H.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of two different low
power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1.Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2.Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 6.2. 12-Bit ADC Track and Conversion Example Timing
CNVSTR
(ADSTM[1:0]=10)
SAR Clocks
ADCTM=1
ADCTM=0
Timer2, Timer3 Overflow;
Write1toADBUSY
(ADSTM[1:0]=00, 01, 11)
SAR Clocks
ADCTM=1
SAR Clocks
ADCTM=0
A. ADC Timing for External Trigger Source
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Low Power or
Convert
TrackConvertLow Power Mode
Track Or Convert
ConvertTrack
B. ADC Timing for Internal Trigger Sources
1 2 3 4 5 6 7 8 9 1011121314151617 18 19
Low Power or
Convert
Track or Convert
TrackConvertLow Power Mode
1 2 3 4 5 6 7 8 9 10111213141516
ConvertTrack
Page 34CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
p
C8051F206
C8051F220/1/6
Figure 6.3. AMX0SL: AMUX Channel Select Register (C8051F220/1/6 and C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
--AMXENPRTSL1PRTSL0PINSL2PINSL1PINSL000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits 7-6: UNUSED. Read = 00b; Write = don’t care
Bit 5:AMXEN enable
0: AMXEN disabled and port pins are unavailable for analog use.
1: AMXEN enabled to use/select port pins for analog use.
Bits 4-3: PRTSL1-0: Port Select Bits*.
00: Port0 select to configure pin for analog input from this port.
01: Port1 select to configure pin for analog input from this port.
10: Port2 select to configure pin for analog input from this port.
11: Port3 select to configure pin for analog input from this port.
Bits 2-0:PINSL2-0: Pin Select Bits
000: Pin 0 of selected port (above) to be used for analog input.
001: Pin 1 of selected port (above) to be used for analog input.
010: Pin 2 of selected port (above) to be used for analog input.
011: Pin 3 of selected port (above) to be used for analog input.
100: Pin 4 of selected port (above) to be used for analog input.
101: Pin 5 of selected port (above) to be used for analog input.
110: Pin 6 of selected port (above) to be used for analog input.
111: Pin 7 of selected
ort(above)to be used for analoginput.
SFR Address:
0xBB
* Selecting a port for analog input does NOT default all pins of that port as analog input. After selecting a
port for analog input, a pin must be selected using pin select bits (PINSL2-0). For example, after setting the
AMXEN to ‘1’, setting PRTSL1-0 to “11”, and setting PINSL2-0 to “100” P3.4 is configured as analog input.
All other Port 3 pins remain as GPIO pins. Also note that in order to use a port pin as analog input, its input
mode should be set to analog. Please see section 14.2.
Page 35CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 6.4. ADC0CF: ADC Configuration Register (C8051F220/1/6 and C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
ADCSC2ADCSC1ADCSC0--AMPGN2AMPGN1AMPGN0
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits
000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks
NOTE: SAR conversion clock should be less than or equal to 2MHz.
Bits4-3: UNUSED. Read = 00b; Write = don’t care
Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
01100000
SFR Address:
0xBC
Page 36CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 6.5. ADC0CN: ADC Control Register (C8051F220/1/6 and C8051F206)
0: ADC Disabled. ADC is in low power shutdown.
1: ADC Enabled. ADC is active and ready for data conversions.
Bit6:ADCTM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits
ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: RESERVED
10: RESERVED
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
Bit5:ADCINT: ADC Conversion Complete Interrupt Flag (cleared by software).
0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion
Bit4:ADBUSY: ADC Busy Bit
Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b
Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits
00: ADC conversion started upon a write of 1 to ADBUSY
01: RESERVED
10: RESERVED
11: ADC conversions initiated on overflows of Timer 2
Bit1:ADWINT: ADC Window Compare Interrupt Flag
0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred
Bit0:ADLJST: ADC Left Justify Data Bit
0: Data in ADC0H:ADC0L registers are right justified.
1: Data in ADC0H:ADC0L registers are left justified.
SFR Address:
0xE8
Page 37CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 6.6. ADC0H: ADC Data Word MSB Register (C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0: ADC Data Word Bits
For ADLJST = 1: Upper 8-bits of the 12-bit ADC Data Word.
For ADLJST = 0: Bits7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4-bits of the
12-bit ADC Data Word.
Figure 6.7. ADC0L: ADC Data Word LSB Register (C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0: ADC Data Word Bits
For ADLJST = 1: Bits7-4 are the lower 4-bits of the 12-bit ADC Data Word. Bits3-0 will
always read 0.
For ADLJST = 0: Bits7-0 are the lower 8-bits of the 12-bit ADC Data Word.
00000000
SFR Address:
0xBF
00000000
SFR Address:
0xBE
NOTE: Resulting 12-bit ADC Data Word appears in the ADC Data Word Registers as follows:
ADC0H[3:0]:ADC0L[7:0], if ADLJST = 0
(ADC0H[7:4] will be sign extension of ADC0H.3 if a differential reading, otherwise = 0000b)
ADC0H[7:0]:ADC0L[7:4], if ADLJST = 1
(ADC0L[3:0] = 0000b)
EXAMPLE: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0CF=0x00, AMX0SL=0x00)
AIN0 – AGND (Volts)
ADC0H:ADC0L
(ADLJST = 0)
ADC0H:ADC0L
(ADLJST = 1)
REF x (4095/4096)0x0FFF0xFFF0
REF x ½0x08000x8000
REF x (2047/4096)0x07FF0x7FF0
00x00000x0000
6.3.ADC Programmable Window Detector
The ADC programmable window detector is very useful in many applications. It continuously compares the ADC
output to user-programmed limits and notifies the system when an out-of-band condition is detected.This is
especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled
mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than
registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL).Figure 6.12 and Figure 6.13 show example
comparisons for reference. Notice that the window detector flag can be asserted when the measured data is inside or
outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
Page 38CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 6.8. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0:
The high byte of the ADC Greater-Than Data Word.
Figure 6.9. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0:
The low byte of the ADC Greater-Than Data Word.
Definition:
ADC Greater-Than Data Word = ADC0GTH:ADC0GTL
11111111
SFR Address:
0xC5
11111111
SFR Address:
0xC4
Figure 6.10. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0:
ThehighbyteoftheADCLess-ThanDataWord.
Figure 6.11. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F206)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-0:
These bits are the low byte of the ADC Less-Than Data Word.
Definition:
ADC Less-Than Data Word = ADC0LTH:ADC0LTL
00000000
SFR Address:
0xC7
00000000
SFR Address:
0xC6
Page 39CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F220/1/6
Figure 6.12. 12-Bit ADC Window Interrupt Examples, Right Justified Data
Resolution12bits
Integral Nonlinearity
Differential NonlinearityGuaranteed Monotonic
Offset Error
Full Scale ErrorDifferential mode
Offset Temperature
Coefficient
DYNAMIC PERFORMANCE (10kHz sine-wave input, 0 to –1dB of full scale, 100ksps)
Signal-to-Noise Plus
Distortion
Total Harmonic DistortionUp to the 5thharmonic-75dB
Spurious-Free Dynamic
Range
CONVERSION RATE
Conversion Time in System
Clocks
Track/Hold Acquisition
Time
Throughput Rate100ksps
ANALOG INPUTS
Voltage Conversion Range0VREFV
Input VoltageAny pin (in Analog Input Mode)GNDVDDV
Input Capacitance10pF
POWER SPECIFICATIONS
Power Supply Current
(VDD supplied to ADC)
Power Supply Rejection
ADC0CF = 000xxxxxb16clocks
Operating Mode, 100ksps450900
64dB
1.5
± 1± 2
± 1
-3 ± 2
-20 ± 3± 0.25ppm/°C
80dB
± 0.3
LSB
LSB
LSB
LSB
µs
µA
mV/V
Page 42CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
7.VOLTAGE REFERENCE (C8051F206/220/221/226)
The voltage reference circuit selects between an externally connected reference and the power supply voltage
(VDD). (See Figure 7.1).
An external reference can be connected to the VREF pin and selected by setting the REF0CN special function
register per Figure 7.1. The external reference supply must be between VDD-0.3V and 1V. VDD may also be
selected using REF0CN per Figure 7.2. The electrical specifications for the Voltage Reference are given in Table 7.1
Figure 7.1. Voltage Reference Functional Block Diagram
Vdd
To ADC Ref
Vref (external)
REF0CN[1:0]
2
Set REF0CN to:
00: Use external Vref
11: Use Vdd
Page 43CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
Figure 7.2. REF0CN: Reference Control Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
------REFSL1REFSL000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits7-2: UNUSED. Read = 00000b; Write = don’t care
Bit1-0: REFSL1- REFSL0: Voltage reference selection.
Bits control which reference is selected.
00: External VREF source is selected.
01: Reserved.
10: Reserved.
11: VDD selected as VREF source.
Page 44CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
8.COMPARATORS
The MCU has two on-board voltage comparators as shown in Figure 8.1. The inputs of each Comparator are
available at the package pins. The output of each comparator is optionally available at port1 by configuring (see
Section 14). When assigned to package pins, each comparator output can be programmed to operate in open drain or
push-pull modes (see section 14.2).
The hysteresis of each comparator is software-programmable via its respective Comparator Control Register
(CPT0CN, CPT1CN). The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive-going and negative-going symmetry of this hysteresis around the threshold voltage. The output of
the comparator can be polled in software, or can be used as an interrupt source. Each comparator can be individually
enabled or disabled (shutdown). When disabled, the comparator output (if assigned to a Port I/O pin via the Port1
MUX) defaults to the logic low state and its interrupt capability is suspended. Comparator inputs can be externally
driven from -0.25V to (VDD) + 0.25V without damage or upset.
The Comparator 0 hysteresis is programmed using bits 3-0 in the Comparator 0 Control Register CPT0CN (shown in
Figure 8.3). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits. As shown
in Figure 8.2, settings of 10, 4 or. 2mV of negative hysteresis can be programmed, or negative hysteresis can be
disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable
and priority control, see Section 9.4). The CP0FIF flag is set upon a Comparator 0 falling-edge interrupt, and the
CP0RIF flag is set upon the Comparator 0 rising-edge interrupt. Once set, these bits remain set until cleared by the
user software. The Output State of Comparator 0 can be obtained at any time by reading the CP0OUT bit.
Comparator 0 is enabled by setting the CP0EN bit, and is disabled by clearing this bit. Note there is a 20µS power
on time between setting CP0EN and the output stabilizing. Comparator 0 can also be programmed as a reset source.
For details, see Section 11. The operation of Comparator 1 is identical to that of Comparator 0, except the
Comparator 1 is controlled by the CPT1CN Register (Figure 8.4). Also, Comparator 1 can not be programmed as a
reset source. The complete electrical specifications for the Comparators are given in Table 8.1.
Figure 8.1. Comparator Functional Block Diagram
CP0EN
CP0OUT
AV+
Reset
Decision
Tree
External Pin
+
Synchronizer
-
AGND
AV+
+
Synchronizer
-
AGND
PORT1
MUX
Interrupt
Handler
PORT1
MUX
Interrupt
Handler
P1.2/CP0
External Pin
P1.5/CP1
P1.0/CP0+
P1.1/CP0-
P1.3/CP1+
P1.4/CP1-
CPT0CN
CPT1CN
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
Page 45CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
Figure 8.2. Comparator Hysteresis Plot
C8051F206
C8051F220/1/6
CP0+
VIN+
CP0-
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYSP Bits)
VIN-
INPUTS
VIN+
V
OUTPUT
V
OL
Positive Hysteresis
Disabled
+
CP0
_
OH
OUT
Negative Hysteresis
Maximum
Positive Hysteresis
Disabled
Negative Hysteresis Voltage
(Programmed by CP0HYSN Bits)
Maximum
Negative Hysteresis
Page 46CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
0: Voltage on CP0+ < CP01: Voltage on CP0+ > CP0-
Bit5:CP0RIF: Comparator 0 Rising-Edge Interrupt Flag
0: No Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared
1: Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared
Bit4:CP0FIF: Comparator 0 Falling-Edge Interrupt Flag
0: No Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared
1: Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared
Bit3-2: CP0HYP1-0: Comparator 0 Positive Hysteresis Control Bits
0: Voltage on CP1+ < CP11: Voltage on CP1+ > CP1-
Bit5:CP1RIF: Comparator 1 Rising-Edge Interrupt Flag
0: No Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared
1: Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared
Bit4:CP1FIF: Comparator 1 Falling-Edge Interrupt Flag
0: No Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared
1: Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared
Bit3-2: CP1HYP1-0: Comparator 1 Positive Hysteresis Control Bits
Power-up TimeCPnEN from 0 to 120
Power Supply Rejection0.11mV/V
Supply CurrentOperating Mode (each comparator) at DC1.54
NOTES: (1) CPnHYP1-0 = CPnHYN1-0 = 00.
-0.25(VDD)
1.54mV/V
+0.25
µs
µs
V
µs
µA
Page 49CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F206
C8051F220/1/6
9.CIP-51 MICROCONTROLLER
General Description
The MCU’s system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-
TM
51
instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The MCU has
a superset of all the peripherals included with a standard 8051.Included are three 16-bit counter/timers (see
description in Section 17), a full-duplex UART (see description in Section 16), 256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (see Section 9.3), and four byte-wide I/O Ports (see description in
Section 14). The CIP-51 also includes on-chip debug hardware (see description in Section 18), and interfaces
directly with the MCU’s analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram). The CIP-51 includes
the following features:
- Fully Compatible with MCS-51 Instruction Set
- 25 MIPS Peak Throughput with 25MHz Clock
- 0 to 25MHz Clock Frequency
- 256 Bytes of Internal RAM
- Optional 1024 Bytes of XRAM
- 8k Byte Flash Program Memory
- Four Byte-Wide I/O Ports
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Circuitry
- Program and Data Memory Security
DATA BUS
RESET
CLOCK
STOP
IDLE
Figure 9.1. CIP-51 Block Diagram
D8
ACCUMULATOR
TMP1TMP2
PSW
D8
BUFFER
DATA POINTER
PC INCREMENTE R
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
CONTROL
LOGIC
POWER CONTROL
REGISTER
PIPELINE
D8
ALU
D8
DATA BUS
D8
DATA BUS
D8
D8
A16
DATA BUS
D8
D8
BREGISTER
SRAM
ADDRESS
REGISTER
D8
INTERFACE
D8
MEMORY
INTERFACE
D8
INTERRUPT
INTERFACE
D8
D8
SFR
BUS
D8
STACK POINTER
SRAM
(256 X 8)
D8
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
MEM_ADDRESS
MEM_CONTROL
MEM_WRITE_DATA
MEM_READ_DATA
SYSTEM_IRQs
EMULATION_IRQ
Page 50CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F206
C8051F220/1/6
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute, and usually have a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. The CIP-51 has a total of
109 instructions. The number of instructions versus the system clock cycles required to execute them is as follows:
Instructions
Clocks to Execute
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the Flash program memory and
communication with on-chip debug support circuitry. The reprogrammable Flash can also be read and changed a
single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows
program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support circuitry facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints and watchpoints, starting, stopping and single stepping through program execution (including interrupt
service routines), examination of the program’s call stack, and reading/writing the contents of registers and memory.
This method of on-chip debugging is completely non-intrusive and non-evasive, requiring no RAM, Stack, timers, or
other on-chip resources.
265051473121
122/333/444/558
The CIP-51 is supported by development tools from Cygnal Integrated Products and third party vendors. Cygnal
provides an integrated development environment (IDE) including editor, macro assembler, debugger and
programmer. The IDE’s debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast and
efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also
available.
Page 51CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F220/1/6
9.1.INSTRUCTION SET
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set.
Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the
binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on
PSW flags. However, instruction timing is different than that of the standard 8051.
9.1.1.Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle
timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as
there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete
when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the CIP-51 Instruction Set
Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
9.1.2.MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory. The CIP-51 does not support external data
or program memory.In the CIP-51, the MOVX instruction accesses the on-chip program memory space
implemented as re-programmable Flash memory and the 1024 bytes of XRAM (optionally available on ‘F226/236
and ‘F206). This feature provides a mechanism for the CIP-51 to update program code and use the program memory
space for non-volatile data storage. Refer to Section 10 (Flash Memory) and Section 11 (External RAM) for further
details.
Table 9.1. CIP-51 Instruction Set Summary
MnemonicDescriptionBytes
ARITHMETIC OPERATIONS
ADD A,RnAdd register to A11
ADD A,directAdd direct byte to A22
ADD A,@RiAdd indirect RAM to A12
ADD A,#dataAdd immediate to A22
ADDC A,RnAdd register to A with carry11
ADDC A,directAdd direct byte to A with carry22
ADDC A,@RiAdd indirect RAM to A with carry12
ADDC A,#dataAdd immediate to A with carry22
SUBB A,RnSubtract register from A with borrow11
SUBB A,directSubtract direct byte from A with borrow22
SUBB A,@RiSubtract indirect RAM from A with borrow12
SUBB A,#dataSubtract immediate from A with borrow22
INC AIncrement A11
INC RnIncrement register11
INC directIncrement direct byte22
INC @RiIncrement indirect RAM12
DEC ADecrement A11
DEC RnDecrement register11
DEC directDecrement direct byte22
DEC @RiDecrement indirect RAM12
INC DPTRIncrement Data Pointer11
MUL ABMultiply A and B14
DIV ABDivide A by B18
Clock
Cycles
Page 52CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F220/1/6
MnemonicDescriptionBytes
DAADecimalAdjustA11
LOGICAL OPERATIONS
ANL A,RnAND Register to A11
ANL A,directAND direct byte to A22
ANL A,@RiAND indirect RAM to A12
ANL A,#dataAND immediate to A22
ANL direct,AAND A to direct byte22
ANL direct,#dataAND immediate to direct byte33
ORL A,RnOR Register to A11
ORL A,directOR direct byte to A22
ORL A,@RiOR indirect RAM to A12
ORL A,#dataOR immediate to A22
ORL direct,AOR A to direct byte22
ORL direct,#dataOR immediate to direct byte33
XRL A,RnExclusive-OR Register to A11
XRL A,directExclusive-OR direct byte to A22
XRL A,@RiExclusive-OR indirect RAM to A12
XRL A,#dataExclusive-OR immediate to A22
XRL direct,AExclusive-OR A to direct byte22
XRL direct,#dataExclusive-OR immediate to direct byte33
CLR AClear A11
CPL AComplement A11
RL ARotate A left11
RLC ARotate A left through carry11
RR ARotate A right11
RRC ARotate A right through carry11
SWAP ASwap nibbles of A11
DATA TRANSFER
MOV A,RnMove register to A11
MOV A,directMove direct byte to A22
MOV A,@RiMove indirect RAM to A12
MOV A,#dataMove immediate to A22
MOV Rn,AMove A to register11
MOV Rn,directMove direct byte to register22
MOV Rn,#dataMove immediate to register22
MOV direct,AMove A to direct byte22
MOV direct,RnMove register to direct byte22
MOV direct,directMove direct byte to direct33
MOV direct,@RiMove indirect RAM to direct byte22
MOV direct,#dataMove immediate to direct byte33
MOV @Ri,AMove A to indirect RAM12
MOV @Ri,directMove direct byte to indirect RAM22
MOV @Ri,#dataMove immediate to indirect RAM22
MOV DPTR,#data16Load data pointer with 16-bit constant33
MOVC A,@A+DPTRMove code byte relative DPTR to A13
MOVC A,@A+PCMove code byte relative PC to A13
MOVX A,@RiMove external data (8-bit address) to A13
MOVX @Ri,AMove A to external data (8-bit address)13
MOVX A,@DPTRMove external data (16-bit address) to A13
MOVX @DPTR,AMove A to external data (16-bit address)13
Clock
Cycles
Page 53CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F206
C8051F220/1/6
MnemonicDescriptionBytes
PUSH directPush direct byte onto stack22
POP directPop direct byte from stack22
XCH A,RnExchange register with A11
XCH A,directExchange direct byte with A22
XCH A,@RiExchange indirect RAM with A12
XCHD A,@RiExchange low nibble of indirect RAM with A12
BOOLEAN MANIPULATION
CLR CClear carry11
CLR bitClear direct bit22
SETB CSet carry11
SETB bitSet direct bit22
CPL CComplement carry11
CPL bitComplement direct bit22
ANL C,bitAND direct bit to carry22
ANL C,/bitAND complement of direct bit to carry22
ORL C,bitOR direct bit to carry22
ORL C,/bitOR complement of direct bit to carry22
MOV C,bitMove direct bit to carry22
MOV bit,CMove carry to direct bit22
JC relJump if carry is set22/3
JNC relJump if carry not set22/3
JB bit,relJump if direct bit is set33/4
JNB bit,relJump if direct bit is not set33/4
JBC bit,relJump if direct bit is set and clear bit33/4
PROGRAM BRANCHING
ACALL addr11Absolute subroutine call23
LCALL addr16Long subroutine call34
RETReturn from subroutine15
RETIReturn from interrupt15
AJMP addr11Absolute jump23
LJMP addr16Long jump34
SJMP relShort jump (relative address)23
JMP @A+DPTRJump indirect relative to DPTR13
JZ relJump if A equals zero22/3
JNZ relJump if A does not equal zero22/3
CJNE A,direct,relCompare direct byte to A and jump if not equal33/4
CJNE A,#data,relCompare immediate to A and jump if not equal33/4
CJNE Rn,#data,relCompare immediate to register and jump if not
equal
CJNE @Ri,#data,relCompare immediate to indirect and jump if not
equal
DJNZ Rn,relDecrement register and jump if not zero22/3
DJNZ direct,relDecrement direct byte and jump if not zero33/4
NOPNo operation11
33/4
34/5
Clock
Cycles
Page 54CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F206
C8051F220/1/6
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through register R0-R1
rel - 8-bit, signed (two’s compliment) offset relative to the first byte of the following instruction. Used by SJMP
and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an
SFR (0x80-0xFF).
#data - 8-bit constant
#data 16 - 16-bit constant
bit - Direct-addressed bit in Data RAM or SFR.
addr 11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte
page of program memory as the first byte of the following instruction.
addr 16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8Kbyte program memory space.
Page 55CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F206
C8051F220/1/6
9.2.MEMORY ORGANIZATION
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two
separate memory spaces: program memory and data memory. Program and data memory share the same address
space but are accessed via different instruction types. There are 256 bytes of internal data memory and 8K bytes of
internal program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown
in Figure 9.2.
9.2.1.Program Memory
The CIP-51 has a 8K-byte program memory space. The MCU implements 8320 bytes of this program memory space
as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x207F.
Note: 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for factory use and are not available for user
program storage.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by
setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a
mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage.
Refer to Section 10 Flash Memory for further details.
9.2.2.Data Memory
The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or
indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are
addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16
bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the
direct bit addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same
address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The
addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses
the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR
space. Instructions using indirect addressing above 0x7F will access the upper 128 bytes of data memory. Figure
9.2 illustrates the data memory organization of the CIP-51.
Additionally, the C8051F206/226/236 feature 1024 Bytes of RAM mapped in the external data memory space. All
address locations may be accessed using the MOVX instruction. (Please see Section 11).
Page 56CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
Figure 9.2. Memory Map
C8051F206
C8051F220/1/6
0x207F
0x2000
0x1FFF
0x1E00
0x1DFF
0x0000
PROGRAM MEMORY
128 Byte ISP FLASH
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0x3FF
0x000
DATA MEMORY
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
1024 Byte
XRAM
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
Mapped into
External Data Memory
Space
(C8051F226/236/206 only)
Page 57CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
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C8051F220/1/6
9.2.3.General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of generalpurpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these
banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the
active register bank (see description of the PSW in Figure 9.6). This allows fast context switching when entering
subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
9.2.4.Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through
0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of
the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F
has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source
or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the
byte address and B is the bit position within the byte. For example, the instruction:
MOVC, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the user Carry flag.
9.2.5.Stack
A programmer’s stack can be located anywhere in the 256-byte data memory. The stack area is designated using the
Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is
placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first
value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if
more than one register bank is to be used, the SP should be initialized to a location in the data memory not being
used for data storage. The stack depth can extend up to 256 bytes.
The MCU also has built-in hardware for a stack record. The stack record is a 32-bit shift register, where each Push
or increment SP pushes one record bit onto the register, and each Call pushes two record bits onto the register. (A
Pop or decrement SP pops one record bit, and a Return pops two record bits, also.) The stack record circuitry can
also detect an overflow or underflow on the 32-bit shift register, and can notify the emulator software even with the
MCU running full-speed debug.
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C8051F220/1/6
9.3.SPECIAL FUNCTION REGISTERS
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51’s resources and peripherals. The CIP-51 duplicates the
SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access
the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with
the MCS-51™ instruction set. Table 9.3 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to
0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well as
byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved
for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the
corresponding pages of the datasheet, as indicated in Table 9.3, for a detailed description of each register.
Table 9.2. Special Function Register Memory Map
SPI0CNWDTCN
F8
BP0MODEP1MODEP2MODE
F0
ADC0CN
E8
ACCPRT0MXPRT1MXPRT2MXEIE1EIE2
E0
1
P3MODE
D8
PSWREF0CN
D0
T2CONRCAP2LRCAP2HTL2TH2
C8
C0
IP
B8
P3OSCXCNOSCICNFLSCLFLACL
B0
IEPRT1IF
A8
P2PRT0CFPRT1CFPRT2CFPRT3CF
A0
SCONSBUFSPI0CFGSPI0DATSPI0CKRCPT0CNCPT1CN
98
P1
90
TCONTMODTL0TL1TH0TH1CKCONPSCTL
88
P0SPDPLDPHPCON
80
AMX0SL
ADC0GTL4ADC0GTH1ADC0LTL4ADC0LTH
1
ADC0CF
0(8)1(9)2(A)3(B)4(C)5(D)6(E)7(F)
2
1
EIP1EIP2
RSTSRC
4
ADC0L
ADC0H
EMI0CN
1
1
3
Bit Addressable
1
C8051F230/1/6 Do not have these registers.
2
C8051F221/231 Does not have this register (32 pin package).
3
On the C8051F206 and C8051F226/236 only.
4
On the C8051F206 only (12-bit ADC)
Table 9.3. Special Function Registers
SFR’s are listed in alphabetical order.
AddressRegister
DescriptionPage No.
0xE0ACCAccumulator64
0xBCADC0CFADC Configuration28
0xE8ADC0CNADC Control29
0xC5ADC0GTH
0xC4ADC0GTL
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1
ADC Greater-Than Data Word (High Byte)30
4
ADC Greater Than Data Word (Low Byte)39
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AddressRegister
0xBFADC0H
0xBEADC0L
0xC7ADC0LTH
0xCEADC0LTL
1
4
DescriptionPage No.
ADC Data Word (High Byte)30
ADC Data Word (Low Byte)38
1
ADC Less-Than Data Word (High Byte)30
4
ADC Less Than Data Word (Low Byte)39
0xBBAMX0SLADC MUX Channel Selection27
0xF0BB Register64
0x8ECKCONClock Control121
0x9ECPT0CNComparator 0 Control46
0x9FCPT1CNComparator 1 Control48
0x83DPHData Pointer (High Byte)62
0x82DPLData Pointer (Low Byte)62
0xE6EIE1Extended Interrupt Enable 169
0xE7EIE2Extended Interrupt Enable 270
0xF6EIP1External Interrupt Priority 171
0xF7EIP2External Interrupt Priority 272
0xAFEMI0CN
3
External Memory Interface Control80
0xB7FLACLFlash Memory Read Limit79
0xB6FLSCLFlash Memory Timing Prescaler79
0xA8IEInterrupt Enable67
0xB8IPInterrupt Priority Control68
0xB2OSCICNInternal Oscillator Control88
0xB1OSCXCNExternal Oscillator Control89
0x80P0Port 0 Latch95
0x90P1Port 1 Latch96
0xA0P2Port 2 Latch98
0xB0P3Port 3 Latch98
0xF1P0MODEPort0 Digital/Analog Output Mode98
0xF2P1MODEPort1 Digital/Analog Output Mode98
0xF3P2MODEPort2 Digital/Analog Output Mode98
0xF4P3MODE
2
Port3 Digital/Analog Output Mode88
0x87PCONPower Control74
0xA4PRT0CFPort 0 Configuration95
0xA5PRT1CFPort 1 Configuration96
0xADPRT1IFPort 1 Interrupt Flags97
0xA6PRT2CFPort 2 Configuration98
0xA7PRT3CFPort 3 Configuration99
0xE1PRT0MXPort 0 Multiplexer I/O Configuration79
0xE2PRT1MXPort 1 Multiplexer I/O Configuration80
0xE3PRT2MXPort 2 Multiplexer I/O Configuration80
0x8FPSCTLProgram Store RW Control78
0xD0PSWProgram Status Word63
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C8051F221/231 Does not have this register (32 pin package).
3
On the C8051F206 and C8051F226/236 only.
4
On the C8051F206 only (12-bit ADC)
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9.3.1.Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should
be set to logic 0. Future product versions may use these bits to implement new features in which case the reset value
of the bit will be logic 0, selecting the feature’s default state. Detailed descriptions of the remaining SFRs are
included in the sections of the datasheet associated with their corresponding system function.
Figure 9.3. SP: Stack Pointer
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bits 7-0: SP: Stack Pointer.
The stack pointer holds the location of the top of the stack. The stack pointer is
incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
Figure 9.4. DPL: Data Pointer Low Byte
SFR Address:
0x81
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address:
0x82
Bits 7-0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
Figure 9.5. DPH: Data Pointer High Byte
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address:
0x83
Bits 7-0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
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Figure 9.6. PSW: Program Status Word
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
CYACF0RS1RS0OVF1PARITY00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
(bit addressable)
Bit7:CY: Carry Flag.
This bit is set when the last arithmetic operation results in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
Bit6:AC: Auxiliary Carry Flag.
This bit is set when the last arithmetic operation results in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic
operations.
Bit5:F0: User Flag 0.
This is a bit-addressable, general-purpose flag for use under software control.
Bits4-3: RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow
(subtraction), or overflow (multiply or divide). It is cleared to 0 by all other arithmetic
operations.
Bit1:F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0:PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
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Figure 9.7. ACC: Accumulator
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
ACC.7ACC.6ACC.5ACC.4ACC.3ACC.2ACC.1ACC.000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
(bit addressable)
Bits 7-0: ACC: Accumulator
This register is the accumulator for arithmetic operations.
Figure 9.8. B: B Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
B.7B.6B.5B.4B.3B.2B.1B.000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
(bit addressable)
SFR Address:
0xE0
SFR Address:
0xF0
Bits 7-0: B: B Register
This register serves as a second accumulator for certain arithmetic operations.
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9.4.INTERRUPT HANDLER
The CIP-51 includes an extended interrupt system supporting up to 22 interrupt sources with two priority levels. The
allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific
version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR.
When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to
logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As
soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to
begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns
program execution to the next instruction that would have been executed if the interrupt request had not occurred. If
interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as
normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt’s enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in
an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before
the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless
of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However,
most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interruptpending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt
request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction.
9.4.1.MCU Interrupt Sources and Vectors
The MCU allocates 9 interrupt sources to on-chip peripherals. Software can simulate an interrupt by setting any
interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the
CPU will vector to the ISR address associated with the interrupt-pending flag. The MCU interrupt sources,
associated vector addresses, priority order and control bits are summarized in Table 9.4. Refer to the datasheet
section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the
peripheral and the behavior of its interrupt-pending flag(s).
9.4.2.External Interrupts
Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active-low
edge-sensitive inputs depending on the setting of IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1
(TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respectively. If an /INT0
or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically
cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending
flag follows the state of the external interrupt’s input pin. The external interrupt source must hold the input active
until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR
completes or another interrupt request will be generated.
The interrupt-pending flags for these interrupts are in the Port 1 Interrupt Flag Register shown in Fig 13.10.
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Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority
interrupt service routine can be preempted by a high priority interrupt.A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority
level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher
priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate.
9.4.4.Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled
and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles:
1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending
when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt.
Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the
new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as
the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5
clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the
LCALL to the ISR. NOTE: If a FLASH write or erase is performed, the MCU is stalled during the operation and
interrupts will not be serviced until the operation is complete. If the CPU is executing an ISR for an interrupt with
equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI
and following instruction.
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9.4.5.Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet
section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the
peripheral and the behavior of its interrupt-pending flag(s).
Figure 9.9. IE: Interrupt Enable
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
EA-ET2ESET1EX1ET0EX000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
(bit addressable)
Bit7:EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask
settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6:UNUSED. Read = 0, Write = don’t care.
SFR Address:
0xA8
Bit5:ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7)
Bit4:ES: Enable Serial Port (UART) Interrupt.
This bit sets the masking of the Serial Port (UART) interrupt.
0: Disable all UART interrupts.
1: Enable interrupt requests generated by the R1 flag (SCON.0) or T1 flag (SCON.1).
Bit3:ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupts.
1: Enable interrupt requests generated by the TF1 flag (TCON.7).
Bit2:EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.
Bit1:ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5).
Bit0:EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.
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Figure 9.10. IP: Interrupt Priority
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
--PT2PSPT1PX1PT0PX000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
(bit addressable)
Bits7-6: UNUSED. Read = 00b, Write = don’t care.
Bit5:PT2 Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupts.
0: Timer 2 interrupt priority determined by default priority order.
1: Timer 2 interrupts set to high priority level.
Bit4:PS: Serial Port (UART) Interrupt Priority Control.
This bit sets the priority of the Serial Port (UART) interrupts.
0: UART interrupt priority determined by default priority order.
1: UART interrupts set to high priority level.
Bit3:PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupts.
0: Timer 1 interrupt priority determined by default priority order.
1: Timer 1 interrupts set to high priority level.
SFR Address:
0xB8
Bit2:PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupts.
0: External Interrupt 1 priority determined by default priority order.
1: External Interrupt 1 set to high priority level.
Bit1:PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupts.
0: Timer 0 interrupt priority determined by default priority order.
1: Timer 0 interrupt set to high priority level.
Bit0:PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupts.
0: External Interrupt 0 priority determined by default priority order.
1: External Interrupt 0 set to high priority level.
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This bit sets the masking of the CP1 interrupt.
0: Disable CP1 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP1RIF flag (CPT1CN.3).
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP1FIF flag (CPT1CN.4).
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP0RIF flag (CPT0CN.3).
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP0FIF flag (CPT0CN.4).
This bit sets the masking of ADC0 window compare interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable Interrupt requests generated by ADC0 Window Comparisons.
Bit1:Reserved. Read = 0, Write = don’t care.
Bit0:ESPI0: Enable Serial Peripheral Interface 0 Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable all SPI0 interrupts.
1: Enable Interrupt requests generated by the SPIF flag (SPI0CN.7).
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This bit sets the masking of the XTLVLD interrupt.
0: Disable all XTLVLD interrupts.
1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7)
Bit6:Reserved. Must write 0. Reads 0.
Bit5:EX7: Enable External Interrupt 7.
This bit sets the masking of External Interrupt 7.
0: Disable External Interrupt 7.
1: Enable interrupt requests generated by the External Interrupt 7 input pin.
Bit4:EX6: Enable External Interrupt 6.
This bit sets the masking of External Interrupt 6.
0: Disable External Interrupt 6.
1: Enable interrupt requests generated by the External Interrupt 6 input pin.
SFR Address:
0xE7
Bit3:EX5: Enable External Interrupt 5.
This bit sets the masking of External Interrupt 5.
0: Disable External Interrupt 5.
1: Enable interrupt requests generated by the External Interrupt 5 input pin.
Bit2:EX4: Enable External Interrupt 4.
This bit sets the masking of External Interrupt 4.
0: Disable External Interrupt 4.
1: Enable interrupt requests generated by the External Interrupt 4 input pin.
Bit1:EADC0: Enable ADC0 End of Conversion Interrupt.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt.
1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.
Bit0:Reserved. Read = 0, Write = don’t care.
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This bit sets the priority of the CP1 interrupt.
0: CP1 rising interrupt set to low priority level.
1: CP1 rising interrupt set to high priority level.
This bit sets the priority of the CP1 interrupt.
0: CP1 falling interrupt set to low priority level.
1: CP1 falling interrupt set to high priority level.
This bit sets the priority of the CP0 interrupt.
0: CP0 rising interrupt set to low priority level.
1: CP0 rising interrupt set to high priority level.
This bit sets the priority of the CP0 interrupt.
0: CP0 falling interrupt set to low priority level.
1: CP0 falling interrupt set to high priority level.
This bit sets the priority of the ADC0 window compare interrupt.
0: ADC0 window compare interrupt set to low priority level.
1: ADC0 window compare interrupt set to high priority level.
Bit1:UNUSED. Read = 0, Write = don’t care.
Bit0:PSPI0: Serial Peripheral Interface 0 Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
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This bit sets the priority of the XTLVLD interrupt.
0: XTLVLD interrupt set to low priority level.
1: XTLVLD interrupt set to high priority level.
Bit6:Reserved. Must write 0. Reads 0.
Bit5:PX7: External Interrupt 7 Priority Control.
This bit sets the priority of the External Interrupt 7.
0: External Interrupt 7 set to low priority level.
1: External Interrupt 7 set to high priority level.
Bit4:PX6: External Interrupt 6 Priority Control.
This bit sets the priority of the External Interrupt 6.
0: External Interrupt 6 set to low priority level.
1: External Interrupt 6 set to high priority level.
SFR Address:
0xF7
Bit3:PX5: External Interrupt 5 Priority Control.
This bit sets the priority of the External Interrupt 5.
0: External Interrupt 5 set to low priority level.
1: External Interrupt 5 set to high priority level.
Bit2:PX4: External Interrupt 4 Priority Control.
This bit sets the priority of the External Interrupt 4.
0: External Interrupt 4 set to low priority level.
1: External Interrupt 4 set to high priority level.
Bit1:PADC0: ADC End of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority level.
1: ADC0 End of Conversion interrupt set to high priority level.
Bit0:Reserved. Read = 0, Write = don’t care.
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9.5.Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the
CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts
and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number of
peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 9.15 describes the
Power Control Register (PCON) used to control the CIP-51’s power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management
of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog
peripheral can be disabled when not in use and put into low power mode. Turning off the active oscillator saves
even more power, but requires a reset to restart the MCU.
9.5.1.Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the
instruction that sets the bit completes. All internal registers and memory maintain their original data. All analog
and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will
cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU will resume operation. The pending interrupt
will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction
immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external
reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This
feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON
register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the
WDT was initially configured to allow this operation. This provides the opportunity for additional power savings,
allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system.
Refer to Section 12.7 Watchdog Timer for more information on the use and configuration of the WDT.
9.5.2.Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets
the bit completes.In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital
peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and
begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The
Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of
100µsec.
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Figure 9.15. PCON: Power Control Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
SMODGF4GF3GF2GF1GF0STOPIDLE00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bit7:SMOD: Serial Port Baud Rate Doubler Enable.
0: Serial Port baud rate is that defined by Serial Port Mode in SCON.
1: Serial Port baud rate is double that defined by Serial Port Mode in SCON.
Bits6-2: GF4-GF0: General Purpose Flags 4-0.
These are general purpose flags for use under software control.
Bit1:STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: Goes into power down mode. (Turns off oscillator).
Bit0:IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
SFR Address:
0x87
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10. FLASH MEMORY
This MCU includes 8k + 128 bytes of on-chip, reprogrammable Flash memory for program code and non-volatile
data storage. The Flash memory can be programmed in-system, a single byte at a time, through the JTAG interface or
by software using the MOVX instruction. Once cleared to 0, a Flash bit must be erased to set it back to 1. The bytes
would typically be erased (set to 0xFF) before being reprogrammed.The write and erase operations are
automatically timed by hardware for proper execution. Data polling to determine the end of the write/erase operation
is not required. The Flash memory is designed to withstand at least 10,000 write/erase cycles. Refer to Table 10.1
for the electrical characteristics of the Flash memory.
10.1.Programming The Flash Memory
The simplest means of programming the Flash memory is through the JTAG interface using programming tools
provided by Cygnal or a third party vendor. This is the only means for programming a non-initialized device. For
details on the JTAG commands to program Flash memory, see Section 18.1.
The Flash memory can be programmed by software using the MOVX instruction with the address and data byte to be
programmed provided as normal operands. Before writing to Flash memory using MOVX, flash write operations
must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1. Writing to Flash
remains enabled until the PSWE bit is cleared by software.
Writes to Flash memory can clear bits but cannot set them. Only an erase operation can set bits in Flash. Therefore,
the byte location to be programmed must be erased before a new value can be written. The 8kbyte Flash memory is
organized in 512-byte sectors. The erase operation applies to an entire sector (setting all bytes in the sector to 0xFF).
Setting the PSEE Program Store Erase Enable bit (PSCTL.1) and PSWE Program Store Write Enable bit (PSCTL.0)
to logic 1 and then using the MOVX command to write a data byte to any byte location within the sector will erase
an entire 512-byte sector. The data byte written can be of any value because it is not actually written to the Flash.
Flash erasure remains enabled until the PSEE bit is cleared by software. The following sequence illustrates the
algorithm for programming the Flash memory by software:
1.Enable Flash Memory write/erase in FLSCL Register using FLASCL bits.
2.Set PSEE (PSCTL.1) to enable Flash sector erase.
3.Set PSWE (PSCTL.0) to enable Flash writes.
4.Use MOVX to write a data byte to any location within the 512-byte sector to be erased.
5.Clear PSEE to disable Flash sector erase.
6.Use MOVX to write a data byte to the desired byte location within the erased 512-byte sector. Repeat until
finished. (Any number of bytes can be written from a single byte to and entire sector.)
7.Clear the PSWE bit to disable Flash writes.
Write/Erase timing is automatically controlled by hardware based on the prescaler value held in the Flash Memory
Timing Prescaler register (FLSCL). The 4-bit prescaler value FLASCL determines the time interval for write/erase
operations. The FLASCL value required for a given system clock is shown in Figure 10.3, along with the formula
used to derive the FLASCL values. When FLASCL is set to 1111b, the write/erase operations are disabled. Note
that code execution in the 8051 is stalled while the Flash is being programmed or erased.
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10.2.Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as
calibration coefficients to be calculated and stored at run time. Data is written using the MOVX instruction and read
using the MOVC instruction.
The MCU incorporates an additional 128-byte sector of Flash memory located at 0x2000 – 0x207F. This sector can
be used for program code or data storage. However, its smaller sector size makes it particularly well suited as general
purpose, non-volatile scratchpad memory. Even though Flash memory can be written a single byte at a time, an
entire sector must be erased first. In order to change a single byte of a multi-byte data set, the data must be moved to
temporary storage. Next, the sector is erased, the data set updated and the data set returned to the original sector.
The 128-byte sector-size facilitates updating data without wasting program memory space by allowing the use of
internal data RAM for temporary storage. (A normal 512-byte sector is too large to be stored in the 256-byte internal
data memory.)
10.3.Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well
as prevent the viewing of proprietary program code and constants. The Program Store Write Enable (PSCTL.0) and
the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from accidental modification by software.
These bits must be explicitly set to logic 1 before software can modify the Flash memory. Additional security
features prevent proprietary program code and data constants from being read or altered across the JTAG interface
or by software running on the system controller.
A set of security lock bytes stored at 0x1DFE and 0x1DFF protect the Flash program memory from being read or
altered across the JTAG interface. Each bit in a security lock-byte protects one 1kbyte block of memory. Clearing a
bit to logic 0 in a Read lock byte prevents the corresponding block of Flash memory from being read across the
JTAG interface. Clearing a bit in the Write/Erase lock byte protects the block from JTAG erasures and/or writes.
The Read lock byte is at location 0x1DFF. The Write/Erase lock byte is located at 0x1DFE. Figure 10.1 shows the
location and bit definitions of the security bytes. The 512-byte sector containing the lock byte cannot be erased by
software.
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Figure 10.1. Flash Program Memory Security Bytes
C8051F206
C8051F220/1/6
(This Block locked only if all
other blocks are locked)
Reserved
Read Lock Byte
Write/Erase Lock Byte
Program Memory
Space
Software Read Limit
0x207F
0x2000
0x1FFF
0x1E00
0x1DFF
0x1DFE
0x1DFD
0x0000
FLASH Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.)
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Access Limit Register (FLACL)
The content of this register is used as the high byte of the 16-bit software read limit address. The 16bit read limit address value is calculated as 0xNN00 where NN is replaced by content of this register
on reset. Software running at or above this address is prohibited from using the MOVX and MOVC
instructions to read, write, or erase, locations below this address. Any attempts to read locations
below this limit will return the value 0x00.
Read and W rite/Erase Security Bits.
(Bit 7 is MSB.)
BitMemory Block
7
0x1C00 - 0x1DFD
6
0x1800 - 0x1BFF
5
0x1400 - 0x17FF
4
0x1000 - 0x13FF
3
0x0C00 - 0x0FFF
2
0x0800 - 0x0BFF
1
0x0400 - 0x07FF
0
0x0000 - 0x03FF
The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the block
containing the security bytes. This allows additional blocks to be protected after the block containing the security
bytes has been locked. However, the only means of removing a lock once set is to erase the entire program memory
space by performing a JTAG erase operation. NOTE: Erasing the Flash memory block containing the security
bytes will automatically initiate erasure of the entire program memory space (except for the reserved area).
This erasure can only be performed via the JTAG. If a non-security byte in the 0x1C00-0x1DFF page is
written to in order to perform an erasure of that page, then that page including the security bytes will be
erased.
The Flash Access Limit security feature protects proprietary program code and data from being read by software
running on the CIP-51. This feature provides support for OEMs that wish to program the MCU with proprietary
value-added firmware before distribution. The value-added firmware can be protected while allowing additional
code to be programmed in remaining program memory space later.
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The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program memory
space. The first is an upper partition consisting of all the program memory locations at or above the SRL address,
and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but
excluding) the SRL address. Software in the upper partition can execute code in the lower partition, but is prohibited
from reading locations in the lower partition using the MOVC instruction. (Executing a MOVC instruction from the
upper partition with a source address in the lower partition will always return a data value of 0x00.) Software
running in the lower partition can access locations in both the upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-added
firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a
predetermined location in the upper partition. If entry points are published, software running in the upper partition
may execute program code in the lower partition, but it cannot read the contents of the lower partition. Parameters
may be passed to the program code running in the lower partition either through the typical method of placing them
on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition.
The SRL address is specified using the contents of the Flash Access Register. The 16-bit SRL address is calculated
as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be located on 256-byte
boundaries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a
512 boundary be used. The contents of a non-initialized SRL security byte is 0x00, thereby setting the SRL address
to 0x0000 and allowing read access to all locations in program memory space by default.
Setting this bit allows an entire page of the Flash program memory to be erased (provided the PSWE
bit is set to ‘1’). After setting this bit, a write to Flash memory using the MOVX instruction will erase
the entire page that contains the location addressed by the MOVX instruction. The value of the data
byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Bit0:PSWE: Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
instruction. The location must be erased before writing data.
0: Write to Flash program memory disabled.
1: Write to Flash program memory enabled.
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This register specifies the prescaler value for a given system clock required to generate the
correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash
write/erase operations are disabled.
0000: System Clock < 50kHz
0001: 50kHz ≤ System Clock < 100kHz
0010: 100kHz ≤ System Clock < 200kHz
0011: 200kHz ≤ System Clock < 400kHz
0100: 400kHz ≤ System Clock < 800kHz
0101: 800kHz ≤ System Clock < 1.6MHz
0110: 1.6MHz ≤ System Clock < 3.2MHz
0111: 3.2MHz ≤ System Clock < 6.4MHz
1000: 6.4MHz ≤ System Clock < 12.8MHz
1001: 12.8MHz ≤ System Clock < 25.6MHz
1010: 25.6MHz ≤ System Clock < 51.2MHz*
1011, 1100, 1101, 1110: Reserved Values
1111: Flash Memory Write/Erase Disabled
10001111
SFR Address:
0xB6
The prescaler value is the smallest value satisfying the following equation:
FLASCL > log
(System Clock / 50kHz)
2
*For test purposes. The C8051F2xx is not guaranteed to operate over 25MHz.
Figure 10.4. FLACL: Flash Access Limit
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address:
0xB7
Bits 7-0: FLACL: Flash Memory Access Limit.
This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. Any
subsequent writes are ignored until the next reset.
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11. ON-BOARD XRAM (C8051F226/236/206)
The C8051F226/F236/206 features 1024 Bytes of RAM mapped into the external data memory space. All address
locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using
indirect MOVX addressing mode. If the MOVX instruction is used with an 8-bit operand (such as @R1), then the
high byte is the External Memory Interface Control Register (EMI0CN, shown in Figure 11.1). Addressing using 8
bits will map to one of four 256-byte pages, and these pages are selected by setting the PGSEL bits in the EMI0CN
register.
NOTE: The MOVX instruction is also used for write to the FLASH memory. Please see section 10 for
details. The MOVX instruction will access XRAM by default.
For any of the addressing modes, the upper 6 bits of the 16-bit external data memory address word are “don’t cares”.
As a result, the 1024-byte RAM is mapped modulo style (“wrap around”) over the entire 64k of possible address
values. For example, the XRAM byte at address 0x0000 is also at address 0x0400, 0x0800, 0x0C00, 0x1000, etc.
This feature is useful when doing a linear memory fill, as the address pointer does not have to be reset when reaching
the RAM block boundary.
Figure 11.1. EMI0CN: External Memory Interface Control
RRRRRRR/WR/WResetValue
------PGSEL1PGSEL000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address:
0xAF
Bits7-2: Not Used –read only 000000b
Bits1-0: XRAM Page Select Bits PGSEL[1:0]
The XRAM Page Select bits provide the high byte of the 16-bit external memory address when using an 8-bit
MOVX command, effectively selecting a 256-byte page of RAM. The upper 6 bits are “don’t cares”, so the
1k address blocks are repeated modulo over the entire data memory address space.
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12. RESET SOURCES
The reset circuitry of the MCU allows the controller to be easily placed in a predefined default condition. On entry
to this reset state, the CIP-51 halts program execution, forces the external port pins to a known state and initializes
the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the program counter (PC) is reset,
and program execution starts at location 0x0000.
All of the SFRs are reset to predefined values. The reset values of the SFR bits are defined in the SFR detailed
descriptions. The contents of internal data memory are not changed during a reset and any previously stored data is
preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the
stack are not altered.
The I/O port latches are reset to 0xFF (all logic ones), activating internal weak pull-ups which take the external I/O
pins to a high state. The external I/O pins do not go high immediately, but will go high within 4 system clock cycles
after entering the reset state. If the source of reset is from the VDD Monitor or writing a ‘1’ to the PORSF bit, the
/RST pin is driven low until the end of the VDD reset timeout.
On exit from the reset state, the MCU uses the internal oscillator running at 2MHz as the system clock by default.
Refer to Section 13 for information on selecting and configuring the system clock source. The Watchdog Timer is
enabled using its longest timeout interval. (Section 12.7 details the use of the Watchdog Timer.) Once the system
clock source is stable, program execution begins at location 0x0000.
There are six sources for putting the MCU into the reset state: power-on/power-fail (VDD monitor), external /RST
pin, software commanded, Comparator 0, Missing Clock Detector, and Watchdog Timer. Each reset source is
described below:
Figure 12.1. Reset Sources Diagram
CP0+
CP0-
System
Clock
Comparator 0
+
-
Missing
Clock
Detector
EN
MCD
Enable
C0RSEF
VDD
WDT
PRE
EN
WDT
WDT
Enable
Strobe
CIP-51
MonEn
Supply
Monitor
+
-
SWRSF
(Software Reset)
System Reset
Supply
Reset
Timeout
(wired-OR)
Reset
Funnel
/RST
Core
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12.1.Power-on Reset
The CIP-51 incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the
V
level during power-up. (See Figure 12.2 for timing diagram, and refer to Table 12.1 for the Electrical
RST
Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the 100msec
VDD Monitor timeout in order to allow the VDD supply to become stable. The VDD monitor is enabled by pulling
the MONEN pin high (available only on 48-pin packages). The VDD monitor may be disabled by pulling the
MONEN pin low.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset
flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all resets cause
program execution to begin at the same location (0x0000), software can read the PORSF flag to determine if a
power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a
power-on reset.
12.2.Software Forced Reset
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 12.1.
Figure 12.2. VDD Monitor Timing Diagram
volts
2.70
2.55
2.0
1.0
Logic HIGH
Logic LOW
/RST
V
RST
D
D
V
t
100ms100ms
12.3.Power-fail Reset
When the VDD monitor is enabled the MONEN pin (not on C8051F221/F231 32 pin parts) is “pulled high”,and
power-down transition or power irregularity causes VDD to drop below V
the /RST pin low and return the CIP-51 to the reset state (see Figure 12.2). When VDD returns to a level above
V
, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even though
RST
internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped
below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.
, the power supply monitor will drive
RST
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12.4.External Reset
The external /RST pin provides a means for external circuitry to force the CIP-51 into a reset state. Asserting an
active-low signal on the /RST pin will cause the CIP-51 to enter the reset state. Although there is a weak pull-up, it
may be desirable to provide an external pull-up and/or decoupling of the /RST pin to avoid erroneous noise-induced
resets. The CIP-51 will remain in reset until at least 12 clock cycles after the active-low /RST signal is removed.
The PINRSF flag (RSTSRC.0) is set on exit from an external reset. The /RST pin is 5V tolerant.
12.5.Missing Clock Detector Reset
The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If the system
clock goes away for more than 100µsec, the one-shot will time out and generate a reset. After a Missing Clock
Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source; otherwise, this bit
reads 0. The state of the /RST pin is unaffected by this reset. Setting the MSCLKE bit in the OSCICN register (see
Figure 13.2) enables the Missing Clock Detector.
12.6.Comparator 0 Reset
Comparator 0 can be configured as a reset input by writing a 1 to the C0RSEF flag (RSTSRC.5). Comparator 0
should be enabled using CPT0CN.7 (see Figure 8.3) prior to writing to C0RSEF to prevent any turn-on chatter on
the output from generating an unwanted reset. When configured as a reset, if the non-inverting input voltage (on
CP0+) is less than the inverting input voltage (on CP0-), the MCU is put into the reset state. After a Comparator 0
Reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator 0 as the reset source; otherwise, this bit
reads 0. The state of the /RST pin is unaffected by this reset.
12.7.Watchdog Timer Reset
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. The WDT will force the
MCU into the reset state when the watchdog timer overflows. To prevent the reset, the WDT must be restarted by
application software before the overflow occurs.If the system experiences a software/hardware malfunction
preventing the software from restarting the WDT, the WDT will overflow and cause a reset. This should prevent the
system from running out of control.
The WDT is automatically enabled and started with the default maximum time interval on exit from all resets. If
desired, the WDT can be disabled by system software or locked ‘on’ to prevent accidental disabling. Once locked,
the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by this reset.
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12.7.1. Watchdog Usage
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period
between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is
generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired.
Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 12.3.
Enable/Reset WDT
The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user’s application
software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The
WDT is enabled and reset as a result of any system reset.
Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates
disabling the WDT.
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored.
Interrupts should be disabled during this procedure to avoid delay between the two writes.
Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the
next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use
the watchdog should write 0xFF to WDTCN in their initialization code.
Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
3+WDTCN[2:0]
4
xT
SYSCLK
,(whereT
is the system clock period).
SYSCLK
For a 2.0 MHz system clock, this provides an interval range of 32msec to 524msec. WDTCN.7 must be written as 0
when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] is 111b after a system
reset.
Figure 12.3. WDTCN: Watchdog Timer Control Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
xxxxx111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address:
0xFF
Bits7-0: WDT Control
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.
Bit4:Watchdog Status Bit (when Read)
Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active
Bits2-0: Watchdog Timeout Interval Bits
The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits,
WDTCN.7 must be set to 0.
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Figure 12.4. RSTSRC: Reset Source Register
RR/WR/WRRR/WRReset Value
-C0RSEFSWRSEFWDTRSFMCDRSFPORSF PINRSFxxxxxxxx
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
(Note: Do not use read-modify-write operations on this register.)
Bit7:RESERVED.
Bit6:Not Used. Read only 0b.
Bit5:C0RSEF: Comparator 0 Reset Enable and Flag
Write
0: Comparator 0 is not a reset source
1: Comparator 0 is a reset source
Read
0: Source of prior reset was not from Comparator 0
1: Source of prior reset was from Comparator 0
Bit4:SWRSF: Software Reset Force and Flag
Write
0: No Effect
1: Forces an internal reset. /RST pin is not affected.
Read
0: Prior reset source was not from write to the SWRSF bit.
1: Prior reset source was from write to the SWRSF bit.
Bit3:WDTRSF: Watchdog Timer Reset Flag (Read only)
0: Source of prior reset was not from WDT timeout.
1: Source of prior reset was from WDT timeout.
Bit2:MCDRSF: Missing Clock Detector Flag (Read only)
0: Source of prior reset was not from Missing Clock Detector timeout.
1: Source of prior reset was from Missing Clock Detector timeout.
Bit1:PORSF: Power-On Reset Force and Flag
Write
0: No effect
1: Forces a Power-On Reset. /RST is driven low.
Read
0: Source of prior reset was not from POR.
1: Source of prior reset was from POR.
Bit0:PINRSF: HW Pin Reset Flag
0: Source of prior reset was not from /RST pin.
1: Source of prior reset was from /RST pin.
SFR Address:
0xEF
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/RST Output Low VoltageIOL= 8.5mA, VDD = 2.7 to 3.6V0.6V
/RST Input High Voltage0.8 x
VDD
/RST Input Low Voltage0.2 x
VDD
/RST Input Leakage Current/RST = 0.0V50
VDD for /RST Output Valid1.0V
Reset Threshold (Vrst)2.402.552.70V
Reset Time Delay/RST rising edge after crossing reset
threshold
Missing Clock Detector
Timeout
Time from last system clock to reset
generation
80100120ms
100220500
µA
µs
V
V
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13. OSCILLATOR
The MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate the
system clock.The MCU boots from the internal oscillator after any reset.This internal oscillator can be
enabled/disabled and its frequency can be set using the Internal Oscillator Control Register (OSCICN) as shown in
Figure 13.2. The internal oscillator’s electrical specifications are given in Table 13.1.
Both oscillators are disabled when the /RST pin is held low. The MCU can run from the internal oscillator
permanently, or it can switch to the external oscillator if desired using CLKSL bit in the OSCICN Register. The
external oscillator requires an external resonator, crystal, capacitor, or RC network connected to the XTAL1/XTAL2
pins (see Figure 13.1). The oscillator circuit must be configured for one of these sources in the OSCXCN register.
An external CMOS clock can also provide the system clock by driving the XTAL1 pin. The XTAL1 and XTAL2
pins are NOT 5V tolerant.
Figure 13.1. Oscillator Diagram
OSCICN
opt. 4
opt. 3
XTAL1
XTAL2
opt. 2
VDD
IFCN1
CLKSL
EN
OSC
IOSCEN
IFCN0
SYSCLK
IFRDY
MSCLKE
Internal Clock
Generator
opt. 1
XTAL1XTAL1
XTAL1
Input
Circuit
XTAL2
XFCN2
XFCN1
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XFCN0
OSCXCN
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Figure 13.2. OSCICN: Internal Oscillator Control Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
MSCLKE--IFRDYCLKSLIOSCENIFCN1IFCN000000100
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bit7:MSCLKE: Missing Clock Enable Bit
0: Missing Clock Detector Disabled
1: Missing Clock Detector Enabled; triggers a reset if a missing clock is detected
Bits6-5: UNUSED. Read = 00b, Write = don’t care
Bit4:IFRDY: Internal Oscillator Frequency Ready Flag
0: Internal Oscillator Frequency not running at speed specified by the IFCN bits.
1: Internal Oscillator Frequency running at speed specified by the IFCN bits.
Bit3:CLKSL: System Clock Source Select Bit
0: Uses Internal Oscillator as System Clock.
1: Uses External Oscillator as System Clock.
Bit2:IOSCEN: Internal Oscillator Enable Bit
0: Internal Oscillator Disabled
1: Internal Oscillator Enabled
Bits1-0: IFCN1-0: Internal Oscillator Frequency Control Bits
00: Internal Oscillator typical frequency is 2MHz.
01: Internal Oscillator typical frequency is 4MHz.
10: Internal Oscillator typical frequency is 8MHz.
11: Internal Oscillator typical frequency is 16MHz.
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C8051F206
C8051F220/1/6
Figure 13.3. OSCXCN: External Oscillator Control Register
RR/WR/WR/WR/WR/WR/WR/WReset Value
XTLVLD
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Bit7:XTLVLD: Crystal Oscillator Valid Flag
Bits6-4: XOSCMD2-0: External Oscillator Mode Bits
Bit3:RESERVED. Read = undefined, Write = don’t care
Bits2-0: XFCN2-0: External Oscillator Frequency Control Bits
XOSCMD2XOSCMD1XOSCMD0
-XFCN2XFCN1XFCN000110000
(Valid only when XOSCMD = 1xx.)
0: Crystal Oscillator is unused or not yet stable
1: Crystal Oscillator is running and stable
00x: Off. XTAL1 pin is grounded internally.
010: System Clock from External CMOS Clock on XTAL1 pin.
011: System Clock from External CMOS Clock on XTAL1 pin divided by 2.
10x: RC/C Oscillator Mode with divide by 2 stage.
110: Crystal Oscillator Mode
111: Crystal Oscillator Mode with divide by 2 stage.
f = frequency of oscillation in MHz
C = capacitor value in pF
R = Pull-up resistor value in kΩ
CMODE(Circuit from Figure 13.1, Option 3; XOSCMD = 10x)
Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C * AV+),where
f = frequency of oscillation in MHz
C = capacitor value on XTAL1, XTAL2 pins in pF
AV+ = Analog Power Supply on MCU in volts
K Factor = 0.44
K Factor = 1.4
K Factor = 4.4
K Factor = 13
K Factor = 38
K Factor = 100
K Factor = 420
K Factor = 1400
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PRELIMINARY
C8051F206
C8051F220/1/6
13.1.External Crystal Example
If a crystal were used to generate the system clock for the MCU, the circuit would be as shown in Figure 13.1,
Option 1. For an ECS-110.5-20-4 crystal, the resonate frequency is 11.0592MHz, the intrinsic capacitance is 7pF,
and the ESR is 60Ω. The compensation capacitors should be 33pF each, and the PWB parasitic capacitance is
estimated to be 2pF. The appropriate External Oscillator Frequency Control value (XFCN) from the Crystal column
in the table in Figure 13.3 (OSCXCN Register) should be 111b.
When the crystal oscillator is enabled, a transient pulse may appear on XTAL2, the crystal driver output, that is
sufficient to cause the XTLVLD bit in OSCXCN to go to '1' before the crystal has actually started. Introducing a
blanking interval of 1ms between enabling the crystal oscillator and checking the XTLVLD bit will prevent a
premature switch to the external oscillator. The recommend procedure is:
1. Enable the external oscillator
2. Wait 1 ms
3. Poll for XTLVLD '0' ==> '1'
4. Switch to the external oscillator
Switching to the external oscillator before the crystal oscillator has stabilized could result in unpredictable behavior.
NOTE: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible
to the XTAL pins on the device, keeping the traces as short as possible and shielded with ground plane from any
other traces which could introduce noise or interference.
13.2.External RC Example
If an external RC network were used to generate the system clock for the MCU, the circuit would be as shown in
Figure 13.1, Option 2. The capacitor must be no greater than 100pF, but using a very small capacitor will increase
the frequency drift due to the PWB parasitic capacitance. To determine the required External Oscillator Frequency
Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency
of oscillation. If the frequency desired is 100kHz, let R = 246kΩ and C = 50pF:
f = 1.23(10
XFCN ≥ log
XFCN ≥ log
3
)/RC = 1.23(103) / [246 * 50] = 0.1MHz = 100kHz
(f/25kHz)
2
(100kHz/25kHz) = log2(4)
2
XFCN ≥ 2, or code 010
13.3.External Capacitor Example
If an external capacitor were used to generate the system clock for the MCU, the circuit would be as shown in Figure
13.1, Option 3. The capacitor must be no greater than 100pF, but using a very small capacitor will increase the
frequency drift due to the PWB parasitic capacitance. To determine the required External Oscillator Frequency
Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation
from the equations below. Assume VDD = 3.0V and C = 50pF:
f = KF / (C * VDD) = KF / (50 * 3)
f = KF / 150
If a frequency of roughly 90kHz is desired, select the K Factor from the table in Figure 13.3 as KF = 13:
f = 13 /150 = 0.087MHz, or 87kHz
Therefore, the XFCN value to use in this example is 011.
Page 90CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
14. PORT INPUT/OUTPUT
Description
The C8051F221/231 have three I/O Ports: Port0, Port1, and Port2.The C8051F206, C8051F220/6 and
C8051F230/6 have four I/O Ports: Port0, Port1, Port2, and Port3. A wide array of digital resources can be assigned
to these ports by the simple configuration of the port’s corresponding multiplexer (MUX). Please see Figure 8.1.
Additionally, all external port pins are available as analog input.
14.1.Port I/O Initialization
Port I/O initialization is straightforward. Registers PRT0MX, PRT1MX and PRT2MX must be loaded with the
appropriate values to select the digital I/O functions required by the design. The output driver characteristics of the
I/O pins are defined using the Port Configuration Registers PRT0CF, PRT1CF, PRT2CF and PRT3CF. Each Port
Output driver can be configured as either Open Drain or Push-Pull. This is required even for the digital resources
selected in the PRTnMX registers, and is not automatic.
Any or all pins may be configured as digital I/O or as analog input. The default mode is digital I/O. The P0MODE,
P1MODE, P2MODE, and P3MODE special function registers are used to configure the port pins as digital or analog
as defined in this section.
The final step is initializing the individual resources selected using the appropriate setup registers. Initialization
procedures for the various digital resources may be found in the detailed explanation of each available function. The
reset state of each register is shown in the figures that describe each individual register.
NOTE: The input mode of pins configured for use with Timer 0, 1, or 2 must be manually configured.
1.The output mode of all ports pins must be configured regardless of whether the port pin is either standard
general-purpose I/O or controlled by a digital peripheral.
2.For all pins used as Timer inputs (P0.4/T0, P0.5/T1, P0.6/T2, and P0.7/T2EX), the output mode must be
“open-drain” (which is the reset state), and “1” must be written to the associated port pin to prevent possible
contention for the port pin that could result in an overcurrent condition. For example, to configure a
Timer0, set PRT0MX’s T0E Timer0 enable bit to ‘1’ to route Timer0 to Port Pin P0.4. Then place P0.4/T0
in open-drain configuration (which is set in PRT0CF by default), and write a ‘1’ to P0.4 to set its output
state to high impedance for use as a digital peripheral input (port pins also default to logic high state upon
reset). Lastly, ensure P0MODE.4 is ‘1’ for digital input mode. (All pins default to digital input mode upon
reset.)
Page 91CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
1: CP1routedtoPortPinP1.5.
Bit0:CP0OEN: Comparator 0 Output Enable Bit
0: CP0 unavailable at port pin.
1: CP0 routed to port pin P1.2.
SFR Address:
0xE2
Figure 14.5. PRT2MX: Port I/O MUX Register 2
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
GWPUD
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
P3WPUDP2WPUDP1WPUDP0WPUD--SPI0OEN00000000
SFR Address:
0xE3
Bit 7:GWPUD: Global Port I/O Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for all ports.
1: Weak Pull-ups Disabled (Bits 6-3 Don’t cares)
Bit 6:P3WPUD: Port 3 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 3
1: Weak Pull-ups Disabled for port 3
Bit 5:P2WPUD: Port 2 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 2.
1: Weak Pull-ups Disabled for port 2
Bit 4:P1WPUD: Port 1 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 1
1: Weak Pull-ups Disabled for port 1
Bit 3:P0WPUD: Port 0 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 0
1: Weak Pull-ups Enabled for port 0
Bits 2-1: UNUSED. Read = 00b, Write = don’t care.
Bit 0:SPI0OEN: SPI Bus I/O Enable Bit.
0: SPI I/O unavailable at port pins.
1: SCK, MISO, MOSI, NSS routed to pins P2.0, P2.1, P2.2, and P2.3 respectively.
Page 94CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1
PRELIMINARY
C8051F206
C8051F220/1/6
14.2.General Purpose Port I/O
Each I/O port is accessed through a corresponding special function register (SFR) that is both byte addressable and
bit addressable. When writing to a port, the value written to the SFR is latched to maintain the output data value at
each pin. When reading, the logic levels of the port’s input pins are returned regardless of the PRTnMX settings
(i.e., even when the pin is assigned to another signal by the MUX, the Port Register can always still read its
corresponding Port I/O pin), provided its pin is configured for digital input mode. The exception to this is the
execution of the read-modify-write instructions. The read-modify-write instructions when operating on a port SFR
are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is
an individual bit in a port SFR. For these instructions, the value of the register (not the pin) is read, modified, and
written back to the SFR.
Figure 14.6. P0: Port0 Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.011111111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
(bit addressable)
Bits7-0: P0.[7:0]
(Write – Output appears on I/O pins per PRT0MX, PRT1MX, and PRT2MX Registers)
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding PRT0CF.n bit = 0)
(Read – Regardless of PRT0MX, PRT1MX, and PRT2MX Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
SFR Address:
0x80
Figure 14.7. PRT0CF: Port0 Configuration Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address:
0xA4
Bits7-0: PRT0CF.[7:0]: Output Configuration Bits for P0.7-P0.0 (respectively)
0: Corresponding P0.n Output mode is Open-Drain.
1: Corresponding P0.n Output mode is Push-Pull.
Page 95CYGNAL Integrated Products, Inc. 20015.2001; Rev. 1.1