Silicon Laboratories C8051F206, C8051F221, C8051F226, C8051F231, C8051F236 User Manual

PRELIMINARY

C8051F206
C8051F220/1/6
C8051F230/1/6

Mixed-Signal 8KB ISP FLASH MCU Family

ANALOG PERIPHERALS

- SAR ADC

• 12-bit Resolution (‘F206)

• 8-Bit Resolution (‘F220/1/6)

• ±1/4 LSB INL (8-bit) and ±2 LSB INL (12-bit)

• Up to 100ksps

• Up to 32 Channel Input Multiplexer; Each Port

I/O Pin can be an ADC Input

- Two Comparators

• 16 Programmable Hysteresis States

• Configurable to Generate Interrupts or Reset

- VDD Monitor and Brown-out Detector

ON-CHIP JTAG DEBUG

- On-Chip Debug Circuitry Facilitates Full Speed, Non­intrusive In-system Debug (No Emulator Required!)

- Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor

- Inspect/Modify Memory and Registers

- Superior Performance to Emulation Systems Using

ICE-Chips, Target Pods, and Sockets

- Complete, Low Cost Development Kit: $99

HIGH SPEED 8051 µµµµC Core

- Pipe-lined Instruction Architecture; Executes 70% of
Instructions in 1 or 2 System Clocks

- Up to 25MIPS Throughput with 25MHz Clock

- Expanded Interrupt Handler

MEMORY

- 256 Bytes Internal Data RAM

- 1024 Bytes XRAM (available on ‘F206/226/236)

- 8k Bytes FLASH; In-System Programmable in 512

byte Sectors

DIGITAL PERIPHERALS

- Four byte wide Port I/O; All are 5V tolerant

- Hardware UART and SPI bus

- 3 General Purpose 16-Bit Counter/Timers

- Dedicated Watch-Dog Timer

- Bi-directional Reset

- System Clock: Internal Programmable Oscillator,

External Crystal, External RC, or External Clock

SUPPLY VOLTAGE .................2.7V to 3.6V

- Typical Operating Current: 10mA @ 25MHz

- Multiple Power Saving Sleep and Shutdown Modes

(48-Pin TQFP and 32-Pin LQFP Version Available)
Temperature Range: –40°°°°Cto+85°°°°C

ANALOG PERIPHERALS

PGA

AMUX

+

-

VOLTAGE

COMPARATORS

SAR

ADC

+

-

DIGITAL I/O

SPI Bus

Timer 0

Timer 1

Timer 2

HIGH-SPEED CONTROLLER CORE

8051 CPU

(25MIPS)

8K x 8

ISP FLASH

CLOCK

CIRCUIT

1280 x 8

SRAM

JTAG

22 INTERRUPTS

Port 0Port 1

UART

Digital MUX

Port 2Port 3

EMULATION

CIRCUITRY

SANITY

CONTROL

Page 1 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

TABLE OF CONTENTS

1. SYSTEM OVERVIEW........................................................................................................5

Table 1.1.1. Product Selection Guide................................................................................................................6

Figure 1.1. C8051F206, C8051F220 and C8051F226 Block Diagram (48 TQFP)........................................... 7

Figure 1.2 C8051F221 Block Diagram (32 LQFP) ...........................................................................................8

Figure 1.3 C8051F230 and C8051F236 Block Diagram (48 TQFP) ................................................................ 9

Figure 1.4 C8051F231 Block Diagram (32 LQFP) .........................................................................................10

1.1. CIP-51

Figure 1.5. Comparison of Peak MCU Throughputs ....................................................................................... 11

Figure 1.6. On-Board Clock and Reset............................................................................................................ 12

1.2. On-Board Memory ................................................................................................................................13

Figure 1.7. On-Board Memory Map................................................................................................................13

1.3. JTAG .....................................................................................................................................................14

Figure 1.8. Debug Environment Diagram........................................................................................................14

1.4. Digital/Analog Configurable I/O ...........................................................................................................15

Figure 1.9. Port I/O Functional Block Diagram .............................................................................................. 15

1.5. Serial Ports ............................................................................................................................................ 15

1.6. Analog to Digital Converter .................................................................................................................. 16

Figure 1.10. ADC Diagram ............................................................................................................................. 16

1.7. Comparators .......................................................................................................................................... 17

Figure 1.11. Comparator Diagram................................................................................................................... 17

2. ABSOLUTE MAXIMUM RATINGS* ............................................................................18

3. GLOBAL DC ELECTRICAL CHARACTERISTICS...................................................18

4. PINOUT AND PACKAGE DEFINITIONS.....................................................................19

Table 4.1 Pin Definitions................................................................................................................................. 19

Figure 4.1 TQFP-48 Pin Diagram .................................................................................................................... 21

Figure 4.2 LQFP-32 Pin Diagram .................................................................................................................... 22

Figure 4.3 TQFP-48 Package Drawing.............................................................................................................23

Figure 4.4 LQFP-32 Package Drawing............................................................................................................ 24

5. ADC (8-Bit, C8051F220/1/6 Only) ....................................................................................25

Figure 5.1. 8-Bit ADC Functional Block Diagram.......................................................................................... 25

5.1. Analog Multiplexer and PGA................................................................................................................ 25

5.2. ADC Modes of Operation......................................................................................................................25

Figure 5.2. 12-Bit ADC Track and Conversion Example Timing ...................................................................26

Figure 5.3. AMX0SL: AMUX Channel Select Register (C8051F220/1/6) ..................................................... 27

Figure 5.4. ADC0CF: ADC Configuration Register (C8051F220/1/6) ........................................................... 28

Figure 5.5. ADC0CN: ADC Control Register (C8051F220/1/6) ....................................................................29

Figure 5.6. ADC0H: ADC Data Word Register (C8051F220/1/6).................................................................30

5.3. ADC Programmable Window Detector ................................................................................................. 30

Figure 5.7. ADC0GTH: ADC Greater-Than Data Register (C8051F220/1/6)................................................ 30

Figure 5.8. ADC0LTH: ADC Less-Than Data Byte Register (C8051F220/1/6).............................................30

Figure 5.9. 8-Bit ADC Window Interrupt Examples.......................................................................................31

Table 5.1. 8-Bit ADC Electrical Characteristics.............................................................................................. 32

6. ADC (12-Bit, C8051F206 Only).........................................................................................33

Figure 6.1. 12-Bit ADC Functional Block Diagram........................................................................................33

6.1. Analog Multiplexer and PGA................................................................................................................ 33

6.2. ADC Modes of Operation......................................................................................................................33

Figure 6.2. 12-Bit ADC Track and Conversion Example Timing ...................................................................34

Figure 6.3. AMX0SL: AMUX Channel Select Register (C8051F220/1/6 and C8051F206) ..........................35

Figure 6.4. ADC0CF: ADC Configuration Register (C8051F220/1/6 and C8051F206).................................36

Figure 6.5. ADC0CN: ADC Control Register (C8051F220/1/6 and C8051F206) ..........................................37

Figure 6.6. ADC0H: ADC Data Word MSB Register (C8051F206) ............................................................. 38

TM

Microcontroller Core.............................................................................................................11

Page 2 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 6.7. ADC0L: ADC Data Word LSB Register (C8051F206) ...............................................................38

6.3. ADC Programmable Window Detector ................................................................................................. 38

Figure 6.8. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F206) ..................................... 39

Figure 6.9. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F206) ......................................39

Figure 6.10. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F206) ........................................ 39

Figure 6.11. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F206) ......................................... 39

Figure 6.12. 12-Bit ADC Window Interrupt Examples, Right Justified Data.................................................. 40

Figure 6.13. 12-Bit ADC Window Interrupt Examples, Left Justified Data....................................................41

Table 6.1. 12-Bit ADC Electrical Characteristics (C8015F206 only) ............................................................. 42

7. VOLTAGE REFERENCE (C8051F220/1/6) ...................................................................43

Figure 7.1. Voltage Reference Functional Block Diagram.............................................................................. 43

Figure 7.2. REF0CN: Reference Control Register ..........................................................................................44

Table 7.1. Reference Electrical Characteristics...............................................................................................44

8. COMPARATORS ..............................................................................................................45

Figure 8.1. Comparator Functional Block Diagram ........................................................................................ 45

Figure 8.2. Comparator Hysteresis Plot........................................................................................................... 46

Figure 8.3. CPT0CN: Comparator 0 Control Register .................................................................................... 47

Figure 8.4. CPT1CN: Comparator 1 Control Register .................................................................................... 48

Table 8.1. Comparator Electrical Characteristics ............................................................................................ 49

9. CIP-51 MICROCONTROLLER ......................................................................................50

Figure 9.1. CIP-51 Block Diagram.................................................................................................................. 50

9.1. INSTRUCTION SET ............................................................................................................................ 52

Table 9.1. CIP-51 Instruction Set Summary.................................................................................................... 52

9.2. MEMORY ORGANIZATION.............................................................................................................. 56

Figure 9.2. Memory Map................................................................................................................................. 57

9.3. SPECIAL FUNCTION REGISTERS....................................................................................................59

Table 9.2. Special Function Register Memory Map ........................................................................................59

Table 9.3. Special Function Registers ............................................................................................................. 59

Figure 9.3. SP: Stack Pointer........................................................................................................................... 62

Figure 9.4. DPL: Data Pointer Low Byte ........................................................................................................62

Figure 9.5. DPH: Data Pointer High Byte .......................................................................................................62

Figure 9.6. PSW: Program Status Word.......................................................................................................... 63

Figure 9.7. ACC: Accumulator........................................................................................................................64

Figure 9.8. B: B Register.................................................................................................................................64

9.4. INTERRUPT HANDLER ..................................................................................................................... 65

Table 9.4. Interrupt Summary..........................................................................................................................66

Figure 9.9. IE: Interrupt Enable....................................................................................................................... 67

Figure 9.10. IP: Interrupt Priority .................................................................................................................... 68

Figure 9.11. EIE1: Extended Interrupt Enable 1 ............................................................................................. 69

Figure 9.12. EIE2: Extended Interrupt Enable 2 ............................................................................................. 70

Figure 9.13. EIP1: Extended Interrupt Priority 1 ............................................................................................ 71

Figure 9.14. EIP2: Extended Interrupt Priority 2 ............................................................................................ 72

9.5. Power Management Modes ................................................................................................................... 73

Figure 9.15. PCON: Power Control Register .................................................................................................. 74

10. FLASH MEMORY.............................................................................................................75

10.1. Programming The Flash Memory ...................................................................................................... 75

Table 10.1. FLASH Memory Electrical Characteristics..................................................................................75

10.2. Non-volatile Data Storage .................................................................................................................76

10.3. Security Options ................................................................................................................................ 76

Figure 10.1. Flash Program Memory Security Bytes........................................................................................77

Figure 10.2. PSCTL: Program Store RW Control ........................................................................................... 78

Figure 10.3. FLSCL: Flash Memory Timing Prescaler ................................................................................... 79

Figure 10.4. FLACL: Flash Access Limit........................................................................................................79

11. ON-BOARD XRAM (C8051F226/236/206)......................................................................80

Page 3 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 11.1. EMI0CN: External Memory Interface Control............................................................................ 80

12. RESET SOURCES .............................................................................................................81

Figure 12.1. Reset Sources Diagram ...............................................................................................................81

12.1. Power-on Reset.................................................................................................................................. 82

12.2. Software Forced Reset ....................................................................................................................... 82

Figure 12.2. VDD Monitor Timing Diagram...................................................................................................82

12.3. Power-fail Reset.................................................................................................................................82

12.4. External Reset.................................................................................................................................... 83

12.5. Missing Clock Detector Reset ........................................................................................................... 83

12.6. Comparator 0 Reset ...........................................................................................................................83

12.7. Watchdog Timer Reset ......................................................................................................................83

Figure 12.3. WDTCN: Watchdog Timer Control Register..............................................................................84

Figure 12.4. RSTSRC: Reset Source Register.................................................................................................85

Table 12.1. VDD Monitor Electrical Characteristics ...................................................................................... 86

13. OSCILLATOR ...................................................................................................................87

Figure 13.1. Oscillator Diagram ...................................................................................................................... 87

Figure 13.2. OSCICN: Internal Oscillator Control Register............................................................................ 88

Table 13.1. Internal Oscillator Electrical Characteristics ................................................................................88

Figure 13.3. OSCXCN: External Oscillator Control Register ......................................................................... 89

13.1. External Crystal Example .................................................................................................................. 90

13.2. External RC Example ........................................................................................................................90

13.3. External Capacitor Example .............................................................................................................. 90

14. PORT INPUT/OUTPUT....................................................................................................91

14.1. Port I/O Initialization......................................................................................................................... 91

Figure 14.1. Port I/O Functional Block Diagram ............................................................................................ 92

Figure 14.2. Port I/O Cell Block Diagram.......................................................................................................92

Figure 14.3. PRT0MX: Port I/O MUX Register 0 .......................................................................................... 93

Figure 14.4. PRT1MX: Port I/O MUX Register 1 .......................................................................................... 94

Figure 14.5. PRT2MX: Port I/O MUX Register 2 .......................................................................................... 94

14.2. General Purpose Port I/O...................................................................................................................95

Figure 14.6. P0: Port0 Register ....................................................................................................................... 95

Figure 14.7. PRT0CF: Port0 Configuration Register ...................................................................................... 95

Figure 14.8. P0MODE: Port0 Digital/Analog Input Mode.............................................................................. 96

Figure 14.9. P1: Port1 Register ....................................................................................................................... 96

Figure 14.10. PRT1CF: Port1 Configuration Register .................................................................................... 96

Figure 14.12. PRT1IF: Port1 Interrupt Flag Register ...................................................................................... 97

Figure 14.13. P2: Port2 Register ..................................................................................................................... 98

Figure 14.14. PRT2CF: Port2 Configuration Register .................................................................................... 98

Figure 14.15

Figure 14.16. P3: Port3 Register* ................................................................................................................... 99

Figure 14.17. PRT3CF: Port3 Configuration Register* ..................................................................................99

Figure 14.18. P3MODE: Port3 Digital/Analog Input Mode*.......................................................................... 99

Table 14.1. Port I/O DC Electrical Characteristics........................................................................................100

. P2MODE: Port2 Digital/Analog Input Mode ........................................................................... 98

15. SERIAL PERIPHERAL INTERFACE BUS.................................................................101

Figure 15.1. SPI Block Diagram ................................................................................................................... 101

Figure 15.2. Typical SPI Interconnection...................................................................................................... 102

15.1. Signal Descriptions..........................................................................................................................102

15.2. Operation ......................................................................................................................................... 103

Figure 15.3. Full Duplex Operation............................................................................................................... 103

15.3. Serial Clock Timing.........................................................................................................................104

Figure 15.4. Data/Clock Timing Diagram .....................................................................................................104

15.4. SPI Special Function Registers........................................................................................................105

Figure 15.5. SPI0CFG: SPI Configuration Register ......................................................................................105

Figure 15.6. SPI0CN: SPI Control Register ..................................................................................................106

Page 4 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 15.7. SPI0CKR: SPI Clock Rate Register ..........................................................................................107

Figure 15.8. SPI0DAT: SPI Data Register .................................................................................................... 107

16. UART.................................................................................................................................108

Figure 16.1. UART Block Diagram .............................................................................................................. 108

16.1. UART Operational Modes...............................................................................................................109

Table 16.1. UART Modes ............................................................................................................................. 109

Figure 16.2. UART Mode 0 Interconnect......................................................................................................109

Figure 16.3. UART Mode 0 Timing Diagram ...............................................................................................109

Figure 16.4. UART Mode 1 Timing Diagram ...............................................................................................110

Figure 16.5. UART Modes 1, 2, and 3 Interconnect Diagram.......................................................................111

Figure 16.6. UART Modes 2 and 3 Timing Diagram.................................................................................... 111

16.2. Multiprocessor Communications..................................................................................................... 112

Figure 16.7. UART Multi-Processor Mode Interconnect Diagram ...............................................................112

Table 16.2. Oscillator Frequencies for Standard Baud Rates ........................................................................ 113

Figure 16.8. SBUF: Serial (UART) Data Buffer Register............................................................................. 113

Figure 16.9. SCON: Serial Port Control Register..........................................................................................114

17. TIMERS ............................................................................................................................115

17.1. Timer 0 and Timer 1........................................................................................................................115

Figure 17.1. T0 Mode 0 Block Diagram .......................................................................................................116

Figure 17.2. T0 Mode 2 Block Diagram .......................................................................................................117

Figure 17.3. T0 Mode 3 Block Diagram .......................................................................................................118

Figure 17.4. TCON: Timer Control Register.................................................................................................119

Figure 17.5. TMOD: Timer Mode Register...................................................................................................120

Figure 17.6. CKCON: Clock Control Register.............................................................................................. 121

Figure 17.7. TL0: Timer 0 Low Byte ............................................................................................................ 122

Figure 17.8. TL1: Timer 1 Low Byte ............................................................................................................ 122

Figure 17.9. TH0: Timer 0 High Byte ........................................................................................................... 122

Figure 17.10. TH1: Timer 1 High Byte ......................................................................................................... 122

17.2. Timer 2 ............................................................................................................................................123

Figure 17.11. T2 Mode 0 Block Diagram .....................................................................................................124

Figure 17.12. T2 Mode 1 Block Diagram .....................................................................................................125

Figure 17.13. T2 Mode 2 Block Diagram .....................................................................................................126

Figure 17.14. T2CON: Timer 2 Control Register..........................................................................................127

Figure 17.15. RCAP2L: Timer 2 Capture Register Low Byte.......................................................................128

Figure 17.16. RCAP2H: Timer 2 Capture Register High Byte......................................................................128

Figure 17.17. TL2: Timer 2 Low Byte .......................................................................................................... 128

Figure 17.18. TH2: Timer 2 High Byte ......................................................................................................... 128

18. JTAG .................................................................................................................................129

Figure 18.1. IR: JTAG Instruction Register ..................................................................................................129

18.1. Flash Programming Commands....................................................................................................... 130

Figure 18.2 FLASHCON: JTAG Flash Control Register .............................................................................. 131

Figure 18.3. FLASHADR: JTAG Flash Address Register ............................................................................. 131

Figure 18.4. FLASHDAT: JTAG Flash Data Register.................................................................................. 132

Figure 18.5. FLASHSCL: JTAG Flash Scale Register.................................................................................. 132

18.2. Boundary Scan Bypass and ID Code ...............................................................................................133

Figure 18.6. DEVICEID: JTAG Device ID Register .................................................................................... 133

18.3. Debug Support.................................................................................................................................133

1. SYSTEM OVERVIEW

The C8051F2xx is a family of fully integrated, mixed-signal System on a Chip MCU’s available with a true 8-bit
multi-channel ADC (‘F220/1/6 and ‘F206), or without an ADC (‘F230/1/6). Each model features an 8051­compatible microcontroller core with 8kbytes of FLASH memory. There are also UART and SPI serial interfaces
implemented in hardware (not “bit-banged” in user software). Products in this family feature 22 or 32 general

Page 5 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

purpose I/O pins, some of which can be used for assigned digital peripheral interface. Any pins may be configured
for use as analog input to the analog-to-digital converter (‘F220/1/6 and ‘F206 only). (See the Product Selection
Guide in Table 1.1.1 for a quick reference of each MCUs’ feature set.)

Other features include an on-board VDD monitor, WDT, and clock oscillator. On-board FLASH memory can be
reprogrammed in-circuit, and may also be used for non-volatile data storage. Integrated peripherals can also
individually shut down any or all of the peripherals to conserve power. All parts have 256 bytes of SRAM. Also, an
additional 1024 bytes of RAM is available in the ‘F226/’F236.

On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit debug using
the production MCU installed in the final application. This debug system supports inspection and modification of
memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and
digital peripherals are fully functional when emulating using JTAG.

Each MCU is specified for 2.7V to 3.6V operation over the industrial temperature range (-45C to +85C) and is
available in the 48-pin TFQP and 32-pin LFQP. The Port I/Os are tolerant for input signals up to 5V.

Table 1.1.1. Product Selection Guide

Part Number

C8051F206 25 8k 1280

C8051F220 25 8k 256

C8051F221 25 8k 256

C8051F226 25 8k 1280

C8051F230 25 8k 256

C8051F231 25 8k 256

C8051F236 25 8k 1280

MIPS (Peak)

FLASH Memory

RAM

√√

√√

√√

√√

√√

√√

√√

SPI

UART

Timers (16-bit)

Digital Port I/O’s

ADC Resolution (bits)

ADC Max Speed (ksps)

ADC Inputs

Voltage Comparators

3 32 12 100 32 2 48TQFP

3 32 8 100 32 2 48TQFP

3 22 8 100 22 2 32LQFP

3 32 8 100 32 2 48TQFP

3 32 - - - 2 48TQFP

3 22 - - - 2 32LQFP

3 32 - - - 2 48TQFP

Package

Page 6 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

VDD
VDD

GND

GND

TCK
TMS
TDI
TDO

/RST

VDDMONEN

XTAL1
XTAL2

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 1.1. C8051F206, C8051F220 and C8051F226 Block Diagram (48 TQFP)

Port I/O Mode

CP0

CP1

ADC

Config. &

Control

& Config.

Port 0
Latch

UART

Timer 0

Timer 1

Timer 2

Port 1
Latch

Comparator

Config.

Port 2
Latch

SPI

Port Mux

Control

Port 3
Latch

P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX

P1.0/CP0+
P1.1/CP0­P1.2/CP0
P1.3/CP1+
P1.4/CP1­P1.5/CP1
P1.6/SYSCLK
P1.7

P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

VREF

AIN0-AIN31

P
0

D

r

v

P
1

D

r

v

P
2

D

r

v

P
3

D

r

v

P
0

M
U
X

P

CP0+

CP0-

CP1+

CP1-

VREF

VREF

1

M
U
X

P
2

M
U
X

A
M
U
X

CP0

CP1

VDD

SAR
ADC

Digital Power

1024 Byte

XRAM

(Available in

8kbyte

FLASH

256 byte

SRAM

SFR Bus

Clock & Reset

Configuration

'F226)

Reset

8
0
5
1

C
o

r

e

JTAG

Emulation HW

Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

NC

NC

NC

System Clock

Page 7 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

VDD

GND

TCK
TMS
TDI
TDO

/RST

XTAL1
XTAL2

Digital Power

JTAG
Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

Emulation HW

PRELIMINARY

Figure 1.2 C8051F221 Block Diagram (32 LQFP)

Port I/O Mode

& Config.

Port 0
Latch

UART

Timer 0

Timer 1

Timer 2

Port 1

Reset

System Clock

8
0
5
1

C
o

r

e

8kbyte
FLASH

256 byte

SRAM

SFR Bus

Clock & Reset

Configuration

CP0

CP1

ADC

Config. &

Control

Latch

Comparator

Config.

Port 2
Latch

SPI

Port Mux

Control

Port 3
Latch

CP0

CP1

VDD

SAR
ADC

CP0+

CP0-

CP1+

CP1-

VREF

VREF

C8051F206

C8051F220/1/6

P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX

P1.0/CP0+
P1.1/CP0­P1.2/CP0
P1.3/CP1+
P1.4/CP1­P1.5/CP1
P1.6/SYSCLK
P1.7

P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5

VREF

AIN0-AIN21

P
0

D

r

v

P
1

D

r

v

P
2

D

r

v

P
0

M
U
X

P
1

M
U
X

P
2

M
U
X

A

M

U
X

Page 8 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

VDD

GND

GND

TCK
TMS
TDI
TDO

/RST

MONEN

XTAL1
XTAL2

NC

NC

NC

NC

NC

Digital P ower

PRELIMINARY

Figure 1.3 C8051F230 and C8051F236 Block Diagram (48 TQFP)

Port I/O Mode

& Config.

Port 0

Latch

UART

Timer 0

Timer 1

Timer 2

Port 1

Latch

CP0

CP1

Comparator

Config.

Port 2

Latch

SPI

Port Mux

Control

Port 3

Latch

CP0+

CP0

CP0-

CP1+

CP1

CP1-

JTAG
Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

Emulation HW

Reset

System Clock

8
0
5
1

C

SFR Bus

o

r

e

1024 Byte

XRAM

(Available in

'F236)

8kbyte

FLASH

256 byte

SRAM

Clock & Reset

Configuration

C8051F220/1/6

P
0

M
U
X

P
1

M
U
X

P
2

M
U
X

C8051F206

P
0

D

v

P
1

D

v

P
2

D

v

P
3

D

v

P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1

r

P0.6/T2
P0.7/T2EX

P1.0/CP0+
P1.1/CP0­P1.2/CP0
P1.3/CP1+
P1.4/CP1­P1.5/CP1

r

P1.6/SYSCLK
P1.7

P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5

r

P2.6
P2.7

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5

r

P3.6
P3.7

Page 9 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

VDD

GND

TCK
TMS
TDI
TDO

/RST

XTAL1
XTAL2

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 1.4 C8051F231 Block Diagram (32 LQFP)

Port I /O Mod e

Digital Power

Reset

8
0
5
1

C
o

r

e

8kbyte

FLASH

256 byte

SRAM

SFR Bus

Clock & Reset
Configurati on

JTAG

Emulation HW

Logic

VDD

Monitor,

WDT

External

Oscillator

Circuit

Internal

Oscillator

NC

System Clock

& Config.

Port 0
Latch

UART

Timer 0

Timer 1

Timer 2

Port 1
Latch

CP0

CP1

Comparator

Config.

Port 2
Latch

SPI

Port Mux

Control

Port 3
Latch

P
0

M
U
X

P

CP0+

CP0-

CP1+

CP1-

1

M
U
X

P
2

M
U
X

CP0

CP1

P
0

D

r

v

P
1

D

r

v

P
2

D

r

v

P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX

P1.0/CP0+
P1.1/CP0­P1.2/CP0
P1.3/CP1+
P1.4/CP1­P1.5/CP1
P1.6/SYSCLK
P1.7

P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5

Page 10 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

1.1. CIP-51TMMicrocontroller Core

1.1.1. Fully 8051 Compatible

The C8051F206, C8051F220/1/6 and C8051F230/1/6 utilize Cygnal’s proprietary CIP-51 microcontroller core. The
CIP-51 is fully compatible with the MCS-51
used to develop software. The core contains the peripherals included with a standard 8052, including three 16-bit
counter/timers, a full-duplex UART, 256 bytes of internal RAM, an optional 1024 bytes of XRAM, 128 byte Special
Function Register (SFR) address space, and four byte-wide I/O Ports.

1.1.2. Improved Throughput

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its instructions in
one or two system clock cycles, with only four instructions taking more than four system clock cycles.

The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:

TM

instruction set. Standard 803x/805x assemblers and compilers can be

Instructions

Clocks to Execute

265051473121

1 2 2/3 3 3/4 4 4/5 5 8

With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.5 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.

Figure 1.5. Comparison of Peak MCU Throughputs

25

20

15

MIPS

10

5

Cygnal
CIP-51

(25MHz clk)

Microchip

PIC17C75x

(33MHz clk)

Philips

80C51

(33MHz clk)

ADuC812

8051

(16MHz clk)

Page 11 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

1.1.3. Additional Features

The C8051F206, C8051F220/1/6 and C8051F230/1/6 have several key enhancements both inside and outside the
CIP-51 core to improve overall performance and ease of use in end applications.

The extended interrupt handler provides 22 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051),
allowing the numerous analog and digital peripherals to interrupt the controller. (An interrupt driven system requires
less intervention by the MCU, giving it more effective throughput.) The extra interrupt sources are very useful when
building multi-tasking, real-time systems.

There are up to six reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock
detector, a voltage level detection from Comparator 0, a forced software reset, and an external reset pin. The /RST
pin is bi-directional, accommodating an external reset, or allowing the internally generated reset to be output on the
/RST pin. The on-board VDD monitor is enabled by pulling the MONEN pin high (digital 1). The user may disable
each reset source except for the VDD monitor and Reset Input Pin from software. The watchdog timer may be
permanently enabled in software after a power-on reset during MCU initialization.

The MCU has an internal, stand-alone clock generator that is used by default as the system clock after reset. If
desired, the clock source may be switched “on the fly” to the external oscillator, which can use a crystal, ceramic
resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low
power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically
switching to the fast (up to 16MHz) internal oscillator as needed.

CP0+

CP0-

System

Clock

Comparator 0

+

-

Missing

Clock

Detector

EN

MCD

Enable

Figure 1.6. On-Board Clock and Reset

C0RSEF

VDD

WDT

PRE

EN

WDT

WDT

Enable

Strobe

CIP-51

MonEn

Supply
Monitor

+

-

SWRSF

(Software Reset)

System Reset

Core

Supply

Reset

Timeout

(wired-OR)

Reset
Funnel

/RST

Page 12 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

1.2. On-Board Memory

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with
the upper 128 bytes dual-mapped. An optional 1024 bytes of XRAM is available on the ‘F206, ‘F226 and ‘F236.
Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128­byte SFR address space. The lower 128 bytes of RAM are accessible via direct or indirect addressing. The first 32
bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit
addressable.

The MCU’s program memory consists of 8k + 128 bytes of FLASH. This memory may be reprogrammed in-system
in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses 0x1E00 to
0x1FFF are reserved for factory use. There is also a user programmable 128-byte sector at address 0x2000 to
0x207F, which may be useful as a table for storing software constants, nonvolatile configuration information, or as
additional program space. See Figure 1.7 for the MCU system memory map.

Figure 1.7. On-Board Memory Map

0x207F

0x2000

0x1FFF

0x1E00

0x1DFF

0x0000

PROGRAM MEMORY

128 Byte ISP FLASH

RESERVED

FLASH

(In-System

Programmable in 512

Byte Sectors)

0xFF

0x80

0x7F

0x30

0x2F

0x20

0x1F

0x00

0x3FF

0x000

DATA MEMORY

Upper 128 RAM

(Indirect Addressing

Only)

(Direct and Indirect

Addressing)

Bit Addressable

General Purpose

Registers

1024 Byte

XRAM

Special Function

Register's

(Direct Addressing Only)

Lower 128 RAM
(Direct and Indirect
Addressing)

Mapped into

External Data Memory

Space

(C8051F226/236/206 only)

Page 13 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

1.3. JTAG

The C8051F2xx have on-chip JTAG and debug logic that provide non-intrusive, full speed, in-circuit debug using
the production part installed in the end application using the four-pin JTAG I/F. The C8051F2xxDK is a

development kit with all the hardware and software necessary to develop application code and perform in-circuit
debug with the C8051F2xx. The kit includes software with a developer’s studio and debugger, an integrated 8051
assembler, and an RS-232 to JTAG interface module referred to as the EC. It also has a target application board
with a C8051F2xx installed and large prototyping area, plus the RS-232 and JTAG cables, and wall-mount power
supply. The Development Kit requires a Windows 9x, NT, or ME computer with one available RS-232 serial port.
As shown in Figure 1.8, the PC is connected via RS-232 to the EC. A six-inch ribbon cable connects the EC to the
user’s application board, picking up the four JTAG pins and VDD and GND. The EC takes its power from the
application board. It requires roughly 20mA at 2.7-3.6V. For applications where there is not sufficient power
available from the target board, the provided power supply can be connected directly to the EC.

This is a vastly superior configuration for developing and debugging embedded applications compared to standard
MCU Emulators, which use on-board “ICE Chips” and target cables and require the MCU in the application board to
be socketed. Cygnal’s debug environment both increases ease of use, and preserves the performance of the precision
analog peripherals.

Figure 1.8. Debug Environment Diagram

WINDOWS 95/98/NT/ME

CYGNAL Integrated

Development Environment

RS-232

EMULATION
CARTRIDGE

JTAG(x4),VDD,GND

VDD GND

C8051

F2XX

TARGET PCB

Page 14 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

1.4. Digital/Analog Configurable I/O

The standard 8051 Ports (0, 1, 2, and 3) are available on the device. The ports behave like standard 8051 ports with
a few enhancements.

Each port pin can be configured as either a push-pull or open-drain output. Any input that is configured as an analog
input will have its corresponding weak pull-up turned off.

Digital resources (timers, SPI, UART, system clock, and comparators) are routed to corresponding I/O pins by
configuring the port multiplexer. Port multiplexers are programmed by setting bits in SFR’s (please see Section 14).
Any of the 32 external port pins may be configured as either analog inputs or digital I/O (See Figure 1.9), so
effectively, all port pins are dual function.

Figure 1.9. Port I/O Functional Block Diagram

PRTnCF &

PnMODE
registers

Port0 I/O Cell

External

pins

P0.0/TX
P0.1/RX
P0.2/INT0
P0.3/INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX

T0,T1,

T2

Timers

UART

External

INT0 &

INT1

PRTnMX

Registers

Port

0

MUX

P1.0/CP0+
P1.1/CP0­P1.2/CP0
P1.3/CP1+
P1.4/CP1­P1.5/CP1
P1.6/SYSCK
P1.7

Any port pin ma y be

configur ed via software as an

analog input to the ADC

P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

SYSCLK

Comparators

0&1

SPI

ADC

Port

1

MUX

Port

2

MUX

A

M

U
X

Port1 I/O Cell

Port2 I/O Cell

Port3 I/O Cell

1.5. Serial Ports

The C8051F206, C8051F220/1/6 and C8051F230/1/6 include a Full-Duplex UART and SPI Bus. Each of the serial
buses is fully implemented in hardware and makes extensive use of the CIP-51’s interrupts, thus requiring very little
intervention by the CPU. The serial buses do not have to “share” resources such as timers, interrupts, or Port I/O, so
both of the serial buses may be used simultaneously. (You may use Timer1, Timer 2, or SYSCLK to generate baud
rates for UART).

Page 15 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

1.6. Analog to Digital Converter

The C8051F220/1/6 has an on-chip 8-bit SAR ADC and the C8051F206 has a 12-bit SAR ADC with a
programmable gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 8-bit with an INL of
±1/4 LSB, and or 12-bit accuracy with ±2 LSB. The voltage reference can be the power supply (VDD), or an
external reference voltage (VREF). Also, the system controller can place the ADC into a power-saving shutdown
mode when not in use. A programmable gain amplifier follows the analog multiplexer. The gain can be set in
software from 0.5 to 16 in powers of 2.

Conversions can be initiated in two ways; a software command or an overflow on Timer 2. This flexibility allows
the start of conversion to be triggered by software events, or convert continuously. A completed conversion causes
an interrupt, or a status bit can be polled in software to determine the end of conversion. The resulting 8-bit data
word is latched into an SFR upon completion of a conversion.

ADC data is continuously monitored by a programmable window detector, which interrupts the CPU when data is
within the user-programmed window. This allows the ADC to monitor key system voltages in background mode,
without the use of CPU resources.

Figure 1.10. ADC Diagram

VREF

AIN0

AIN1

AIN0-31 are port 0-3

pins -- any external

port pin may be configured as

an analog input

(only 22 input port pins on

'F221)

AIN31

...

32-to-1

AMUX

Programmable

Gain Amp

+

X

-

GND

Control & Data

SFR's

VDD

100ksps

SAR

ADC

SFR Bus

Page 16 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

1.7. Comparators

The MCU’s have two on-chip voltage comparators. The inputs of the comparators are available at package pins as
illustrated in Figure 1.11. Each comparator’s hysteresis is software programmable via special function registers
(SFR’s). Both voltage level and positive/negative going symmetry can be easily programmed by the user.
Additionally, comparator interrupts can be implemented on either rising or falling-edge output transitions. Please
see section 8 for details.

Figure 1.11. Comparator Diagram

P1.2

P1.5

P1.0

P1.1

P1.3

P1.4

CP0

CP1

+

CP0

-

+

CP1

-

Port1
MUX

CP0

CP1

SFR's

(Data

and

Cntrl)

CIP-51

and

Interrupt

Handler

Page 17 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

2. ABSOLUTE MAXIMUM RATINGS*

Ambient temperature under bias................................................................................................................. -55 to 125°C

Storage Temperature .................................................................................................................................. -65 to 150°C

Voltage on any Pin (except VDD and Port I/O) with respect to DGND ................................... -0.3V to (VDD + 0.3V)

Voltage on any Port I/O Pin or /RST with respect to DGND .................................................................... -0.3V to 5.8V

Voltage on VDD with respect to DGND ................................................................................................... -0.3V to 4.2V

Total Power Dissipation ......................................................................................................................................... 1.0W

Maximum output current sink by any Port pin .................................................................................................... 200mA

Maximum output current sink by any other I/O pin............................................................................................... 25mA

Maximum output current sourced by any Port pin............................................................................................... 200mA

Maximum output current sourced by any other I/O pin......................................................................................... 25mA

*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

3. GLOBAL DC ELECTRICAL CHARACTERISTICS

-40°Cto+85°C unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Power supply voltage (Note 1) 2.7 3.6 V
VDD supply current with
ADC and comparators
active, and CPU active
VDD supply current with
ADC and comparators
active, and CPU inactive
(Idle Mode).
VDD supply current with
ADC and comparators
inactive, and CPU active
Digital Supply Current with
CPU inactive (Idle Mode)

Digital Supply Current (Stop
mode), VDD monitor
enabled.
Digital Supply Current (Stop
Mode), VDD monitor
disabled
Digital Supply RAM Data
Retention Voltage
Specified Operating
Temperature Range

Clock=25MHz
Clock=1MHz
Clock=32kHz

Clock=25MHz
Clock=1MHz
Clock=32kHz

Clock=25MHz
Clock=1MHz
Clock=32kHz

Clock=25MHz
Clock=1MHz
Clock=32kHz

Oscillator not running 10

Oscillator not running 0.1

-40 +85

9.5

3.6

125

1.8

125

20

4.5

0.1
10

1.5 V

mA

µA

5

9
1

mA

µA

mA

µA

mA

µA
µA

µA

°C

Note 1: Power Supply must be greater than 1V and the MONEN pin must be pulled high for VDD monitor to
operate.

Page 18 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

4. PINOUT AND PACKAGE DEFINITIONS

Table 4.1 Pin Definitions

‘F220,
226,

‘F221,

Name

VDD

230,
236
48-Pin 32-Pin

11,318

231

Type Description

Digital Voltage Supply.

C8051F206

C8051F220/1/6

GND

MONEN

TCK
TMS
TDI

TDO

XTAL1

XTAL2

/RST

VREF

CP0+
CP0­CP0
CP1+
CP1­CP1
P0.0/

TX
P0.1/
RX
P0.2/
INT0
P0.3/
INT1
P0.4/
T0
P0.5/
T1
P0.6/
T2
P0.7/
T2EX
P1.0/
CP0+

5,6,

9

8,

13,

32
12

25 17
26 18
28 20

27 19

96

10 7

14 10

75

44
33
22

11
48 32
47 31
40 28

39 27

38 26

37 25

36 24

35 23

34 22

33 21

44

DIn

DIn
DIn
DIn

D Out

AIn

A Out

D I/O

A I/O

AIn
AIn
D Out
AIn
AIn
D Out
D I/O

AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn

Ground. (Note: Pins 5,6, and 8 on the 48-pin package are not connected
(NC), but it is recommended that they be connected to ground.)

Monitor Enable (on 48 pin package ONLY). Enables reset voltage monitor
function when pulled high (logic “1”).
JTAG Test Clock with internal pull-up.

JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of

TCK.
JTAG Test Data Output. Data is shifted out on TDO on the falling edge of
TCK. TDO output is a tri-state driver.
Crystal Input. This pin is the return for the internal oscillator circuit for a
crystal or ceramic resonator. For a precision internal clock, connect a crystal
or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external
CMOS clock, this becomes the system clock.
Crystal Output. This pin is the excitation driver for a crystal or ceramic
resonator.
Chip Reset. Open-drain output of internal Voltage Supply monitor. Is driven
low when VDD is < 2.7V and MONEN=1, or when a ‘1’is written to PORSF.
An external source can force a system reset by driving this pin low.
Voltage Reference. When configured as an input, this pin is the voltage
reference for the ADC. Otherwise, VDD will be the reference. NOTE: this
pin is Not Connected (NC) on ‘F230/1/6.
Comparator 0 Non-Inverting Input.

Comparator 0 Inverting Input.
Comparator 0 Output
Comparator 1 Non-Inverting Input.
Comparator 1 Inverting Input.
Comparator 1 Output
Port0 Bit0. (See the Port I/O Sub-System section for complete description).

Port0 Bit1. (See the Port I/O Sub-System section for complete description).

Port0 Bit2. (See the Port I/O Sub-System section for complete description).

Port0 Bit3. (See the Port I/O Sub-System section for complete description).

Port0 Bit4. (See the Port I/O Sub-System section for complete description).

Port0 Bit5. (See the Port I/O Sub-System section for complete description).

Port0 Bit6. (See the Port I/O Sub-System section for complete description).

Port0 Bit7. (See the Port I/O Sub-System section for complete description).

Port1 Bit0. (See the Port I/O Sub-System section for complete description).

Page 19 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

Name

P1.1/
CP0­P1.2/
CP0
P1.3/
CP1+
P1.4/
CP1­P1.5/
CP1
P1.6/

SYSCLK

P1.7

P2.0/
SCK
P2.1/
MISO
P2.2/
MOSI
P2.3/
NSS
P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

‘F220,
226,

‘F221,
230,
236
48-Pin 32-Pin

231

33

22

11

48 32

47 31

46 30

45 29

24 16

23 15

22 14

21 13

15 11

16 12

17

18

44

43

42

41

30

29

20

19

PRELIMINARY

Type Description

D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn
D I/O
AIn

Port1 Bit1. (See the Port I/O Sub-System section for complete description).

Port1 Bit2. (See the Port I/O Sub-System section for complete description).

Port1 Bit3. (See the Port I/O Sub-System section for complete description).

Port1 Bit4. (See the Port I/O Sub-System section for complete description).

Port1 Bit5. (See the Port I/O Sub-System section for complete description).

Port1 Bit6. (See the Port I/O Sub-System section for complete description).

Port1 Bit7. (See the Port I/O Sub-System section for complete description).

Port2 Bit0. (See the Port I/O Sub-System section for complete description).

Port2 Bit1. (See the Port I/O Sub-System section for complete description).

Port2 Bit2. (See the Port I/O Sub-System section for complete description).

Port2 Bit3. (See the Port I/O Sub-System section for complete description).

Port2 Bit4. (See the Port I/O Sub-System section for complete description).

Port2 Bit5. (See the Port I/O Sub-System section for complete description).

Port2 Bit6. (See the Port I/O Sub-System section for complete description).

Port2 Bit7. (See the Port I/O Sub-System section for complete description).

Port3 Bit0. (See the Port I/O Sub-System section for complete description).

Port3 Bit1. (See the Port I/O Sub-System section for complete description).

Port3 Bit2. (See the Port I/O Sub-System section for complete description).

Port3 Bit3. (See the Port I/O Sub-System section for complete description).

Port3 Bit4. (See the Port I/O Sub-System section for complete description).

Port3 Bit5. (See the Port I/O Sub-System section for complete description).

Port3 Bit6. (See the Port I/O Sub-System section for complete description).

Port3 Bit7. (See the Port I/O Sub-System section for complete description).

C8051F206

C8051F220/1/6

Page 20 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

Figure 4.1 TQFP-48 Pin Diagram

P1.4/CP1-

P1.5/CP1

48

47

P1.7

P1.6/SYSCLK

46

45

P3.1

P3.0

44

P3.2

P3.3

43

42

41

C8051F206

C8051F220/1/6

P0.2/INT0

P0.1/RX

P0.0/TX

40

39

P0.3/INT1

38

37

P1.3/CP1+

P1.2/CP0

P1.1/CP0-

P1.0/CP0+

NC

NC

VREF*

NC

XTAL1

XTAL2

VDD

MONEN

1

2

3

4

5

6

7

8

9

10

11

12

C8051F220/6
C8051F230/6

C8051F206

*Pin 7 is a No Connect on

36

35

34

33

32

31

30

29

28

27

26

25

P0.4/T0

P0.5/T1

P0.6/T2

P0.7/T2EX

GND

VDD

P3.4

P3.5

TDI

TDO

TMS

TCK

'F230/6

13

14

15

16

17

18

19

20

21

22

23

24

P2.5

P2.4

/RST

GND

P2.6

P3.7

P2.7

P3.6

P2.3/NSS

P2.2/MOSI

P2.0/SCK

P2.1/MISO

Page 21 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

Figure 4.2 LQFP-32 Pin Diagram

P0.1/RX

P1.4/CP1-

32

P1.5/CP1

31

P1.6/SYSCLK

30

P1.7

29

P0.0/TX

28

27

P0.2/INT0

26

C8051F206

C8051F220/1/6

P0.3/INT1

25

P1.3/CP1+

P1.2/CP0

P1.1/CP0-

P1.0/CP0+

VREF*

XTAL1

XTAL2

VDD

1

2

3

4

5

6

7

8

9

GND

C8051F221
C8051F231

*Pin 5 is a No Connect

(NC) on 'F231

10

11

12

13

P2.5

P2.4

RESTB

P2.3/NSS

14

P2.2/MOSI

15

P2.1/MISO

16

P2.0/SCK

24

23

22

21

20

19

18

17

P0.4/T0

P0.5/T1

P0.6/T2

P0.7/T2EX

TDI

TDO

TMS

TCK

Page 22 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

Figure 4.3 TQFP-48 Package Drawing

C8051F206

C8051F220/1/6

48

PIN 1

IDENTIFIER

A2

D

D1

E1

E

1

e

A

A

A1

A2

b

D

D1

e

E

MIN

(mm)

-

0.05

0.95

0.17

-

-

-

-

NOM
(mm)

-

-

1.00

0.22

9.00

7.00

0.50

9.00

MAX

(mm)

1.20

0.15

1.05

0.27

-

-

-

-

E1

A1

b

-

7.00

-

Page 23 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

Figure 4.4 LQFP-32 Package Drawing

D

D1

A

A1

C8051F206

C8051F220/1/6

MIN

NOM

(mm)

0.05

(mm)

-

MAX

(mm)

-

1.60

-

0.15

32

PIN 1

IDENTIFIER

A2

E1

1

E

A

A1

A2

b

D

D1

e

E

E1

1.35

0.30

-

-

-

-

-

1.40

0.37

9.00

7.00

0.80

9.00

7.00

1.45

0.45

-

-

-

-

-

eb

Page 24 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

5. ADC (8-Bit, C8051F220/1/6 Only)

Description

The ADC subsystem for the C8051F220/1/6 consists of configurable analog multiplexer (AMUX), a programmable
gain amplifier (PGA), and a 100ksps, 8-bit successive-approximation-register ADC with integrated track-and-hold
and programmable window detector (see Figure 5.1). The AMUX, PGA, Data Conversion Modes, and Window
Detector are all configurable under software control via the Special Function Register’s shown in Figure 5.1. The
ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the ADCEN bit in the ADC Control register
(ADC0CN, Figure 5.5) is set to 1. The ADC subsystem is in low power shutdown when this bit is 0.

Figure 5.1. 8-Bit ADC Functional Block Diagram

AIN0-31 are port 0-3

pins -- any external

port pin may be configured as an

analog input

AIN0

AIN31

...

32-to-1

AMUX

X

AMXEN

PRTSL0

PRTSL1

AMX0SL

GND

PINSL2

+

ADCEN

VDD

VDD

8-Bit

SAR

ADC0LTHADC0GTH

VDD VREF

SYSCLK

REF

8

16

ADC0H

Dig

Comp

ADWINT

8

-

ADC

GND

PINSL0

PINSL1

ADCSC0

ADCSC1

ADCSC2

ADC0CF

AMPGN2

AMPGN1

AMPGN0

ADCEN

ADCTM

ADCINT

ADC0CN

ADBUSY

ADLJST

ADWINT

ADSTM0

ADSTM1

Conversion Start

T2 OV

S

Y

U

B

D

A

)

w

(

5.1. Analog Multiplexer and PGA

Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the desired
analog input pin. (See Figure 5.3). When the AMUX is enabled, the user selects which port is to be used (bits
PRTSL0-1), and then the pin in the selected port (bits PINSL0-2) to be the analog input.
The table in shows AMUX functionality by channel for each possible configuration. The PGA amplifies the AMUX
output signal by an amount determined by the states of the AMPGN2-0 bits in the ADC Configuration register,
ADC0CF (Figure 5.4). The PGA can be software-programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain
of 1 on reset.

5.2. ADC Modes of Operation

The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the system
clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of 1,2,4,8, or 16 are
supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to
accommodate different system clock speeds.

Page 25 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:

1. Writing a 1 to the ADBUSY bit of ADC0CN;

2. A Timer 2 overflow (i.e. timed continuous conversions).

Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the ADC0CN register.
Converted data is available in the ADC data word register, ADC0H.

The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of two different low
power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):

1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;

2. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.

Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.

Figure 5.2. 12-Bit ADC Track and Conversion Example Timing

CNVSTR

(ADSTM[1:0]=10)

SAR Clocks

ADCTM=1

ADCTM=0

Timer2, Timer3 Overflow;

Write1toADBUSY

(ADSTM[1:0]=00, 01, 11)

SAR Clocks

ADCTM=1

SAR Clocks

ADCTM=0

A. ADC Timing for External Trigger Source

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Low Power or

Convert

Track Convert Low Power Mode

Track Or Convert

Convert Track

B. ADC Timing for Internal Trigger Sources

1 2 3 4 5 6 7 8 9 1011121314151617 18 19

Low Power or

Convert

Track or Convert

Track Convert Low Power Mode

1 2 3 4 5 6 7 8 9 10111213141516

Convert Track

Page 26 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

p

C8051F206

C8051F220/1/6

Figure 5.3. AMX0SL: AMUX Channel Select Register (C8051F220/1/6 and C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - AMXEN PRTSL1 PRTSL0 PINSL2 PINSL1 PINSL0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bits 7-6: UNUSED. Read = 00b; Write = don’t care
Bit 5: AMXEN enable

0: AMXEN disabled and port pins are unavailable for analog use.
1: AMXEN enabled to use/select port pins for analog use.

Bits 4-3: PRTSL1-0: Port Select Bits*.

00: Port0 select to configure pin for analog input from this port.
01: Port1 select to configure pin for analog input from this port.
10: Port2 select to configure pin for analog input from this port.
11: Port3 select to configure pin for analog input from this port.

Bits 2-0:PINSL2-0: Pin Select Bits

000: Pin 0 of selected port (above) to be used for analog input.
001: Pin 1 of selected port (above) to be used for analog input.
010: Pin 2 of selected port (above) to be used for analog input.
011: Pin 3 of selected port (above) to be used for analog input.
100: Pin 4 of selected port (above) to be used for analog input.
101: Pin 5 of selected port (above) to be used for analog input.
110: Pin 6 of selected port (above) to be used for analog input.
111: Pin 7 of selected

ort(above)to be used for analoginput.

SFR Address:

0xBB

* Selecting a port for analog input does NOT default all pins of that port as analog input. After selecting a
port for analog input, a pin must be selected using pin select bits (PINSL2-0). For example, after setting the
AMXEN to ‘1’, setting PRTSL1-0 to “11”, and setting PINSL2-0 to “100” P3.4 is configured as analog input.
All other Port 3 pins remain as GPIO pins. Also note that in order to use a port pin as analog input, its input
mode should be set to analog. Please see section 14.2.

Page 27 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 5.4. ADC0CF: ADC Configuration Register (C8051F220/1/6 and C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ADCSC2 ADCSC1 ADCSC0 - - AMPGN2 AMPGN1 AMPGN0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits

000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks

NOTE: SAR conversion clock should be less than or equal to 2MHz.
Bits4-3: UNUSED. Read = 00b; Write = don’t care
Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain

000: Gain = 1

001: Gain = 2

010: Gain = 4

011: Gain = 8

10x: Gain = 16

11x: Gain = 0.5

01100000

SFR Address:

0xBC

Page 28 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 5.5. ADC0CN: ADC Control Register (C8051F220/1/6 and C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ADCEN ADCTM ADCINT ADBUSY ADSTM1 ADSTM0 ADWINT ADLJST 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

(bit addressable)

Bit7: ADCEN: ADC Enable Bit

0: ADC Disabled. ADC is in low power shutdown.

1: ADC Enabled. ADC is active and ready for data conversions.
Bit6: ADCTM: ADC Track Mode Bit

0: When the ADC is enabled, tracking is continuous unless a conversion is in process

1: Tracking Defined by ADSTM1-0 bits

ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: RESERVED
10: RESERVED
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks

Bit5: ADCINT: ADC Conversion Complete Interrupt Flag (cleared by software).

0: ADC has not completed a data conversion since the last time this flag was cleared

1: ADC has completed a data conversion
Bit4: ADBUSY: ADC Busy Bit

Read

0: ADC Conversion complete or no valid data has been converted since a reset. The falling

edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b

Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits

00: ADC conversion started upon a write of 1 to ADBUSY
01: RESERVED
10: RESERVED
11: ADC conversions initiated on overflows of Timer 2

Bit1: ADWINT: ADC Window Compare Interrupt Flag

0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred

Bit0: ADLJST: ADC Left Justify Data Bit (Used on C8051F206 only)

0: Data in ADC0H:ADC0L registers are right justified.
1: Data in ADC0H:ADC0L registers are left justified.

SFR Address:

0xE8

Page 29 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1

PRELIMINARY

C8051F206

C8051F220/1/6

Figure 5.6. ADC0H: ADC Data Word Register (C8051F220/1/6 and C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

MSB LSB 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bits7-0: ADC Data Word Bits

EXAMPLE: ADC Data Word Conversion Map

SFR Address:

0xBF

AIN – GND(Volts)

ADC0H

REF x (255/256) 0xFF
REF x ½ 0x80
REF x (127/256) 0x7F
00x00

5.3. ADC Programmable Window Detector

The ADC programmable window detector is very useful in many applications. It continuously compares the ADC
output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is
especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled
mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than
registers (ADC0GTH and ADC0LTH).

Figure 5.7. ADC0GTH: ADC Greater-Than Data Register (C8051F220/1/6 and C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bits7-0:
The high byte of the ADC Greater-Than Data Word.

SFR Address:

0xC5

Figure 5.8. ADC0LTH: ADC Less-Than Data Byte Register (C8051F220/1/6 and C8051F206)

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

0xC7

Bits7-0:
ThehighbyteoftheADCLess-ThanDataWord.

Page 30 CYGNAL Integrated Products, Inc.  2001 5.2001; Rev. 1.1