Silicon Laboratories C8051F120 Technical data

C8051F120

100 MIPS, 128 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU

Analog Peripherals

12-Bit ADC

- ±1 LSB INL; no missing codes

- Programmable throughput up to 100 ksps

- 8 external inputs; programmable as single-ended or differential

- Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5

- Data-dependent windowed interrupt generator

- Built-in temperature sensor (±3 °C)

8-Bit ADC

- ±1 LSB INL; no missing codes

- Programmable throughput up to 500 ksps

- 8 external inputs

- Programmable amplifier gain: 4, 2, 1, 0.5

Two 12-Bit DACs

- Can synchronize outputs to timers for jitter-free waveform generation

Two Comparators
Internal Voltage Reference
VDD Monitor/Brown-out Detector

On-Chip JTAG Debug & Boundary Scan

- On-chip debug circuitry facilitates full speed, non-intrusive in-system

debug (no emulator required)

- Provides breakpoints, single stepping, watchpoints, stack monitor

- Inspect/modify memory and registers

- Superior performance to emulation systems using ICE-chips, target

pods, and sockets

- IEEE1149.1 compliant boundary scan

VDD
VDD

VDD
DGND
DGND
DGND

AV+

AV+
AGND
AGND

TCK

TMS

TDO

RST

MONEN

XTAL1
XTAL2

VREF

VREFD

DAC1

DAC0

VREF0

AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7

CP0+

CP0-

CP1+

CP1-

TDI

Digital Power

Analog Power

Monitor

External

Oscillator

Circuit

Internal

2%

Oscillator

A
M
U
X

CP0

VDD

JTAG
Logic

VREF

DAC1

(12-Bit)

DAC0

(12-Bit)

CP1

Boundary Scan

WDT

Prog
Gain

TEMP

SENSOR

Debug HW

N/M
PLL

Reset

System
Clock

ADC

100 ksps

(12-Bit)

8

SFR Bus

0

8

Target Buffer

5
1

C

o

r

e

16 x 16 Mult/Acc

128 kB
FLASH

256 B

RAM

8 kB

XRAM

External Data Memory Bus

(2-cycle)

256 Byte

Branch

Prefetch

HW

32

High-Speed 8051 µC Core

- Pipelined instruction architecture; executes 70% of instructions in 1 or 2

system clocks

- Up to 100 MIPS throughput with 100 MHz system clock

- 16 x 16 multiply/accumulate engine (2-cycle)

Memory

- 8448 bytes data RAM

- 128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes

are reserved)

- External parallel data memory interface

Digital Peripherals

- 64 port I/O; all are 5 V tolerant

- Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial

ports available concurrently

- Programmable 16-bit counter/timer array with six capture/compare

modules

- 5 general-purpose 16-bit counter/timers

- Dedicated watchdog timer; bidirectional reset

- Real-time clock mode using timer 3 or PCA

Clock Sources

- Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation

- On-chip programmable PLL: up to 100 MHz

- External oscillator: Crystal, RC, C, or Clock

Supply Voltage: 3.0 to 3.6 V

- Typical operating current: 50 mA at 100 MHz

- Typical stop mode current: 0.4 uA

100-Pin TQFP
Temperature Range: –40 to +85 °C

UART0

UART1

SMBus

SPI Bus

6 Chnl

PCA

Timers

0, 1, 2, 4

Timer 3

P0, P1,

P2, P3

Latches

Bus Control

Address Bus

Data Bus

ADC
500 ksps
(8-Bit)

C
T
L

A
d
d

r

D
a

t

a

C
R
O
S
S
B
A
R

P4 Latch

P5 Latch

P6 Latch

P7 Latch

P0

Drv

P1

Drv

P2

Drv

P3

Drv

A

8:1

M

Prog
Gain

U
X

P4

DRV

P5

DRV

P6

DRV

P7

DRV

P0.0

P0.7

P1.0/AIN1.0

P1.7/AIN1.7

P2.0

P2.7

P3.0

P3.7

VREF1

P4.0

P4.4
P4.5/ALE
P4.6/RD
P4.7/WR

P5.0/A8

P5.7/A15

P6.0/A0

P6.7/A7

P7.0/D0

P7.7/D7

Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 10.6.2004

C8051F120

100 MIPS, 128 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU

Selected Electrical Specifications

(TA = –40 to +85 C°, VDD = 3.0 V unless otherwise specified)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GLOBAL CHARACTERISTICS

Supply Voltage 3.0 3.6 V
Supply Current
(CPU active)

Supply Current
(shutdown)
Clock Frequency Range DC 100 MHz

INTERNAL CLOCKS

Oscillator Frequency 24.0 24.5 25.0 MHz
PLL Frequency 96 98 100 MHz

A/D CONVERTER

Resolution 12 bits
Integral Nonlinearity
Differential Nonlinearity Guaranteed Monotonic
Signal-to-Noise Plus
Distortion
Throughput Rate 100 ksps

D/A CONVERTERS

Resolution 12 bits
Differential Nonlinearity Guaranteed Monotonic
Output Settling Time 10 µS

Clock = 100 MHz
Clock = 1 MHz
Clock = 32 kHz
Oscillator off; VDD Monitor Enabled
Oscillator off; V

Monitor Disabled

DD

50

0.6
16

10

0.4

mA

mA

µA

µA

µA

±1
±1

LSB
LSB

66 69 dB

±1

LSB

100

PIN 1

DESIGNATOR

A2

Package Information

D

D1

1

e

b

C8051F120DK Development Kit

MIN

NOM

(mm)

A

A1

0.05

A2

0.95

b

0.17

D

D1

E1 E

e

E

E1

A

A1

MAX

(mm)

(mm)

-

-

1.20

-

0.15

1.00

1.05

0.22

0.27

-

16.00

-

-

14.00

-

-

0.50

-

-

16.00

-

-

14.00

-

Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 10.6.2004

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