Silicon Laboratories C8051F065 User Manual

C8051F065

25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU

Analog Peripherals

Two 16-Bit ADCs

- ±0.75 LSB INL; no missing codes

- Programmable throughput up to 1 Msps (each ADC)

- 1 external input each; programmable as two single-ended or one differ-

ential ADC

- DMA to XRAM or external memory interface

- Data-dependent windowed interrupt generator

Three Comparators

- 16 programmable hysteresis values

- Configurable to generate interrupts or reset

Internal Voltage Reference
Precision VDD Monitor/Brown-out Detector

On-Chip JTAG Debug & Boundary Scan

- On-chip debug circuitry facilitates full speed, non-intrusive in-system

debug (no emulator required)

- Provides breakpoints, single stepping, watchpoints, stack monitor

- Inspect/modify memory and registers

- Superior performance to emulation systems using ICE-chips, target

pods, and sockets

- IEEE1149.1 compliant boundary scan

High-Speed 8051 µC Core

- Pipelined instruction architecture; executes 70% of instructions in 1 or 2

system clocks

- Up to 25 MIPS throughput with 25 MHz system clock

- Expanded interrupt handler

Memory

- 4352 bytes data RAM

- 64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes

are reserved)

Digital Peripherals

- 24 port I/O; all are 5 V tolerant

- Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial

ports available concurrently

- Programmable 16-bit counter/timer array with six capture/compare mod-

ules

- 5 general-purpose 16-bit counter/timers

- Dedicated watchdog timer; bidirectional reset

- Real-time clock mode using timers or PCA

Clock Sources

- Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation

- External oscillator: Crystal, RC, C, or Clock

- Can switch between clock sources on-the-fly

Supply Voltage: 2.7 to 3.6 V

- Typical operating current: 18 mA at 25 MHz

- Multiple power saving sleep and shutdown modes

64-Pin TQFP
Temperature Range: –40 to +85 °C

VDD
VDD
VDD

DGND
DGND
DGND

AV+

AGND

TCK
TMS

TDO

RST

MONEN

XTAL1
XTAL2

VREF

AVDD

ADGND

AV+

AGND

VREF0

VRGND0

AIN0

AIN0G

VBGAP0

CNVSTR0

AV+

AGND

VREF1

VRGND1

AIN1

AIN1G

VBGAP1

CNVSTR1

Digital Power

8

Analog Power

Boundary Scan

TDI

JTAG
Logic

VDD Monitor

External

Oscillator

Circuit

25 MHz 2%

Internal

Oscillator

VREF

Debug HW

WDT

AVDD

ADGND

System Clock

ADC0
1 Msps
(16-Bit)

ADC1
1 Msps
(16-Bit)

R
E
S
U
L
T
0

R
E
S
U
L
T
1

Reset

0
5
1

C

o

r

e

+

Σ

-

SFR Bus

64 kB

FLASH

256 Byte

RAM

4 kB

RAM

External Data

Memory Bus

D

I

DMA

F
F

EMIF

Cntrl

UART0

UART1

SMBus

SPI Bus

PCA

Timers 0,

1, 2,3,4

P0, P1,

P2, P3

Latches

C
R
O
S
S
B
A
R

CP1

Ctrl Latch

Data Latch

CP0

+

-

CP2

P4 Latch

P5 Latch

Addr15-8

P6 Latch

Addr7-0

P7 Latch

P0

Drv

P1

Drv

P2

Drv

P3

Drv

P2.6

+

P2.7

­P2.2
P2.3

P2.4

+

P2.5

-

P4

DRV

P5

DRV

P6

DRV

P7

DRV

P0.0

P0.7

P1.0/AIN2.0

P1.7/AIN2.7

P2.0

P2.7

Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 7.28.04

C8051F065

25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU

Selected Electrical Specifications

(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GLOBAL CHARACTERISTICS

Supply Voltage 2.7 3.6 V
Supply Current
(CPU active)

Supply Current
(shutdown)

Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz; V

Monitor Enabled

DD

Oscillator not running; VDD Monitor
Disabled

18

0.7
20

0.1 µA

Clock Frequency Range DC 25 MHz

16-BIT A/D CONVERTERS

Resolution 16 bits
Integral Nonlinearity Single-ended Mode

Differential Mode
Differential Nonlinearity Guaranteed Monotonic
Signal-to-Noise Plus

Distortion

Fin = 10 kHz, Single-ended

Fin = 10 kHz, Differential
Total Harmonic Distortion Fin = 10 kHz, Single-ended

Fin = 10 kHz, Differential
Spurious-Free Dynamic
Range

Fin = 10 kHz, Single-ended

Fin = 10 kHz, Differential

±0.75

0.50

±

0.5

±

86

89

96

103

97

104
Throughput Rate 1 Msps
Input Voltage Range Single-ended (AINn–AINnG)

Differential (AIN0–AIN1)
Power Supply Current
(each ADC)

Operating Mode, 1 Msps

(AVDD + AV+)

Shutdown Mode

–V

0

REF

V

5.5
1

mA

mA

µA

±2
±
±

1
1

LSB
LSB

LSB

dB

dB

dB

dB

dB

dB

REF

V

REF

V
V

mA

µA

64

PIN 1

DESIGNATOR

A2

Package Information

D

D1

1

e

b

A1

C8051F060DK Development Kit

MIN

NOM

(mm)

A

A1

E1

E

A

0.05

A2

0.95

b

0.17

D

D1

e

E

E1

MAX

(mm)

(mm)

-

-

1.20

-

0.15

-

1.05

0.22

0.27

-

12.00

-

-

10.00

-

-

0.50

-

-

12.00

-

-

10.00

-

Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 7.28.04

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