C8051F040/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 10 or 12-Bit SAR ADC
• 12-bit (C8051F040/1) or
10-bit (C8051F042/3/4/5/6/7) resolution
• ± 1 LSB INL, guaranteed no missing codes
• Programmable throughput up to 100 ksps
• 13 External Inputs; single-ended or differential
• SW programmable high voltage difference amplifier
• Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
• Data-dependent windowed interrupt generator
• Built-in temperature sensor
- 8-bit SAR ADC (C8051F040/1/2/3 only)
• Programmable throughput up to 500 ksps
• 8 External Inputs, single-ended or differential
• Programmable amplifier gain: 4, 2, 1, 0.5
- Two 12-bit DACs (C8051F040/1/2/3 only)
• Can synchronize outputs to timers for jitter-free waveform generation
- Three Analog Comparators
• Programmable hysteresis/response time
- Voltage Reference
- Precision V
Monitor/Brown-Out Detector
DD
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full- speed, non-
intrusive in-circuit/in-system debugging
- Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- IEEE1149.1 compliant boundary scan
- Complete development kit
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- 20 vectored interrupt sources
Memory
- 4352 bytes internal data RAM (4 k + 256)
- 64 kB (C8051F040/1/2/3/4/5)
or 32 kB (C8051F046/7) Flash; in-system programmable in 512-byte sectors
- External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
Digital Peripherals
- 8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant
- 4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant
- Bosch Controller Area Network (CAN 2.0B), hard-
ware SMBus™ (I2C™ Compatible), SPI™, and
two
UART serial ports available concurrently
- Programmable 16-bit counter/timer array with
capture/compare modules
6
- 5 general purpose 16-bit counter/timers
- Dedicated watch-dog timer; bi-directional reset pin
Clock Sources
- Internal calibrated programmable oscillator: 3 to
MHz
24.5
- External oscillator: crystal, RC, C, or clock
- Real-time clock mode using Timer 2, 3, 4, or PCA
Supply Voltage: 2.7 to 3.6 V
- Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
- Temperature Range: –40 to +85 °C
ANALOG PERIPHERALS
TEMP
AMUX
PGA
AMUX
12-Bit
DAC
12-Bit
DAC
C8051F041/2/3
ONLY
SENSOR
PGA
VREF
500 ksps
12/10-bit
100 ksps
ADC
8-bit
ADC
+
-
VOLTAGE COMPARATORS
HV
DIFF
AMP
+
+
-
-
DIGITAL I/O
CAN
2.0B
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
CROSSBAR
External Memory Interface
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
100 pin64 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25 MIPS)
20
INTERRUPTS
64 kB/32 kB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
CLOCK
CIRCUIT
JTAG
SANITY
CONTROL
Rev. 1.4 11/04 Copyright © 2004 by Silicon Laboratories C8051F04x
C8051F040/1/2/3/4/5/6/7
NOTES:
2 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 25
1.1.1. Fully 8051 Compatible.............................................................................. 25
1.1.2. Improved Throughput............................................................................... 25
1.1.3. Additional Features .................................................................................. 26
1.2. On-Chip Memory............................................................................................... 27
1.3. JTAG Debug and Boundary Scan..................................................................... 28
1.4. Programmable Digital I/O and Crossbar ........................................................... 29
1.5. Programmable Counter Array ........................................................................... 30
1.6. Controller Area Network.................................................................................... 31
1.7. Serial Ports ....................................................................................................... 31
1.8. 12/10-Bit Analog to Digital Converter................................................................ 32
1.9. 8-Bit Analog to Digital Converter (C8051F040/1/2/3 Only) ............................... 33
1.10.Comparators and DACs ................................................................................... 34
2. Absolute Maximum Ratings .................................................................................. 35
3. Global DC Electrical Characteristic ...................................................................... 36
4. Pinout and Package Definitions............................................................................ 37
5. 12-Bit ADC (ADC0, C8051F040/1 Only)................................................................. 47
5.1. Analog Multiplexer and PGA............................................................................. 47
5.1.1. Analog Input Configuration....................................................................... 48
5.2. High Voltage Difference Amplifier ..................................................................... 52
5.3. ADC Modes of Operation.................................................................................. 54
5.3.1. Starting a Conversion............................................................................... 54
5.3.2. Tracking Modes........................................................................................ 54
5.3.3. Settling Time Requirements..................................................................... 56
5.4. ADC0 Programmable Window Detector ........................................................... 62
6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)..................................................... 69
6.1. Analog Multiplexer and PGA............................................................................. 69
6.1.1. Analog Input Configuration....................................................................... 70
6.2. High Voltage Difference Amplifier ..................................................................... 74
6.3. ADC Modes of Operation.................................................................................. 76
6.3.1. Starting a Conversion............................................................................... 76
6.3.2. Tracking Modes........................................................................................ 76
6.3.3. Settling Time Requirements..................................................................... 78
6.4. ADC0 Programmable Window Detector ........................................................... 84
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)............................................................. 91
7.1. Analog Multiplexer and PGA............................................................................. 91
7.2. ADC2 Modes of Operation................................................................................ 92
7.2.1. Starting a Conversion............................................................................... 92
7.2.2. Tracking Modes........................................................................................ 92
7.2.3. Settling Time Requirements..................................................................... 94
7.3. ADC2 Programmable Window Detector ......................................................... 100
7.3.1. Window Detector In Single-Ended Mode ............................................... 100
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C8051F040/1/2/3/4/5/6/7
7.3.2. Window Detector In Differential Mode.................................................... 102
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) ......................................... 105
8.1. DAC Output Scheduling.................................................................................. 106
8.1.1. Update Output On-Demand ................................................................... 106
8.1.2. Update Output Based on Timer Overflow .............................................. 106
8.2. DAC Output Scaling/Justification .................................................................... 106
9. Voltage Reference (C8051F040/2/4/6) ................................................................. 113
10.Voltage Reference (C8051F041/3/5/7) ................................................................. 117
11.Comparators ......................................................................................................... 121
11.1.Comparator Inputs.......................................................................................... 123
12.CIP-51 Microcontroller ......................................................................................... 127
12.1.Instruction Set................................................................................................. 129
12.1.1.Instruction and CPU Timing ................................................................... 129
12.1.2.MOVX Instruction and Program Memory ............................................... 129
12.2.Memory Organization ..................................................................................... 133
12.2.1.Program Memory ................................................................................... 133
12.2.2.Data Memory.......................................................................................... 134
12.2.3.General Purpose Registers.................................................................... 134
12.2.4.Bit Addressable Locations...................................................................... 134
12.2.5.Stack ..................................................................................................... 134
12.2.6.Special Function Registers .................................................................... 135
12.2.7.Register Descriptions ............................................................................. 151
12.3.Interrupt Handler............................................................................................. 154
12.3.1.MCU Interrupt Sources and Vectors ...................................................... 154
12.3.2.External Interrupts.................................................................................. 155
12.3.3.Interrupt Priorities................................................................................... 157
12.3.4.Interrupt Latency .................................................................................... 157
12.3.5.Interrupt Register Descriptions............................................................... 157
12.4.Power Management Modes............................................................................ 164
12.4.1.Idle Mode ............................................................................................... 164
12.4.2.Stop Mode.............................................................................................. 165
13.Reset Sources....................................................................................................... 167
13.1.Power-on Reset.............................................................................................. 168
13.2.Power-Fail Reset ............................................................................................ 168
13.3.External Reset................................................................................................ 168
13.4.Missing Clock Detector Reset ........................................................................ 169
13.5.Comparator0 Reset ........................................................................................ 169
13.6.External CNVSTR0 Pin Reset ........................................................................ 169
13.7.Watchdog Timer Reset................................................................................... 169
13.7.1.Enable/Reset WDT ................................................................................ 170
13.7.2.Disable WDT .......................................................................................... 170
13.7.3.Disable WDT Lockout ............................................................................ 170
13.7.4.Setting WDT Interval .............................................................................. 170
14.Oscillators ............................................................................................................. 175
14.1.Programmable Internal Oscillator ................................................................... 175
4 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
14.2.External Oscillator Drive Circuit...................................................................... 177
14.3.System Clock Selection.................................................................................. 177
14.4.External Crystal Example ............................................................................... 179
14.5.External RC Example ..................................................................................... 180
14.6.External Capacitor Example ........................................................................... 180
15.Flash Memory ....................................................................................................... 181
15.1.Programming The Flash Memory ................................................................... 181
15.2.Non-volatile Data Storage .............................................................................. 182
15.3.Security Options ............................................................................................. 182
15.3.1.Summary of Flash Security Options....................................................... 184
16.External Data Memory Interface and On-Chip XRAM........................................ 189
16.1.Accessing XRAM............................................................................................ 189
16.1.1.16-Bit MOVX Example ........................................................................... 189
16.1.2.8-Bit MOVX Example ............................................................................. 189
16.2.Configuring the External Memory Interface .................................................... 190
16.3.Port Selection and Configuration.................................................................... 190
16.4.Multiplexed and Non-multiplexed Selection.................................................... 193
16.4.1.Multiplexed Configuration....................................................................... 193
16.4.2.Non-multiplexed Configuration............................................................... 194
16.5.Memory Mode Selection................................................................................. 195
16.5.1.Internal XRAM Only ............................................................................... 195
16.5.2.Split Mode without Bank Select.............................................................. 195
16.5.3.Split Mode with Bank Select................................................................... 196
16.5.4.External Only.......................................................................................... 196
16.6.Timing .......................................................................................................... 196
16.6.1.Non-multiplexed Mode ........................................................................... 198
16.6.2.Multiplexed Mode ................................................................................... 201
17.Port Input/Output.................................................................................................. 205
17.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 206
17.1.1.Crossbar Pin Assignment and Allocation ............................................... 207
17.1.2.Configuring the Output Modes of the Port Pins...................................... 208
17.1.3.Configuring Port Pins as Digital Inputs................................................... 209
17.1.4.Weak Pullups ......................................................................................... 209
17.1.5.Configuring Port 1, 2, and 3 Pins as Analog Inputs ............................... 209
17.1.6.External Memory Interface Pin Assignments ......................................... 210
17.1.7.Crossbar Pin Assignment Example........................................................ 212
17.2.Ports 4 through 7............................................................................................ 222
17.2.1.Configuring Ports which are not Pinned Out.......................................... 223
17.2.2.Configuring the Output Modes of the Port Pins...................................... 223
17.2.3.Configuring Port Pins as Digital Inputs................................................... 223
17.2.4.Weak Pull-ups........................................................................................ 223
17.2.5.External Memory Interface ..................................................................... 223
18.Controller Area Network (CAN0) ......................................................................... 229
18.1.Bosch CAN Controller Operation.................................................................... 230
18.1.1.CAN Controller Timing ........................................................................... 231
Rev. 1.4 5
C8051F040/1/2/3/4/5/6/7
18.1.2.Example Timing Calculation for 1 Mbit/Sec Communication ................. 231
18.2.CAN Registers................................................................................................ 233
18.2.1.CAN Controller Protocol Registers......................................................... 233
18.2.2.Message Object Interface Registers...................................................... 233
18.2.3.Message Handler Registers................................................................... 234
18.2.4.CIP-51 MCU Special Function Registers ............................................... 234
18.2.5.Using CAN0ADR, CAN0DATH, and CANDATL to
Access CAN Registers .......................................................................... 234
18.2.6.CAN0ADR Autoincrement Feature ........................................................ 234
19.System Management BUS / I2C BUS (SMBUS0)................................................ 241
19.1.Supporting Documents................................................................................... 242
19.2.SMBus Protocol.............................................................................................. 243
19.2.1.Arbitration............................................................................................... 243
19.2.2.Clock Low Extension.............................................................................. 244
19.2.3.SCL Low Timeout................................................................................... 244
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 244
19.3.SMBus Transfer Modes.................................................................................. 244
19.3.1.Master Transmitter Mode ....................................................................... 244
19.3.2.Master Receiver Mode........................................................................... 245
19.3.3.Slave Transmitter Mode ......................................................................... 245
19.3.4.Slave Receiver Mode............................................................................. 246
19.4.SMBus Special Function Registers ................................................................ 247
19.4.1.Control Register ..................................................................................... 247
19.4.2.Clock Rate Register ............................................................................... 250
19.4.3.Data Register ......................................................................................... 251
19.4.4.Address Register.................................................................................... 251
19.4.5.Status Register....................................................................................... 252
20.Enhanced Serial Peripheral Interface (SPI0) ...................................................... 257
20.1.Signal Descriptions......................................................................................... 258
20.1.1.Master Out, Slave In (MOSI).................................................................. 258
20.1.2.Master In, Slave Out (MISO).................................................................. 258
20.1.3.Serial Clock (SCK) ................................................................................. 258
20.1.4.Slave Select (NSS) ................................................................................ 258
20.2.SPI0 Master Mode Operation ......................................................................... 259
20.3.SPI0 Slave Mode Operation ........................................................................... 261
20.4.SPI0 Interrupt Sources ................................................................................... 261
20.5.Serial Clock Timing......................................................................................... 262
20.6.SPI Special Function Registers...................................................................... 263
21.UART0.................................................................................................................... 267
21.1.UART0 Operational Modes ............................................................................ 268
21.1.1.Mode 0: Synchronous Mode .................................................................. 268
21.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 269
21.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 271
21.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 272
21.2.Multiprocessor Communications .................................................................... 272
6 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
21.3.Configuration of a Masked Address ............................................................... 273
21.4.Broadcast Addressing .................................................................................... 273
21.5.Frame and Transmission Error Detection....................................................... 274
22.UART1.................................................................................................................... 279
22.1.Enhanced Baud Rate Generation................................................................... 280
22.2.Operational Modes ......................................................................................... 281
22.2.1.8-Bit UART............................................................................................. 281
22.2.2.9-Bit UART............................................................................................. 282
22.3.Multiprocessor Communications .................................................................... 283
23.Timers.................................................................................................................... 289
23.1.Timer 0 and Timer 1 ....................................................................................... 289
23.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 289
23.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 290
23.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 291
23.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 292
23.2.Timer 2, Timer 3, and Timer 4 ........................................................................ 297
23.2.1.Configuring Timer 2, 3, and 4 to Count Down........................................ 297
23.2.2.Capture Mode ........................................................................................ 298
23.2.3.Auto-Reload Mode ................................................................................. 299
23.2.4.Toggle Output Mode .............................................................................. 300
24.Programmable Counter Array ............................................................................. 305
24.1.PCA Counter/Timer ........................................................................................ 306
24.2.Capture/Compare Modules ............................................................................ 307
24.2.1.Edge-triggered Capture Mode................................................................ 308
24.2.2.Software Timer (Compare) Mode........................................................... 309
24.2.3.High Speed Output Mode....................................................................... 310
24.2.4.Frequency Output Mode ........................................................................ 311
24.2.5.8-Bit Pulse Width Modulator Mode......................................................... 312
24.2.6.16-Bit Pulse Width Modulator Mode....................................................... 313
24.3.Register Descriptions for PCA0...................................................................... 314
25.JTAG (IEEE 1149.1) .............................................................................................. 319
25.1.Boundary Scan............................................................................................... 320
25.1.1.EXTEST Instruction................................................................................ 321
25.1.2.SAMPLE Instruction............................................................................... 321
25.1.3.BYPASS Instruction ............................................................................... 321
25.1.4.IDCODE Instruction................................................................................ 321
25.2.Flash Programming Commands..................................................................... 323
25.3.Debug Support ............................................................................................... 326
Document Change List............................................................................................. 327
Contact Information.................................................................................................. 328
Rev. 1.4 7
C8051F040/1/2/3/4/5/6/7
NOTES:
8 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
List of Figures
1. System Overview
Figure 1.1. C8051F040/2 Block Diagram ................................................................. 21
Figure 1.2. C8051F041/3 Block Diagram ................................................................. 22
Figure 1.3. C8051F044/6 Block Diagram ................................................................. 23
Figure 1.4. C8051F045/7 Block Diagram ................................................................. 24
Figure 1.5. Comparison of Peak MCU Execution Speeds ....................................... 25
Figure 1.6. On-Board Clock and Reset .................................................................... 26
Figure 1.7. On-Chip Memory Map ............................................................................ 27
Figure 1.8. Development/In-System Debug Diagram............................................... 28
Figure 1.9. Digital Crossbar Diagram ....................................................................... 29
Figure 1.10. PCA Block Diagram.............................................................................. 30
Figure 1.11. CAN Controller Diagram....................................................................... 31
Figure 1.12. 10/12-Bit ADC Block Diagram .............................................................. 32
Figure 1.13. 8-Bit ADC Diagram............................................................................... 33
Figure 1.14. Comparator and DAC Diagram ............................................................ 34
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristic
4. Pinout and Package Definitions
Figure 4.1. TQFP-100 Pinout Diagram..................................................................... 42
Figure 4.2. TQFP-100 Package Drawing ................................................................. 43
Figure 4.3. TQFP-64 Pinout Diagram....................................................................... 44
Figure 4.4. TQFP-64 Package Drawing ................................................................... 45
5. 12-Bit ADC (ADC0, C8051F040/1 Only)
Figure 5.1. 12-Bit ADC0 Functional Block Diagram ................................................. 47
Figure 5.2. Analog Input Diagram ............................................................................ 48
Figure 5.3. High Voltage Difference Amplifier Functional Diagram .......................... 52
Figure 5.4. 12-Bit ADC Track and Conversion Example Timing .............................. 55
Figure 5.5. ADC0 Equivalent Input Circuits .............................................................. 56
Figure 5.6. Temperature Sensor Transfer Function ................................................. 57
Figure 5.7. ADC0 Data Word Example .................................................................... 61
Figure 5.8. 12-Bit ADC0 Window Interrupt Example:
Right Justified Single-Ended Data ........................................................ 63
Figure 5.9. 12-Bit ADC0 Window Interrupt Example:
Right Justified Differential Data............................................................. 64
Figure 5.10. 12-Bit ADC0 Window Interrupt Example:
Left Justified Single-Ended Data........................................................... 65
Figure 5.11. 12-Bit ADC0 Window Interrupt Example:
Left Justified Differential Data ............................................................... 66
6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
Figure 6.1. 10-Bit ADC0 Functional Block Diagram ................................................. 69
Figure 6.2. Analog Input Diagram ............................................................................ 70
Figure 6.3. High Voltage Difference Amplifier Functional Diagram .......................... 74
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing .............................. 77
Rev. 1.4 9
C8051F040/1/2/3/4/5/6/7
Figure 6.5. ADC0 Equivalent Input Circuits .............................................................. 78
Figure 6.6. Temperature Sensor Transfer Function ................................................. 79
Figure 6.7. ADC0 Data Word Example .................................................................... 83
Figure 6.8. 10-Bit ADC0 Window Interrupt Example:
Right Justified Single-Ended Data ........................................................ 85
Figure 6.9. 10-Bit ADC0 Window Interrupt Example:
Right Justified Differential Data............................................................. 86
Figure 6.10. 10-Bit ADC0 Window Interrupt Example:
Left Justified Single-Ended Data......................................................... 87
Figure 6.11. 10-Bit ADC0 Window Interrupt Example:
Left Justified Differential Data.............................................................. 88
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)
Figure 7.1. ADC2 Functional Block Diagram............................................................ 91
Figure 7.2. ADC2 Track and Conversion Example Timing....................................... 93
Figure 7.3. ADC2 Equivalent Input Circuit................................................................ 94
Figure 7.4. ADC2 Data Word Example .................................................................... 99
Figure 7.5. ADC Window Compare Examples, Single-Ended Mode...................... 101
Figure 7.6. ADC Window Compare Examples, Differential Mode .......................... 102
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only)
Figure 8.1. DAC Functional Block Diagram............................................................ 105
9. Voltage Reference (C8051F040/2/4/6)
Figure 9.1. Voltage Reference Functional Block Diagram ..................................... 113
10.Voltage Reference (C8051F041/3/5/7)
Figure 10.1. Voltage Reference Functional Block Diagram.................................... 117
11.Comparators
Figure 11.1. Comparator Functional Block Diagram .............................................. 121
Figure 11.2. Comparator Hysteresis Plot ............................................................... 122
12.CIP-51 Microcontroller
Figure 12.1. CIP-51 Block Diagram........................................................................ 127
Figure 12.2. Memory Map ...................................................................................... 133
Figure 12.3. SFR Page Stack................................................................................. 136
Figure 12.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 137
Figure 12.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs . 138
Figure 12.6. SFR Page Stack Upon PCA Interrupt Occurring
During an ADC2 ISR ........................................................................... 139
Figure 12.7. SFR Page Stack Upon Return From PCA Interrupt ........................... 140
Figure 12.8. SFR Page Stack Upon Return From ADC2 Window Interrupt ........... 141
13.Reset Sources
Figure 13.1. Reset Sources.................................................................................... 167
Figure 13.2. Reset Timing ...................................................................................... 168
14.Oscillators
Figure 14.1. Oscillator Diagram.............................................................................. 175
Figure 14.2. 32.768 kHz External Crystal Example................................................ 179
15.Flash Memory
Figure 15.1. Flash Program Memory Map and Security Bytes............................... 183
10 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
16.External Data Memory Interface and On-Chip XRAM
Figure 16.1. Multiplexed Configuration Example.................................................... 193
Figure 16.2. Non-multiplexed Configuration Example ............................................ 194
Figure 16.3. EMIF Operating Modes ...................................................................... 195
Figure 16.4. Non-multiplexed 16-bit MOVX Timing ................................................ 198
Figure 16.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 199
Figure 16.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 200
Figure 16.7. Multiplexed 16-bit MOVX Timing........................................................ 201
Figure 16.8. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 202
Figure 16.9. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 203
17.Port Input/Output
Figure 17.1. Port I/O Cell Block Diagram ............................................................... 205
Figure 17.2. Port I/O Functional Block Diagram ..................................................... 206
Figure 17.3. Priority Crossbar Decode Table ......................................................... 207
Figure 17.4. Priority Crossbar Decode Table ......................................................... 210
Figure 17.5. Priority Crossbar Decode Table ......................................................... 211
Figure 17.6. Crossbar Example:............................................................................. 213
18.Controller Area Network (CAN0)
Figure 18.1. Typical CAN Bus Configuration.......................................................... 229
Figure 18.2. CAN Controller Diagram..................................................................... 230
Figure 18.3. Four Segments of a CAN Bit Time ..................................................... 231
Figure 18.4. CAN0DATH: CAN Data Access Register High Byte .......................... 236
19.System Management BUS / I2C BUS (SMBUS0)
Figure 19.1. SMBus0 Block Diagram ..................................................................... 241
Figure 19.2. Typical SMBus Configuration ............................................................. 242
Figure 19.3. SMBus Transaction ............................................................................ 243
Figure 19.4. Typical Master Transmitter Sequence................................................ 244
Figure 19.5. Typical Master Receiver Sequence.................................................... 245
Figure 19.6. Typical Slave Transmitter Sequence.................................................. 245
Figure 19.7. Typical Slave Receiver Sequence...................................................... 246
20.Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram ............................................................................. 257
Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 260
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 260
Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 260
Figure 20.5. Data/Clock Timing Diagram ............................................................... 262
21.UART0
Figure 21.1. UART0 Block Diagram ....................................................................... 267
Figure 21.2. UART0 Mode 0 Timing Diagram ........................................................ 268
Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 269
Figure 21.4. UART0 Mode 1 Timing Diagram ........................................................ 269
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 271
Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 272
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................... 274
Rev. 1.4 11
C8051F040/1/2/3/4/5/6/7
22.UART1
Figure 22.1. UART1 Block Diagram ....................................................................... 279
Figure 22.2. UART1 Baud Rate Logic .................................................................... 280
Figure 22.3. UART Interconnect Diagram .............................................................. 281
Figure 22.4. 8-Bit UART Timing Diagram............................................................... 281
Figure 22.5. 9-Bit UART Timing Diagram............................................................... 282
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 283
23.Timers
Figure 23.1. T0 Mode 0 Block Diagram.................................................................. 290
Figure 23.2. T0 Mode 2 Block Diagram.................................................................. 291
Figure 23.3. T0 Mode 3 Block Diagram.................................................................. 292
Figure 23.4. Tn Capture Mode Block Diagram ....................................................... 298
Figure 23.5. Tn Auto-reload Mode Block Diagram ................................................. 299
24.Programmable Counter Array
Figure 24.1. PCA Block Diagram............................................................................ 305
Figure 24.2. PCA Counter/Timer Block Diagram.................................................... 306
Figure 24.3. PCA Interrupt Block Diagram ............................................................. 307
Figure 24.4. PCA Capture Mode Diagram.............................................................. 308
Figure 24.5. PCA Software Timer Mode Diagram .................................................. 309
Figure 24.6. PCA High Speed Output Mode Diagram............................................ 310
Figure 24.7. PCA Frequency Output Mode ............................................................ 311
Figure 24.8. PCA 8-Bit PWM Mode Diagram ......................................................... 312
Figure 24.9. PCA 16-Bit PWM Mode...................................................................... 313
25.JTAG (IEEE 1149.1)
12 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 20
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 35
3. Global DC Electrical Characteristic
Table 3.1. Global DC Electrical Characteristics ....................................................... 36
4. Pinout and Package Definitions
Table 4.1. Pin Definitions ......................................................................................... 37
5. 12-Bit ADC (ADC0, C8051F040/1 Only)
Table 5.1. AMUX Selection Chart (AMX0AD3–0 and AMX0CF3–0 bits) ................ 50
Table 5.2. 12-Bit ADC0 Electrical Characteristics ................................................... 67
Table 5.3. High Voltage Difference Amplifier Electrical Characteristics .................. 68
6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
Table 6.1. AMUX Selection Chart (AMX0AD3-0 and AMX0CF3-0 bits) .................. 72
Table 6.2. 10-Bit ADC0 Electrical Characteristics ................................................... 89
Table 6.3. High Voltage Difference Amplifier Electrical Characteristics .................. 90
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)
Table 7.1. AMUX Selection Chart (AMX2AD2-0 and AMX2CF3-0 bits) .................. 96
Table 7.2. ADC2 Electrical Characteristics ............................................................ 103
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only)
Table 8.1. DAC Electrical Characteristics .............................................................. 111
9. Voltage Reference (C8051F040/2/4/6)
Table 9.1. Voltage Reference Electrical Characteristics ....................................... 115
10.Voltage Reference (C8051F041/3/5/7)
Table 10.1. Voltage Reference Electrical Characteristics ..................................... 119
11.Comparators
Table 11.1. Comparator Electrical Characteristics ................................................ 126
12.CIP-51 Microcontroller
Table 12.1. CIP-51 Instruction Set Summary ........................................................ 129
Table 12.2. Special Function Register (SFR) Memory Map .................................. 144
Table 12.3. Special Function Registers ................................................................. 147
Table 12.4. Interrupt Summary .............................................................................. 155
13.Reset Sources
Table 13.1. Reset Electrical Characteristics .......................................................... 173
14.Oscillators
Table 14.1. Internal Oscillator Electrical Characteristics ....................................... 177
15.Flash Memory
Table 15.1. Flash Electrical Characteristics .......................................................... 182
16.External Data Memory Interface and On-Chip XRAM
Table 16.1. AC Parameters for External Memory Interface ................................... 204
17.Port Input/Output
Table 17.1. Port I/O DC Electrical Characteristics ................................................. 205
Rev. 1.4 13
C8051F040/1/2/3/4/5/6/7
18.Controller Area Network (CAN0)
Table 18.1. Background System Information ........................................................ 231
Table 18.2. CAN Register Index and Reset Values .............................................. 235
19.System Management BUS / I2C BUS (SMBUS0)
Table 19.1. SMB0STA Status Codes and States .................................................. 254
20.Enhanced Serial Peripheral Interface (SPI0)
21.UART0
Table 21.1. UART0 Modes .................................................................................... 268
Table 21.2. Oscillator Frequencies for Standard Baud Rates ............................... 275
22.UART1
Table 22.1. Timer Settings for Standard Baud Rates Using
the Internal 24.5 MHz Oscillator ......................................................... 286
Table 22.2. Timer Settings for Standard Baud Rates Using
an External 25.0 MHz Oscillator ......................................................... 286
Table 22.3. Timer Settings for Standard Baud Rates Using
an External 22.1184 MHz Oscillator ................................................... 287
Table 22.4. Timer Settings for Standard Baud Rates Using
an External 18.432 MHz Oscillator ..................................................... 287
Table 22.5. Timer Settings for Standard Baud Rates Using
an External 11.0592 MHz Oscillator ................................................... 288
Table 22.6. Timer Settings for Standard Baud Rates Using
an External 3.6864 MHz Oscillator ..................................................... 288
23.Timers
24.Programmable Counter Array
Table 24.1. PCA Timebase Input Options ............................................................. 306
Table 24.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 307
25.JTAG (IEEE 1149.1)
Table 25.1. Boundary Data Register Bit Definitions .............................................. 320
14 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
List of Registers
SFR Definition 5.1. AMX0CF: AMUX0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.2. AMX0SL: AMUX0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.3. AMX0PRT: Port 3 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 5.4. HVA0CN: High Voltage Difference Amplifier Control . . . . . . . . . . . 53
SFR Definition 5.5. ADC0CF: ADC0 Configuration Register . . . . . . . . . . . . . . . . . . . . 58
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SFR Definition 5.7. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 5.8. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 5.9. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 62
SFR Definition 5.10. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . 62
SFR Definition 5.11. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . 62
SFR Definition 5.12. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 63
SFR Definition 6.1. AMX0CF: AMUX0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 6.2. AMX0SL: AMUX0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 6.3. AMX0PRT: Port 3 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 6.4. HVA0CN: High Voltage Difference Amplifier Control . . . . . . . . . . . 75
SFR Definition 6.5. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SFR Definition 6.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 6.7. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 6.8. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 84
SFR Definition 6.10. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . 84
SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . 84
SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 85
SFR Definition 7.1. AMX2CF: AMUX2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 7.2. AMX2SL: AMUX2 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 7.3. ADC2CF: ADC2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SFR Definition 7.4. ADC2CN: ADC2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 7.5. ADC2: ADC2 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 7.6. ADC2GT: ADC2 Greater-Than Data . . . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 7.7. ADC2LT: ADC2 Less-Than Data . . . . . . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 8.1. DAC0H: DAC0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 8.2. DAC0L: DAC0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 8.3. DAC0CN: DAC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 8.4. DAC1H: DAC1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.5. DAC1L: DAC1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.6. DAC1CN: DAC1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 9.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 10.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SFR Definition 11.1. CPTnCN: Comparator 0, 1, and 2 Control . . . . . . . . . . . . . . . . . 124
SFR Definition 11.2. CPTnMD: Comparator Mode Selection . . . . . . . . . . . . . . . . . . . 125
SFR Definition 12.1. SFR Page Control Register: SFRPGCN . . . . . . . . . . . . . . . . . . 142
SFR Definition 12.2. SFR Page Register: SFRPAGE . . . . . . . . . . . . . . . . . . . . . . . . . 142
Rev. 1.4 15
C8051F040/1/2/3/4/5/6/7
SFR Definition 12.3. SFR Next Register: SFRNEXT . . . . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 12.4. SFR Last Register: SFRLAST . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 12.5. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 12.6. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 12.7. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 12.8. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 12.9. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 12.10. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 12.11. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 12.12. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 12.13. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . 160
SFR Definition 12.14. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . 161
SFR Definition 12.15. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . 162
SFR Definition 12.16. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . 163
SFR Definition 12.18. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
SFR Definition 13.1. WDTCN: Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . 171
SFR Definition 13.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 14.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 176
SFR Definition 14.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 176
SFR Definition 14.3. CLKSEL: Oscillator Clock Selection . . . . . . . . . . . . . . . . . . . . . 177
SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 178
SFR Definition 15.1. FLACL: Flash Access Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
SFR Definition 15.2. FLSCL: Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . 186
SFR Definition 15.3. PSCTL: Program Store Read/Write Control . . . . . . . . . . . . . . . 187
SFR Definition 16.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 191
SFR Definition 16.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 192
SFR Definition 16.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 197
SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 214
SFR Definition 17.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 215
SFR Definition 17.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 17.4. XBR3: Port I/O Crossbar Register 3 . . . . . . . . . . . . . . . . . . . . . 217
SFR Definition 17.5. P0: Port0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
SFR Definition 17.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 218
SFR Definition 17.7. P1: Port1 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SFR Definition 17.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SFR Definition 17.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 219
SFR Definition 17.10. P2: Port2 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SFR Definition 17.11. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SFR Definition 17.12. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 17.13. P3: Port3 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 17.14. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
SFR Definition 17.15. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 222
SFR Definition 17.16. P4: Port4 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 17.17. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 17.18. P5: Port5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 17.19. P5MDOUT: Port5 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 225
SFR Definition 17.20. P6: Port6 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 17.21. P6MDOUT: Port6 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 17.22. P7: Port7 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SFR Definition 17.23. P7MDOUT: Port7 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 227
SFR Definition 18.1. CAN0DATL: CAN Data Access Register Low Byte . . . . . . . . . . 237
SFR Definition 18.2. CAN0ADR: CAN Address Index . . . . . . . . . . . . . . . . . . . . . . . . 237
SFR Definition 18.3. CAN0CN: CAN Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 18.4. CAN0TST: CAN Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 18.5. CAN0STA: CAN Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SFR Definition 19.1. SMB0CN: SMBus0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
SFR Definition 19.2. SMB0CR: SMBus0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 19.3. SMB0DAT: SMBus0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
SFR Definition 19.4. SMB0ADR: SMBus0 Address . . . . . . . . . . . . . . . . . . . . . . . . . . 252
SFR Definition 19.5. SMB0STA: SMBus0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 263
SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
SFR Definition 21.1. SCON0: UART0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
SFR Definition 21.2. SSTA0: UART0 Status and Clock Selection . . . . . . . . . . . . . . . 277
SFR Definition 21.3. SBUF0: UART0 Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SFR Definition 21.4. SADDR0: UART0 Slave Address . . . . . . . . . . . . . . . . . . . . . . . 278
SFR Definition 21.5. SADEN0: UART0 Slave Address Enable . . . . . . . . . . . . . . . . . 278
SFR Definition 22.1. SCON1: Serial Port 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 284
SFR Definition 22.2. SBUF1: Serial (UART1) Port Data Buffer . . . . . . . . . . . . . . . . . 285
SFR Definition 23.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
SFR Definition 23.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
SFR Definition 23.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
SFR Definition 23.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
SFR Definition 23.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 23.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 23.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 23.8. TMRnCN: Timer n Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
SFR Definition 23.9. TMRnCF: Timer n Configuration . . . . . . . . . . . . . . . . . . . . . . . . 302
SFR Definition 23.10. RCAPnL: Timer n Capture Register Low Byte . . . . . . . . . . . . . 303
SFR Definition 23.11. RCAPnH: Timer n Capture Register High Byte . . . . . . . . . . . . 303
SFR Definition 23.12. TMRnL: Timer n Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
SFR Definition 23.13. TMRnH Timer n High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
SFR Definition 24.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
SFR Definition 24.2. PCA0MD: PCA0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
SFR Definition 24.3. PCA0CPMn: PCA0 Capture/Compare Mode . . . . . . . . . . . . . . 316
SFR Definition 24.4. PCA0L: PCA0 Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . 317
SFR Definition 24.5. PCA0H: PCA0 Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 317
SFR Definition 24.6. PCA0CPLn: PCA0 Capture Module Low Byte . . . . . . . . . . . . . . 318
Rev. 1.4 17
C8051F040/1/2/3/4/5/6/7
SFR Definition 24.7. PCA0CPHn: PCA0 Capture Module High Byte . . . . . . . . . . . . . 318
JTAG Register Definition 25.1. IR: JTAG Instruction Register . . . . . . . . . . . . . . . . . . 319
JTAG Register Definition 25.2. DEVICEID: JTAG Device ID Register . . . . . . . . . . . . 322
JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control Register . . . . . . . . 324
JTAG Register Definition 25.4. FLASHDAT: JTAG Flash Data . . . . . . . . . . . . . . . . . 325
JTAG Register Definition 25.5. FLASHADR: JTAG Flash Address . . . . . . . . . . . . . . 325
18 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1. System Overview
The C8051F04x family of devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital
I/O pins (C8051F040/2/4/6) or 32 digital I/O pins (C8051F041/3/5/7), and an integrated CAN 2.0B controller. Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.
• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)
• Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier
mask.
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 12-bit (C8051F040/1) or 10-bit (C8051F042/3/4/5/6/7) 100 ksps 8-channel ADC with PGA and
analog multiplexer
• High Voltage Difference Amplifier input to the 12/10-bit ADC (60 V Peak-to-Peak) with programmable
gain.
• True 8-bit 500 ksps 8-channel ADC with PGA and analog multiplexer (C8051F040/1/2/3)
• Two 12-bit DACs with programmable update scheduling (C8051F040/1/2/3)
•64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) of in-system programmable Flash memory
• 4352 (4096 + 256) bytes of on-chip RAM
• External Data Memory Interface with 64 kB address space
• SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with six capture/compare modules
• On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor
With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F04x family of devices are truly
stand-alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and con-
figured by user firmware. The Flash memory can be reprogrammed even in-circuit, providing non-volatile
data storage, and also allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit programming and debugging using the production MCU installed in the final application. This debug system
supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single
stepping, Run, and Halt commands. All analog and digital peripherals are fully functional while debugging
using JTAG.
Each MCU is specified for 2.7 V to 3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5 V. The C8051F040/2/4/6 are available in a 100-pin TQFP and the C8051F041/3/5/7 are available in a 64-pin TQFP.
Rev. 1.4 19
C8051F040/1/2/3/4/5/6/7
Table 1.1. Product Selection Guide
C and SPI
2
MIPS (Peak)
Flash Memory
RAM
External Memory Interface
SMBus/I
CAN
UARTS
C8051F040 25 64 kB 4352
3 3 3
2 5
Timers (16-bit)
3
Programmable Counter Array
Digital Port I/O’s
12-bit 100ksps ADC
10-bit 100ksps ADC
8-bit 500ksps ADC Inputs
High Voltage Diff Amp
Voltage Reference
Temperature Sensor
DAC Resolution (bits)
DAC Outputs
64
3
- 8
3 3 3
Analog Comparators
12 2 3 100TQFP
Package
C8051F041 25 64 kB 4352
C8051F042 25 64 kB 4352
C8051F043 25 64 kB 4352
C8051F044 25 64 kB 4352
C8051F045 25 64 kB 4352
C8051F046 25 32 kB 4352
C8051F047 25 32 kB 4352
3 3 3
3 3 3
3 3 3
3 3 3
3 3 3
3 3 3
3 3 3
2 5
2 5
2 5
2 5
2 5
2 5
2 5
3
3
3
3
3
3
3
32
64 -
32 -
64 -
32 -
64 -
32 -
3
- 8
3
8
3
8
3 3 3 3
3 3 3 3
3 3 3 3
3 3 3 3
3 3 3
3 3 3
3 3 3
12 2 3 64TQFP
12 2 3 100TQFP
12 2 3 64TQFP
3 100TQFP
3 64TQFP
3 100TQFP
3 64TQFP
20 Rev. 1.4
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AV+
AGND
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREFD
DAC1
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
Prog
Gain
Boundary Scan
Debug HW
WDT
Internal
Oscillator
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(12 or 10-
Bit)
A
M
U
X
8
SFR Bus
0
5
Memories
1
64 kB
Flash
C
o
r
e
External Memory Data
8:2
32x136
CANRAM
256 byte
RAM
4 kB
RAM
Bus
C8051F040/1/2/3/4/5/6/7
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
ADC
500 ksps
(8-Bit)
CP0
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
M
Prog
8:1
Gain
U
X
P2.6
+
P2.7
-
+
-
P2.2
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
VREF2
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A51
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Figure 1.1. C8051F040/2 Block Diagram
Rev. 1.4 21
C8051F040/1/2/3/4/5/6/7
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
DAC1
DAC0
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
Prog
Boundary Scan
Debug HW
WDT
Internal
Oscillator
Gain
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(12 or 10-
Bit)
A
M
U
X
8
0
SFR Bus
5
1
C
o
Memories
32x136
CANRAM
r
256 byte
e
External Memory Data
8:2
64 kB
Flash
RAM
4 kB
RAM
Bus
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
ADC
500 ksps
(8-Bit)
VREFA
CP0
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
M
Prog
8:1
Gain
U
X
P2.6
+
P2.7
-
+
-
P2.2
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
Figure 1.2. C8051F041/3 Block Diagram
22 Rev. 1.4
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AV+
AGND
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
Prog
Gain
Boundary Scan
Debug HW
WDT
Internal
Oscillator
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(10-Bit)
A
M
U
X
8
0
SFR Bus
5
1
C
o
e
8:2
Memories
64/32 kB
Flash
32x136
CANRAM
r
256 byte
RAM
4 kB
RAM
External Memory Data
Bus
C8051F040/1/2/3/4/5/6/7
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
CP0
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
P2.6
+
P2.7
-
+
-
P2.2
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A51
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Figure 1.3. C8051F044/6 Block Diagram
Rev. 1.4 23
C8051F040/1/2/3/4/5/6/7
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
Prog
Gain
Boundary Scan
Debug HW
WDT
Internal
Oscillator
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(10-Bit)
A
M
U
X
8
0
SFR Bus
5
1
C
o
Memories
64/32 kB
32x136
CANRAM
r
256 byte
e
External Memory Data
8:2
Flash
RAM
4 kB
RAM
Bus
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
CP0
+
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
P2.6
+
P2.7
-
P2.2
-
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
Figure 1.4. C8051F045/7 Block Diagram
24 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F04x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers
can be used to develop software. The core has all the peripherals included with a standard 8052, including
five 16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space, and up to 8 byte-wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5
shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system
clocks.
25
20
15
MIPS
10
5
Silicon Labs
CIP-51
(25 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Philips
80C51
(33 MHz clk)
ADuC812
8051
(16 MHz clk)
Figure 1.5. Comparison of Peak MCU Execution Speeds
Rev. 1.4 25
C8051F040/1/2/3/4/5/6/7
1.1.3. Additional Features
The C8051F04x MCU family includes several key enhancements to the CIP-51 core and peripherals to
improve overall performance and ease of use in end applications.
The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt
driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board V
monitor, a Watchdog Timer, a missing
DD
clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input
pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the
internally generated POR to be output on the /RST pin. Each reset source except for the V
Reset Input pin may be disabled by the user in software; the V
monitor is enabled/disabled via the
DD
monitor and
DD
MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during
MCU initialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after
any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed.
V
DD
(Port I/O)
CP0+
CP0-
Crossbar
CNVSTR
(CNVSTR
reset
enable)
Comparator0
+
-
(CP0
reset
enable)
Missing
Clock
Detector
(one-
shot)
EN
WDT
EN
Supply
Monitor
+
-
PRE
Supply
Reset
Timeout
(wired-OR)
Reset
Funnel
RST
WDT
Enable
Enable
CIP-51
Core
Extended Interrupt
Handler
XTAL1
XTAL2
Internal
Clock
Generator
OSC
System
Clock
Clock Select
MCD
Microcontroller
Figure 1.6. On-Board Clock and Reset
26 Rev. 1.4
WDT
Strobe
Software Reset
System Reset
C8051F040/1/2/3/4/5/6/7
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The CIP-51 SFR
address space contains up to 256 SFR Pages. In this way, the CIP-51 MCU can accommodate the many
SFR’s required to control and configure the various peripherals featured on the device. The lower
128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as
four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The CIP-51 in the C8051F04x MCUs additionally has an on-chip 4 kB RAM block and an external memory
interface (EMIF) for accessing off-chip data memory or memory-mapped peripherals. The on-chip 4 byte
block can be addressed over the entire 64 kB external data memory address range (overlapping 4 kB
boundaries). External data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4 kB directed to on-chip, above 4 kB directed to
EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines.
The MCU's program memory consists of 64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) of Flash.
This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses 0xFE00 to 0xFFFF are reserved for the 64 kB devices.
There is also a single 128 byte sector at address 0x10000 to 0x1007F, which may be useful as a small
table for software constants. See Figure 1.7 for the MCU system memory map.
PROGRAM/DATA MEMORY
(FLASH)
C8051F040/1/2/3/4/5
0x1007F
0x10000
0xFE00
0xFDFF
0x0000
0x1007F
0x10000
0x8000
0x7FFF
Scrachpad Memory
(DATA only)
RESERVED
64 kB
Flash
(In-System
Programmable in 512
Byte Sectors)
C8051F046/7
Scrachpad Memory
(DATA only)
RESERVED
32 kB
Flash
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
0x1000
0x0FFF
0x0000
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Registers
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-chip XRAM space
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
0
1
2
3
F
Up To
256 SFR Pages
0x0000
Figure 1.7. On-Chip Memory Map
Rev. 1.4 27
C8051F040/1/2/3/4/5/6/7
1.3. JTAG Debug and Boundary Scan
The C8051F04x family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive,
full speed, in-circuit debugging using the production part installed in the end application, via the four-pin
JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and
manufacturing purposes.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and
work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the
MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized with instruction execution.
The C8051F040DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F04x MCUs. The development kit includes two
target boards and a cable to facilitate evaluating a simple CAN communication network. The kit also
includes software with a developer's studio and debugger, a target application board with the associated
MCU installed, and the required cables and wall-mount power supply. The Serial Adapter takes its power
from the application board; it requires roughly 20 mA at 2.7-3.6 V. For applications where there is not sufficient power available from the target system, the provided power supply can be connected directly to the
Serial Adapter.
Silicon Labs’ debug environment is a vastly superior configuration for developing and debugging embedded applications compared to standard MCU emulators, which use on-board "ICE Chips" and target cables
and require the MCU in the application board to be socketed. Silicon Labs' debug environment both
increases ease of use and preserves the performance of the precision, on-chip analog peripherals.
Integrated Development
Environment
WINDO WS 95 o r later
Serial
Adapter
JTAG (x4), VDD, GND
VDD GND
C8051
TARGET PCB
F040
Figure 1.8. Development/In-System Debug Diagram
28 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1.4. Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F040/2/4/6 have 4 additional 8-bit ports (4, 5, 6, and 7) for a total of 64 general-purpose I/O Ports. The Ports behave like the standard 8051 with a few enhancements.
Each port pin can be configured as either a push-pull or open-drain output. Also, the "weak pullups" which
are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for
low-power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching
network that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3
(See Figure 1.9). Unlike microcontrollers with standard multiplexed digital I/O ports, all combinations of
functions are supported with all package options offered.
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in
the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and
digital resources needed for the particular application.
XBR0, XBR1, XBR2,
Highest
Priority
Lowest
Priority
Port
Latches
(Internal Digital Signals)
UART0
SPI
SMBus
UART1
PCA
Comptr.
Outputs
T0, T1,
T2, T2EX,
T3, T3EX,
T4,T4EX,
/INT0,
/INT1
/SYSCLK
CNVSTR0
CNVSTR2
P0
P1
P2
P3
8
(P0.0-P0.7)
8
(P1.0-P1.7)
8
(P2.0-P2.7)
8
(P3.0-P3.7)
2
4
2
2
6
2
XBR3 P1MDIN,
P2MDIN, P3MDIN
Registers
Priority
Decoder
Digital
Crossbar
8
To External
Memory
Interface
(EMIF)
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
8
8
8
8
P0
I/O
Cells
P1
I/O
Cells
P2
I/O
Cells
P3
I/O
Cells
To
ADC2
Input
To
Comparators
To
ADC0
Input
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Priority
Lowest
Priority
Figure 1.9. Digital Crossbar Diagram
Rev. 1.4 29
C8051F040/1/2/3/4/5/6/7
1.5. Programmable Counter Array
The C8051F04x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition
to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer
time base with six programmable capture/compare modules. The timebase is clocked from one of six
sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External
Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width
Modulator. The PCA Capture/Compare Module I/O and External Clock Input are routed to the MCU Port
I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
ECI
Capture/Compare
Module 0
CEX0
Capture/Compare
Module 1
CEX1
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
Crossbar
Port I/O
Figure 1.10. PCA Block Diagram
CEX3
Capture/Compare
Module 4
CEX4
Capture/Compare
Module 5
CEX5
30 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1.6. Controller Area Network
The C8051F04x family of devices feature a Controller Area Network (CAN) controller that implements
serial communication using the CAN protocol. The CAN controller facilitates communication on a CAN network in accordance with the Bosch specification 2.0A (basic CAN) and 2.0B (full CAN). The CAN controller
consists of a CAN Core, Message RAM (separate from the C8051 RAM), a message handler state
machine, and control registers.
The CAN controller can operate at bit rates up to 1 Mbit/second. Silicon Labs CAN has 32 message
objects each having its own identifier mask used for acceptance filtering of received messages. Incoming
data, message objects and identifier masks are stored in the CAN message RAM. All protocol functions for
transmission of data and acceptance filtering is performed by the CAN controller and not by the C8051
MCU. In this way, minimal CPU bandwidth is used for CAN communication. The C8051 configures the
CAN controller, accesses received data, and passes data for transmission via Special Function Registers
(SFR) in the C8051.
CANTX
TX RX
CAN
Core
Message RAM
(32 Message Objects)
Message Handler
Figure 1.11. CAN Controller Diagram
CANRX
CAN Controller
BRP
Prescaler
REGISTERS
CAN_CLK
(f
Interrupt
C8051F04x
)
sys
S
Y
S
C
L
K
CIP-51
MCU
S
F
R
's
1.7. Serial Ports
The C8051F04x MCU Family includes two Enhanced Full-Duplex UARTs, an enhanced SPI Bus, and
SMBus/I2C. Each of the serial buses is fully implemented in hardware and makes extensive use of the
CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share"
resources such as timers, interrupts, or Port I/O, so any or all of the serial buses may be used together with
any other.
Rev. 1.4 31
C8051F040/1/2/3/4/5/6/7
1.8. 12/10-Bit Analog to Digital Converter
The C8051F040/1 devices have an on-chip 12-bit SAR ADC (ADC0) with a 9-channel input multiplexer
and programmable gain amplifier. With a maximum throughput of 100 ksps, the ADC offers true 12-bit performance with an INL of ±1LSB. C8051F042/3/4/5/6/7 devices include a 10-bit SAR ADC with similar specifications and configuration options. The ADC0 voltage reference is selected between the DAC0 output
and an external VREF pin. On C8051F040/2/4/6 devices, ADC0 has its own dedicated VREF0 input pin;
on C8051F041/3/5/7 devices, the ADC0 uses the VREFA input pin and, on the C8051F041/3, shares it
with the 8-bit ADC2. The on-chip 15 ppm/°C voltage reference may generate the voltage reference for the
on-chip ADCs or other system components via the VREF output pin.
The ADC is under full control of the CIP-51 microcontroller via its associated Special Function Registers.
One input channel is tied to an internal temperature sensor, while the other eight channels are available
externally. Each pair of the eight external input channels can be configured as either two single-ended
inputs or a single differential input. The system controller can also put the ADC into shutdown mode to
save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set to 0.5, 1, 2, 4, 8, or 16
and is software programmable. The gain stage can be especially useful when different ADC input channels
have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large dc
offset (in differential mode, a DAC could be used to provide the dc offset).
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of
Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software
events, external HW signals, or a periodic timer overflow signal. Conversion completions are indicated by a
status bit and an interrupt (if enabled). The resulting 10- or 12-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Window Compare registers for the ADC data can be configured to interrupt the controller when ADC data
is within or outside of a specified range. The ADC can monitor a key voltage continuously in background
mode, but not interrupt the controller unless the converted data is within the specified window.
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN +
HVAIN -
Port 3
Pins
Analog Multiplexer
HVDA
TEMP
SENSOR
AGND
+
-
+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
Configuration, Control, and Data
Progra mmab le Gain
Amplifie r
AV+
+
X
-
External VREF
(C8051F040/1/2/3 Only)
DAC0 Output
Registers
Pin
12/10-Bit
SAR
ADC
VREF
Start
Conversion
Window Compare
Logic
12
Write to AD0BUSY
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
Window
Compare
Interrupt
ADC Data
Registers
Conversion
Complete
Interrupt
Figure 1.12. 10/12-Bit ADC Block Diagram
32 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1.9. 8-Bit Analog to Digital Converter (C8051F040/1/2/3 Only)
The C8051F040/1/2/3 devices have an on-board 8-bit SAR ADC (ADC2) with an 8-channel input multiplexer and programmable gain amplifier. This ADC features a 500 ksps maximum throughput and true 8bit performance with an INL of ±1LSB. Eight input pins are available for measurement and can be programmed as single-ended or differential inputs. The ADC is under full control of the CIP-51 microcontroller
via the Special Function Registers. The ADC2 voltage reference is selected between the analog power
supply (AV+) and an external VREF pin. On C8051F040/2 devices, ADC2 has its own dedicated VREF2
input pin; on C8051F041/3 devices, ADC2 shares the VREFA input pin with the 12/10-bit ADC0. User software may put ADC2 into shutdown mode to save power.
A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful
when different ADC input channels have widely varied input voltage signals, or when it is necessary to
"zoom in" on a signal with a large dc offset (in differential mode, a DAC could be used to provide the dc offset). The PGA gain can be set in software to 0.5, 1, 2, or 4.
A flexible conversion scheduling system allows ADC2 conversions to be initiated by software commands,
timer overflows, or an external input signal. ADC2 conversions may also be synchronized with ADC0 software-commanded conversions. Conversion completions are indicated by a status bit and an interrupt (if
enabled), and the resulting 8-bit data word is latched into an SFR upon completion.
Analog Multiplexer
AIN2.0
AIN2.1
AIN2.2
AIN2.3
AIN2.4
AIN2.5
AIN2.6
AIN2.7
+
-
+
-
+
-
+
-
8-to-1
AMUX
Single-ended or
Differential Measurement
Configuration, Control, and Data Registers
Programmable Gain
Ampli fier
X
AV+
+
-
8-Bit
SAR
ADC
External VREF
Figure 1.13. 8-Bit ADC Diagram
Pin
AV+
VREF
Start Conversion
8
Window
Compare Logic
Write to AD2BUSY
Timer 3 Overflow
CNVSTR2 Input
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
Window
Compare
Interrupt
ADC Data
Register
Conversion
Complete
Interrupt
Rev. 1.4 33
C8051F040/1/2/3/4/5/6/7
1.10. Comparators and DACs
Each C8051F040/1/2/3 MCU has two 12-bit DACs, and all C8051F04x devices have three comparators on
chip. The MCU data and control interface to each comparator and DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low power shutdown mode.
The comparators have software programmable hysteresis and response time. Each comparator can generate an interrupt on its rising edge, falling edge, or both; these interrupts are capable of waking up the
MCU from sleep mode. The comparators' output state can also be polled in software. The comparator outputs can be programmed to appear on the Port I/O pins via the Crossbar.
The DACs are voltage output mode and include a flexible output scheduling mechanism. This scheduling
mechanism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The
DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F040/2 devices or via the
internal voltage reference on C8051F041/3 devices. The DACs are especially useful as references for the
comparators or offsets for the differential inputs of the ADC.
(Po rt I/O )
Comparator inputs
Port 2.[7:2]
CPn+
CPn-
DAC0
(C8051F040/1/2/3 only)
DAC1
CPn Output
3 Comparators
+
CPn
-
VREF
DAC0
VREF
DAC1
CROSSBAR
SFR's
(Data
and
Cntrl)
CIP-51
and
Interrupt
Handler
(C8051F040/1/2/3 only)
Figure 1.14. Comparator and DAC Diagram
34 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on any Pin (except V
pins) with respect to DGND
Voltage on any Port I/O Pin, /RST, and JTAG pins with
respect to DGND
Voltage on V
with respect to DGND –0.3 — 4.2 V
DD
Maximum Total current through V
AGND
Maximum output current sunk by any Port pin — — 100 mA
Maximum output current sunk by any other I/O pin — — 50 mA
Maximum output current sourced by any Port pin — — 100 mA
Maximum output current sourced by any other I/O pin — — 50 mA
, Port I/O, and JTAG
DD
, AV+, DGND, and
DD
–0.3 — VDD +
0.3
–0.3 — 5.8 V
——800mA
V
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Due to special I/O design requirements of the High Voltage Difference Amplifier, undue electrical over-voltage
stress (i.e., ESD) experienced by these pads may result in impedance degredation of these inputs (HVAIN+
and HVAIN–). For this reason, care should be taken to ensure proper handling and use as typically required to
prevent ESD damage to electrostatically sensitive CMOS devices (e.g., static-free workstations, use of
grounding straps, over-voltage protection in end-applications, etc.)
Rev. 1.4 35
C8051F040/1/2/3/4/5/6/7
3. Global DC Electrical Characteristic
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Analog Supply Voltage
1
Analog Supply Current Internal REF, ADC, DAC, Com-
2.7 3.0 3.6 V
—1.7—mA
parators all active
Analog Supply Current with
analog sub-systems inactive
Internal REF, ADC, DAC, Comparators all disabled, oscillator
—0.2—mA
disabled
Analog-to-Digital Supply
Delta (|V
- AV+|)
DD
——0.5V
Digital Supply Voltage 2.7 3.0 3.6 V
Digital Supply Current with
CPU active
(Normal Mode)
Digital Supply Current with
CPU inactive (not accessing
Flash) (Idle Mode)
Digital Supply Current
= 2.7 V, Clock = 25 MHz
V
DD
V
= 2.7 V, Clock = 1 MHz
DD
= 2.7 V, Clock = 32 kHz
V
DD
V
= 2.7 V, Clock = 25 MHz
DD
V
= 2.7 V, Clock = 1 MHz
DD
= 2.7 V, Clock = 32 kHz
V
DD
Oscillator not running — 0.2 — µA
—
—
—
—
—
—
10
0.5
20
5
0.2
10
—
—
—
—
—
—
mA
mA
µA
mA
mA
µA
(shutdown) (Stop Mode)
Digital Supply RAM Data
—1.5— V
Retention Voltage
Specified Operating
–40 — +85 °C
Temperature Range
SYSCLK (system clock
frequency)
2
0—25MHz
Tsysl (SYSCLK low time) 18 — — ns
Tsysh (SYSCLK high time) 18 — — ns
Notes:
1. Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.
2. SYSCLK must be at least 32 kHz to enable debugging.
36 Rev. 1.4
4. Pinout and Package Definitions
Table 4.1. Pin Definitions
C8051F040/1/2/3/4/5/6/7
Name
V
DD
DGND 38, 63, 89 25, 40, 56 Digital Ground. Must be tied to Ground.
AV+ 8, 11, 14 3, 6 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
AGND 9, 10, 13 4, 5 Analog Ground. Must be tied to Ground.
TMS 1 58 D In JTAG Test Mode Select with internal pullup.
TCK 2 59 D In JTAG Test Clock with internal pullup.
TDI 3 60 D In JTAG Test Data Input with internal pullup. TDI is latched on the
TDO 4 61 D Out JTAG Test Data Output with internal pullup. Data is shifted out on
/RST 5 62 D I/O Device Reset. Open-drain output of internal VDD monitor. Is
XTAL1 26 17 A In Crystal Input. This pin is the return for the internal oscillator circuit
Pin Numbers
F040/2/4/6 F041/3/5/7
37, 64, 90 24, 41, 57 Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
Typ e Description
rising edge of TCK.
TDO on the falling edge of TCK. TDO output is a tri-state driver.
driven low when V
source can initiate a system reset by driving this pin low.
for a crystal or ceramic resonator. For a precision internal clock,
connect a crystal or ceramic resonator from XTAL1 to XTAL2. If
overdriven by an external CMOS clock, this becomes the system
clock.
is < 2.7 V and MONEN is high. An external
DD
XTAL2 27 18 A Out Crystal Output. This pin is the excitation driver for a crystal or
ceramic resonator.
MONEN 28 19 D In VDD Monitor Enable. When tied high, this pin enables the internal
monitor, which forces a system reset when VDD is < 2.7 V.
V
DD
When tied low, the internal V
In most applications, MONEN should be connected directly
to V
VREF 12 7 A I/O Bandgap Voltage Reference Output (all devices).
DAC Voltage Reference Input (C8051F041/3 only).
VREFA 8 A In ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only)
Voltage Reference Input.
VREF0 16 A In ADC0 Voltage Reference Input.
VREF2 17 A In ADC2 Voltage Reference Input (C8051F040/2 only).
VREF 15 A In DAC Voltage Reference Input (C8051F040/2 only).
AIN0.0 18 9 A In ADC0 Input Channel 0 (See ADC0 Specification for complete
description).
AIN0.1 19 10 A In ADC0 Input Channel 1 (See ADC0 Specification for complete
description).
DD
.
monitor is disabled.
DD
Rev. 1.4 37
C8051F040/1/2/3/4/5/6/7
Table 4.1. Pin Definitions (Continued)
Name
AIN0.2 20 11 A In ADC0 Input Channel 2 (See ADC0 Specification for complete
AIN0.3 21 12 A In ADC0 Input Channel 3 (See ADC0 Specification for complete
HVCAP 22 13 A I/O High Voltage Difference Amplifier Capacitor.
HVREF 23 14 A In High Voltage Difference Amplifier Reference.
HVAIN+ 24 15 A In High Voltage Difference Amplifier Positive Signal Input.
HVAIN- 25 16 A In High Voltage Difference Amplifier Positive Signal Input.
CANTX 7 2 D Out Controller Area Network Transmit Output.
CANRX 6 1 D In Controller Area Network Receive Input.
DAC0 100 64 A Out Digital to Analog Converter 0 Voltage Output. (See DAC Specifi-
DAC1 99 63 A Out Digital to Analog Converter 1 Voltage Output. (See DAC Specifi-
P0.0 62 55 D I/O Port 0.0. See Port Input/Output section for complete description.
P0.1 61 54 D I/O Port 0.1. See Port Input/Output section for complete description.
P0.2 60 53 D I/O Port 0.2. See Port Input/Output section for complete description.
Pin Numbers
Typ e Description
F040/2/4/6 F041/3/5/7
description).
description).
cation for complete description). (C8051F040/1/2/3 only)
cation for complete description). (C8051F040/1/2/3 only)
P0.3 59 52 D I/O Port 0.3. See Port Input/Output section for complete description.
P0.4 58 51 D I/O Port 0.4. See Port Input/Output section for complete description.
P0.5/ALE 57 50 D I/O ALE Strobe for External Memory Address bus (multiplexed mode)
Port 0.5
See Port Input/Output section for complete description.
P0.6/RD 56 49 D I/O /RD Strobe for External Memory Address bus
Port 0.6
See Port Input/Output section for complete description.
P0.7/WR 55 48 D I/O /WR Strobe for External Memory Address bus
Port 0.7
See Port Input/Output section for complete description.
P1.0/AIN2.0/A8 36 29 A In
D I/O
P1.1/AIN2.1/A9 35 28 A In
D I/O
P1.2/AIN2.2/A10 34 27 A In
D I/O
P1.3/AIN2.3/A11 33 26 A In
D I/O
ADC1 Input Channel 0 (See ADC1 Specification for complete
description).
Bit 8 External Memory Address bus (Non-multiplexed mode)
Port 1.0
See Port Input/Output section for complete description.
Port 1.1. See Port Input/Output section for complete description.
Port 1.2. See Port Input/Output section for complete description.
Port 1.3. See Port Input/Output section for complete description.
38 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Table 4.1. Pin Definitions (Continued)
Name
P1.4/AIN2.4/A12 32 23 A In
P1.5/AIN2.5/A13 31 22 A In
P1.6/AIN2.6/A14 30 21 A In
P1.7/AIN2.7/A15 29 20 A In
P2.0/A8m/A0 46 37 D I/O Bit 8 External Memory Address bus (Multiplexed mode)
P2.1/A9m/A1 45 36 D I/O Port 2.1. See Port Input/Output section for complete description.
P2.2/A10m/A2 44 35 D I/O Port 2.2. See Port Input/Output section for complete description.
P2.3/A11m/A3 43 34 D I/O Port 2.3. See Port Input/Output section for complete description.
P2.4/A12m/A4 42 33 D I/O Port 2.4. See Port Input/Output section for complete description.
P2.5/A13m/A5 41 32 D I/O Port 2.5. See Port Input/Output section for complete description.
P2.6/A14m/A6 40 31 D I/O Port 2.6. See Port Input/Output section for complete description.
P2.7/A15m/A7 39 30 D I/O Port 2.7. See Port Input/Output section for complete description.
P3.0/AD0/D0 54 47 A In
Pin Numbers
F040/2/4/6 F041/3/5/7
Typ e Description
Port 1.4. See Port Input/Output section for complete description.
D I/O
Port 1.5. See Port Input/Output section for complete description.
D I/O
Port 1.6. See Port Input/Output section for complete description.
D I/O
Port 1.7. See Port Input/Output section for complete description.
D I/O
Bit 0 External Memory Address bus (Non-multiplexed mode) Port
2.0
See Port Input/Output section for complete description.
Bit 0 External Memory Address/Data bus (Multiplexed mode)
D I/O
Bit 0 External Memory Data bus (Non-multiplexed mode)
Port 3.0
See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
P3.1/AD1/D1 53 46 A In
D I/O
P3.2/AD2/D2 52 45 A In
D I/O
P3.3/AD3/D3 51 44 A In
D I/O
P3.4/AD4/D4 50 43 A In
D I/O
P3.5/AD5/D5 49 42 A In
D I/O
P3.6/AD6/D6 48 39 A In
D I/O
P3.7/AD7/D7 47 38 A In
D I/O
P4.0 98 D I/O Port 4.0. See Port Input/Output section for complete description.
Port 3.1. See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
Port 3.2. See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
Port 3.3. See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
Port 3.4. See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
Port 3.5. See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
Port 3.6. See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
Port 3.7. See Port Input/Output section for complete description.
ADC0 Input. (See ADC0 Specification for complete description.)
Rev. 1.4 39
C8051F040/1/2/3/4/5/6/7
Table 4.1. Pin Definitions (Continued)
Name
P4.1 97 D I/O Port 4.1. See Port Input/Output section for complete description.
P4.2 96 D I/O Port 4.2. See Port Input/Output section for complete description.
P4.3 95 D I/O Port 4.3. See Port Input/Output section for complete description.
P4.4 94 D I/O Port 4.4. See Port Input/Output section for complete description.
P4.5/ALE 93 D I/O ALE Strobe for External Memory Address bus (multiplexed mode)
P4.6/RD 92 D I/O /RD Strobe for External Memory Address bus
P4.7/WR 91 D I/O /WR Strobe for External Memory Address bus
P5.0/A8 88 D I/O Bit 8 External Memory Address bus (Non-multiplexed mode)
P5.1/A9 87 D I/O Port 5.1. See Port Input/Output section for complete description.
P5.2/A10 86 D I/O Port 5.2. See Port Input/Output section for complete description.
Pin Numbers
Typ e Description
F040/2/4/6 F041/3/5/7
Port 4.5
See Port Input/Output section for complete description.
Port 4.6
See Port Input/Output section for complete description.
Port 4.7
See Port Input/Output section for complete description.
Port 5.0
See Port Input/Output section for complete description.
P5.3/A11 85 D I/O Port 5.3. See Port Input/Output section for complete description.
P5.4/A12 84 D I/O Port 5.4. See Port Input/Output section for complete description.
P5.5/A13 83 D I/O Port 5.5. See Port Input/Output section for complete description.
P5.6/A14 82 D I/O Port 5.6. See Port Input/Output section for complete description.
P5.7/A15 81 D I/O Port 5.7. See Port Input/Output section for complete description.
P6.0/A8m/A0 80 D I/O Bit 8 External Memory Address bus (Multiplexed mode)
Bit 0 External Memory Address bus (Non-multiplexed mode)
Port 6.0
See Port Input/Output section for complete description.
P6.1/A9m/A1 79 D I/O Port 6.1. See Port Input/Output section for complete description.
P6.2/A10m/A2 78 D I/O Port 6.2. See Port Input/Output section for complete description.
P6.3/A11m/A3 77 D I/O Port 6.3. See Port Input/Output section for complete description.
P6.4/A12m/A4 76 D I/O Port 6.4. See Port Input/Output section for complete description.
P6.5/A13m/A5 75 D I/O Port 6.5. See Port Input/Output section for complete description.
P6.6/A14m/A6 74 D I/O Port 6.6. See Port Input/Output section for complete description.
P6.7/A15m/A7 73 D I/O Port 6.7. See Port Input/Output section for complete description.
P7.0/AD0/D0 72 D I/O Bit 0 External Memory Address/Data bus (Multiplexed mode)
Bit 0 External Memory Data bus (Non-multiplexed mode)
Port 7.0
See Port Input/Output section for complete description.
40 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Table 4.1. Pin Definitions (Continued)
Name
P7.1/AD1/D1 71 D I/O Port 7.1. See Port Input/Output section for complete description.
P7.2/AD2/D2 70 D I/O Port 7.2. See Port Input/Output section for complete description.
P7.3/AD3/D3 69 D I/O Port 7.3. See Port Input/Output section for complete description.
P7.4/AD4/D4 68 D I/O Port 7.4. See Port Input/Output section for complete description.
P7.5/AD5/D5 67 D I/O Port 7.5. See Port Input/Output section for complete description.
P7.6/AD6/D6 66 D I/O Port 7.6. See Port Input/Output section for complete description.
P7.7/AD7/D7 65 D I/O Port 7.7. See Port Input/Output section for complete description.
Pin Numbers
Typ e Description
F040/2/4/6 F041/3/5/7
Rev. 1.4 41
C8051F040/1/2/3/4/5/6/7
DAC0
DAC1
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
VDD
DGND
9998979695949392919089888786858483828180797877
100
P5.0/A8
P5.1/A9
P5.2/A10
P5.3/A11
P5.4/A12
P5.5/A13
P5.6/A14
P5.7/A15
P6.0/A8m/A0
P6.1/A9m/A1
P6.2/A10m/A2
P6.3/A11m/A3
P6.4/A12m/A4
76
TMS
TCK
TDI
TDO
/RST
CANRX
CANTX
AV+
AGND
AGND
AV+
VREF
AGND
AV+
VREFD
VREF0
VREF2
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVCAP
HVREF
HVAIN+
HVAIN-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
C8051F040/2/4/6
262728293031323334353637383940
41
424344454647484950
75
P6.5/A13m/A5
74
P6.6/A14m/A6
73
P6.7/A15m/A7
72
P7.0/AD0/D0
71
P7.1/AD1/D1
70
P7.2/AD2/D2
69
P7.3/AD3/D3
68
P7.4/AD4/D4
67
P7.5/AD5/D5
66
P7.6/AD6/D6
65
P7.7/AD7/D7
64
VDD
63
DGND
62
P0.0
61
P0.1
60
P0.2
59
P0.3
58
P0.4
57
P0.5/ALE
56
P0.6/RD
55
P0.7/WR
54
P3.0/AD0/D0
53
P3.1/AD1/D1
52
P3.2/AD2/D2
51
P3.3/AD3/D3
VDD
P1.0/AIN2.0/A8
DGND
P2.7/A15m/A7
P2.6/A14m/A6
XTAL1
XTAL2
MONEN
P1.7/AIN2.7/A15
P1.6/AIN2.6/A14
P1.5/AIN2.5/A13
P1.4/AIN2.4/A12
P1.1/AIN2.1/A9
P1.3/AIN2.3/A11
P1.2/AIN2.2/A10
Figure 4.1. TQFP-100 Pinout Diagram
42 Rev. 1.4
P2.5/A13m/A5
P2.4/A12m/A4
P2.3/A11m/A3
P2.2/A10m/A2
P3.7/AD7/D7
P3.6/AD6/D6
P3.5/AD5/D5
P2.1/A9m/A1
P2.0/A8m/A0
P3.4/AD4/D4
C8051F040/1/2/3/4/5/6/7
100
PIN 1
DESIGNATOR
D
D1
E1 E
1
A
A1
A2
b
D
D1
e
E
E1
L
MIN
(mm)
-
0.05
0.95
0.17
-
-
-
-
-
0.45
NOM
(mm)
-
-
1.00
0.22
16.00
14.00
0.50
16.00
14.00
0.60
MAX
(mm)
1.20
0.15
1.05
0.27
-
-
-
-
-
0.75
A2
L
e
A
b
A1
Figure 4.2. TQFP-100 Package Drawing
Rev. 1.4 43
C8051F040/1/2/3/4/5/6/7
DAC0
DAC1
/RST
TDO
TDI
TCK
TMS
64
63
62
61
60
59
58
VDD
57
DGND
56
P0.0
55
P0.1
54
P0.2
53
P0.3
52
P0.4
51
P0.5/ALE
50
P0.6/RD
49
CANRX
CANTX
AV+
AGND
AGND
AV+
VREF
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVCAP
HVREF
HVAIN+
HVAIN-
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
17
18
C8051F041/3/5/7
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
P0.7/WR
47
P3.0/AD0/D0
46
P3.1/AD1/D1
45
P3.2/AD2/D2
44
P3.3/AD3/D3
43
P3.4/AD4/D4
42
P3.5/AD5/D5
41
VDD
40
DGND
39
P3.6/AD6/D6
38
P3.7/AD7/D7
37
P2.0/A8m/A0
36
P2.1/A9m/A1
35
P2.2/A10m/A2
34
P2.3/A11m/A3
33
P2.4/A12m/A4
VDD
XTAL1
XTAL2
MONEN
P1.7/AIN2.7/A15
P1.6/AIN2.6/A14
P1.5/AIN2.5/A13
P1.4/AIN2.4/A12
DGND
Figure 4.3. TQFP-64 Pinout Diagram
44 Rev. 1.4
P1.3/AIN2.3/A11
P1.2/AIN2.2/A10
P1.1/AIN2.1/A9
P1.0/AIN2.0/A8
P2.7/A15m/A7
P2.6/A14m/A6
P2.5/A13m/A5
D
D1
C8051F040/1/2/3/4/5/6/7
64
PIN 1
DESIGNATOR
A2
L
1
MIN
(mm)
A
A1
0.05
A2
E1
E
0.95
b
0.17
D
D1
e
e
A
b
A1
E
E1
L
0.45
-
-
-
-
-
-
NOM
(mm)
-
-
-
0.22
12.00
10.00
0.50
12.00
10.00
0.6
MAX
(mm)
1.20
0.15
1.05
0.27
-
-
-
-
-
0.75
Figure 4.4. TQFP-64 Package Drawing
Rev. 1.4 45
C8051F040/1/2/3/4/5/6/7
NOTES:
46 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
5. 12-Bit ADC (ADC0, C8051F040/1 Only)
The ADC0 subsystem for the C8051F040/1 consists of a 9-channel, configurable analog multiplexer
(AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in
Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under
software control via the Special Function Registers shown in Figure 5.1. The voltage reference used by
ADC0 is selected as described in Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113 for
C8051F040 devices, or Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117 for
C8051F041 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when the
AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power
shutdown when this bit is logic 0.
ADC0LTLADC0LTHADC0GTLADC0GTH
24
HV
Input
Port 3
I/O Pins
Analog
Input
Pins
9-to-1
AMUX
(SE or
DIFF)
X
+
-
AD0EN
AV+
AGND
AV+
12-Bit
SAR
ADC
Comb.
Logic
12
REF
SYSCLK
12
ADC0L ADC0H
AD0WINT
00
01
10
11
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
TEMP
SENSOR
AGND Timer 2 Overflow
HVDAIC
AIN01IC
AIN23IC
PORT3IC
AMX0CF
AMX0SL
AMX0AD0
AMX0AD1
AMX0AD2
AMX0AD3
AD0SC3
AD0SC4
ADC0CF
AD0SC1
AD0SC2
AMP0GN0
AMP0GN1
AMP0GN2
AD0SC0
AD0INT
AD0TM
AD0EN
ADC0CN
AD0BUSY
AD0CM1
AD0CM0
Start Conversion
AD0LJST
AD0WINT
Figure 5.1. 12-Bit ADC0 Functional Block Diagram
5.1. Analog Multiplexer and PGA
The analog multiplexer can input analog signals to the ADC from four external analog input pins (AIN0.0 AIN0.3), Port 3 port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, or
an internally connected on-chip temperature sensor (temperature transfer function is shown in Figure 5.6).
AMUX input pairs can be programmed to operate in either differential or single-ended mode. This allows
the user to select the best measurement technique for each input channel, and even accommodates mode
changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers
associated with the AMUX: the Channel Selection register AMX0SL (SFR Definition 5.2), the Configuration
register AMX0CF (SFR Definition 5.1), and the Port Pin Selection register AMX0PRT (SFR Definition 5.3).
Table 5.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the
AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (SFR Definition 5.5). The PGA can be software-programmed for gains of 0.5, 2, 4,
8 or 16. Gain defaults to unity on reset.
Rev. 1.4 47
C8051F040/1/2/3/4/5/6/7
5.1.1. Analog Input Configuration
The analog multiplexer routes signals from external analog input pins, Port 3 I/O pins (See Section
“17.1.5. Configuring Port 1, 2, and 3 Pins as Analog Inputs” on page 209), a High Voltage Difference
Amplifier, and an on-chip temperature sensor as shown in Figure 5.2.
AIN01IC
AIN23IC
HVDAIC
PORT3IC
12-Bit
SAR
ADC
PAIN0EN
PAIN2EN
PAIN4EN
PAIN6EN
PAIN1EN
PAIN3EN
AMX0PRT
PAIN5EN
PAIN7EN
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN +
HVAIN -
HVCAP
HVREF
P3.6
P3.4
P3.2
P3.0
P3.7
P3.5
P3.3
P3.1
HV
AMP
AGND
(WIRED -OR)
P3EVEN
P3ODD
(WIRED -OR)
+
0
-
1
2
+
-
3
+
4
-
5
9-to-1
AMUX
(SE or
DIFF)
6
+
7
8
AMX0CF
X
TEMP SENSOR
AMX0AD0
AMX0AD1
AMX0AD2
AMX0AD3
AGND
AMX0SL
Figure 5.2. Analog Input Diagram
Analog signals may be input from four external analog input pins (AIN0.0 through AIN0.3) as differential or
single-ended measurements. Additionally, Port 3 I/O Port Pins may be configured to input analog signals.
Port 3 pins configured as analog inputs are selected using the Port Pin Selection register (AMX0PRT). Any
number of Port 3 pins may be selected simultaneously as inputs to the AMUX. Even numbered Port 3 pins
and odd numbered Port 3 pins are routed to separate AMUX inputs. (Note: Even port pins and odd port
pins that are simultaneously selected will be shorted together as “wired-OR”.) In this way, differential measurements may be made when using the Port 3 pins (voltage difference between selected even and odd
Port 3 pins) as shown in Figure 5.2.
The High Voltage Difference Amplifier (HVDA) will accept analog input signals and reject up to 60 volts
common-mode for differential measurement of up to the reference voltage to the ADC (0 to VREF volts).
The output of the HVDA can be selected as an input to the ADC using the AMUX as any other channel is
selected for input. (See Section “5.2. High Voltage Difference Amplifier” on page 52).
48 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 5.1. AMX0CF: AMUX0 Configuration
R R R R R/W R/W R/W R/W Reset Value
- - - - PORT3IC HVDA2C AIN23IC AIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bit3: PORT3IC: Port 3 even/odd Pin Input Pair Configuration Bit
0: Port 3 even and odd input channels are independent single-ended inputs
1: Port 3 even and odd input channels are (respectively) +, - difference input pair
Bit2: HVDA2C: HVDA 2’s Compliment Bit
0: HVDA output measured as an independent single-ended input
1: HVDA result for 2’s compliment value
Bit1: AIN23IC: AIN0.2, AIN0.3 Input Pair Configuration Bit
0: AIN0.2 and AIN0.3 are independent single-ended inputs
1: AIN0.2, AIN0.3 are (respectively) +, - difference input pair
Bit0: AIN01IC: AIN0.0, AIN0.1 Input Pair Configuration Bit
0: AIN0.0 and AIN0.1 are independent single-ended inputs
1: AIN0.0, AIN0.1 are (respectively) +, - difference input pair
SFR
Address:
0xBA
0
NOTE: The ADC0 Data Word is in 2’s complement format for channels configured as difference.
SFR Definition 5.2. AMX0SL: AMUX0 Channel Select
R R R R R/W R/W R/W R/W Reset Value
- - - - AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bits3-0: AMX0AD3-0: AMX0 Address Bits
0000-1111b: ADC Inputs selected per Table 5.1.
0xBB
0
Rev. 1.4 49
C8051F040/1/2/3/4/5/6/7
Table 5.1. AMUX Selection Chart (AMX0AD3–0 and AMX0CF3–0 bits)
0000 0001 0010 0011 0100 0101 0110 0111 1xxx
AIN0.0 AIN0.1 AIN0.2 AIN0.3 HVDA AGND P3EVEN P3ODD
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1 AIN0.2 AIN0.3 P3EVEN P3ODD
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1 AIN0.2 AIN0.3 HVDA AGND
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1 AIN0.2 AIN0.3
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.2 AIN0.3 HVDA AGND P3EVEN P3ODD
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AIN0.2 AIN0.3 P3EVEN P3ODD
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AIN0.2 AIN0.3 HVDA AGND
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AIN0.2 AIN0.3
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AMX0CF Bits 3-0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AMX0AD3-0
HVDA AGND P3EVEN P3ODD
HVDA AGND P3EVEN P3ODD
P3EVEN P3ODD
P3EVEN P3ODD
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
HVDA AGND
HVDA AGND
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD)
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
Note: “P3EVEN” denotes even numbered and “P3ODD” odd numbered Port 3 pins selected in the AMX0PRT
register.
50 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 5.3. AMX0PRT: Port 3 Pin Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PAIN7EN PAIN6EN PAIN5EN PAIN4EN PAIN3EN PAIN2EN PAIN1EN PAIN0EN 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bit7: PAIN7EN: Pin 7 Analog Input Enable Bit
0: P3.7 is not selected as an analog input to the AMUX.
1: P3.7 is selected as an analog input to the AMUX.
Bit6: PAIN6EN: Pin 6 Analog Input Enable Bit
0: P3.6 is not selected as an analog input to the AMUX.
1: P3.6 is selected as an analog input to the AMUX.
Bit5: PAIN5EN: Pin 5 Analog Input Enable Bit
0: P3.5 is not selected as an analog input to the AMUX.
1: P3.5 is selected as an analog input to the AMUX.
Bit4: PAIN4EN: Pin 4 Analog Input Enable Bit
0: P3.4 is not selected as an analog input to the AMUX.
1: P3.4 is selected as an analog input to the AMUX.
Bit3: PAIN3EN: Pin 3 Analog Input Enable Bit
0: P3.3 is not selected as an analog input to the AMUX.
1: P3.3 is enabled as an analog input to the AMUX.
Bit2: PAIN2EN: Pin 2 Analog Input Enable Bit
0: P3.2 is not selected as an analog input to the AMUX.
1: P3.2 is enabled as an analog input to the AMUX.
Bit1: PAIN1EN: Pin 1 Analog Input Enable Bit
0: P3.1 is not selected as an analog input to the AMUX.
1: P3.1 is enabled as an analog input to the AMUX.
Bit0: PAIN0EN: Pin 0 Analog Input Enable Bit
0: P3.0 is not selected as an analog input to the AMUX.
1: P3.0 is enabled as an analog input to the AMUX.
0xBD
0
Note:Any number of Port 3 pins may be selected simultaneously inputs to the AMUX. Odd numbered and even
numbered pins that are selected simultaneously are shorted together as “wired-OR”.
Rev. 1.4 51
C8051F040/1/2/3/4/5/6/7
5.2. High Voltage Difference Amplifier
The High Voltage Difference Amplifier (HVDA) can be used to measure high differential voltages up to 60 V
peak-to-peak, reject high common-mode voltages up to ±60 V, and condition the signal voltage range to be
suitable for input to ADC0. The input signal to the HVDA may be below AGND to –60 volts, and as high as
+60 volts, making the device suitable for both single and dual supply applications. The HVDA will provides
a common-mode signal for the ADC via the High Voltage Reference Input (HVREF), allowing measurement of signals outside the specified ADC input range using on-chip circuitry. The HVDA has a gain of
0.05 V/V to 14 V/V. The first stage 20:1 difference amplifier has a gain of 0.05 V/V when the output amplifier is used as a unity gain buffer. When the output amplifier is set to a gain of 280 (selected using the
HVGAIN bits in the High Voltage Control Register), the overall gain of 14 can be attained. The HVDA is
factory calibrated for a high common-mode rejection of 72 dB.
The HVDA uses four available external pins: +HVAIN, –HVAIN, HVCAP, and the aforementioned HVREF.
HVAIN+ and HVAIN- serve as the differential inputs to the HVDA. HVREF can be used to provide a common mode reference for input to ADC0. HVCAP facilitates the use of a capacitor for noise filtering in conjunction with R7 (see Figure 5.3 for R7 and other approximate resistor values). Alternatively, the HVCAP
could also be used to access amplification of the first stage of the HVDA at an external pin. (See Table 5.3
on page 68 for electrical specifications of the HVDA.)
V
OUT
Note: The output voltage of the HVDA is selected as an input to ADC0 via its analog multiplexer (AMUX0). HVDA
output voltages greater than the ADC0 reference voltage (Vref) or less than 0 volts (with respect to analog
ground) will result in saturation (output codes > full-scale or output codes < 0 respectively.) Allow for adequate
settle/tracking time for proper voltage measurements.
HVAIN+()HVAIN-()–[]Gain HVREF+⋅=
Equation 5.1. Calculating HVDA Output Voltage to ADC0
HVCAP
100kΩ
HVAIN-
HVAIN+
100k
Resistor values are
approximate
5k
Ω
5k
Ω
HVA0CN
5k
Ω
Ω
Gain Setting
HVREF
Vout
(To AMUX0)
Figure 5.3. High Voltage Difference Amplifier Functional Diagram
52 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 5.4. HVA0CN: High Voltage Difference Amplifier Control
R/W R R R R/W R/W R/W R/W Reset Value
HVDAEN - - - HVGAIN3 HVGAIN2 HVGAIN1 HVGAIN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bit7: HVDAEN: High Voltage Difference Amplifier (HVDA) Enable Bit.
0: The HVDA is disabled.
1: The HVDA is enabled.
Bits6-3: Reserved.
Bits2-0: HVGAIN3-HVGAIN0: HVDA Gain Control Bits.
HVDA Gain Control Bits set the amplification gain if the difference signal input to the HVDA
as defined in the table below:
HVGAIN3:HVGAIN0 HVDA Gain
0000 0.05
0001 0.1
0010 0.125
0011 0.2
0100 0.25
0101 0.4
0110 0.5
0111 0.8
1000 1.0
1001 1.6
1010 2.0
1011 3.2
1100 4.0
1101 6.2
1110 7.6
1111 14
0xD6
0
Rev. 1.4 53
C8051F040/1/2/3/4/5/6/7
5.3. ADC Modes of Operation
ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the system clock divided by the value held in the ADC0SC bits of register ADC0CF.
5.3.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by the following:
• Writing a ‘1’ to the AD0BUSY bit of ADC0CN;
• A Timer 3 overflow (i.e., timed continuous conversions);
• A rising edge detected on the external ADC convert start signal, CNVSTR0;
• A Timer 2 overflow (i.e., timed continuous conversions).
The AD0BUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete.
The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the AD0INT interrupt flag
(ADC0CN.5). Converted data is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L.
Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in
Figure 5.7) depending on the programmed state of the AD0LJST bit in the ADC0CN register.
When initiating conversions by writing a ‘1’ to AD0BUSY, the AD0INT bit should be polled to determine
when a conversion has completed (ADC0 interrupts may also be used). The recommended polling procedure is shown below.
Step 1. Write a ‘0’ to AD0INT;
Step 2. Write a ‘1’ to AD0BUSY;
Step 3. Poll AD0INT for ‘1’;
Step 4. Process ADC0 data.
5.3.2. Tracking Modes
According to Table 5.2, each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode.
In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the
AD0TM bit is logic 1, ADC0 operates in low-power tracking mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks after the start-of-conversion signal. When the CNVSTR0 signal
is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low; conversion begins on the rising edge of CNVSTR0 (see Figure 5.4). Tracking can also be disabled when the
entire chip is in low power standby or sleep modes. Low-power tracking mode is also useful when AMUX
or PGA settings are frequently changed, to ensure that settling time requirements are met (see Section
“5.3.3. Settling Time Requirements” on page 56).
54 Rev. 1.4
(AD0STM[1:0]=10)
CNVSTR
SAR Clocks
C8051F040/1/2/3/4/5/6/7
A. ADC Timing for External Trigger Source
12345678910111213141516
ADC0TM=1
ADC0TM=0
Timer 2, Timer 3 Overflow;
Write '1' to AD0BUSY
(AD0STM[1:0]=00, 01, 11)
SAR Clocks
ADC0TM=1
SAR Clocks
ADC0TM=0
Figure 5.4. 12-Bit ADC Track and Conversion Example Timing
Low Power
or Convert
Track Or Convert Convert Track
Track Convert Low Power Mode
B. ADC Timing for Internal Trigger Sources
1234567891011121314151617 18 19
Low Power
or Convert
Track or
Convert
Track Convert Low Power Mode
12345678910111213141516
Convert Track
Rev. 1.4 55
C8051F040/1/2/3/4/5/6/7
5.3.3. Settling Time Requirements
A minimum tracking time is required before an accurate conversion can be performed. This tracking time is
determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Figure 5.5 shows the equivalent ADC0 input circuits
for both differential and Single-ended modes. Notice that the equivalent time constant for both input circuits
is the same. The required settling time for a given settling accuracy (SA) may be approximated by
Equation 5.2. When measuring the Temperature Sensor output, R
Low-Power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For
most applications, these three SAR clocks will meet the tracking requirements. See Table 5.2 for absolute
minimum settling/tracking time requirements.
n
2
⎛⎞
t
-------
×ln=
⎝⎠
SA
R
TOTALCSAMPLE
Equation 5.2. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (12).
is the sum of the ADC0 MUX resistance and any external source resistance.
TOTAL
reduces to R
TOTAL
. Note that in
MUX
AIN0.x
AIN0.y
Differential Mode
MUX Select
R
= 5k
MUX
RC
= R
Input
MUX Select
* C
MUX
SAMP LE
R
= 5k
MUX
Figure 5.5. ADC0 Equivalent Input Circuits
C
SAMPLE
C
SAMPLE
= 10pF
= 10pF
Single-Ended Mode
MUX Select
AIN0.x
RC
Input
= R
MUX
R
* C
MUX
SAMPL E
= 5k
C
SAMPLE
= 10pF
56 Rev. 1.4
(Volts)
1.000
0.900
0.800
0.700
0.600
0.500
C8051F040/1/2/3/4/5/6/7
V
= 0.00286(TEMPC) + 0.776
TEMP
for PGA Gain = 1
0-50 50 100
Figure 5.6. Temperature Sensor Transfer Function
(Celsius)
Rev. 1.4 57
C8051F040/1/2/3/4/5/6/7
SFR Definition 5.5. ADC0CF: ADC0 Configuration Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC4 A D 0 S C3 AD 0 S C 2 A D 0 SC1 AD 0 S C 0 AMP0GN2 AM P 0 G N1 AMP0G N 0 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in AD0SC4-0, and CLK
SAR clock. See Table 5.2 for SAR clock configuration requirements.
SYSCLK
AD0SC
*Note: AD0SC is the rounded-up result.
Bits2-0: AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA)
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
-----------------------
CLK
SAR0
* or
1–≥ CLK
SAR0
SAR0
SYSCLK
----------------------------
=
AD0SC 1+
SFR Address:
SFR Page:
refers to the desired ADC0
0xBC
0
58 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 5.6. ADC0CN: ADC0 Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT AD0LJST 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: AD0TM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by AD0CM1-0 bits
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC0 has not completed a data conversion since the last time this flag was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0STM1-0 = 00b
Bit3-2: AD0CM1-0: ADC0 Start of Conversion Mode Select.
If AD0TM = 0:
00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR0.
11: ADC0 conversion initiated on overflow of Timer 2.
If AD0TM = 1:
00: Tracking starts with the write of ‘1’ to AD0BUSY and lasts for 3 SAR clocks, followed by
conversion.
01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks, followed by conversion.
10: ADC0 tracks only when CNVSTR0 input is logic low; conversion starts on rising
CNVSTR0 edge.
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks, followed by conversion.
Bit1: AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bit0: AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bit
Addressable
0xE8
0
Rev. 1.4 59
C8051F040/1/2/3/4/5/6/7
SFR Definition 5.7. ADC0H: ADC0 Data Word MSB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
SFR Address:
SFR Page:
Bits7-0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4 bits of the
12-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7-0 are the most-significant bits of the 12-bit ADC0 Data Word.
SFR Definition 5.8. ADC0L: ADC0 Data Word LSB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
SFR Address:
SFR Page:
00000000
0xBF
0
00000000
0xBE
0
Bits7-0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 12-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7-4 are the lower 4 bits of the 12-bit ADC0 Data Word. Bits3-0 will
always read ‘0’.
60 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
12-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows:
ADC0H[3:0]:ADC0L[7:0], if AD0LJST = 0
(ADC0H[7:4] will be sign-extension of ADC0H.3 for a differential reading,
otherwise = 0000b).
ADC0H[7:0]:ADC0L[7:4], if AD0LJST = 1
(ADC0L[3:0] = 0000b).
Example: ADC0 Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0CF = 0x00, AMX0SL = 0x00)
AIN0-AGND (Volts)
VREF * (4095/4096) 0x0FFF 0xFFF0
VREF / 2 0x0800 0x8000
VREF * (2047/4096) 0x07FF 0x7FF0
0 0x0000 0x0000
Example: ADC0 Data Word Conversion Map, AIN0-AIN1 Differential Input Pair
(AMX0CF = 0x01, AMX0SL = 0x00)
AIN0-AGND (Volts)
VREF * (2047/2048) 0x07FF 0x7FF0
VREF / 2 0x0400 0x4000
VREF * (1/2048) 0x0001 0x0010
0 0x0000 0x0000
-VREF * (1/2048) 0xFFFF (-1d) 0xFFF0
-VREF / 2 0xFC00 (-1024d) 0xC000
-VREF 0xF800 (-2048d) 0x8000
ADC0H:ADC0L
(AD0LJST = 0)
ADC0H:ADC0L
(AD0LJST = 0)
ADC0H:ADC0L
(AD0LJST = 1)
ADC0H:ADC0L
(AD0LJST = 1)
For AD0LJST = 0:
Code Vin
× 2n×=
Figure 5.7. ADC0 Data Word Example
Gain
---------------
VREF
; ‘n’ = 12 for Single-Ended; ‘n’=11 for Differential.
Rev. 1.4 61
C8051F040/1/2/3/4/5/6/7
5.4. ADC0 Programmable Window Detector
The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed
limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an
interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response
times. The window detector interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. The
high and low bytes of the reference words are loaded into the ADC0 Greater-Than and ADC0 Less-Than
registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Reference comparisons are shown starting
on page 63. Notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
SFR Definition 5.9. ADC0GTH: ADC0 Greater-Than Data High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: High byte of ADC0 Greater-Than Data Word.
0xC5
0
SFR Definition 5.10. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xC4
0
Bits7-0: Low byte of ADC0 Greater-Than Data Word.
SFR Definition 5.11. ADC0LTH: ADC0 Less-Than Data High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: High byte of ADC0 Less-Than Data Word.
0xC7
0
11111111
62 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 5.12. ADC0LTL: ADC0 Less-Than Data Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: Low byte of ADC0 Less-Than Data Word.
0xC6
0
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
REF x (512/4096)
REF x (256/4096)
0
ADC Data
Word
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x00
AD0LJST = ‘0’,
ADC0LTH:ADC0LTL = 0x0200,
ADC0GTH:ADC0GTL = 0x0100.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x0200 and > 0x0100.
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
REF x (512/4096)
REF x (256/4096)
0
ADC Data
Word
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x00,
AD0LJST = ‘0’,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0x0200.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
> 0x0200 or < 0x0100.
Figure 5.8. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended
Data
Rev. 1.4 63
C8051F040/1/2/3/4/5/6/7
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
REF x (256/2048)
REF x (-1/2048)
-REF
ADC Data
Word
0x07FF
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
0xF800
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = ‘0’,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0xFFFF.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x0100 and > 0xFFFF. (In two’s-complement
math, 0xFFFF = -1.)
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
REF x (256/2048)
REF x (-1/2048)
-REF
ADC Data
Word
0x07FF
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
0xF800
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = ‘0’,
ADC0LTH:ADC0LTL = 0xFFFF,
ADC0GTH:ADC0GTL = 0x0100.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0xFFFF or > 0x0100. (In two’s-complement
math, 0xFFFF = -1.)
Figure 5.9. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential
Data
64 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
REF x (512/4096)
REF x (256/4096)
0
ADC Data
Word
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
0x0000
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x00,
AD0LJST = ‘1’,
ADC0LTH:ADC0LTL = 0x2000,
ADC0GTH:ADC0GTL = 0x1000.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x2000 and > 0x1000.
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
REF x (512/4096)
REF x (256/4096)
0
ADC Data
Word
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
0x0000
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x00,
AD0LJST = ‘1’
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0x2000.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x1000 or > 0x2000.
Figure 5.10. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended
Data
Rev. 1.4 65
C8051F040/1/2/3/4/5/6/7
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
REF x (256/2048)
REF x (-1/2048)
-REF
ADC Data
Word
0x7FF0
0x1010
0x1000
0x0FF0
0x0000
0xFFF0
0xFFE0
0x8000
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = ‘1’,
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0xFFF0.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x1000 and > 0xFFF0. (Two’s-complement
math.)
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
REF x (256/2048)
REF x (-1/2048)
-REF
ADC Data
Word
0x7FF0
0x1010
0x1000
0x0FF0
0x0000
0xFFF0
0xFFE0
0x8000
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = ‘1’,
ADC0LTH:ADC0LTL = 0xFFF0,
ADC0GTH:ADC0GTL = 0x1000.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0xFFF0 or > 0x1000. (Two’s-complement
math.)
Figure 5.11. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data
66 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Table 5.2. 12-Bit ADC0 Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 12 bits
Integral Nonlinearity — — ±1 LSB
Differential Nonlinearity Guaranteed Monotonic — — ±1 LSB
Offset Error Note 1 — 0.5±3 — LSB
Full Scale Error Differential mode; See Note 1 — 0.4±3 — LSB
Offset Temperature Coefficient — ±0.25 — ppm/°C
Dynamic Performance (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps)
Signal-to-Noise Plus Distortion 66 — — dB
Total Harmonic Distortion
Spurious-Free Dynamic Range — 80 — dB
Conversion Rate
Maximum SAR Clock Frequency — — 2.5 MHz
Conversion Time in SAR Clocks 16 — — clocks
Track/Hold Acquisition Time 1.5 — — µs
Throughput Rate — — 100 ksps
Analog Inputs
Input Voltage Range Single-ended operation 0 — VREF V
Common-mode Voltage Range Differential operation AGND — AV+ V
Input Capacitance — 10 — pF
Temperature Sensor
Nonlinearity Notes 1, 2 — ±1 — °C
Absolute Accuracy Notes 1, 2 — ±3 — °C
Gain Notes 1, 2 —
Offset Notes 1, 2 (Temp = 0 °C) —
Power Specifications
Power Supply Current (AV+ supplied to ADC)
Power Supply Rejection — ±0.3 — mV/V
Up to the 5th harmonic
Operating Mode, 100 ksps — 450 900 µA
— –75 — dB
2.86
±0.034
0.776
±0.009
— mV/°C
— V
Notes:
1. Represents one standard deviation from the mean.
2. Includes ADC offset, gain, and linearity variations.
Rev. 1.4 67
C8051F040/1/2/3/4/5/6/7
Table 5.3. High Voltage Difference Amplifier Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, V
Parameter Conditions Min Typ Max Units
Analog Inputs
Differential range peak-to-peak ——60 V
Common Mode Range (HVAIN+) – (HVAIN–) = 0 V –60 — +60 V
Analog Output
Output Voltage Range 0.1 — 2.9 V
DC Performance
Common Mode Rejection Ratio Vcm= –10 V to +10 V, R s= 0 70 72 — dB
Offset Voltage —±3— mV
Noise HVCAP floating —500—nV/rtHz
Nonlinearity G = 1 —72— dB
Dynamic Performance
Small Signal Bandwidth G = 0.05 —3— MHz
Small Signal Bandwidth G = 1 —150— kHz
Slew Rate —2—V/µS
Settling Time 0.01%, G = 0.05, 10 V step —10— µS
Input/Output Impedance
Differential (HVAIN+) input —105— kΩ
Differential (HVAIN-) input —98— kΩ
Common Mode input —51— kΩ
HVCAP —5— kΩ
Power Specification
Quiescent Current — 450 1000 µA
= 3.0 V, –40 to +85 °C unless otherwise specified.
REF
68 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
The ADC0 subsystem for the C8051F042/3/4/5/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram
in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable
under software control via the Special Function Registers shown in Figure 6.1. The voltage reference used
by ADC0 is selected as described in Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113 for
C8051F042/4/6 devices, or Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117 for
C8051F043/5/7 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low
power shutdown when this bit is logic 0.
ADC0LTLADC0LTHADC0GTLADC0GTH
10-Bit
SAR
ADC
AMP0GN0
AMP0GN1
AV+
AD0INT
AD0TM
AD0EN
ADC0CN
AD0BUSY
AD0CM1
REF
SYSCLK
AD0LJST
AD0WINT
AD0CM0
HV
Input
PORT3IC
HVDA2IC
9-to-1
AMUX
(SE or
DIFF)
AIN01IC
AIN23IC
X
AMX0AD3
AMX0SL
Port 3
I/O Pins
Analog
Input
Pins
TEMP
SENSOR
AGND Timer 2 Overflow
AMX0CF
AMX0AD2
AMX0AD1
+
-
AMX0AD0
AD0EN
AV+
AGND
AD0SC4
AD0SC0
AD0SC1
AD0SC2
AD0SC3
ADC0CF
AMP0GN2
20
10
ADC0L ADC0H
Start Conversion
Comb.
Logic
10
00
01
10
11
AD0WINT
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
6.1. Analog Multiplexer and PGA
The analog multiplexer can input analog signals to the ADC from four external analog input pins, Port 3
port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, and an internally
connected on-chip temperature sensor (temperature transfer function is shown in Figure 6.6). AMUX input
pairs can be programmed to operate in either differential or single-ended mode. This allows the user to
select the best measurement technique for each input channel, and even accommodates mode changes
"on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers associated
with the AMUX: the Channel Selection register AMX0SL (SFR Definition 6.2), the Configuration register
AMX0CF (SFR Definition 6.1), and the Port Pin Selection register AMX0PRT (SFR Definition 6.3).
Table 6.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the
AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (SFR Definition 6.5). The PGA can be software-programmed for gains of 0.5, 2, 4,
8 or 16. Gain defaults to unity on reset.
Rev. 1.4 69
C8051F040/1/2/3/4/5/6/7
6.1.1. Analog Input Configuration
The analog multiplexer routes signals from external analog input pins, Port 3 I/O pins (programmed to be
analog inputs), a High Voltage Difference Amplifier, and an on-chip temperature sensor as shown in
Figure 6.2.
AIN01IC
AIN23IC
AIN45IC
AMX0CF
X
AIN67IC
10-Bit
SAR
ADC
PAIN0EN
PAIN2EN
PAIN4EN
PAIN6EN
PAIN1EN
PAIN3EN
AMX0PRT
PAIN5EN
PAIN7EN
AIN0.0
AIN0.1
AIN0.2
AIN0.3
P3.6
P3.4
P3.2
P3.0
P3.7
P3.5
P3.3
P3.1
HVAIN +
HVAIN -
HVREF
HVCAP
(WIRED-OR)
P3EVEN
P3ODD
(WIRED-OR)
AGND
HV
AMP
+
0
-
1
2
+
-
3
9-to-1
+
6
AMUX
(SE or
-
7
DIFF)
5
4
8
TEMP SENSOR
AMX0AD0
AMX0AD1
AMX0AD2
AMX0AD3
AGND
AMX0SL
Figure 6.2. Analog Input Diagram
Analog signals may be input from four external analog input pins (AIN0.0 through AIN0.3) as differential or
single-ended measurements. Additionally, Port 3 I/O Port Pins may be configured to input analog signals.
Port 3 pins configured as analog inputs are selected using the Port Pin Selection register (AMX0PRT). Any
number of Port 3 pins may be selected simultaneously as inputs to the AMUX. Even numbered Port 3 pins
and odd numbered Port 3 pins are routed to separate AMUX inputs. (NOTE: Even port pins and odd port
pins that are simultaneously selected will be shorted together as “wired-OR”.) In this way, differential measurements may be made when using the Port 3 pins (voltage difference between selected even and odd
Port 3 pins) as shown in Figure 6.2.
The High Voltage Difference Amplifier (HVDA) will accept analog input signals and reject up to 60 volts
common-mode for differential measurement of up to the reference voltage to the ADC (0 to VREF volts).
The output of the HVDA can be selected as an input to the ADC using the AMUX as any other channel is
selected for measurement.
70 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 6.1. AMX0CF: AMUX0 Configuration
R R R R R/W R/W R/W R/W Reset Value
- - - - PORT3IC HVDA2C AIN23IC AIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
SFR Address:
SFR Page:
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bit3: PORT3IC: Port 3 even/odd Pin Input Pair Configuration Bit
0: Port 3 even and odd input channels are independent single-ended inputs
1: Port 3 even and odd input channels are (respectively) +, - differential input pair
Bit2: HVDA2C: HVDA 2’s Compliment Bit
0: HVDA output measured as an independent single-ended input
1: 2’s compliment value Result from HVDA
Bit1: AIN23IC: AIN2, AIN3 Input Pair Configuration Bit
0: AIN2 and AIN3 are independent single-ended inputs
1: AIN2, AIN3 are (respectively) +, - differential input pair
Bit0: AIN01IC: AIN0, AIN1 Input Pair Configuration Bit
0: AIN0 and AIN1 are independent single-ended inputs
1: AIN0, AIN1 are (respectively) +, - differential input pair
0xBA
0
NOTE: The ADC0 Data Word is in 2’s complement format for channels configured as differential.
SFR Definition 6.2. AMX0SL: AMUX0 Channel Select
R R R R R/W R/W R/W R/W Reset Value
- - - - AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bits3-0: AMX0AD3-0: AMX0 Address Bits
0000-1111b: ADC Inputs selected per Table 6.1.
0xBB
0
Rev. 1.4 71
C8051F040/1/2/3/4/5/6/7
Table 6.1. AMUX Selection Chart (AMX0AD3-0 and AMX0CF3-0 bits)
0000 0001 0010 0011 0100 0101 0110 0111 1xxx
AIN0.0 AIN0.1 AIN0.2 AIN0.3 HVDA AGND P3EVEN P3ODD
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1 AIN0.2 AIN0.3 P3EVEN P3ODD
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1 AIN0.2 AIN0.3 HVDA AGND
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1 AIN0.2 AIN0.3
+(AIN0.0)
-(AIN0.1)
AIN0.0 AIN0.1
+(AIN0.0)
-(AIN0.1)
AIN0.2 AIN0.3 HVDA AGND P3EVEN P3ODD
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AIN0.2 AIN0.3 P3EVEN P3ODD
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AIN0.2 AIN0.3 HVDA AGND
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AIN0.2 AIN0.3
+(AIN0.2)
-(AIN0.3)
+(AIN0.2)
-(AIN0.3)
AMX0CF Bits 3-0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AMX0AD3-0
HVDA AGND P3EVEN P3ODD
HVDA AGND P3EVEN P3ODD
P3EVEN P3ODD
P3EVEN P3ODD
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
HVDA AGND
HVDA AGND
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD)
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
+P3EVEN
-P3ODD
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
Note: “P3EVEN” denotes even numbered and “P3ODD” odd numbered Port 3 pins selected in the AMX0PRT
register.
72 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 6.3. AMX0PRT: Port 3 Pin Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PAIN7EN PAIN6EN PAIN5EN PAIN4EN PAIN3EN PAIN2EN PAIN1EN PAIN0EN 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bit7: PAIN7EN: Pin 7 Analog Input Enable Bit
0: P3.7 is not selected as an analog input to the AMUX.
1: P3.7 is selected as an analog input to the AMUX.
Bit6: PAIN6EN: Pin 6 Analog Input Enable Bit
0: P3.6 is not selected as an analog input to the AMUX.
1: P3.6 is selected as an analog input to the AMUX.
Bit5: PAIN5EN: Pin 5 Analog Input Enable Bit
0: P3.5 is not selected as an analog input to the AMUX.
1: P3.5 is selected as an analog input to the AMUX.
Bit4: PAIN4EN: Pin 4 Analog Input Enable Bit
0: P3.4 is not selected as an analog input to the AMUX.
1: P3.4 is selected as an analog input to the AMUX.
Bit3: PAIN3EN: Pin 3 Analog Input Enable Bit
0: P3.3 is not selected as an analog input to the AMUX.
1: P3.3 is enabled as an analog input to the AMUX.
Bit2: PAIN2EN: Pin 2 Analog Input Enable Bit
0: P3.2 is not selected as an analog input to the AMUX.
1: P3.2 is enabled as an analog input to the AMUX.
Bit1: PAIN1EN: Pin 1 Analog Input Enable Bit
0: P3.1 is not selected as an analog input to the AMUX.
1: P3.1 is enabled as an analog input to the AMUX.
Bit0: PAIN0EN: Pin 0 Analog Input Enable Bit
0: P3.0 is not selected as an analog input to the AMUX.
1: P3.0 is enabled as an analog input to the AMUX.
0xBA
0
NOTE: Any number of Port 3 pins may be selected simultaneously inputs to the AMUX. Odd num-
bered and even numbered pins that are selected simultaneously are shorted together as
“wired-OR”.
Rev. 1.4 73
C8051F040/1/2/3/4/5/6/7
6.2. High Voltage Difference Amplifier
The High Voltage Difference Amplifier (HVDA) can be used to measure high differential voltages up to 60 V
peak-to-peak, reject high common-mode voltages up to ±60 V, and condition the signal voltage range to be
suitable for input to ADC0. The input signal to the HVDA may be below AGND to -60 volts, and as high as
+60 volts, making the device suitable for both single and dual supply applications. The HVDA will provides
a common-mode signal for the ADC via the High Voltage Reference Input (HVREF), allowing measurement of signals outside the specified ADC input range using on-chip circuitry. The HVDA has a gain of
0.05 V/V to 14 V/V. The first stage 20:1 difference amplifier has a gain of 0.05 V/V when the output amplifier is used as a unity gain buffer. When the output amplifier is set to a gain of 280 (selected using the
HVGAIN bits in the High Voltage Control Register), the overall gain of 14 can be attained. The HVDA is
factory calibrated for a high common-mode rejection of 72 dB.
The HVDA uses four available external pins: +HVAIN, -HVAIN, HVCAP, and the aforementioned HVREF.
HVAIN+ and HVAIN- serve as the differential inputs to the HVDA. HVREF can be used to provide a common mode reference for input to ADC0. HVCAP facilitates the use of a capacitor for noise filtering in conjunction with R7 (see Figure 6.3 for R7 and other approximate resistor values). Alternatively, the HVCAP
could also be used to access amplification of the first stage of the HVDA at an external pin. (See Table 6.3
on page 90 for electrical specifications of the HVDA.)
HVCAP
100kΩ
HVAIN-
5k
Ω
5k
Ω
Vout
(To AMUX0)
HVAIN+
5k
100k
Ω
Ω
Resistor values are
HVA0CN
Gain Setting
approximate
HVREF
Figure 6.3. High Voltage Difference Amplifier Functional Diagram
V
OUT
Note: The output voltage of the HVDA is selected as an input to ADC0 via its analog multiplexer (AMUX0). HVDA
output voltages greater than the ADC0 reference voltage (Vref) or less than 0 volts (with respect to analog
ground) will result in saturation (output codes > full-scale or output codes < 0 respectively.) Allow for adequate
settle/tracking time for proper voltage measurements.
HVAIN+()HVAIN-()–[]Gain HVREF+⋅=
Equation 6.1. Calculating HVDA Output Voltage to ADC0
74 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 6.4. HVA0CN: High Voltage Difference Amplifier Control
R/W R R R R/W R/W R/W R/W Reset Value
HVDAEN - - - HVGAIN3 HVGAIN2 HVGAIN1 HVGAIN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bit7: HVDAEN: High Voltage Difference Amplifier (HVDA) Enable Bit.
0: The HVDA is disabled.
1: The HVDA is enabled.
Bits6-3: Reserved.
Bits2-0: HVGAIN3-HVGAIN0: HVDA Gain Control Bits.
HVDA Gain Control Bits set the amplification gain if the difference signal input to the HVDA
as defined in the table below:
HVGAIN3:HVGAIN0 HVDA Gain
0000 0.05
0001 0.1
0010 0.125
0011 0.2
0100 0.25
0101 0.4
0110 0.5
0111 0.8
1000 1.0
1001 1.6
1010 2.0
1011 3.2
1100 4.0
1101 6.2
1110 7.6
1111 14
0xD6
0
Rev. 1.4 75
C8051F040/1/2/3/4/5/6/7
6.3. ADC Modes of Operation
ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the system clock divided by the value held in the ADC0SC bits of register ADC0CF.
6.3.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by the following:
• Writing a ‘1’ to the AD0BUSY bit of ADC0CN;
• A Timer 3 overflow (i.e. timed continuous conversions);
• A rising edge detected on the external ADC convert start signal, CNVSTR0;
• A Timer 2 overflow (i.e. timed continuous conversions).
The AD0BUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete.
The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the AD0INT interrupt flag
(ADC0CN.5). Converted data is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L.
Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in
Figure 6.7) depending on the programmed state of the AD0LJST bit in the ADC0CN register.
When initiating conversions by writing a ‘1’ to AD0BUSY, the AD0INT bit should be polled to determine
when a conversion has completed (ADC0 interrupts may also be used). The recommended polling procedure is shown below.
Step 1. Write a ‘0’ to AD0INT;
Step 2. Write a ‘1’ to AD0BUSY;
Step 3. Poll AD0INT for ‘1’;
Step 4. Process ADC0 data.
6.3.2. Tracking Modes
According to Table 6.2, each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode.
In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the
AD0TM bit is logic 1, ADC0 operates in low-power tracking mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks after the start-of-conversion signal. When the CNVSTR0 signal
is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low; conversion begins on the rising edge of CNVSTR0 (see Figure 6.4). Tracking can also be disabled when the
entire chip is in low power standby or sleep modes. Low-power tracking mode is also useful when AMUX
or PGA settings are frequently changed, to ensure that settling time requirements are met (see Section
“6.3.3. Settling Time Requirements” on page 78).
76 Rev. 1.4
(AD0STM[1:0]=10)
CNVSTR
SAR Clocks
C8051F040/1/2/3/4/5/6/7
A. ADC Timing for External Trigger Source
12345678910111213141516
ADC0TM=1
ADC0TM=0
Timer 2, Timer 3 Overflow;
Write '1' to AD0BUSY
(AD0STM[1:0]=00, 01, 11)
SAR Clocks
ADC0TM=1
SAR Clocks
ADC0TM=0
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing
Low Power
or Convert
Track Or Convert Convert Track
Track Convert Low Power Mode
B. ADC Timing for Internal Trigger Sources
1234567891011121314151617 18 19
Low Power
or Convert
Track or
Convert
Track Convert Low Power Mode
12345678910111213141516
Convert Track
Rev. 1.4 77
C8051F040/1/2/3/4/5/6/7
6.3.3. Settling Time Requirements
A minimum tracking time is required before an accurate conversion can be performed. This tracking time is
determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Figure 6.5 shows the equivalent ADC0 input circuits
for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required settling time for a given settling accuracy (SA) may be approximated by
Equation 6.2. When measuring the Temperature Sensor output, R
power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most
applications, these three SAR clocks will meet the tracking requirements. See Table 6.2 for absolute minimum settling/tracking time requirements.
n
2
⎛⎞
t
-------
×ln=
⎝⎠
SA
R
TOTALCSAMPLE
reduces to R
TOTAL
. Note that in low-
MUX
Equation 6.2. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
is the sum of the ADC0 MUX resistance and any external source resistance.
TOTAL
AIN0.x
AIN0.y
Differential Mode
MUX Select
R
= 5k
MUX
RC
= R
MUX
* C
R
MUX
SAMP LE
= 5k
Input
MUX Select
C
SAMPLE
C
SAMPLE
= 10pF
= 10pF
Single-Ended Mode
MUX Select
AIN0.x
RC
Input
= R
MUX
R
* C
MUX
= 5k
SAMPL E
C
SAMPLE
= 10pF
Figure 6.5. ADC0 Equivalent Input Circuits
78 Rev. 1.4
(Volts)
1.000
0.900
0.800
0.700
0.600
0.500
C8051F040/1/2/3/4/5/6/7
V
= 0.00286(TEMPC) + 0.776
TEMP
for PGA Gain = 1
0-50 50 100
Figure 6.6. Temperature Sensor Transfer Function
(Celsius)
Rev. 1.4 79
C8051F040/1/2/3/4/5/6/7
SFR Definition 6.5. ADC0CF: ADC0 Configuration
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC4 A D 0 S C3 AD 0 S C 2 A D 0 SC1 AD 0 S C 0 AMP0GN2 AM P 0 G N1 AMP0G N 0 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in AD0SC4-0, and CLK
SAR clock. See Table 6.2 on page 89 for SAR clock setting requirements.
SYSCLK
AD0SC
*Note: AD0SC is the rounded-up result.
Bits2-0: AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA)
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
-----------------------
CLK
SAR0
1–≥ CLK
* or
SAR0
SAR0
SYSCLK
----------------------------
=
AD0SC 1+
SFR Address:
SFR Page:
refers to the desired ADC0
0xBC
0
80 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 6.6. ADC0CN: ADC0 Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT AD0LJST 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: AD0TM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by AD0CM1-0 bits
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC0 has not completed a data conversion since the last time this flag was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0STM1-0 = 00b
Bit3-2: AD0CM1-0: ADC0 Start of Conversion Mode Select.
If AD0TM = 0:
00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR0.
11: ADC0 conversion initiated on overflow of Timer 2.
If AD0TM = 1:
00: Tracking starts with the write of ‘1’ to AD0BUSY and lasts for 3 SAR clocks, followed by
conversion.
01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks, followed by conversion.
10: ADC0 tracks only when CNVSTR0 input is logic low; conversion starts on rising
CNVSTR0 edge.
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks, followed by conversion.
Bit1: AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bit0: AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bit
Addressable
0xE8
0
Rev. 1.4 81
C8051F040/1/2/3/4/5/6/7
SFR Definition 6.7. ADC0H: ADC0 Data Word MSB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7-2 are the sign extension of Bit 1. Bits 0 and 1 are the upper 2 bits of
the 10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7-0 are the most-significant bits of the 10-bit ADC0 Data Word.
SFR Definition 6.8. ADC0L: ADC0 Data Word LSB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
00000000
SFR
Address:
0xBF
0
00000000
SFR
Address:
0xBE
0
Bits7-0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 6 and 7 are the lower 2 bits of the 10-bit ADC0 Data Word. Bits 5-0
82 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
10-bit ADC Data Word appears in the ADC Data Word Registers as follows:
ADC0H[1:0]:ADC0L[7:0], if ADLJST = 0
(ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading,
otherwise = 000000b).
ADC0H[7:0]:ADC0L[7:6], if ADLJST = 1
(ADC0L[5:0] = 000000b).
Example: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0CF = 0x00, AMX0SL = 0x00)
AIN0-AGND (Volts)
VREF * (1023/1024) 0x03FF 0xFFC0
VREF / 2 0x0200 0x8000
VREF * (511/1024) 0x01FF 0x7FC0
0 0x0000 0x0000
Example: ADC Data Word Conversion Map, AIN0-AIN1 Differential Input Pair
(AMX0CF = 0x01, AMX0SL = 0x00)
AIN0-AGND (Volts)
VREF * (511/512) 0x01FF 0x7FC0
VREF / 2 0x0100 0x4000
VREF * (1/512) 0x0001 0x0040
0 0x0000 0x0000
-VREF * (1/512) 0xFFFF (-1) 0xFFC0
-VREF / 2 0xFF00 (-256) 0xC000
-VREF 0xFE00 (-512) 0x8000
ADC0H:ADC0L
(ADLJST = 0)
ADC0H:ADC0L
(ADLJST = 0)
ADC0H:ADC0L
(ADLJST = 1)
ADC0H:ADC0L
(ADLJST = 1)
ADLJST = 0:
Code Vin
Gain
---------------
× 2n×=
VREF
; ‘n’ = 10 for Single-Ended; ‘n’=9 for Differential.
Figure 6.7. ADC0 Data Word Example
Rev. 1.4 83
C8051F040/1/2/3/4/5/6/7
6.4. ADC0 Programmable Window Detector
The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed
limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an
interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response
times. The window detector interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. The
high and low bytes of the reference words are loaded into the ADC0 Greater-Than and ADC0 Less-Than
registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Reference comparisons are shown starting
on page 85. Notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: High byte of ADC0 Greater-Than Data Word.
0xC5
0
SFR Definition 6.10. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xC4
0
Bits7-0: Low byte of ADC0 Greater-Than Data Word.
SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: High byte of ADC0 Less-Than Data Word.
0xC7
0
11111111
84 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: Low byte of ADC0 Less-Than Data Word.
0xC6
0
Input Voltage
(AD0 - AGND)
REF x (1023/1024)
REF x (512/1024)
REF x (256/1024)
0
ADC Data
Word
0x03FF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0200,
ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x0200 and
> 0x0100.
Given:
Input Voltage
(AD0 - AGND)
REF x (1023/1024)
REF x (512/1024)
REF x (256/1024)
0
ADC Data
Word
0x03FF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0x0200.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is > 0x0200 or
< 0x0100.
Figure 6.8. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended
Data
Rev. 1.4 85
C8051F040/1/2/3/4/5/6/7
Input Voltage
(AD0 - AD 1)
REF x (511/512)
REF x (256/512)
REF x (-1/512)
-REF
ADC Data
Word
0x01FF
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
0xFE00
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0xFFFF.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x0100 and
> 0xFFFF. (In two’s-complement math,
0xFFFF = -1.)
Given:
Input Voltage
(AD0 - AD 1)
REF x (511/512)
REF x (256/512)
REF x (-1/512)
-REF
ADC Data
Word
0x01FF
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
0xFE00
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0,
ADC0LTH:ADC0LTL = 0xFFFF,
ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0xFFFF or
> 0x0100. (In two’s-complement math,
0xFFFF = -1.)
Figure 6.9. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential
Data
86 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Input Voltage
(AD0 - AG ND)
REF x (1023/1024)
REF x (512/1024)
REF x (256/1024)
0
ADC Data
Word
0xFFC0
0x8040
0x8000
0x7FC0
0x4040
0x4000
0x3FC0
0x0000
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x8000,
ADC0GTH:ADC0GTL = 0x4000.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x8000 and
> 0x4000.
Given:
Input Voltage
(AD0 - AG ND)
REF x (1023/1024)
REF x (512/1024)
REF x (256/1024)
0
ADC Data
Word
0xFFC0
0x8040
0x8000
0x7FC0
0x4040
0x4000
0x3FC0
0x0000
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x4000,
ADC0GTH:ADC0GTL = 0x8000.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x4000 or
> 0x8000.
Figure 6.10. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended
Data
Rev. 1.4 87
C8051F040/1/2/3/4/5/6/7
Input Voltage
(AD0 - AD1)
REF x (511/512)
REF x (256/512)
REF x (-1/512)
-REF
ADC Data
Word
0x7FC0
0x4040
0x4000
0x3FC0
0x0000
0xFFC0
0xFF80
0x8000
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x4000,
ADC0GTH:ADC0GTL = 0xFFC0.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0x4000 and
> 0xFFC0. (Two’s-complement math.)
Given:
Input Voltage
(AD0 - AD 1)
REF x (511/512)
REF x (256/512)
REF x (-1/512)
-REF
ADC Data
Word
0x7FC0
0x4040
0x4000
0x3FC0
0x0000
0xFFC0
0xFF80
0x8000
AD0WINT=1
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1,
ADC0LTH:ADC0LTL = 0xFFC0,
ADC0GTH:ADC0GTL = 0x4000.
An ADC End of Conversion will cause an ADC
Window Compare Interrupt (ADWINT=1) if the
resulting ADC Data Word is < 0xFFC0 or
> 0x4000. (Two’s-complement math.)
Figure 6.11. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data
88 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Table 6.2. 10-Bit ADC0 Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, V
Parameter Conditions Min Ty p Max Units
DC Accuracy
Resolution 10 bits
Integral Nonlinearity ——±1 LSB
Differential Nonlinearity Guaranteed Monotonic ——±1 LSB
Offset Error —0.2±1— LSB
Full Scale Error Differential mode —0.1±1— LSB
Offset Temperature Coefficient — ±0.25 — ppm/°C
Dynamic Performance (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps)
Signal-to-Noise Plus Distortion 59 — — dB
Total Harmonic Distortion
Spurious-Free Dynamic Range —80— dB
Conversion Rate
SAR Clock Frequency ——2.5MHz
Conversion Time in SAR Clocks 16 — — clocks
Track/Hold Acquisition Time 1.5 — — µs
Throughput Rate ——100ksps
Analog Inputs
Input Voltage Range Single-ended operation 0 — VREF V
Common-mode Voltage Range Differential operation AGND — AV+ V
Input Capacitance —10— pF
Temperature Sensor
Nonlinearity
Absolute Accuracy
1,2
Gain
Offset
1,2
1,2
1,2
Power Specifications
Power Supply Current
(AV+ supplied to ADC)
Power Supply Rejection —±0.3— mV/V
= 2.40 V (REFBE = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
REF
Up to the 5th harmonic
—–70— dB
—±1— °C
—±3— °C
—2.86
—mV/°C
±0.034
Tem p = 0 °C
Operating Mode, 100 ksps
—0.776
±0.009
—450900 µA
—V
Notes:
1. Represents one standard deviation from the mean.
2. Includes ADC offset, gain, and linearity variations.
Rev. 1.4 89
C8051F040/1/2/3/4/5/6/7
Table 6.3. High Voltage Difference Amplifier Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, V
Parameter Conditions Min Typ Max Units
Analog Inputs
Differential range peak-to-peak ——60 V
Common Mode Range (HVAIN+) – (HVAIN–) = 0 V –60 — +60 V
Analog Output
Output Voltage Range 0.1 — 2.9 V
DC Performance
Common Mode Rejection Ratio Vcm = –10 V to +10 V, Rs = 0 70 72 — dB
Offset Voltage —±3— mV
Noise HVCAP floating —500—nV/rtHz
Nonlinearity G = 1 —72— dB
Dynamic Performance
Small Signal Bandwidth G = 0.05 —3—MHz
Small Signal Bandwidth G = 1 —150— kHz
Slew Rate —2—V/µS
Settling Time 0.01%, G = 0.05, 10 V step —10— µS
Input/Output Impedance
Differential (HVAIN+) input —105— kΩ
Differential (HVAIN–) input —98— kΩ
Common Mode input —51— kΩ
HVCAP —5—kΩ
Power Specification
Quiescent Current — 450 1000 µA
= 3.0 V, –40 to +85 °C unless otherwise specified.
REF
90 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)
The ADC2 subsystem for the C8051F040/1/2/3 consists of an 8-channel, configurable analog multiplexer,
a programmable gain amplifier, and a 500 ksps, 8-bit successive-approximation-register ADC with integrated track-and-hold (see block diagram in Figure 7.1). The AMUX2, PGA2, and Data Conversion Modes,
are all configurable under software control via the Special Function Registers shown in Figure 7.1. The
ADC2 subsystem (8-bit ADC, track-and-hold and PGA) is enabled only when the AD2EN bit in the ADC2
Control register (ADC2CN) is set to logic 1. The ADC2 subsystem is in low power shutdown when this bit is
logic 0. The voltage reference used by ADC2 is selected as described in Section “9. Voltage Reference
(C8051F040/2/4/6)” on page 113 for C8051F040/2 devices, or Section “10. Voltage Reference
(C8051F041/3/5/7)” on page 117 for C8051F041/3 devices.
AIN67IC
AMX2CF
AIN45IC
+
-
+
-
+
-
+
-
8-to-1
AMUX
AIN01IC
AIN23IC
X
AMX2AD1
AMX2AD2
AMX2SL ADC2CN
AIN2.0 (P1.0)
AIN2.1 (P1.1)
AIN2.2 (P1.2)
AIN2.3 (P1.3)
AIN2.4 (P1.4)
AIN2.5 (P1.5)
AIN2.6 (P1.6)
AIN2.7 (P1.7)
Figure 7.1. ADC2 Functional Block Diagram
7.1. Analog Multiplexer and PGA
AD2EN
AV+
AV+
ADC2LTHADC2GTH
REF
SYSCLK
16
Dig
Comp
ADC Window
Interrupt
8-Bit
+
SAR
-
AD2SC1
AD2SC0
ADC
AMP2GN0
AMP2GN1
AD2TM
AD2EN
AD2BUSY
AD2INT
AGND
AMX2AD0
AD2SC3
AD2SC4
ADC2CF
AD2SC2
Start Conversion
AD2CM0
AD2CM1
AD2CM2
8
ADC2
000
Write to AD2BUSY
Timer 3 Overflow
001
010
CNVSTR
Timer 2 Overflow
011
Write to AD0BUSY
1xx
(synchronized with
ADC0)
Eight ADC2 channels are available for measurement, as selected by the AMX2SL register (see SFR Definition 7.2). The PGA amplifies the ADC2 output signal by an amount determined by the states of the
AMP2GN2-0 bits in the ADC2 Configuration register, ADC2CF (SFR Definition 7.1). The PGA can be software-programmed for gains of 0.5, 1, 2, or 4. Gain defaults to 0.5 on reset.
Important Note: AIN2 pins also function as Port 1 I/O pins, and must be configured as analog inputs when
used as ADC2 inputs. To configure an AIN2 pin for analog input, set to ‘0’ the corresponding bit in register
P1MDIN. Port 1 pins selected as analog inputs are skipped by the Digital I/O Crossbar. See Section
“17.1.5. Configuring Port 1, 2, and 3 Pins as Analog Inputs” on page 209 for more information on con-
figuring the AIN2 pins.
Rev. 1.4 91
C8051F040/1/2/3/4/5/6/7
7.2. ADC2 Modes of Operation
ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock) is a
divided version of the system clock, determined by the AD2SC bits in the ADC2CF register (system clock
divided by (AD2SC + 1) for 0 ≤ AD2SC ≤ 31). The maximum ADC2 conversion clock is 7.5 MHz.
7.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC2 Start
of Conversion Mode bits (AD2STM2-AD2STM0) in ADC2CN. Conversions may be initiated by the following:
•Writing a ‘1’ to the AD2BUSY bit of ADC2CN;
•A Timer 3 overflow (i.e. timed continuous conversions);
•A rising edge detected on the external ADC convert start signal, CNVSTR2 or CNVSTR0 (see
important note below);
•A Timer 2 overflow (i.e. timed continuous conversions);
•Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC2 and ADC0 with a
single software command).
An important note about external convert start (CNVSTR0 and CNVSTR2): If CNVSTR2 is enabled in
the digital crossbar (Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on
page 206), CNVSTR2 will be the external convert start signal for ADC2. However, if only CNVSTR0 is
enabled in the digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may serve as the start of
conversion for both ADC0 and ADC2. This permits synchronous sampling of both ADC0 and ADC2.
During conversion, the AD2BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The
falling edge of AD2BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC2CN. Converted data is available in the ADC2 data word, ADC2.
When a conversion is initiated by writing a ‘1’ to AD2BUSY, it is recommended to poll AD2INT to determine
when the conversion is complete. The recommended procedure is:
Step 1. Write a ‘0’ to AD2INT;
Step 2. Write a ‘1’ to AD2BUSY;
Step 3. Poll AD2INT for ‘1’;
Step 4. Process ADC2 data.
7.2.2. Tracking Modes
According to Table 7.2, each ADC2 conversion must be preceded by a minimum tracking time for the converted result to be accurate. The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode.
In its default state, the ADC2 input is continuously tracked, except when a conversion is in progress. When
the AD2TM bit is logic 1, ADC2 operates in low-power tracking mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 (or
CNVSTR0, See Section 7.2.1 above) signal is used to initiate conversions in low-power tracking mode,
ADC2 tracks only when CNVSTR2 is low; conversion begins on the rising edge of CNVSTR2 (see
Figure 7.2). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or
sleep modes. Low-power Track-and-Hold mode is also useful when AMUX or PGA settings are frequently
changed, due to the settling time requirements described in Section “7.2.3. Settling Time Require-
ments” on page 94.
92 Rev. 1.4
CNVSTR2/CNVSTR0
(AD2CM[2:0]=010)
SAR2 Clocks
C8051F040/1/2/3/4/5/6/7
A. ADC Timing for External Trigger Source
123456789
AD2TM=1
Write '1' to AD2BUSY,
Timer 3 Overflow,
Timer 2 Overflow,
Write '1' to AD0BUSY
(AD2CM[2:0]=000, 001, 011, 0xx)
SAR2 Clocks
AD2TM=1
SAR2 Clocks
AD2TM=0
Figure 7.2. ADC2 Track and Conversion Example Timing
Low Power
or Convert
Track or Convert Convert TrackAD2TM=0
Track Convert Low Power Mode
B. ADC Timing for Internal Trigger Source
123456789101112
Low Power
or Convert
Track or
Convert
Track Convert Low Power Mode
123456789
Convert Track
Rev. 1.4 93
C8051F040/1/2/3/4/5/6/7
7.2.3. Settling Time Requirements
A minimum tracking time is required before an accurate conversion can be performed. This tracking time is
determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit.
The required ADC2 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1.
Note: An absolute minimum settling time of 0.8 µs required after any MUX selection. Note that in lowpower tracking mode, three SAR2 clocks are used for tracking at the start of every conversion. For most
applications, these three SAR2 clocks will meet the tracking requirements.
n
2
⎛⎞
t
Equation 7.1. ADC2 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (8).
is the sum of the ADC2 MUX resistance and any external source resistance.
TOTAL
-------
×ln=
⎝⎠
SA
R
TOTALCSAMPLE
MUX Select
AIN2.x
R
= 5k
MUX
C
= 10pF
SAMPLE
RC
= R
MUX
* C
SAMP LE
Input
Figure 7.3. ADC2 Equivalent Input Circuit
94 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 7.1. AMX2CF: AMUX2 Configuration
RRRRR/WR/WR/WR/WReset Value
- - - - PIN67IC PIN45IC PIN23IC PIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bit3: PIN67IC: P1.6, P1.7 Input Pair Configuration Bit
0: P1.6 and P1.7 are independent single-ended inputs
1: P1.6, P1.7 are (respectively) +, - differential input pair
Bit2: PIN45IC: P1.4, P1.5 Input Pair Configuration Bit
0: P1.4 and P1.5 are independent single-ended inputs
1: P1.4, P1.5 are (respectively) +, - differential input pair
Bit1: PIN23IC: P1.2, P1.3 Input Pair Configuration Bit
0: P1.2 and P1.3 are independent single-ended inputs
1: P1.2, P1.3 are (respectively) +, - differential input pair
Bit0: PIN01IC: P1.0, P1.1 Input Pair Configuration Bit
0: P1.0 and P1.1 are independent single-ended inputs
1: P1.0, P1.1 are (respectively) +, - differential input pair
0xBA
2
NOTE: The ADC2 Data Word is in 2’s complement format for channels configured as differential.
SFR Definition 7.2. AMX2SL: AMUX2 Channel Select
RRRRRR/WR/WR/WReset Value
- - - - - AMX2AD2 AMX2AD1 AMX2AD0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-3: UNUSED. Read = 00000b; Write = don’t care
Bits2-0: AMX2AD2-0: AMX2 Address Bits
000-111b: ADC Inputs selected per Table 7.1.
0xBB
2
Rev. 1.4 95
C8051F040/1/2/3/4/5/6/7
Table 7.1. AMUX Selection Chart (AMX2AD2-0 and AMX2CF3-0 bits)
000 001 010 011 100 101 110 111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
AMX2CF Bits 3-0
1010
1011
1100
1101
1110
1111
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
+(P1.0)
-(P1.1)
P1.0 P1.1
+(P1.0)
-(P1.1)
P1.0 P1.1 P1.2 P1.3
+(P1.0)
-(P1.1)
P1.0 P1.1
+(P1.0)
-(P1.1)
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5
+(P1.0)
-(P1.1)
P1.0 P1.1
+(P1.0)
-(P1.1)
P1.0 P1.1 P1.2 P1.3
+(P1.0)
-(P1.1)
P1.0 P1.1
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
-(P1.0)
+(P1.1)
-(P1.0)
+(P1.1)
-(P1.0)
+(P1.1)
-(P1.0)
+(P1.1)
-(P1.0)
+(P1.1)
-(P1.0)
+(P1.1)
-(P1.0)
+(P1.1)
P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
+(P1.2)
-(P1.3)
+(P1.2)
-(P1.3)
P1.2 P1.3
+(P1.2)
-(P1.3)
+(P1.2)
-(P1.3)
P1.2 P1.3 P1.4 P1.5
+(P1.2)
-(P1.3)
+(P1.2)
-(P1.3)
P1.2 P1.3
+(P1.2)
-(P1.3)
+(P1.2)
-(P1.3)
AMX2AD2-0
-(P1.2)
+(P1.3)
-(P1.2)
+(P1.3)
-(P1.2)
+(P1.3)
-(P1.2)
+(P1.3)
-(P1.2)
+(P1.3)
-(P1.2)
+(P1.3)
-(P1.2)
+(P1.3)
-(P1.2)
+(P1.3)
P1.4 P1.5 P1.6 P1.7
P1.4 P1.5 P1.6 P1.7
+(P1.4)
-(P1.5)
+(P1.4)
-(P1.5)
+(P1.4)
-(P1.5)
+(P1.4)
-(P1.5)
P1.4 P1.5
P1.4 P1.5
+(P1.4)
-(P1.5)
+(P1.4)
-(P1.5)
+(P1.4)
-(P1.5)
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
-(P1.4)
+(P1.5)
-(P1.4)
+(P1.5)
-(P1.4)
+(P1.5)
-(P1.4)
+(P1.5)
-(P1.4)
+(P1.5)
-(P1.4)
+(P1.5)
-(P1.4)
+(P1.5)
P1.6 P1.7
P1.6 P1.7
P1.6 P1.7
P1.6 P1.7
+(P1.6)
-(P1.7)
+(P1.6)
-(P1.7)
+(P1.6)
-(P1.7)
+(P1.6)
-(P1.7)
+(P1.6)
-(P1.7)
+(P1.6)
-(P1.7)
+(P1.6)
-(P1.7)
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
-(P1.6)
+(P1.7)
-(P1.6)
+(P1.7)
-(P1.6)
+(P1.7)
-(P1.6)
+(P1.7)
-(P1.6)
+(P1.7)
-(P1.6)
+(P1.7)
-(P1.6)
+(P1.7)
96 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 7.3. ADC2CF: ADC2 Configuration
R/W R/W R/W R/W R/W R R/W R/W Reset Value
AD2SC4 A D 2 S C3 AD 2 S C 2 A D 2 SC1 AD 2 S C 0 - AMP 2 G N 1 AMP2 G N 0 1111100 0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where
AD2SC refers to the 5-bit value held in AD2SC4-0. SAR conversion clock requirements are
given in Table 7.2.
SYSCLK
AD2SC
*Note: AD2SC is the rounded-up result.
Bit2: UNUSED. Read = 0b. Write = don’t care.
Bits1-0: AMP2GN1-0: ADC2 Internal Amplifier Gain (PGA)
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
-----------------------
CLK
SAR2
* or
1–≥ CLK
SAR2
SYSCLK
---------------------------AD2SC 1+
SFR Address:
SFR Page:
–=
0xBC
2
Rev. 1.4 97
C8051F040/1/2/3/4/5/6/7
SFR Definition 7.4. ADC2CN: ADC2 Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD2EN AD2TM AD2INT AD2BUSY AD2CM2 AD2CM1 AD2CM0 AD2WINT 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7: AD2EN: ADC2 Enable Bit.
0: ADC2 Disabled. ADC2 is in low-power shutdown.
1: ADC2 Enabled. ADC2 is active and ready for data conversions.
Bit6: AD2TM: ADC2 Track Mode Bit.
0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion is in
process.
1: Low-power Track Mode: Tracking defined by AD2STM2-0 bits (see below).
Bit5: AD2INT: ADC2 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC2 has not completed a data conversion since the last time this flag was cleared.
1: ADC2 has completed a data conversion.
Bit4: AD2BUSY: ADC2 Busy Bit.
Read:
0: ADC2 Conversion is complete or a conversion is not currently in progress. AD2INT is set to
logic 1 on the falling edge of AD2BUSY.
1: ADC2 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC2 Conversion if AD2STM2-0 = 000b
Bits3-1: AD2CM2-0: ADC2 Start of Conversion Mode Select.
AD2TM = 0:
000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
001: ADC2 conversion initiated on overflow of Timer 3.
010: ADC2 conversion initiated on rising edge of external CNVSTR2 or CNVSTR0.
011: ADC2 conversion initiated on overflow of Timer 2.
1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 softwarecommanded conversions).
AD2TM = 1:
000: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR2 clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.
010: ADC2 tracks only when CNVSTR2 (or CNVSTR0, See Section 7.2.1) input is logic low; conversion starts on rising CNVSTR2 edge.
011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.
1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by conversion.
Bit0: AD2WINT: ADC2 Window Compare Interrupt Flag.
0: ADC2 window comparison data match has not occurred since this flag was last cleared.
1: ADC2 window comparison data match has occurred. This flag must be cleared in software.
An important note about external convert start (CNVSTR0 and CNVSTR2)
the digital crossbar (
on page 206
CNVSTR0 is enabled in the digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may
serve as the start of conversion for both ADC0 and ADC2.
Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder”
), CNVSTR2 will be the external convert start signal for ADC2. However, if only
SFR Address:
SFR Page:
: If CNVSTR2 is enabled in
0xE8
2
98 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 7.5. ADC2: ADC2 Data Word
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits7-0: ADC2 Data Word.
8-bit ADC Data Word appears in the ADC2 Data Word Register as follows:
Example: ADC2 Data Word Conversion Map, AIN1.0 Input
(AMX2SL = 0x00)
AIN1.0-AGND
(Volts)
VREF * (255/256) 0xFF
VREF / 2 0x80
VREF * (127/256) 0x7F
0 0x00
SFR Address:
SFR Page:
ADC2
0xBE
2
Code Vin
Gain
---------------
× 256×=
VREF
Figure 7.4. ADC2 Data Word Example
Rev. 1.4 99
C8051F040/1/2/3/4/5/6/7
7.3. ADC2 Programmable Window Detector
The ADC2 Programmable Window Detector continuously compares the ADC2 output to user-programmed
limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an
interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response
times. The window detector interrupt flag (AD2WINT in ADC2CN) can also be used in polled mode. The
reference words are loaded into the ADC2 Greater-Than and ADC2 Less-Than registers (ADC2GT and
ADC2LT). Notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the ADC2GT and ADC2LT registers.
SFR Definition 7.6. ADC2GT: ADC2 Greater-Than Data
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: High byte of ADC2 Greater-Than Data Word.
0xC4
2
SFR Definition 7.7. ADC2LT: ADC2 Less-Than Data
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Bits7-0: Low byte of ADC2 Greater-Than Data Word.
7.3.1. Window Detector In Single-Ended Mode
Figure 7.5 shows two example window comparisons for Single-ended mode, with ADC2LT = 0x20 and
ADC2GT = 0x10. In Single-ended mode, the codes vary from 0 to VREF*(255/256) and are represented as
8-bit unsigned integers. In the left example, an AD2WINT interrupt will be generated if the ADC2 conversion word (ADC2) is within the range defined by ADC2GT and ADC2LT (if 0x10 < ADC2 < 0x20). In the
right example, and AD2WINT interrupt will be generated if ADC2 is outside of the range defined by
ADC2GT and ADC2LT (if ADC2 < 0x10 or ADC2 > 0x20).
0xC6
2
100 Rev. 1.4
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