Silicon Laboratories C8051F040, C8051F041, C8051F042, C8051F043, C8051F044 User Manual
...
C8051F040/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 10 or 12-Bit SAR ADC
• 12-bit (C8051F040/1) or
10-bit (C8051F042/3/4/5/6/7) resolution
• ± 1 LSB INL, guaranteed no missing codes
• Programmable throughput up to 100 ksps
• 13 External Inputs; single-ended or differential
• SW programmable high voltage difference amplifier
• Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
• Data-dependent windowed interrupt generator
• Built-in temperature sensor
- 8-bit SAR ADC (C8051F040/1/2/3 only)
• Programmable throughput up to 500 ksps
• 8 External Inputs, single-ended or differential
• Programmable amplifier gain: 4, 2, 1, 0.5
- Two 12-bit DACs (C8051F040/1/2/3 only)
• Can synchronize outputs to timers for jitter-free waveform generation
- Three Analog Comparators
• Programmable hysteresis/response time
- Voltage Reference
- Precision V
Monitor/Brown-Out Detector
DD
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full- speed, non-
intrusive in-circuit/in-system debugging
- Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- IEEE1149.1 compliant boundary scan
- Complete development kit
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- 20 vectored interrupt sources
Memory
- 4352 bytes internal data RAM (4 k + 256)
- 64 kB (C8051F040/1/2/3/4/5)
or 32 kB (C8051F046/7) Flash; in-system programmable in 512-byte sectors
- External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
Digital Peripherals
- 8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant
- 4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant
- Bosch Controller Area Network (CAN 2.0B), hard-
ware SMBus™ (I2C™ Compatible), SPI™, and
two
UART serial ports available concurrently
- Programmable 16-bit counter/timer array with
capture/compare modules
6
- 5 general purpose 16-bit counter/timers
- Dedicated watch-dog timer; bi-directional reset pin
Clock Sources
- Internal calibrated programmable oscillator: 3 to
MHz
24.5
- External oscillator: crystal, RC, C, or clock
- Real-time clock mode using Timer 2, 3, 4, or PCA
Supply Voltage: 2.7 to 3.6 V
- Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
- Temperature Range: –40 to +85 °C
ANALOG PERIPHERALS
TEMP
AMUX
PGA
AMUX
12-Bit
DAC
12-Bit
DAC
C8051F041/2/3
ONLY
SENSOR
PGA
VREF
500 ksps
12/10-bit
100 ksps
ADC
8-bit
ADC
+
-
VOLTAGE COMPARATORS
HV
DIFF
AMP
+
+
-
-
DIGITAL I/O
CAN
2.0B
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
CROSSBAR
External Memory Interface
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
100 pin64 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25 MIPS)
20
INTERRUPTS
64 kB/32 kB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
CLOCK
CIRCUIT
JTAG
SANITY
CONTROL
Rev. 1.4 11/04 Copyright © 2004 by Silicon Laboratories C8051F04x
C8051F040/1/2/3/4/5/6/7
NOTES:
2 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 25
1.1.1. Fully 8051 Compatible.............................................................................. 25
1.1.2. Improved Throughput............................................................................... 25
1.1.3. Additional Features .................................................................................. 26
1.2. On-Chip Memory............................................................................................... 27
1.3. JTAG Debug and Boundary Scan..................................................................... 28
1.4. Programmable Digital I/O and Crossbar ........................................................... 29
1.5. Programmable Counter Array ........................................................................... 30
1.6. Controller Area Network.................................................................................... 31
1.7. Serial Ports ....................................................................................................... 31
1.8. 12/10-Bit Analog to Digital Converter................................................................ 32
1.9. 8-Bit Analog to Digital Converter (C8051F040/1/2/3 Only) ............................... 33
1.10.Comparators and DACs ................................................................................... 34
2. Absolute Maximum Ratings .................................................................................. 35
3. Global DC Electrical Characteristic ...................................................................... 36
4. Pinout and Package Definitions............................................................................ 37
5. 12-Bit ADC (ADC0, C8051F040/1 Only)................................................................. 47
5.1. Analog Multiplexer and PGA............................................................................. 47
5.1.1. Analog Input Configuration....................................................................... 48
5.2. High Voltage Difference Amplifier ..................................................................... 52
5.3. ADC Modes of Operation.................................................................................. 54
5.3.1. Starting a Conversion............................................................................... 54
5.3.2. Tracking Modes........................................................................................ 54
5.3.3. Settling Time Requirements..................................................................... 56
5.4. ADC0 Programmable Window Detector ........................................................... 62
6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)..................................................... 69
6.1. Analog Multiplexer and PGA............................................................................. 69
6.1.1. Analog Input Configuration....................................................................... 70
6.2. High Voltage Difference Amplifier ..................................................................... 74
6.3. ADC Modes of Operation.................................................................................. 76
6.3.1. Starting a Conversion............................................................................... 76
6.3.2. Tracking Modes........................................................................................ 76
6.3.3. Settling Time Requirements..................................................................... 78
6.4. ADC0 Programmable Window Detector ........................................................... 84
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)............................................................. 91
7.1. Analog Multiplexer and PGA............................................................................. 91
7.2. ADC2 Modes of Operation................................................................................ 92
7.2.1. Starting a Conversion............................................................................... 92
7.2.2. Tracking Modes........................................................................................ 92
7.2.3. Settling Time Requirements..................................................................... 94
7.3. ADC2 Programmable Window Detector ......................................................... 100
7.3.1. Window Detector In Single-Ended Mode ............................................... 100
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7.3.2. Window Detector In Differential Mode.................................................... 102
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) ......................................... 105
8.1. DAC Output Scheduling.................................................................................. 106
8.1.1. Update Output On-Demand ................................................................... 106
8.1.2. Update Output Based on Timer Overflow .............................................. 106
8.2. DAC Output Scaling/Justification .................................................................... 106
9. Voltage Reference (C8051F040/2/4/6) ................................................................. 113
10.Voltage Reference (C8051F041/3/5/7) ................................................................. 117
11.Comparators ......................................................................................................... 121
11.1.Comparator Inputs.......................................................................................... 123
12.CIP-51 Microcontroller ......................................................................................... 127
12.1.Instruction Set................................................................................................. 129
12.1.1.Instruction and CPU Timing ................................................................... 129
12.1.2.MOVX Instruction and Program Memory ............................................... 129
12.2.Memory Organization ..................................................................................... 133
12.2.1.Program Memory ................................................................................... 133
12.2.2.Data Memory.......................................................................................... 134
12.2.3.General Purpose Registers.................................................................... 134
12.2.4.Bit Addressable Locations...................................................................... 134
12.2.5.Stack ..................................................................................................... 134
12.2.6.Special Function Registers .................................................................... 135
12.2.7.Register Descriptions ............................................................................. 151
12.3.Interrupt Handler............................................................................................. 154
12.3.1.MCU Interrupt Sources and Vectors ...................................................... 154
12.3.2.External Interrupts.................................................................................. 155
12.3.3.Interrupt Priorities................................................................................... 157
12.3.4.Interrupt Latency .................................................................................... 157
12.3.5.Interrupt Register Descriptions............................................................... 157
12.4.Power Management Modes............................................................................ 164
12.4.1.Idle Mode ............................................................................................... 164
12.4.2.Stop Mode.............................................................................................. 165
13.Reset Sources....................................................................................................... 167
13.1.Power-on Reset.............................................................................................. 168
13.2.Power-Fail Reset ............................................................................................ 168
13.3.External Reset................................................................................................ 168
13.4.Missing Clock Detector Reset ........................................................................ 169
13.5.Comparator0 Reset ........................................................................................ 169
13.6.External CNVSTR0 Pin Reset ........................................................................ 169
13.7.Watchdog Timer Reset................................................................................... 169
13.7.1.Enable/Reset WDT ................................................................................ 170
13.7.2.Disable WDT .......................................................................................... 170
13.7.3.Disable WDT Lockout ............................................................................ 170
13.7.4.Setting WDT Interval .............................................................................. 170
14.Oscillators ............................................................................................................. 175
14.1.Programmable Internal Oscillator ................................................................... 175
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14.2.External Oscillator Drive Circuit...................................................................... 177
14.3.System Clock Selection.................................................................................. 177
14.4.External Crystal Example ............................................................................... 179
14.5.External RC Example ..................................................................................... 180
14.6.External Capacitor Example ........................................................................... 180
15.Flash Memory ....................................................................................................... 181
15.1.Programming The Flash Memory ................................................................... 181
15.2.Non-volatile Data Storage .............................................................................. 182
15.3.Security Options ............................................................................................. 182
15.3.1.Summary of Flash Security Options....................................................... 184
16.External Data Memory Interface and On-Chip XRAM........................................ 189
16.1.Accessing XRAM............................................................................................ 189
16.1.1.16-Bit MOVX Example ........................................................................... 189
16.1.2.8-Bit MOVX Example ............................................................................. 189
16.2.Configuring the External Memory Interface .................................................... 190
16.3.Port Selection and Configuration.................................................................... 190
16.4.Multiplexed and Non-multiplexed Selection.................................................... 193
16.4.1.Multiplexed Configuration....................................................................... 193
16.4.2.Non-multiplexed Configuration............................................................... 194
16.5.Memory Mode Selection................................................................................. 195
16.5.1.Internal XRAM Only ............................................................................... 195
16.5.2.Split Mode without Bank Select.............................................................. 195
16.5.3.Split Mode with Bank Select................................................................... 196
16.5.4.External Only.......................................................................................... 196
16.6.Timing .......................................................................................................... 196
16.6.1.Non-multiplexed Mode ........................................................................... 198
16.6.2.Multiplexed Mode ................................................................................... 201
17.Port Input/Output.................................................................................................. 205
17.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 206
17.1.1.Crossbar Pin Assignment and Allocation ............................................... 207
17.1.2.Configuring the Output Modes of the Port Pins...................................... 208
17.1.3.Configuring Port Pins as Digital Inputs................................................... 209
17.1.4.Weak Pullups ......................................................................................... 209
17.1.5.Configuring Port 1, 2, and 3 Pins as Analog Inputs ............................... 209
17.1.6.External Memory Interface Pin Assignments ......................................... 210
17.1.7.Crossbar Pin Assignment Example........................................................ 212
17.2.Ports 4 through 7............................................................................................ 222
17.2.1.Configuring Ports which are not Pinned Out.......................................... 223
17.2.2.Configuring the Output Modes of the Port Pins...................................... 223
17.2.3.Configuring Port Pins as Digital Inputs................................................... 223
17.2.4.Weak Pull-ups........................................................................................ 223
17.2.5.External Memory Interface ..................................................................... 223
18.Controller Area Network (CAN0) ......................................................................... 229
18.1.Bosch CAN Controller Operation.................................................................... 230
18.1.1.CAN Controller Timing ........................................................................... 231
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18.1.2.Example Timing Calculation for 1 Mbit/Sec Communication ................. 231
18.2.CAN Registers................................................................................................ 233
18.2.1.CAN Controller Protocol Registers......................................................... 233
18.2.2.Message Object Interface Registers...................................................... 233
18.2.3.Message Handler Registers................................................................... 234
18.2.4.CIP-51 MCU Special Function Registers ............................................... 234
18.2.5.Using CAN0ADR, CAN0DATH, and CANDATL to
Access CAN Registers .......................................................................... 234
18.2.6.CAN0ADR Autoincrement Feature ........................................................ 234
19.System Management BUS / I2C BUS (SMBUS0)................................................ 241
19.1.Supporting Documents................................................................................... 242
19.2.SMBus Protocol.............................................................................................. 243
19.2.1.Arbitration............................................................................................... 243
19.2.2.Clock Low Extension.............................................................................. 244
19.2.3.SCL Low Timeout................................................................................... 244
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 244
19.3.SMBus Transfer Modes.................................................................................. 244
19.3.1.Master Transmitter Mode ....................................................................... 244
19.3.2.Master Receiver Mode........................................................................... 245
19.3.3.Slave Transmitter Mode ......................................................................... 245
19.3.4.Slave Receiver Mode............................................................................. 246
19.4.SMBus Special Function Registers ................................................................ 247
19.4.1.Control Register ..................................................................................... 247
19.4.2.Clock Rate Register ............................................................................... 250
19.4.3.Data Register ......................................................................................... 251
19.4.4.Address Register.................................................................................... 251
19.4.5.Status Register....................................................................................... 252
20.Enhanced Serial Peripheral Interface (SPI0) ...................................................... 257
20.1.Signal Descriptions......................................................................................... 258
20.1.1.Master Out, Slave In (MOSI).................................................................. 258
20.1.2.Master In, Slave Out (MISO).................................................................. 258
20.1.3.Serial Clock (SCK) ................................................................................. 258
20.1.4.Slave Select (NSS) ................................................................................ 258
20.2.SPI0 Master Mode Operation ......................................................................... 259
20.3.SPI0 Slave Mode Operation ........................................................................... 261
20.4.SPI0 Interrupt Sources ................................................................................... 261
20.5.Serial Clock Timing......................................................................................... 262
20.6.SPI Special Function Registers...................................................................... 263
21.UART0.................................................................................................................... 267
21.1.UART0 Operational Modes ............................................................................ 268
21.1.1.Mode 0: Synchronous Mode .................................................................. 268
21.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 269
21.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 271
21.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 272
21.2.Multiprocessor Communications .................................................................... 272
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21.3.Configuration of a Masked Address ............................................................... 273
21.4.Broadcast Addressing .................................................................................... 273
21.5.Frame and Transmission Error Detection....................................................... 274
22.UART1.................................................................................................................... 279
22.1.Enhanced Baud Rate Generation................................................................... 280
22.2.Operational Modes ......................................................................................... 281
22.2.1.8-Bit UART............................................................................................. 281
22.2.2.9-Bit UART............................................................................................. 282
22.3.Multiprocessor Communications .................................................................... 283
23.Timers.................................................................................................................... 289
23.1.Timer 0 and Timer 1 ....................................................................................... 289
23.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 289
23.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 290
23.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 291
23.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 292
23.2.Timer 2, Timer 3, and Timer 4 ........................................................................ 297
23.2.1.Configuring Timer 2, 3, and 4 to Count Down........................................ 297
23.2.2.Capture Mode ........................................................................................ 298
23.2.3.Auto-Reload Mode ................................................................................. 299
23.2.4.Toggle Output Mode .............................................................................. 300
24.Programmable Counter Array ............................................................................. 305
24.1.PCA Counter/Timer ........................................................................................ 306
24.2.Capture/Compare Modules ............................................................................ 307
24.2.1.Edge-triggered Capture Mode................................................................ 308
24.2.2.Software Timer (Compare) Mode........................................................... 309
24.2.3.High Speed Output Mode....................................................................... 310
24.2.4.Frequency Output Mode ........................................................................ 311
24.2.5.8-Bit Pulse Width Modulator Mode......................................................... 312
24.2.6.16-Bit Pulse Width Modulator Mode....................................................... 313
24.3.Register Descriptions for PCA0...................................................................... 314
25.JTAG (IEEE 1149.1) .............................................................................................. 319
25.1.Boundary Scan............................................................................................... 320
25.1.1.EXTEST Instruction................................................................................ 321
25.1.2.SAMPLE Instruction............................................................................... 321
25.1.3.BYPASS Instruction ............................................................................... 321
25.1.4.IDCODE Instruction................................................................................ 321
25.2.Flash Programming Commands..................................................................... 323
25.3.Debug Support ............................................................................................... 326
Document Change List............................................................................................. 327
Contact Information.................................................................................................. 328
Rev. 1.4 7
C8051F040/1/2/3/4/5/6/7
NOTES:
8 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
List of Figures
1. System Overview
Figure 1.1. C8051F040/2 Block Diagram ................................................................. 21
Figure 1.2. C8051F041/3 Block Diagram ................................................................. 22
Figure 1.3. C8051F044/6 Block Diagram ................................................................. 23
Figure 1.4. C8051F045/7 Block Diagram ................................................................. 24
Figure 1.5. Comparison of Peak MCU Execution Speeds ....................................... 25
Figure 1.6. On-Board Clock and Reset .................................................................... 26
Figure 1.7. On-Chip Memory Map ............................................................................ 27
Figure 1.8. Development/In-System Debug Diagram............................................... 28
Figure 1.9. Digital Crossbar Diagram ....................................................................... 29
Figure 1.10. PCA Block Diagram.............................................................................. 30
Figure 1.11. CAN Controller Diagram....................................................................... 31
Figure 1.12. 10/12-Bit ADC Block Diagram .............................................................. 32
Figure 1.13. 8-Bit ADC Diagram............................................................................... 33
Figure 1.14. Comparator and DAC Diagram ............................................................ 34
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristic
4. Pinout and Package Definitions
Figure 4.1. TQFP-100 Pinout Diagram..................................................................... 42
Figure 4.2. TQFP-100 Package Drawing ................................................................. 43
Figure 4.3. TQFP-64 Pinout Diagram....................................................................... 44
Figure 4.4. TQFP-64 Package Drawing ................................................................... 45
5. 12-Bit ADC (ADC0, C8051F040/1 Only)
Figure 5.1. 12-Bit ADC0 Functional Block Diagram ................................................. 47
Figure 5.2. Analog Input Diagram ............................................................................ 48
Figure 5.3. High Voltage Difference Amplifier Functional Diagram .......................... 52
Figure 5.4. 12-Bit ADC Track and Conversion Example Timing .............................. 55
Figure 5.5. ADC0 Equivalent Input Circuits .............................................................. 56
Figure 5.6. Temperature Sensor Transfer Function ................................................. 57
Figure 5.7. ADC0 Data Word Example .................................................................... 61
Figure 5.8. 12-Bit ADC0 Window Interrupt Example:
Right Justified Single-Ended Data ........................................................ 63
Figure 5.9. 12-Bit ADC0 Window Interrupt Example:
Right Justified Differential Data............................................................. 64
Figure 5.10. 12-Bit ADC0 Window Interrupt Example:
Left Justified Single-Ended Data........................................................... 65
Figure 5.11. 12-Bit ADC0 Window Interrupt Example:
Left Justified Differential Data ............................................................... 66
6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
Figure 6.1. 10-Bit ADC0 Functional Block Diagram ................................................. 69
Figure 6.2. Analog Input Diagram ............................................................................ 70
Figure 6.3. High Voltage Difference Amplifier Functional Diagram .......................... 74
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing .............................. 77
Rev. 1.4 9
C8051F040/1/2/3/4/5/6/7
Figure 6.5. ADC0 Equivalent Input Circuits .............................................................. 78
Figure 6.6. Temperature Sensor Transfer Function ................................................. 79
Figure 6.7. ADC0 Data Word Example .................................................................... 83
Figure 6.8. 10-Bit ADC0 Window Interrupt Example:
Right Justified Single-Ended Data ........................................................ 85
Figure 6.9. 10-Bit ADC0 Window Interrupt Example:
Right Justified Differential Data............................................................. 86
Figure 6.10. 10-Bit ADC0 Window Interrupt Example:
Left Justified Single-Ended Data......................................................... 87
Figure 6.11. 10-Bit ADC0 Window Interrupt Example:
Left Justified Differential Data.............................................................. 88
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)
Figure 7.1. ADC2 Functional Block Diagram............................................................ 91
Figure 7.2. ADC2 Track and Conversion Example Timing....................................... 93
Figure 7.3. ADC2 Equivalent Input Circuit................................................................ 94
Figure 7.4. ADC2 Data Word Example .................................................................... 99
Figure 7.5. ADC Window Compare Examples, Single-Ended Mode...................... 101
Figure 7.6. ADC Window Compare Examples, Differential Mode .......................... 102
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only)
Figure 8.1. DAC Functional Block Diagram............................................................ 105
9. Voltage Reference (C8051F040/2/4/6)
Figure 9.1. Voltage Reference Functional Block Diagram ..................................... 113
10.Voltage Reference (C8051F041/3/5/7)
Figure 10.1. Voltage Reference Functional Block Diagram.................................... 117
11.Comparators
Figure 11.1. Comparator Functional Block Diagram .............................................. 121
Figure 11.2. Comparator Hysteresis Plot ............................................................... 122
12.CIP-51 Microcontroller
Figure 12.1. CIP-51 Block Diagram........................................................................ 127
Figure 12.2. Memory Map ...................................................................................... 133
Figure 12.3. SFR Page Stack................................................................................. 136
Figure 12.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 137
Figure 12.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs . 138
Figure 12.6. SFR Page Stack Upon PCA Interrupt Occurring
During an ADC2 ISR ........................................................................... 139
Figure 12.7. SFR Page Stack Upon Return From PCA Interrupt ........................... 140
Figure 12.8. SFR Page Stack Upon Return From ADC2 Window Interrupt ........... 141
13.Reset Sources
Figure 13.1. Reset Sources.................................................................................... 167
Figure 13.2. Reset Timing ...................................................................................... 168
14.Oscillators
Figure 14.1. Oscillator Diagram.............................................................................. 175
Figure 14.2. 32.768 kHz External Crystal Example................................................ 179
15.Flash Memory
Figure 15.1. Flash Program Memory Map and Security Bytes............................... 183
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C8051F040/1/2/3/4/5/6/7
16.External Data Memory Interface and On-Chip XRAM
Figure 16.1. Multiplexed Configuration Example.................................................... 193
Figure 16.2. Non-multiplexed Configuration Example ............................................ 194
Figure 16.3. EMIF Operating Modes ...................................................................... 195
Figure 16.4. Non-multiplexed 16-bit MOVX Timing ................................................ 198
Figure 16.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 199
Figure 16.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 200
Figure 16.7. Multiplexed 16-bit MOVX Timing........................................................ 201
Figure 16.8. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 202
Figure 16.9. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 203
17.Port Input/Output
Figure 17.1. Port I/O Cell Block Diagram ............................................................... 205
Figure 17.2. Port I/O Functional Block Diagram ..................................................... 206
Figure 17.3. Priority Crossbar Decode Table ......................................................... 207
Figure 17.4. Priority Crossbar Decode Table ......................................................... 210
Figure 17.5. Priority Crossbar Decode Table ......................................................... 211
Figure 17.6. Crossbar Example:............................................................................. 213
18.Controller Area Network (CAN0)
Figure 18.1. Typical CAN Bus Configuration.......................................................... 229
Figure 18.2. CAN Controller Diagram..................................................................... 230
Figure 18.3. Four Segments of a CAN Bit Time ..................................................... 231
Figure 18.4. CAN0DATH: CAN Data Access Register High Byte .......................... 236
19.System Management BUS / I2C BUS (SMBUS0)
Figure 19.1. SMBus0 Block Diagram ..................................................................... 241
Figure 19.2. Typical SMBus Configuration ............................................................. 242
Figure 19.3. SMBus Transaction ............................................................................ 243
Figure 19.4. Typical Master Transmitter Sequence................................................ 244
Figure 19.5. Typical Master Receiver Sequence.................................................... 245
Figure 19.6. Typical Slave Transmitter Sequence.................................................. 245
Figure 19.7. Typical Slave Receiver Sequence...................................................... 246
20.Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram ............................................................................. 257
Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 260
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 260
Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 260
Figure 20.5. Data/Clock Timing Diagram ............................................................... 262
21.UART0
Figure 21.1. UART0 Block Diagram ....................................................................... 267
Figure 21.2. UART0 Mode 0 Timing Diagram ........................................................ 268
Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 269
Figure 21.4. UART0 Mode 1 Timing Diagram ........................................................ 269
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 271
Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 272
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................... 274
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22.UART1
Figure 22.1. UART1 Block Diagram ....................................................................... 279
Figure 22.2. UART1 Baud Rate Logic .................................................................... 280
Figure 22.3. UART Interconnect Diagram .............................................................. 281
Figure 22.4. 8-Bit UART Timing Diagram............................................................... 281
Figure 22.5. 9-Bit UART Timing Diagram............................................................... 282
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 283
23.Timers
Figure 23.1. T0 Mode 0 Block Diagram.................................................................. 290
Figure 23.2. T0 Mode 2 Block Diagram.................................................................. 291
Figure 23.3. T0 Mode 3 Block Diagram.................................................................. 292
Figure 23.4. Tn Capture Mode Block Diagram ....................................................... 298
Figure 23.5. Tn Auto-reload Mode Block Diagram ................................................. 299
24.Programmable Counter Array
Figure 24.1. PCA Block Diagram............................................................................ 305
Figure 24.2. PCA Counter/Timer Block Diagram.................................................... 306
Figure 24.3. PCA Interrupt Block Diagram ............................................................. 307
Figure 24.4. PCA Capture Mode Diagram.............................................................. 308
Figure 24.5. PCA Software Timer Mode Diagram .................................................. 309
Figure 24.6. PCA High Speed Output Mode Diagram............................................ 310
Figure 24.7. PCA Frequency Output Mode ............................................................ 311
Figure 24.8. PCA 8-Bit PWM Mode Diagram ......................................................... 312
Figure 24.9. PCA 16-Bit PWM Mode...................................................................... 313
25.JTAG (IEEE 1149.1)
12 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 20
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 35
3. Global DC Electrical Characteristic
Table 3.1. Global DC Electrical Characteristics ....................................................... 36
4. Pinout and Package Definitions
Table 4.1. Pin Definitions ......................................................................................... 37
5. 12-Bit ADC (ADC0, C8051F040/1 Only)
Table 5.1. AMUX Selection Chart (AMX0AD3–0 and AMX0CF3–0 bits) ................ 50
Table 5.2. 12-Bit ADC0 Electrical Characteristics ................................................... 67
Table 5.3. High Voltage Difference Amplifier Electrical Characteristics .................. 68
6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
Table 6.1. AMUX Selection Chart (AMX0AD3-0 and AMX0CF3-0 bits) .................. 72
Table 6.2. 10-Bit ADC0 Electrical Characteristics ................................................... 89
Table 6.3. High Voltage Difference Amplifier Electrical Characteristics .................. 90
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)
Table 7.1. AMUX Selection Chart (AMX2AD2-0 and AMX2CF3-0 bits) .................. 96
Table 7.2. ADC2 Electrical Characteristics ............................................................ 103
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only)
Table 8.1. DAC Electrical Characteristics .............................................................. 111
9. Voltage Reference (C8051F040/2/4/6)
Table 9.1. Voltage Reference Electrical Characteristics ....................................... 115
10.Voltage Reference (C8051F041/3/5/7)
Table 10.1. Voltage Reference Electrical Characteristics ..................................... 119
11.Comparators
Table 11.1. Comparator Electrical Characteristics ................................................ 126
12.CIP-51 Microcontroller
Table 12.1. CIP-51 Instruction Set Summary ........................................................ 129
Table 12.2. Special Function Register (SFR) Memory Map .................................. 144
Table 12.3. Special Function Registers ................................................................. 147
Table 12.4. Interrupt Summary .............................................................................. 155
13.Reset Sources
Table 13.1. Reset Electrical Characteristics .......................................................... 173
14.Oscillators
Table 14.1. Internal Oscillator Electrical Characteristics ....................................... 177
15.Flash Memory
Table 15.1. Flash Electrical Characteristics .......................................................... 182
16.External Data Memory Interface and On-Chip XRAM
Table 16.1. AC Parameters for External Memory Interface ................................... 204
17.Port Input/Output
Table 17.1. Port I/O DC Electrical Characteristics ................................................. 205
Rev. 1.4 13
C8051F040/1/2/3/4/5/6/7
18.Controller Area Network (CAN0)
Table 18.1. Background System Information ........................................................ 231
Table 18.2. CAN Register Index and Reset Values .............................................. 235
19.System Management BUS / I2C BUS (SMBUS0)
Table 19.1. SMB0STA Status Codes and States .................................................. 254
20.Enhanced Serial Peripheral Interface (SPI0)
21.UART0
Table 21.1. UART0 Modes .................................................................................... 268
Table 21.2. Oscillator Frequencies for Standard Baud Rates ............................... 275
22.UART1
Table 22.1. Timer Settings for Standard Baud Rates Using
the Internal 24.5 MHz Oscillator ......................................................... 286
Table 22.2. Timer Settings for Standard Baud Rates Using
an External 25.0 MHz Oscillator ......................................................... 286
Table 22.3. Timer Settings for Standard Baud Rates Using
an External 22.1184 MHz Oscillator ................................................... 287
Table 22.4. Timer Settings for Standard Baud Rates Using
an External 18.432 MHz Oscillator ..................................................... 287
Table 22.5. Timer Settings for Standard Baud Rates Using
an External 11.0592 MHz Oscillator ................................................... 288
Table 22.6. Timer Settings for Standard Baud Rates Using
an External 3.6864 MHz Oscillator ..................................................... 288
23.Timers
24.Programmable Counter Array
Table 24.1. PCA Timebase Input Options ............................................................. 306
Table 24.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 307
25.JTAG (IEEE 1149.1)
Table 25.1. Boundary Data Register Bit Definitions .............................................. 320
14 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
List of Registers
SFR Definition 5.1. AMX0CF: AMUX0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.2. AMX0SL: AMUX0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.3. AMX0PRT: Port 3 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 5.4. HVA0CN: High Voltage Difference Amplifier Control . . . . . . . . . . . 53
SFR Definition 5.5. ADC0CF: ADC0 Configuration Register . . . . . . . . . . . . . . . . . . . . 58
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SFR Definition 5.7. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 5.8. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 5.9. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 62
SFR Definition 5.10. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . 62
SFR Definition 5.11. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . 62
SFR Definition 5.12. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 63
SFR Definition 6.1. AMX0CF: AMUX0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 6.2. AMX0SL: AMUX0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 6.3. AMX0PRT: Port 3 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 6.4. HVA0CN: High Voltage Difference Amplifier Control . . . . . . . . . . . 75
SFR Definition 6.5. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SFR Definition 6.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 6.7. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 6.8. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 84
SFR Definition 6.10. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . 84
SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . 84
SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 85
SFR Definition 7.1. AMX2CF: AMUX2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 7.2. AMX2SL: AMUX2 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 7.3. ADC2CF: ADC2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SFR Definition 7.4. ADC2CN: ADC2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 7.5. ADC2: ADC2 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 7.6. ADC2GT: ADC2 Greater-Than Data . . . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 7.7. ADC2LT: ADC2 Less-Than Data . . . . . . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 8.1. DAC0H: DAC0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 8.2. DAC0L: DAC0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 8.3. DAC0CN: DAC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 8.4. DAC1H: DAC1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.5. DAC1L: DAC1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.6. DAC1CN: DAC1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 9.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 10.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SFR Definition 11.1. CPTnCN: Comparator 0, 1, and 2 Control . . . . . . . . . . . . . . . . . 124
SFR Definition 11.2. CPTnMD: Comparator Mode Selection . . . . . . . . . . . . . . . . . . . 125
SFR Definition 12.1. SFR Page Control Register: SFRPGCN . . . . . . . . . . . . . . . . . . 142
SFR Definition 12.2. SFR Page Register: SFRPAGE . . . . . . . . . . . . . . . . . . . . . . . . . 142
Rev. 1.4 15
C8051F040/1/2/3/4/5/6/7
SFR Definition 12.3. SFR Next Register: SFRNEXT . . . . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 12.4. SFR Last Register: SFRLAST . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 12.5. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 12.6. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 12.7. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 12.8. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 12.9. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 12.10. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 12.11. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 12.12. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 12.13. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . 160
SFR Definition 12.14. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . 161
SFR Definition 12.15. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . 162
SFR Definition 12.16. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . 163
SFR Definition 12.18. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
SFR Definition 13.1. WDTCN: Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . 171
SFR Definition 13.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 14.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 176
SFR Definition 14.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 176
SFR Definition 14.3. CLKSEL: Oscillator Clock Selection . . . . . . . . . . . . . . . . . . . . . 177
SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 178
SFR Definition 15.1. FLACL: Flash Access Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
SFR Definition 15.2. FLSCL: Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . 186
SFR Definition 15.3. PSCTL: Program Store Read/Write Control . . . . . . . . . . . . . . . 187
SFR Definition 16.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 191
SFR Definition 16.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 192
SFR Definition 16.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 197
SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 214
SFR Definition 17.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 215
SFR Definition 17.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 17.4. XBR3: Port I/O Crossbar Register 3 . . . . . . . . . . . . . . . . . . . . . 217
SFR Definition 17.5. P0: Port0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
SFR Definition 17.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 218
SFR Definition 17.7. P1: Port1 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SFR Definition 17.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SFR Definition 17.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 219
SFR Definition 17.10. P2: Port2 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SFR Definition 17.11. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SFR Definition 17.12. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 17.13. P3: Port3 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 17.14. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
SFR Definition 17.15. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 222
SFR Definition 17.16. P4: Port4 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 17.17. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 17.18. P5: Port5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
SFR Definition 17.19. P5MDOUT: Port5 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 225
SFR Definition 17.20. P6: Port6 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 17.21. P6MDOUT: Port6 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 17.22. P7: Port7 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SFR Definition 17.23. P7MDOUT: Port7 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 227
SFR Definition 18.1. CAN0DATL: CAN Data Access Register Low Byte . . . . . . . . . . 237
SFR Definition 18.2. CAN0ADR: CAN Address Index . . . . . . . . . . . . . . . . . . . . . . . . 237
SFR Definition 18.3. CAN0CN: CAN Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 18.4. CAN0TST: CAN Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 18.5. CAN0STA: CAN Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SFR Definition 19.1. SMB0CN: SMBus0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
SFR Definition 19.2. SMB0CR: SMBus0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 19.3. SMB0DAT: SMBus0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
SFR Definition 19.4. SMB0ADR: SMBus0 Address . . . . . . . . . . . . . . . . . . . . . . . . . . 252
SFR Definition 19.5. SMB0STA: SMBus0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 263
SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
SFR Definition 21.1. SCON0: UART0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
SFR Definition 21.2. SSTA0: UART0 Status and Clock Selection . . . . . . . . . . . . . . . 277
SFR Definition 21.3. SBUF0: UART0 Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SFR Definition 21.4. SADDR0: UART0 Slave Address . . . . . . . . . . . . . . . . . . . . . . . 278
SFR Definition 21.5. SADEN0: UART0 Slave Address Enable . . . . . . . . . . . . . . . . . 278
SFR Definition 22.1. SCON1: Serial Port 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 284
SFR Definition 22.2. SBUF1: Serial (UART1) Port Data Buffer . . . . . . . . . . . . . . . . . 285
SFR Definition 23.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
SFR Definition 23.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
SFR Definition 23.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
SFR Definition 23.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
SFR Definition 23.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 23.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 23.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 23.8. TMRnCN: Timer n Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
SFR Definition 23.9. TMRnCF: Timer n Configuration . . . . . . . . . . . . . . . . . . . . . . . . 302
SFR Definition 23.10. RCAPnL: Timer n Capture Register Low Byte . . . . . . . . . . . . . 303
SFR Definition 23.11. RCAPnH: Timer n Capture Register High Byte . . . . . . . . . . . . 303
SFR Definition 23.12. TMRnL: Timer n Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
SFR Definition 23.13. TMRnH Timer n High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
SFR Definition 24.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
SFR Definition 24.2. PCA0MD: PCA0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
SFR Definition 24.3. PCA0CPMn: PCA0 Capture/Compare Mode . . . . . . . . . . . . . . 316
SFR Definition 24.4. PCA0L: PCA0 Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . 317
SFR Definition 24.5. PCA0H: PCA0 Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 317
SFR Definition 24.6. PCA0CPLn: PCA0 Capture Module Low Byte . . . . . . . . . . . . . . 318
Rev. 1.4 17
C8051F040/1/2/3/4/5/6/7
SFR Definition 24.7. PCA0CPHn: PCA0 Capture Module High Byte . . . . . . . . . . . . . 318
JTAG Register Definition 25.1. IR: JTAG Instruction Register . . . . . . . . . . . . . . . . . . 319
JTAG Register Definition 25.2. DEVICEID: JTAG Device ID Register . . . . . . . . . . . . 322
JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control Register . . . . . . . . 324
JTAG Register Definition 25.4. FLASHDAT: JTAG Flash Data . . . . . . . . . . . . . . . . . 325
JTAG Register Definition 25.5. FLASHADR: JTAG Flash Address . . . . . . . . . . . . . . 325
18 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1. System Overview
The C8051F04x family of devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital
I/O pins (C8051F040/2/4/6) or 32 digital I/O pins (C8051F041/3/5/7), and an integrated CAN 2.0B controller. Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.
• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)
• Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier
mask.
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 12-bit (C8051F040/1) or 10-bit (C8051F042/3/4/5/6/7) 100 ksps 8-channel ADC with PGA and
analog multiplexer
• High Voltage Difference Amplifier input to the 12/10-bit ADC (60 V Peak-to-Peak) with programmable
gain.
• True 8-bit 500 ksps 8-channel ADC with PGA and analog multiplexer (C8051F040/1/2/3)
• Two 12-bit DACs with programmable update scheduling (C8051F040/1/2/3)
•64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) of in-system programmable Flash memory
• 4352 (4096 + 256) bytes of on-chip RAM
• External Data Memory Interface with 64 kB address space
• SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with six capture/compare modules
• On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor
With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F04x family of devices are truly
stand-alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and con-
figured by user firmware. The Flash memory can be reprogrammed even in-circuit, providing non-volatile
data storage, and also allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit programming and debugging using the production MCU installed in the final application. This debug system
supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single
stepping, Run, and Halt commands. All analog and digital peripherals are fully functional while debugging
using JTAG.
Each MCU is specified for 2.7 V to 3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5 V. The C8051F040/2/4/6 are available in a 100-pin TQFP and the C8051F041/3/5/7 are available in a 64-pin TQFP.
Rev. 1.4 19
C8051F040/1/2/3/4/5/6/7
Table 1.1. Product Selection Guide
C and SPI
2
MIPS (Peak)
Flash Memory
RAM
External Memory Interface
SMBus/I
CAN
UARTS
C8051F040 25 64 kB 4352
3 3 3
2 5
Timers (16-bit)
3
Programmable Counter Array
Digital Port I/O’s
12-bit 100ksps ADC
10-bit 100ksps ADC
8-bit 500ksps ADC Inputs
High Voltage Diff Amp
Voltage Reference
Temperature Sensor
DAC Resolution (bits)
DAC Outputs
64
3
- 8
3 3 3
Analog Comparators
12 2 3 100TQFP
Package
C8051F041 25 64 kB 4352
C8051F042 25 64 kB 4352
C8051F043 25 64 kB 4352
C8051F044 25 64 kB 4352
C8051F045 25 64 kB 4352
C8051F046 25 32 kB 4352
C8051F047 25 32 kB 4352
3 3 3
3 3 3
3 3 3
3 3 3
3 3 3
3 3 3
3 3 3
2 5
2 5
2 5
2 5
2 5
2 5
2 5
3
3
3
3
3
3
3
32
64 -
32 -
64 -
32 -
64 -
32 -
3
- 8
3
8
3
8
3 3 3 3
3 3 3 3
3 3 3 3
3 3 3 3
3 3 3
3 3 3
3 3 3
12 2 3 64TQFP
12 2 3 100TQFP
12 2 3 64TQFP
3 100TQFP
3 64TQFP
3 100TQFP
3 64TQFP
20 Rev. 1.4
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AV+
AGND
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREFD
DAC1
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
Prog
Gain
Boundary Scan
Debug HW
WDT
Internal
Oscillator
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(12 or 10-
Bit)
A
M
U
X
8
SFR Bus
0
5
Memories
1
64 kB
Flash
C
o
r
e
External Memory Data
8:2
32x136
CANRAM
256 byte
RAM
4 kB
RAM
Bus
C8051F040/1/2/3/4/5/6/7
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
ADC
500 ksps
(8-Bit)
CP0
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
M
Prog
8:1
Gain
U
X
P2.6
+
P2.7
-
+
-
P2.2
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
VREF2
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A51
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Figure 1.1. C8051F040/2 Block Diagram
Rev. 1.4 21
C8051F040/1/2/3/4/5/6/7
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
DAC1
DAC0
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
Prog
Boundary Scan
Debug HW
WDT
Internal
Oscillator
Gain
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(12 or 10-
Bit)
A
M
U
X
8
0
SFR Bus
5
1
C
o
Memories
32x136
CANRAM
r
256 byte
e
External Memory Data
8:2
64 kB
Flash
RAM
4 kB
RAM
Bus
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
ADC
500 ksps
(8-Bit)
VREFA
CP0
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
M
Prog
8:1
Gain
U
X
P2.6
+
P2.7
-
+
-
P2.2
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
Figure 1.2. C8051F041/3 Block Diagram
22 Rev. 1.4
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AV+
AGND
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
Prog
Gain
Boundary Scan
Debug HW
WDT
Internal
Oscillator
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(10-Bit)
A
M
U
X
8
0
SFR Bus
5
1
C
o
e
8:2
Memories
64/32 kB
Flash
32x136
CANRAM
r
256 byte
RAM
4 kB
RAM
External Memory Data
Bus
C8051F040/1/2/3/4/5/6/7
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
CP0
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
P2.6
+
P2.7
-
+
-
P2.2
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A51
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Figure 1.3. C8051F044/6 Block Diagram
Rev. 1.4 23
C8051F040/1/2/3/4/5/6/7
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
Digital Power
Analog Power
JTAG
Logic
V
DD
Monitor
External
Oscillator
Circuit
A
M
U
X
HVAMP
VREF
Prog
Gain
Boundary Scan
Debug HW
WDT
Internal
Oscillator
TEMP
SENSOR
Reset
System
Clock
ADC
100 ksps
(10-Bit)
A
M
U
X
8
0
SFR Bus
5
1
C
o
Memories
64/32 kB
32x136
CANRAM
r
256 byte
e
External Memory Data
8:2
Flash
RAM
4 kB
RAM
Bus
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
Bus Control
Address [15:0]
Data [7:0]
C
R
O
S
S
B
A
R
CP0
+
CP1
+
CP2
-
Port 4 <from crossbar>
Ctrl Latch
P5 Latch
Addr [15:8]
P6 Latch
Addr [7:0]
P7 Latch
Data Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
P2.6
+
P2.7
-
P2.2
-
P2.3
P2.4
P2.5
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
CANTX
CANRX
Figure 1.4. C8051F045/7 Block Diagram
24 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F04x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers
can be used to develop software. The core has all the peripherals included with a standard 8052, including
five 16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space, and up to 8 byte-wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5
shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system
clocks.
25
20
15
MIPS
10
5
Silicon Labs
CIP-51
(25 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Philips
80C51
(33 MHz clk)
ADuC812
8051
(16 MHz clk)
Figure 1.5. Comparison of Peak MCU Execution Speeds
Rev. 1.4 25
C8051F040/1/2/3/4/5/6/7
1.1.3. Additional Features
The C8051F04x MCU family includes several key enhancements to the CIP-51 core and peripherals to
improve overall performance and ease of use in end applications.
The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt
driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board V
monitor, a Watchdog Timer, a missing
DD
clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input
pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the
internally generated POR to be output on the /RST pin. Each reset source except for the V
Reset Input pin may be disabled by the user in software; the V
monitor is enabled/disabled via the
DD
monitor and
DD
MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during
MCU initialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after
any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed.
V
DD
(Port I/O)
CP0+
CP0-
Crossbar
CNVSTR
(CNVSTR
reset
enable)
Comparator0
+
-
(CP0
reset
enable)
Missing
Clock
Detector
(one-
shot)
EN
WDT
EN
Supply
Monitor
+
-
PRE
Supply
Reset
Timeout
(wired-OR)
Reset
Funnel
RST
WDT
Enable
Enable
CIP-51
Core
Extended Interrupt
Handler
XTAL1
XTAL2
Internal
Clock
Generator
OSC
System
Clock
Clock Select
MCD
Microcontroller
Figure 1.6. On-Board Clock and Reset
26 Rev. 1.4
WDT
Strobe
Software Reset
System Reset
C8051F040/1/2/3/4/5/6/7
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The CIP-51 SFR
address space contains up to 256 SFR Pages. In this way, the CIP-51 MCU can accommodate the many
SFR’s required to control and configure the various peripherals featured on the device. The lower
128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as
four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The CIP-51 in the C8051F04x MCUs additionally has an on-chip 4 kB RAM block and an external memory
interface (EMIF) for accessing off-chip data memory or memory-mapped peripherals. The on-chip 4 byte
block can be addressed over the entire 64 kB external data memory address range (overlapping 4 kB
boundaries). External data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4 kB directed to on-chip, above 4 kB directed to
EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines.
The MCU's program memory consists of 64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) of Flash.
This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses 0xFE00 to 0xFFFF are reserved for the 64 kB devices.
There is also a single 128 byte sector at address 0x10000 to 0x1007F, which may be useful as a small
table for software constants. See Figure 1.7 for the MCU system memory map.
PROGRAM/DATA MEMORY
(FLASH)
C8051F040/1/2/3/4/5
0x1007F
0x10000
0xFE00
0xFDFF
0x0000
0x1007F
0x10000
0x8000
0x7FFF
Scrachpad Memory
(DATA only)
RESERVED
64 kB
Flash
(In-System
Programmable in 512
Byte Sectors)
C8051F046/7
Scrachpad Memory
(DATA only)
RESERVED
32 kB
Flash
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
0x1000
0x0FFF
0x0000
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Registers
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-chip XRAM space
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
0
1
2
3
F
Up To
256 SFR Pages
0x0000
Figure 1.7. On-Chip Memory Map
Rev. 1.4 27
C8051F040/1/2/3/4/5/6/7
1.3. JTAG Debug and Boundary Scan
The C8051F04x family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive,
full speed, in-circuit debugging using the production part installed in the end application, via the four-pin
JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and
manufacturing purposes.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and
work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the
MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized with instruction execution.
The C8051F040DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F04x MCUs. The development kit includes two
target boards and a cable to facilitate evaluating a simple CAN communication network. The kit also
includes software with a developer's studio and debugger, a target application board with the associated
MCU installed, and the required cables and wall-mount power supply. The Serial Adapter takes its power
from the application board; it requires roughly 20 mA at 2.7-3.6 V. For applications where there is not sufficient power available from the target system, the provided power supply can be connected directly to the
Serial Adapter.
Silicon Labs’ debug environment is a vastly superior configuration for developing and debugging embedded applications compared to standard MCU emulators, which use on-board "ICE Chips" and target cables
and require the MCU in the application board to be socketed. Silicon Labs' debug environment both
increases ease of use and preserves the performance of the precision, on-chip analog peripherals.
Integrated Development
Environment
WINDO WS 95 o r later
Serial
Adapter
JTAG (x4), VDD, GND
VDD GND
C8051
TARGET PCB
F040
Figure 1.8. Development/In-System Debug Diagram
28 Rev. 1.4
C8051F040/1/2/3/4/5/6/7
1.4. Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F040/2/4/6 have 4 additional 8-bit ports (4, 5, 6, and 7) for a total of 64 general-purpose I/O Ports. The Ports behave like the standard 8051 with a few enhancements.
Each port pin can be configured as either a push-pull or open-drain output. Also, the "weak pullups" which
are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for
low-power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching
network that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3
(See Figure 1.9). Unlike microcontrollers with standard multiplexed digital I/O ports, all combinations of
functions are supported with all package options offered.
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in
the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and
digital resources needed for the particular application.
XBR0, XBR1, XBR2,
Highest
Priority
Lowest
Priority
Port
Latches
(Internal Digital Signals)
UART0
SPI
SMBus
UART1
PCA
Comptr.
Outputs
T0, T1,
T2, T2EX,
T3, T3EX,
T4,T4EX,
/INT0,
/INT1
/SYSCLK
CNVSTR0
CNVSTR2
P0
P1
P2
P3
8
(P0.0-P0.7)
8
(P1.0-P1.7)
8
(P2.0-P2.7)
8
(P3.0-P3.7)
2
4
2
2
6
2
XBR3 P1MDIN,
P2MDIN, P3MDIN
Registers
Priority
Decoder
Digital
Crossbar
8
To External
Memory
Interface
(EMIF)
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
8
8
8
8
P0
I/O
Cells
P1
I/O
Cells
P2
I/O
Cells
P3
I/O
Cells
To
ADC2
Input
To
Comparators
To
ADC0
Input
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Priority
Lowest
Priority
Figure 1.9. Digital Crossbar Diagram
Rev. 1.4 29
C8051F040/1/2/3/4/5/6/7
1.5. Programmable Counter Array
The C8051F04x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition
to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer
time base with six programmable capture/compare modules. The timebase is clocked from one of six
sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External
Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width
Modulator. The PCA Capture/Compare Module I/O and External Clock Input are routed to the MCU Port
I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
ECI
Capture/Compare
Module 0
CEX0
Capture/Compare
Module 1
CEX1
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
Crossbar
Port I/O
Figure 1.10. PCA Block Diagram
CEX3
Capture/Compare
Module 4
CEX4
Capture/Compare
Module 5
CEX5
30 Rev. 1.4
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