Silicon Laboratories C8051F000, C8051F001, C8051F002, C8051F005, C8051F006 User Manual

...
C8051F000/1/2/5/6/7
ANALOG PERIPHERALS
- SAR ADC
12-Bit (C8051F000/1/2, C8051F005/6/7) 10-bit (C8051F010/1/2, C8051F015/6/7) ±1LSB INL; No Missing Codes Programmable Throughput up to 100ksps Up to 8 External Inputs; Programmable as Single-
- Two 12-bit DACs
- Two Analog Comparators
- Voltage Reference
- Precision VDD Monitor/Brown-out Detector
ON-CHIP JTAG DEBUG & BOUNDRY SCAN
- On-Chip Debug Circuitry Facilitates Full Speed, Non-
- Provides Breakpoints, Single Stepping, Watchpoints, Stack
- Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
- IEEE1149.1 Compliant Boundary Scan
- Low Cost Development Kit
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5 Data Dependent Windowed Interrupt Generator Built-in Temperature Sensor (± 3°C)
Programmable Hysteresis Values Configurable to Generate Interrupts or Reset
2.4V; 15 ppm/°C Available on External Pin
Intrusive In-System Debug (No Emulator Required!)
Monitor
Chips, Target Pods, and Sockets
Mixed-Signal 32KB ISP FLASH MCU Family
C8051F010/1/2/5/6/7
HIGH SPEED 8051 µµµµC CORE
- Pipelined Instruction Architecture; Executes 70% of Instruction Set in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- 21 Vectored Interrupt Sources
MEMORY
- 256 Bytes Internal Data RAM (F000/01/02/10/11/12)
- 2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
- 32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
DIGITAL PERIPHERALS
- 4 Byte-Wide Port I/O; All are 5V tolerant
- Hardware SMBus
Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with Five Capture/Compare Modules
- Four General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer
- Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC,C, or Clock
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
SUPPLY VOLTAGE ........................ 2.7V to 3.6V
- Typical Operating Current: 12.5mA @ 25MHz
- Multiple Power Saving Sleep and Shutdown Modes
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP Temperature Range: –40°°°°C to +85°°°°C
TM
(I2CTM Compatible), SPITM, and UART
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
AMUX
VREF
SAR
ADC
12-Bit
DAC
12-Bit
DAC
+
-
COMPARATORS
+
-
VOLTAGE
DIGITAL I/O
PCA
SMBus
SPI Bus
UART
Timer 0
Timer 1
Timer 2
Timer 3
CROSSBAR
Port 0Port 1
Port 2Port 3
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
32KB
ISP FLASH
CLOCK
CIRCUIT
256/2304 B
SRAM
21
INTERRUPTS
DEBUG
CIRCUITRY
SANITY
CONTROL
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TABLE OF CONTENTS
1. SYSTEM OVERVIEW ....................................................................................................... 8
Table 1.1. Product Selection Guide................................................................................................................... 8
Figure 1.1. C8051F000/05/10/15 Block Diagram............................................................................................. 9
Figure 1.2. C8051F001/06/11/16 Block Diagram........................................................................................... 10
Figure 1.3. C8051F002/07/12/17 Block Diagram........................................................................................... 11
1.1. CIP-51TM CPU ...................................................................................................................................... 12
Figure 1.4. Comparison of Peak MCU Execution Speeds............................................................................... 12
Figure 1.5. On-Board Clock and Reset ........................................................................................................... 13
1.2. On-Board Memory................................................................................................................................ 14
Figure 1.6. On-Board Memory Map ............................................................................................................... 14
1.3. JTAG Debug and Boundary Scan ......................................................................................................... 15
Figure 1.7. Debug Environment Diagram ....................................................................................................... 15
1.4. Programmable Digital I/O and Crossbar ............................................................................................... 16
Figure 1.8. Digital Crossbar Diagram ............................................................................................................. 16
1.5. Programmable Counter Array ............................................................................................................... 17
Figure 1.9. PCA Block Diagram..................................................................................................................... 17
1.6. Serial Ports ............................................................................................................................................ 17
1.7. Analog to Digital Converter.................................................................................................................. 18
Figure 1.10. ADC Diagram............................................................................................................................. 18
1.8. Comparators and DACs......................................................................................................................... 19
Figure 1.11. Comparator and DAC Diagram .................................................................................................. 19
2. ABSOLUTE MAXIMUM RATINGS*............................................................................ 20
3. GLOBAL DC ELECTRICAL CHARACTERISTICS .................................................. 20
4. PINOUT AND PACKAGE DEFINITIONS.................................................................... 21
Table 4.1. Pin Definitions ............................................................................................................................... 21
Figure 4.1. TQFP-64 Pinout Diagram............................................................................................................. 23
Figure 4.2. TQFP-64 Package Drawing.......................................................................................................... 24
Figure 4.3. TQFP-48 Pinout Diagram............................................................................................................. 25
Figure 4.4. TQFP-48 Package Drawing.......................................................................................................... 26
Figure 4.5. LQFP-32 Pinout Diagram............................................................................................................. 27
Figure 4.6. LQFP-32 Package Drawing .......................................................................................................... 28
5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only) ........................................................................ 29
Figure 5.1. 12-Bit ADC Functional Block Diagram........................................................................................ 29
5.1. Analog Multiplexer and PGA................................................................................................................ 29
5.2. ADC Modes of Operation ..................................................................................................................... 30
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing................................................................... 30
Figure 5.3. Temperature Sensor Transfer Function......................................................................................... 31
Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x) ............................................................ 31
Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x)........................................................... 32
Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x)................................................................. 33
Figure 5.7. ADC0CN: ADC Control Register (C8051F00x) .......................................................................... 34
Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x) ............................................................. 35
Figure 5.9. ADC0L: ADC Data Word LSB Register (C8051F00x)............................................................... 35
5.3. ADC Programmable Window Detector................................................................................................. 36
Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x)................................... 36
Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x).................................... 36
Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x)........................................ 36
Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x)......................................... 36
Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data................................................. 37
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 37
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 38
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Table 5.1. 12-Bit ADC Electrical Characteristics ........................................................................................... 38
Table 5.1. 12-Bit ADC Electrical Characteristics ........................................................................................... 39
6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only) ........................................................................ 40
Figure 6.1. 10-Bit ADC Functional Block Diagram........................................................................................ 40
6.1. Analog Multiplexer and PGA................................................................................................................ 40
6.2. ADC Modes of Operation ..................................................................................................................... 41
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing................................................................... 41
Figure 6.3. Temperature Sensor Transfer Function......................................................................................... 42
Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x) ............................................................ 42
Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)........................................................... 43
Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x)................................................................. 44
Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) .......................................................................... 45
Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x) ............................................................. 46
Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x)............................................................... 46
6.3. ADC Programmable Window Detector................................................................................................. 47
Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x)................................... 47
Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x).................................... 47
Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x)........................................ 47
Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x)......................................... 47
Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data................................................. 48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 49
Table 6.1. 10-Bit ADC Electrical Characteristics ........................................................................................... 49
Table 6.1. 10-Bit ADC Electrical Characteristics ........................................................................................... 50
7. DACs, 12 BIT VOLTAGE MODE................................................................................... 51
Figure 7.1. DAC Functional Block Diagram.................................................................................................... 51
Figure 7.2. DAC0H: DAC0 High Byte Register............................................................................................. 52
Figure 7.3. DAC0L: DAC0 Low Byte Register .............................................................................................. 52
Figure 7.4. DAC0CN: DAC0 Control Register............................................................................................... 52
Figure 7.5. DAC1H: DAC1 High Byte Register............................................................................................. 53
Figure 7.6. DAC1L: DAC1 Low Byte Register .............................................................................................. 53
Figure 7.7. DAC1CN: DAC1 Control Register............................................................................................... 53
Table 7.1. DAC Electrical Characteristics ...................................................................................................... 54
8. COMPARATORS.............................................................................................................. 55
Figure 8.1. Comparator Functional Block Diagram........................................................................................ 55
Figure 8.2. Comparator Hysteresis Plot .......................................................................................................... 56
Figure 8.3. CPT0CN: Comparator 0 Control Register .................................................................................... 57
Figure 8.4. CPT1CN: Comparator 1 Control Register .................................................................................... 58
Table 8.1. Comparator Electrical Characteristics............................................................................................ 59
9. VOLTAGE REFERENCE................................................................................................ 60
Figure 9.1. Voltage Reference Functional Block Diagram ............................................................................. 60
Figure 9.2. REF0CN: Reference Control Register.......................................................................................... 61
Table 9.1. Reference Electrical Characteristics............................................................................................... 61
10. CIP-51 CPU........................................................................................................................ 62
Figure 10.1. CIP-51 Block Diagram ............................................................................................................... 62
10.1. INSTRUCTION SET ........................................................................................................................ 63
Table 10.1. CIP-51 Instruction Set Summary.................................................................................................. 64
10.2. MEMORY ORGANIZATION.......................................................................................................... 67
Figure 10.2. Memory Map .............................................................................................................................. 68
10.3. SPECIAL FUNCTION REGISTERS ............................................................................................... 69
Table 10.2. Special Function Register Memory Map...................................................................................... 69
Table 10.3. Special Function Registers........................................................................................................... 69
Figure 10.3. SP: Stack Pointer ........................................................................................................................ 73
Figure 10.4. DPL: Data Pointer Low Byte...................................................................................................... 73
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Figure 10.5. DPH: Data Pointer High Byte..................................................................................................... 73
Figure 10.6. PSW: Program Status Word ....................................................................................................... 74
Figure 10.7. ACC: Accumulator ..................................................................................................................... 75
Figure 10.8. B: B Register............................................................................................................................... 75
10.4. INTERRUPT HANDLER................................................................................................................. 76
Table 10.4. Interrupt Summary....................................................................................................................... 77
Figure 10.9. IE: Interrupt Enable .................................................................................................................... 78
Figure 10.10. IP: Interrupt Priority ................................................................................................................. 79
Figure 10.11. EIE1: Extended Interrupt Enable 1........................................................................................... 80
Figure 10.12. EIE2: Extended Interrupt Enable 2........................................................................................... 81
Figure 10.13. EIP1: Extended Interrupt Priority 1.......................................................................................... 82
Figure 10.14. EIP2: Extended Interrupt Priority 2.......................................................................................... 83
10.5. Power Management Modes ............................................................................................................... 84
Figure 10.15. PCON: Power Control Register ................................................................................................ 85
C8051F010/1/2/5/6/7
11. FLASH MEMORY............................................................................................................ 86
11.1. Programming The Flash Memory...................................................................................................... 86
Table 11.1. FLASH Memory Electrical Characteristics.................................................................................. 86
11.2. Non-volatile Data Storage................................................................................................................. 87
11.3. Security Options................................................................................................................................ 87
Figure 11.1. PSCTL: Program Store RW Control........................................................................................... 87
Figure 11.2. Flash Program Memory Security Bytes ....................................................................................... 88
Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only) ............................................... 89
Figure 11.4. FLSCL: Flash Memory Timing Prescaler................................................................................... 90
12. EXTERNAL RAM (C8051F005/06/07/15/16/17) ............................................................ 91
Figure 12.1. EMI0CN: External Memory Interface Control ........................................................................... 91
13. RESET SOURCES ............................................................................................................ 92
Figure 13.1. Reset Sources Diagram............................................................................................................... 92
13.1. Power-on Reset ................................................................................................................................. 93
13.2. Software Forced Reset....................................................................................................................... 93
Figure 13.2. VDD Monitor Timing Diagram .................................................................................................. 93
13.3. Power-fail Reset................................................................................................................................ 93
13.4. External Reset ................................................................................................................................... 94
13.5. Missing Clock Detector Reset ........................................................................................................... 94
13.6. Comparator 0 Reset........................................................................................................................... 94
13.7. External CNVSTR Pin Reset ............................................................................................................ 94
13.8. Watchdog Timer Reset...................................................................................................................... 94
Figure 13.3. WDTCN: Watchdog Timer Control Register ............................................................................. 95
Figure 13.4. RSTSRC: Reset Source Register ................................................................................................ 96
Table 13.1. Reset Electrical Characteristics.................................................................................................... 97
14. OSCILLATOR................................................................................................................... 98
Figure 14.1. Oscillator Diagram...................................................................................................................... 98
Figure 14.2. OSCICN: Internal Oscillator Control Register ........................................................................... 99
Table 14.1. Internal Oscillator Electrical Characteristics................................................................................ 99
Figure 14.3. OSCXCN: External Oscillator Control Register....................................................................... 100
14.1. External Crystal Example................................................................................................................ 101
14.2. External RC Example...................................................................................................................... 101
14.3. External Capacitor Example............................................................................................................ 101
15. PORT INPUT/OUTPUT................................................................................................. 102
15.1. Priority Cross Bar Decoder ............................................................................................................. 102
15.2. Port I/O Initialization ...................................................................................................................... 102
Figure 15.1. Port I/O Functional Block Diagram.......................................................................................... 103
Figure 15.2. Port I/O Cell Block Diagram .................................................................................................... 103
Table 15.1. Crossbar Priority Decode........................................................................................................... 104
Figure 15.3. XBR0: Port I/O CrossBar Register 0........................................................................................ 105
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Figure 15.4. XBR1: Port I/O CrossBar Register 1........................................................................................ 106
Figure 15.5. XBR2: Port I/O CrossBar Register 2........................................................................................ 107
15.3. General Purpose Port I/O ................................................................................................................ 108
15.4. Configuring Ports Which are not Pinned Out.................................................................................. 108
Figure 15.6. P0: Port0 Register..................................................................................................................... 108
Figure 15.7. PRT0CF: Port0 Configuration Register.................................................................................... 108
Figure 15.8. P1: Port1 Register..................................................................................................................... 109
Figure 15.9. PRT1CF: Port1 Configuration Register.................................................................................... 109
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register ................................................................................... 109
Figure 15.11. P2: Port2 Register................................................................................................................... 110
Figure 15.12. PRT2CF: Port2 Configuration Register.................................................................................. 110
Figure 15.13. P3: Port3 Register................................................................................................................... 111
Figure 15.14. PRT3CF: Port3 Configuration Register.................................................................................. 111
Table 15.2. Port I/O DC Electrical Characteristics ....................................................................................... 111
16. SMBus / I2C Bus.............................................................................................................. 112
Figure 16.1. SMBus Block Diagram............................................................................................................. 112
Figure 16.2. Typical SMBus Configuration .................................................................................................. 113
16.1. Supporting Documents.................................................................................................................... 113
16.2. Operation......................................................................................................................................... 114
Figure 16.3. SMBus Transaction................................................................................................................... 114
16.3. Arbitration....................................................................................................................................... 115
16.4. Clock Low Extension ...................................................................................................................... 115
16.5. Timeouts.......................................................................................................................................... 115
16.6. SMBus Special Function Registers ................................................................................................. 115
Figure 16.4. SMB0CN: SMBus Control Register .......................................................................................... 117
Figure 16.5. SMB0CR: SMBus Clock Rate Register.................................................................................... 118
Figure 16.6. SMB0DAT: SMBus Data Register ........................................................................................... 119
Figure 16.7. SMB0ADR: SMBus Address Register ..................................................................................... 119
Figure 16.8. SMB0STA: SMBus Status Register.......................................................................................... 120
Table 16.1. SMBus Status Codes.................................................................................................................. 121
17. SERIAL PERIPHERAL INTERFACE BUS................................................................ 122
Figure 17.1. SPI Block Diagram................................................................................................................... 122
Figure 17.2. Typical SPI Interconnection ..................................................................................................... 123
17.1. Signal Descriptions ......................................................................................................................... 123
17.2. Operation......................................................................................................................................... 124
Figure 17.3. Full Duplex Operation .............................................................................................................. 124
17.3. Serial Clock Timing ........................................................................................................................ 125
Figure 17.4. Data/Clock Timing Diagram..................................................................................................... 125
17.4. SPI Special Function Registers ....................................................................................................... 126
Figure 17.5. SPI0CFG: SPI Configuration Register...................................................................................... 126
Figure 17.6. SPI0CN: SPI Control Register.................................................................................................. 127
Figure 17.7. SPI0CKR: SPI Clock Rate Register.......................................................................................... 128
Figure 17.8. SPI0DAT: SPI Data Register.................................................................................................... 128
18. UART ................................................................................................................................ 129
Figure 18.1. UART Block Diagram.............................................................................................................. 129
18.1. UART Operational Modes .............................................................................................................. 130
Table 18.1. UART Modes............................................................................................................................. 130
Figure 18.2. UART Mode 0 Interconnect ..................................................................................................... 130
Figure 18.3. UART Mode 0 Timing Diagram............................................................................................... 130
Figure 18.4. UART Mode 1 Timing Diagram............................................................................................... 131
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram ...................................................................... 132
Figure 18.6. UART Modes 2 and 3 Timing Diagram ................................................................................... 132
18.2. Multiprocessor Communications..................................................................................................... 133
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram............................................................... 133
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Table 18.2. Oscillator Frequencies for Standard Baud Rates........................................................................ 134
Figure 18.8. SBUF: Serial (UART) Data Buffer Register............................................................................. 134
Figure 18.9. SCON: Serial Port Control Register ......................................................................................... 135
C8051F010/1/2/5/6/7
19. TIMERS............................................................................................................................ 136
19.1. Timer 0 and Timer 1 ....................................................................................................................... 136
Figure 19.1. T0 Mode 0 Block Diagram....................................................................................................... 137
Figure 19.2. T0 Mode 2 Block Diagram....................................................................................................... 138
Figure 19.3. T0 Mode 3 Block Diagram....................................................................................................... 139
Figure 19.4. TCON: Timer Control Register ................................................................................................ 140
Figure 19.5. TMOD: Timer Mode Register .................................................................................................. 141
Figure 19.6. CKCON: Clock Control Register.............................................................................................. 142
Figure 19.7. TL0: Timer 0 Low Byte............................................................................................................ 143
Figure 19.8. TL1: Timer 1 Low Byte............................................................................................................ 143
Figure 19.9. TH0: Timer 0 High Byte........................................................................................................... 143
Figure 19.10. TH1: Timer 1 High Byte......................................................................................................... 143
19.2. Timer 2............................................................................................................................................ 144
Figure 19.11. T2 Mode 0 Block Diagram..................................................................................................... 145
Figure 19.12. T2 Mode 1 Block Diagram..................................................................................................... 146
Figure 19.13. T2 Mode 2 Block Diagram..................................................................................................... 147
Figure 19.14. T2CON: Timer 2 Control Register ......................................................................................... 148
Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte ...................................................................... 149
Figure 19.16. RCAP2H: Timer 2 Capture Register High Byte ..................................................................... 149
Figure 19.17. TL2: Timer 2 Low Byte.......................................................................................................... 149
Figure 19.18. TH2: Timer 2 High Byte......................................................................................................... 149
19.3. Timer 3............................................................................................................................................ 150
Figure 19.19. Timer 3 Block Diagram.......................................................................................................... 150
Figure 19.20. TMR3CN: Timer 3 Control Register...................................................................................... 150
Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte .................................................................... 151
Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte ................................................................... 151
Figure 19.23. TMR3L: Timer 3 Low Byte.................................................................................................... 151
Figure 19.24. TMR3H: Timer 3 High Byte................................................................................................... 151
20. PROGRAMMABLE COUNTER ARRAY ................................................................... 152
Figure 20.1. PCA Block Diagram................................................................................................................. 152
20.1. Capture/Compare Modules.............................................................................................................. 153
Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules........................................... 153
Figure 20.2. PCA Interrupt Block Diagram .................................................................................................. 153
Figure 20.3. PCA Capture Mode Diagram.................................................................................................... 154
Figure 20.4. PCA Software Timer Mode Diagram........................................................................................ 155
Figure 20.5. PCA High Speed Output Mode Diagram.................................................................................. 155
Figure 20.6. PCA PWM Mode Diagram....................................................................................................... 156
20.2. PCA Counter/Timer ........................................................................................................................ 157
Table 20.2. PCA Timebase Input Options .................................................................................................... 157
Figure 20.7. PCA Counter/Timer Block Diagram......................................................................................... 157
20.3. Register Descriptions for PCA........................................................................................................ 158
Figure 20.8. PCA0CN: PCA Control Register............................................................................................... 158
Figure 20.9. PCA0MD: PCA Mode Register................................................................................................ 159
Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers...................................................................... 160
Figure 20.11. PCA0L: PCA Counter/Timer Low Byte ................................................................................. 161
Figure 20.12. PCA0H: PCA Counter/Timer High Byte................................................................................ 161
Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte ........................................................................ 161
Figure 20.14. PCA0CPHn: PCA Capture Module High Byte....................................................................... 161
21. JTAG (IEEE 1149.1) ....................................................................................................... 162
Figure 21.1. IR: JTAG Instruction Register .................................................................................................. 162
21.1. Boundary Scan ................................................................................................................................ 163
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Table 21.1. Boundary Data Register Bit Definitions..................................................................................... 163
Figure 21.2. DEVICEID: JTAG Device ID Register.................................................................................... 164
21.2. Flash Programming Commands....................................................................................................... 165
Figure 21.3. FLASHCON: JTAG Flash Control Register............................................................................. 166
Figure 21.4. FLASHADR: JTAG Flash Address Register............................................................................ 166
Figure 21.5. FLASHDAT: JTAG Flash Data Register.................................................................................. 167
Figure 21.6. FLASHSCL: JTAG Flash Scale Register ................................................................................. 167
21.3. Debug Support ................................................................................................................................ 168
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C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
1. SYSTEM OVERVIEW
The C8051F000 family are fully integrated mixed-signal System on a Chip MCUs with a true 12-bit multi-channel ADC (F000/01/02/05/06/07), or a true 10-bit multi-channel ADC (F010/11/12/15/16/17). See the Product Selection Guide in Table 1.1 for a quick reference of each MCUs’ feature set. Each has a programmable gain pre-amplifier, two 12-bit DACs, two voltage comparators (except for the F002/07/12/17, which have one), a voltage reference, and an 8051-compatible microcontroller core with 32kbytes of FLASH memory. There are also I2C/SMBus, UART, and SPI serial interfaces implemented in hardware (not “bit-banged” in user software) as well as a Programmable Counter/Timer Array (PCA) with five capture/compare modules. There are also 4 general-purpose 16-bit timers and 4 byte-wide general-purpose digital Port I/O. The C8051F000/01/02/10/11/12 have 256 bytes of RAM and execute up to 20MIPS, while the C8051F005/06/07/15/16/17 have 2304 bytes of RAM and execute up to 25MIPS.
With an on-board VDD monitor, WDT, and clock oscillator, the MCUs are truly stand-alone System-on-a-Chip solutions. Each MCU effectively configures and manages the analog and digital peripherals. The FLASH memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. Each MCU can also individually shut down any or all of the peripherals to conserve power.
On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit debug using the production MCU installed in the final application. This debug system supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional when using JTAG debug.
Each MCU is specified for 2.7V-to-3.6V operation over the industrial temperature range (-45C to +85C). The Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5V. The C8051F000/05/10/15 are available in the 64­pin TQFP (see block diagram in Figure 1.1). The C8051F001/06/11/16 are available in the 48-pin TQFP (see block diagram in Figure 1.2). The C8051F002/07/12/17 are available in the 32-pin LQFP (see block diagram in Figure
1.3).
Table 1.1. Product Selection Guide
C8051F000 20 32k 256
C8051F001 20 32k 256
C8051F002 20 32k 256
C8051F005 25 32k 2304
C8051F006 25 32k 2304
C8051F007 25 32k 2304
C8051F010 20 32k 256
C8051F011 20 32k 256
C8051F012 20 32k 256
C8051F015 25 32k 2304
C8051F016 25 32k 2304
C8051F017 25 32k 2304
MIPS (Peak)
FLASH Memory
RAM
SMBus/I2C
SPI
√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/O’s
ADC Resolution (bits)
ADC Max Speed (ksps)
ADC Inputs
Voltage Reference
Temperature Sensor
DAC Resolution
DAC Outputs
Voltage Comparators
Package
4
4
4
4
4
4
4
4
4
4
4
4
32 12 100 8
16 12 100 8
8 12 100 4
32 12 100 8
16 12 100 8
8 12 100 4
32 10 100 8
16 10 100 8
8 10 100 4
32 10 100 8
16 10 100 8
8 10 100 4
√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √
12 2 2 64TQFP
12 2 2 48TQFP
12 2 1 32LQFP
12 2 2 64TQFP
12 2 2 48TQFP
12 2 1 32LQFP
12 2 2 64TQFP
12 2 2 48TQFP
12 2 1 32LQFP
12 2 2 64TQFP
12 2 2 48TQFP
12 2 1 32LQFP
Page 8 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 1.1. C8051F000/05/10/15 Block Diagram
VDD VDD
VDD DGND DGND DGND
AV+
AV+ AGND AGND
TCK
TMS
TDI
TDO
/RST
XTAL1 XTAL2
VREF
DAC0
DAC1
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
CP0+
CP0-
CP1+
CP1-
Digital Power
Analog Power
VREF
A M U X
JTAG Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
DAC0
(12-Bit)
DAC1
(12-Bit)
Boundary Scan
Debug HW
WDT
Prog Gain
ADC
100ksps
Reset
System Clock
8 0 5 1
C o
r
e
32kbyte
FLASH
256 byte
RAM
2048 byte
XRAM
(F005/15 only)
SFR Bus
UART
SMBus
SPI Bus
PCA
Timers
0,1,2
Timer 3
Port 0 Latch
Port 1 Latch
Port 2
Latch
Port 3
Latch
C R O S S B A R
S W
I
T C H
TEMP
CP0
CP1
P 0
D r v
P 1
D r v
P 2
D r v
P 3
D r v
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 9
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 1.2. C8051F001/06/11/16 Block Diagram
VDD
VDD DGND DGND DGND DGND
AV+
AV+ AGND AGND
TCK
TMS
TDI
TDO
/RST
XTAL1 XTAL2
VREF
DAC0
DAC1
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
CP0+
CP0-
CP1+
CP1-
Digital Power
Analog Power
VREF
A M U
X
JTAG Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
DAC0
(12-Bit)
DAC1
(12-Bit)
Prog Gain
Boundary Scan
Debug HW
WDT
ADC
100ksps
Reset
System Clock
8 0 5 1
C
o
r
e
32kbyte
FLASH
256 byte
RAM
2048 byte
XRAM
(F006/16 only)
SFR Bus
UART
SMBus
SPI Bus
PCA
Timers
0,1,2
Timer 3
Port 0 Latch
Port 1 Latch
Port 2 Latch
Port 3 Latch
C R O S S B A R
S W
I T C H
TEMP
CP0
CP1
P 0
D
r
v
P 1
D
r
v
P 2
D
r
v
P 3
D
r
v
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Page 10 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 1.3. C8051F002/07/12/17 Block Diagram
VDD VDD
DGND DGND
AV+
AV+ AGND AGND
TCK
TMS
TDI
TDO
/RST
XTAL1 XTAL2
VREF
DAC0
DAC1
AIN0 AIN1 AIN2 AIN3
CP0+
CP0-
Digital Po wer
Analog Power
VREF
A M U X
JTAG Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
DAC0
(12-Bit)
DAC1
(12-Bit)
Prog Gain
CP0
CP1
Boundary Scan
Debug HW
WDT
TEMP
ADC
100ksps
Reset
System Clock
8 0 5 1
C o
r
e
32kbyte
FLASH
256 byte
RAM
2048 byte
XRAM
(F007/17 on ly)
SFR Bus
UART
SMBus
SPI Bus
PCA
Timers
0,1,2
Timer 3
Port 0
Latch
Port 1
Latch
Port 2
Latch
Port 3
Latch
C R O S S B A R
S W
I
T C H
P 0
D
r
v
P 1
D
r
v
P 2
D
r
v
P 3
D
r
v
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 11
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
1.1. CIP-51TM CPU
1.1.1. Fully 8051 Compatible
The C8051F000 family utilizes Cygnal’s proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51 The core has all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR) address space, and four byte­wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute them is as follows:
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
TM
instruction set. Standard 803x/805x assemblers and compilers can be used to develop software.
Instructions
Clocks to Execute
26 50 5 14 7 3 1 2 1
1 2 2/3 3 3/4 4 4/5 5 8
Figure 1.4. Comparison of Peak MCU Execution Speeds
25
20
15
MIPS
10
5
Cygnal CIP-51
(25MHz clk)
Microchip
PIC17C75x
(33MHz clk)
Philips
80C51
(33MHz clk)
ADuC812
8051
(16MHz clk)
Page 12 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
1.1.3. Additional Features
The C8051F000 MCU family has several key enhancements both inside and outside the CIP-51 core to improve its overall performance and ease of use in the end applications.
The extended interrupt handler provides 21 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock detector, a voltage level detection from Comparator 0, a forced software reset, the CNVSTR pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be output on the /RST pin. Each reset source except for the VDD monitor and Reset Input Pin may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the fast (up to 16MHz) internal oscillator as needed.
Figure 1.5. On-Board Clock and Reset
(Port
I/O)
Crossbar
CP0+
CP0-
CNVSTR
(CNVSTR
reset
enable)
Comparator 0
+
-
(CP0 reset
enable)
Missing
Clock
Detector
(one-
Internal
Clock
XTAL1
XTAL2
Generator
OSC
System Clock
Clock Select
VDD
WDT
shot)
EN
MCD
Enable
EN
WDT
Enable
CIP-51
Microcontroller
Core
Supply Monitor
+
-
PRE
WDT
Supply
Reset
Timeout
Strobe
Software Reset
System Reset
(wired-OR)
Reset Funnel
/RST
Extended Interrupt
Handler
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 13
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
1.2. On-Board Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general-purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The CIP-51 in the C8051F005/06/07/15/16/17 MCUs additionally has a 2048 byte RAM block in the external data memory address space. This 2048 byte block can be addressed over the entire 64k external data memory address range (see Figure 1.6).
The MCU’s program memory consists of 32k + 128 bytes of FLASH. This memory may be reprogrammed in­system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses 0x7E00 to 0x7FFF are reserved for factory use. There is also a single 128-byte sector at address 0x8000 to 0x807F, which may be useful as a small table for software constants or as additional program space. See Figure 1.6 for the MCU system memory map.
Figure 1.6. On-Board Memory Map
0x807F
0x8000
0x7FFF
0x7E00
0x7DFF
0x0000
PROGRAM MEMORY
128 Byte ISP FLASH
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80 0x7F
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM (Direct and Indirect Addressing)
EXTERNAL DATA ADDRESS SPACE
0xFFFF
0xF800
0x17FF
0x1000
0x0FFF
0x0800
0x07FF
0x0000
(same 2048 byte RAM block )
(same 2048 byte RAM block )
(same 2048 byte RAM block )
RAM - 2048 Bytes
(accessable using MOVX
instruction)
The same 2048 byte RAM block can be addressed on 2k boundaries throughout the 64k External Data Memory space.
Page 14 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

1.3. JTAG Debug and Boundary Scan

The C8051F000 family has on-chip JTAG and debug circuitry that provide non-intrusive, full speed, in-circuit debug using the production part installed in the end application using the four-pin JTAG I/F. The JTAG port is
fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes.
Cygnal’s debug system supports inspection and modification of memory and registers, breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them in sync.
The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the hardware and software necessary to develop application code and perform in-circuit debug with the C8051F000/1/2, F005/6/7, F010/1/2, and F015/6/7 MCUs respectively. The kit includes software with a developer’s studio and debugger, an integrated 8051 assembler, and an RS-232 to JTAG protocol translator module referred to as the EC. It also has a target application board with the associated MCU installed and a large prototyping area, plus the RS-232 and JTAG cables, and wall-mount power supply. The Development Kit requires a Windows 95/98/NT/2000/XP computer with one available RS-232 serial port. As shown in Figure 1.7, the PC is connected via RS-232 to the EC. A six-inch ribbon cable connects the EC to the user’s application board, picking up the four JTAG pins and VDD and GND. The EC takes its power from the application board. It requires roughly 20mA at 2.7-3.6V. For applications where there is not sufficient power available from the target board, the provided power supply can be connected directly to the EC.
This is a vastly superior configuration for developing and debugging embedded applications compared to standard MCU Emulators, which use on-board “ICE Chips” and target cables and require the MCU in the application board to be socketed. Cygnal’s debug environment both increases ease of use and preserves the performance of the precision analog peripherals.
Figure 1.7. Debug Environment Diagram
WINDOWS 95/98/NT/2000/XP
RS-232
JTAG (x4), VDD, GND
CYGNAL Integrated
Development Environment
VDD GND
C8051
F005
EC
TARGET PCB
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 15
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

1.4. Programmable Digital I/O and Crossbar

The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. All four ports are pinned out on the F000/05/10/15. Ports 0 and 1 are pinned out on the F001/06/11/16, and only Port 0 is pinned out on the F002/07/12/17. The Ports not pinned out are still available for software use as general purpose registers. The Port I/O behave like the standard 8051 with a few enhancements.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the “weak pull-ups” which are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network that allows mapping of internal digital system resources to Port I/O pins on P0, P1, and P2. (See Figure 1.8.) Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported.
The on-board counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for his particular application.
Figure 1.8. Digital Crossbar Diagram
Highest Priority
SMBus
SPI
UART
(Internal Digital Signals)
Lowest Priority
PCA
Comptr.
Outputs
T0, T1,
T2
SYSCLK
CNVSTR
2
4
2
6
2
6
XBR0, XBR1,
XBR2 Registers
Priority
Decoder
Digital
Crossbar
PRT0CF, PRT1CF,
PRT2CF Registers
P0
8
I/O
Cells
P1
8
I/O
Cells
External
Pins
P0.0
P0.7
P1.0
P1.7
Highest
Priority
P0
P1
Port
Latches
P2
P3
8
(P0.0-P0.7)
8
(P1.0-P1.7)
8
(P2.0-P2.7)
8
(P3.0-P3.7)
P2
8
I/O
Cells
PRT3CF
Register
P3 I/O
Cells
P2.0
P2.7
P3.0
P3.7
Lowest Priority
Page 16 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

1.5. Programmable Counter Array

The C8051F000 MCU family has an on-board Programmable Counter/Timer Array (PCA) in addition to the four 16­bit general-purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer timebase with 5 programmable capture/compare modules. The timebase gets its clock from one of four sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, or an External Clock Input (ECI).
Each capture/compare module can be configured to operate in one of four modes: Edge-Triggered Capture, Software Timer, High Speed Output, or Pulse Width Modulator. The PCA Capture/Compare Module I/O and External Clock Input are routed to the MCU Port I/O via the Digital Crossbar.
Figure 1.9. PCA Block Diagram
System
Clock
T0 Overflow
/4
/12
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
ECI
CEX0
CEX1
CEX2
CEX3
CEX4
Crossbar
Port I/O

1.6. Serial Ports

The C8051F000 MCU Family includes a Full-Duplex UART, SPI Bus, and I2C/SMBus. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51’s interrupts, thus requiring very little intervention by the CPU. The serial buses do not “share” resources such as timers, interrupts, or Port I/O, so any or all of the serial buses may be used together.
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 17
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

1.7. Analog to Digital Converter

The C8051F000/1/2/5/6/7 has an on-chip 12-bit SAR ADC with a 9-channel input multiplexer and programmable gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 12-bit accuracy with an INL of ±1LSB. The ADC in the C8051F010/1/2/5/6/7 is similar, but with 10-bit resolution. Each ADC has a maximum throughput of 100ksps. Each ADC has an INL of ±1LSB, offering true 12-bit accuracy with the C8051F00x, and true 10-bit accuracy with the C8051F01x. There is also an on-board 15ppm voltage reference, or an external reference may be used via the VREF pin.
The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. One input channel is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the eight external input channels can be configured as either two single-ended inputs or a single differential input. The system controller can also put the ADC into shutdown to save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input voltage signals, or when it is necessary to “zoom in” on a signal with a large DC offset (in differential mode, a DAC could be used to provide the DC offset).
Conversions can be started in four ways; a software command, an overflow on Timer 2, an overflow on Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software events, external HW signals, or convert continuously. A completed conversion causes an interrupt, or a status bit can be polled in software to determine the end of conversion. The resulting 10 or 12-bit data word is latched into two SFRs upon completion of a conversion. The data can be right or left justified in these registers under software control.
Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within a specified window. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within the specified window.
Figure 1.10. ADC Diagram
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
(not bonded out on F002, F007, F012, and F017
+
-
+
-
+
-
+
-
9-to-1 AMUX (SE or
DIFF)
SENSOR
TEMP
Programmable
Gain Amp
+
X
-
Control & Data
SFR's
REF
100ksps
SAR
SFR Bus
VREF
ADC
Page 18 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

1.8. Comparators and DACs

The C8051F000 MCU Family has two 12-bit DACs and two comparators on chip (the second comparator, CP1, is not bonded out on the F002, F007, F012, and F017). The MCU data and control interface to each comparator and DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low power shutdown mode.
The comparators have software programmable hysteresis. Each comparator can generate an interrupt on its rising edge, falling edge, or both. The comparators’ output state can also be polled in software. These interrupts are capable of waking up the MCU from idle mode. The comparator outputs can be programmed to appear on the Port I/O pins via the Crossbar.
The DACs are voltage output mode and use the same voltage reference as the ADC. They are especially useful as references for the comparators or offsets for the differential inputs of the ADC.
Figure 1.11. Comparator and DAC Diagram
(Port I/O)
(Port I/O)
CP0
CP1
CROSSBAR
CP0+
CP0-
+
CP0
-
(not bonded out on
F002, F007, F012, and
F017)
CP1+
CP1-
DAC0
+
CP1
-
REF
DAC0
CP0
CP1
SFR's
(Data
and
Cntrl)
CIP-51
and Interrupt Handler
DAC1
REF
DAC1
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 19
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

2. ABSOLUTE MAXIMUM RATINGS*

Ambient temperature under bias .................................................................................................................-55 to 125°C
Storage Temperature...................................................................................................................................-65 to 150°C
Voltage on any Pin (except VDD and Port I/O) with respect to DGND.................................... -0.3V to (VDD + 0.3V)
Voltage on any Port I/O Pin or /RST with respect to DGND.................................................................... -0.3V to 5.8V
Voltage on VDD with respect to DGND................................................................................................... -0.3V to 4.2V
Maximum Total current through VDD, AV+, DGND and AGND ......................................................................800mA
Maximum output current sunk by any Port pin ....................................................................................................100mA
Maximum output current sunk by any other I/O pin ..............................................................................................25mA
Maximum output current sourced by any Port pin ...............................................................................................100mA
Maximum output current sourced by any other I/O pin .........................................................................................25mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

3. GLOBAL DC ELECTRICAL CHARACTERISTICS

-40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Supply Voltage (Note 1) 2.7 3.0 3.6 V Analog Supply Current Internal REF, ADC, DAC, Comparators
all active Analog Supply Current with analog sub-systems inactive Analog-to-Digital Supply Delta ( | VDD – AV+ | ) Digital Supply Voltage 2.7 3.0 3.6 V Digital Supply Current with CPU active
Digital Supply Current (shutdown) Digital Supply RAM Data Retention Voltage Specified Operating Temperature Range
Note 1: Analog Supply AV+ must be greater than 1V for VDD monitor to operate.
Internal REF, ADC, DAC, Comparators
all disabled, oscillator disabled
0.5 V
VDD = 2.7V, Clock=25MHz
VDD = 2.7V, Clock=1MHz
VDD = 2.7V, Clock=32kHz
Oscillator not running 5
1.5 V
-40 +85
1 2 mA
5 20
12.5
0.5 10
mA
µA
mA
µA µA
°C
Page 20 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

4. PINOUT AND PACKAGE DEFINITIONS

Table 4.1. Pin Definitions
Pin Numbers
F000
F001
Name
VDD
DGND
AV+
AGND
TCK TMS TDI
TDO
XTAL1
XTAL2
/RST
VREF
CP0+ CP0­CP1+ CP1­DAC0
DAC1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
F005 F010 F015
31, 40,
62 30, 41,
61
16,
17
5, 15 22 18 14 21 17 13 28 20 15
29 21 16
18 14 10
19 15 11
20 16 12
6 3 3
4 2 2 3 1 1 2 45 1 46
64 48 32
63 47 31
7 4 4
8 5 5
9 6 6
10 7 7
11 8
12 9
F006 F011 F016
23,
32
22, 33, 27,
19
13,
43
44,
12
F002 F007 F012 F017
18,
20
17,
21
9,
29
8,
30
Type Description
Digital Voltage Supply.
Digital Ground.
Positive Analog Voltage Supply.
Analog Ground.
DIn DIn DIn
D Out
AIn
A Out
D I/O
A I/O
AIn AIn AIn AIn A Out
A Out
AIn
AIn
AIn
AIn
AIn
AIn
JTAG Test Clock with internal pull-up. JTAG Test-Mode Select with internal pull-up. JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of
TCK. JTAG Test Data Output with internal pull-up. Data is shifted out on TDO on the falling edge of TCK. TDO output is a tri-state driver. Crystal Input. This pin is the return for the internal oscillator circuit for a crystal or ceramic resonator. For a precision internal clock, connect a crystal or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external CMOS clock, this becomes the system clock. Crystal Output. This pin is the excitation driver for a crystal or ceramic resonator. Chip Reset. Open-drain output of internal Voltage Supply monitor. Is driven low when VDD is < 2.7V. An external source can force a system reset by driving this pin low. Voltage Reference. When configured as an input, this pin is the voltage reference for the MCU. Otherwise, the internal reference drives this pin. Comparator 0 Non-Inverting Input.
Comparator 0 Inverting Input. Comparator 1 Non-Inverting Input. Comparator 1 Inverting Input. Digital to Analog Converter Output 0. The DAC0 voltage output. (See
Section 7 DAC Specification for complete description). Digital to Analog Converter Output 1. The DAC1 voltage output. (See Section 7 DAC Specification for complete description). Analog Mux Channel Input 0. (See ADC Specification for complete description). Analog Mux Channel Input 1. (See ADC Specification for complete description). Analog Mux Channel Input 2. (See ADC Specification for complete description). Analog Mux Channel Input 3. (See ADC Specification for complete description). Analog Mux Channel Input 4. (See ADC Specification for complete description). Analog Mux Channel Input 5. (See ADC Specification for complete description).
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 21
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Pin Numbers
F000
F001
Name
AIN6
AIN7
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
F005 F010 F015
13 10
14 11
39 31 19 42 34 22 47 35 23 48 36 24 49 37 25 50 38 26 55 39 27 56 40 28 38 30 37 29 36 28 35 26 34 25 32 24 60 42 59 41 33 27 54 53 52 51 44 43 26 25 24 23 58 57 46 45
F006 F011 F016
F002 F007 F012 F017
Type Description
AIn
AIn
D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O
Analog Mux Channel Input 6. (See ADC Specification for complete description). Analog Mux Channel Input 7. (See ADC Specification for complete description). Port0 Bit0. (See the Port I/O Sub-System section for complete description).
Port0 Bit1. (See the Port I/O Sub-System section for complete description). Port0 Bit2. (See the Port I/O Sub-System section for complete description). Port0 Bit3. (See the Port I/O Sub-System section for complete description). Port0 Bit4. (See the Port I/O Sub-System section for complete description). Port0 Bit5. (See the Port I/O Sub-System section for complete description). Port0 Bit6. (See the Port I/O Sub-System section for complete description). Port0 Bit7. (See the Port I/O Sub-System section for complete description). Port1 Bit0. (See the Port I/O Sub-System section for complete description). Port1 Bit1. (See the Port I/O Sub-System section for complete description). Port1 Bit2. (See the Port I/O Sub-System section for complete description). Port1 Bit3. (See the Port I/O Sub-System section for complete description). Port1 Bit4. (See the Port I/O Sub-System section for complete description). Port1 Bit5. (See the Port I/O Sub-System section for complete description). Port1 Bit6. (See the Port I/O Sub-System section for complete description). Port1 Bit7. (See the Port I/O Sub-System section for complete description). Port2 Bit0. (See the Port I/O Sub-System section for complete description). Port2 Bit1. (See the Port I/O Sub-System section for complete description). Port2 Bit2. (See the Port I/O Sub-System section for complete description). Port2 Bit3. (See the Port I/O Sub-System section for complete description). Port2 Bit4. (See the Port I/O Sub-System section for complete description). Port2 Bit5. (See the Port I/O Sub-System section for complete description). Port2 Bit6. (See the Port I/O Sub-System section for complete description). Port2 Bit7. (See the Port I/O Sub-System section for complete description). Port3 Bit0. (See the Port I/O Sub-System section for complete description). Port3 Bit1. (See the Port I/O Sub-System section for complete description). Port3 Bit2. (See the Port I/O Sub-System section for complete description). Port3 Bit3. (See the Port I/O Sub-System section for complete description). Port3 Bit4. (See the Port I/O Sub-System section for complete description). Port3 Bit5. (See the Port I/O Sub-System section for complete description). Port3 Bit6. (See the Port I/O Sub-System section for complete description). Port3 Bit7. (See the Port I/O Sub-System section for complete description).
Page 22 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 4.1. TQFP-64 Pinout Diagram
CP1-
CP1+
CP0-
CP0+
AGND
VREF
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AGND
AV+
10
11
15
16
12
13
14
P1.6
DAC0
DAC1
64
63
1
2
3
4
5
6
7
8
9
VDD
62
DGND
61
P1.7
60
59
58
C8051F000 C8051F005
P3.4
57
P3.5
P0.7
56
55
54
P2.2
P2.3
53
P0.6
C8051F010 C8051F015
17
18
19
20
21
22
23
24
25
26
27
AV+
XTAL1
/RST
XTAL2
TCK
TMS
P3.2
P3.3
P3.0
P3.1
P2.1
28
P2.5
P0.5
30
50
31
VDD
P0.4
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P1.5
P2.4
52
51
29
TDI
TDO
DGND
P0.3
P0.2 P3.6
P3.7
P2.6
P2.7
P0.1
DGND
VDD
P0.0
P1.0
P1.1
P1.2
P1.3
P1.4
P2.0
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 23
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 4.2. TQFP-64 Package Drawing
64
PIN 1
DESIGNATOR
1
A2
D
D1
MIN
NOM
MAX
(mm)
(mm)
(mm)
A
-
-
1.20
A1
0.05
E1
E
e
A
b
A1
A2
b
D
D1
e
E
E1
0.95
0.17
-
0.15
-
1.05
0.22
0.27
-
12.00
-
10.00
-
0.50
-
12.00
-
10.00
-
-
-
-
-
Page 24 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 4.3. TQFP-48 Pinout Diagram
AGND
CP0-
CP0+
VREF
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
1
2
3
4
5
6
7
8
9
10
11
12
DAC0
48
13
AV+
DAC1
47
14
XTAL1
CP1-
46
CP1+
45
AGND
44
AV+
43
P1.6
42
C8051F001 C8051F006 C8051F011 C8051F016
15
16
17
18
19
TCK
TMS
/RST
XTAL2
DGND
41
20
P1.7
TDI
40
21
P0.7
TDO
P0.6
39
38
22
23
DGND
P0.5
VDD
P0.4
37
36
35
34
33
32
31
30
29
28
27
26
25
24
P1.5
P0.3
P0.2
P0.1
DGND
VDD
P0.0
P1.0
P1.1
P1.2
DGND
P1.3
P1.4
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 25
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 4.4. TQFP-48 Package Drawing
48
PIN 1
IDENTIFIER
A2
1
D
D1
E1
E
e
A
A1
b
A
A1
A2
b
D
D1
e
E
E1
MIN
(mm)
-
0.05
0.95
0.17
-
-
-
-
-
NOM
(mm)
-
-
1.00
0.22
9.00
7.00
0.50
9.00
7.00
MAX
(mm)
1.20
0.15
1.05
0.27
-
-
-
-
-
Page 26 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 4.5. LQFP-32 Pinout Diagram
AGND
CP0-
CP0+
VREF
AIN0
AIN1
AIN2
AIN3
DAC0
32
DAC1
31
AGND
30
AV+
29
P0.7
28
1
2
3
4
5
6
C8051F002 C8051F007 C8051F012 C8051F017
7
8
9
10
11
12
13
AV+
XTAL1
XTAL2
/RST
TMS
P0.6
27
14
TCK
P0.5
26
15
TDI
P0.4
25
16
TDO
24
23
22
21
20
19
18
17
P0.3
P0.2
P0.1
DGND
VDD
P0.0
VDD
DGND
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 27
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 4.6. LQFP-32 Package Drawing
IDENTIFIER
32
PIN 1
1
A2
D
D1
A1
eb
MIN
NOM
(mm)
A
A1
0.05
E1
E
A2
b
1.35
0.30
D
D1
e
A
E
E1
(mm)
-
1.40
0.37
-
9.00
-
7.00
-
0.80
-
9.00
-
7.00
MAX
(mm)
-
-
1.60
0.15
1.45
0.45
-
-
-
-
-
Page 28 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only)

The ADC subsystem for the C8051F000/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX), a programmable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1). The AMUX, PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Register’s shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the ADCEN bit in the ADC Control register (ADC0CN, Figure 5.7) is set to 1. The ADC subsystem is in low power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be set to 1 in order to supply bias to the ADC.
Figure 5.1. 12-Bit ADC Functional Block Diagram
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
+
-
+
-
+
-
+
-
9-to-1 AMUX (SE or
DIFF)
X
+
-
ADCEN
AV+
AGND
12-Bit
SAR
ADC0LTLADC0LTHADC0GTLADC0GTH
AV+
ADC
SYSCLK
REF
12
ADC0LADC0H
Conversion Start
24
COMB LOGIC
12
ADWINT
TEMP
SENSOR
AGND
V
O
R
3
M
T
V
T
2
O
R
T
C
N
S
V
B
S
A
D
U
Y
)
(
w
ADCEN
AMX0CF
AIN67IC
AIN45IC
AIN23IC
AIN01IC
AMXAD3
AMX0SL
AMXAD1
AMXAD2
AMXAD0
ADCSC0
ADCSC1
ADCSC2
ADC0CF
AMPGN1
AMPGN2
AMPGN0
ADCTM
ADCINT
ADSTM1
ADBUSY
ADC0CN
ADLJST
ADWINT
ADSTM0

5.1. Analog Multiplexer and PGA

Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected to an on-board temperature sensor (temperature transfer function is shown in Figure 5.3). Note that the PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either the differential or single-ended mode. This allows the user to select the best measurement technique for each input channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 5.5), and the Configuration register AMX0CF (Figure 5.4). The table in Figure 5.5 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 5.6). The PGA can be software-programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 29
C8051F000/1/2/5/6/7
A
e
C8051F010/1/2/5/6/7

5.2. ADC Modes of Operation

The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or 16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate different system clock speeds.
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1. Writing a 1 to the ADBUSY bit of ADC0CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR;
4. A Timer 2 overflow (i.e. timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”. During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of ADBUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC0CN. Converted data is available in the ADC data word MSB and LSB registers, ADC0H, ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in Figure 5.9) depending on the programmed state of the ADLJST bit in the ADC0CN register.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2. Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;
3. Tracking is active only when the CNVSTR input is low;
4. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing
CNVSTR
(ADSTM[1:0]=10)
SAR Clocks
ADCTM=1
ADCTM=0
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
SAR Clocks
ADCTM=1
Page 30 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
SAR Clocks
ADCTM=0
. ADC Timing for External Trigger Sourc
12345678910111213141516
Low Power or
Convert
Track Convert Low Power Mode
Track Or Convert
Convert Track
B. ADC Timing for Internal Trigger Sources
1234567891011121314151617 18 19
Low Power or
Convert
Track or Convert
Track Convert Low Power Mode
12345678910111213141516
Convert Track
C8051F000/1/2/5/6/7
N
C8051F010/1/2/5/6/7
Figure 5.3. Temperature Sensor Transfer Function
(Volts)
1.000
0.900
0.800
0.700
0.600
0.500
V
= 0.00286(TEMPC) + 0.776
TEMP
for PGA Gain = 1
0-50 50 100
(Celsius)
Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - AIN67IC AIN45IC AIN23IC AIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBA
Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: AIN67IC: AIN6, AIN7 Input Pair Configuration Bit
Bit2: AIN45IC: AIN4, AIN5 Input Pair Configuration Bit
Bit1: AIN23IC: AIN2, AIN3 Input Pair Configuration Bit
Bit0: AIN01IC: AIN0, AIN1 Input Pair Configuration Bit
0: AIN6 and AIN7 are independent singled-ended inputs 1: AIN6, AIN7 are (respectively) +, - differential input pair
0: AIN4 and AIN5 are independent singled-ended inputs 1: AIN4, AIN5 are (respectively) +, - differential input pair
0: AIN2 and AIN3 are independent singled-ended inputs 1: AIN2, AIN3 are (respectively) +, - differential input pair
0: AIN0 and AIN1 are independent singled-ended inputs 1: AIN0, AIN1 are (respectively) +, - differential input pair
OTE: The ADC Data Word is in 2’s complement format for channels configured as differential.
SFR Address:
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 31
C8051F000/1/2/5/6/7
M
C8051F010/1/2/5/6/7
Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - -
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBB
Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMXAD3-0: AMUX Address Bits
0000-1111: ADC Inputs selected per chart below
AMXAD3-0
A
0000
X
0001
0 C
0010
F
0011
B I T
0100
S
0101
3
-
0110
0
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000 0001 0010 0011 0100 0101 0110 0111 1xxx
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN0 AIN1 AIN2 AIN3
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN0 AIN1 AIN2 AIN3
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AIN2 AIN3
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AIN2 AIN3 AIN4 AIN5
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AIN2 AIN3
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AMXAD3 AMXAD2 AMXAD1 AMXAD0
TEMP
SENSOR
TEMP
SENSOR
AIN4 AIN5 AIN6 AIN7
AIN4 AIN5 AIN6 AIN7
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
AIN4 AIN5
AIN4 AIN5
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
AIN6 AIN7
AIN6 AIN7
AIN6 AIN7
AIN6 AIN7
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
00000000
SFR Address:
Page 32 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ADCSC2 ADCSC1 ADCSC0 - - AMPGN2 AMPGN1 AMPGN0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBC
Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits
Bits4-3: UNUSED. Read = 00b; Write = don’t care Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain
000: SAR Conversion Clock = 1 System Clock 001: SAR Conversion Clock = 2 System Clocks 010: SAR Conversion Clock = 4 System Clocks 011: SAR Conversion Clock = 8 System Clocks 1xx: SAR Conversion Clock = 16 Systems Clocks (Note: the SAR Conversion Clock should be 2MHz)
000: Gain = 1 001: Gain = 2 010: Gain = 4 011: Gain = 8 10x: Gain = 16 11x: Gain = 0.5
01100000
SFR Address:
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 33
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 5.7. ADC0CN: ADC Control Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ADCEN ADCTM ADCINT ADBUSY ADSTM1 ADSTM0 ADWINT ADLJST 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7: ADCEN: ADC Enable Bit
Bit6: ADCTM: ADC Track Mode Bit
Bit5: ADCINT: ADC Conversion Complete Interrupt Flag (Must be cleared by software) 0: ADC has not completed a data conversion since the last time this flag was cleared
Bit4: ADBUSY: ADC Busy Bit Read
Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits
Bit1: ADWINT: ADC Window Compare Interrupt Flag
0: ADC Window Comparison Data match has not occurred 1: ADC Window Comparison Data match occurred Bit0: ADLJST: ADC Left Justify Data Bit 0: Data in ADC0H:ADC0L Registers is right justified 1: Data in ADC0H:ADC0L Registers is left justified
0: ADC Disabled. ADC is in low power shutdown. 1: ADC Enabled. ADC is active and ready for data conversions.
0: When the ADC is enabled, tracking is always done unless a conversion is in process 1: Tracking Defined by ADSTM1-0 bits ADSTM1-0: 00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks 01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks 10: ADC tracks only when CNVSTR input is logic low 11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
1: ADC has completed a data conversion
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled. 1: ADC Busy converting data Write 0: No effect 1: Starts ADC Conversion if ADSTM1-0 = 00b
00: ADC conversion started upon every write of 1 to ADBUSY 01: ADC conversions taken on every overflow of Timer 3 10: ADC conversion started upon every rising edge of CNVSTR 11: ADC conversions taken on every overflow of Timer 2
(Must be cleared by software)
(bit addressable)
SFR Address:
0xE8
Page 34 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBF
Bits7-0: ADC Data Word Bits For ADLJST = 1: Upper 8-bits of the 12-bit ADC Data Word. For ADLJST = 0: Bits7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4-bits of the
12-bit ADC Data Word.
Figure 5.9. ADC0L: ADC Data Word LSB Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBE
Bits7-0: ADC Data Word Bits For ADLJST = 1: Bits7-4 are the lower 4-bits of the 12-bit ADC Data Word. Bits3-0 will
For ADLJST = 0: Bits7-0 are the lower 8-bits of the 12-bit ADC Data Word.
always read 0.
NOTE: Resulting 12-bit ADC Data Word appears in the ADC Data Word Registers as follows:
ADC0H[3:0]:ADC0L[7:0], if ADLJST = 0
(ADC0H[7:4] will be sign extension of ADC0H.3 if a differential reading, otherwise = 0000b)
ADC0H[7:0]:ADC0L[7:4], if ADLJST = 1
(ADC0L[3:0] = 0000b)
EXAMPLE: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0CF=0x00, AMX0SL=0x00)
AIN0 – AGND (Volts)
REF x (4095/4096) 0x0FFF 0xFFF0 REF x ½ 0x0800 0x8000 REF x (2047/4096) 0x07FF 0x7FF0 0 0x0000 0x0000
EXAMPLE: ADC Data Word Conversion Map, AIN0-AIN1 Differential Input Pair
(AMX0CF=0x01, AMX0SL=0x00)
AIN0 – AIN1 (Volts)
REF x (2047/2048) 0x07FF 0x7FF0 0 0x0000 0x0000
-REF x (1/2048) 0xFFFF 0xFFF0
-REF 0xF800 0x8000
ADC0H:ADC0L
(ADLJST = 0)
ADC0H:ADC0L
(ADLJST = 0)
ADC0H:ADC0L
(ADLJST = 1)
ADC0H:ADC0L
(ADLJST = 1)
SFR Address:
SFR Address:
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 35
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

5.3. ADC Programmable Window Detector

The ADC programmable window detector is very useful in many applications. It continuously compares the ADC output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Figure 5.14 and Figure 5.15 show example comparisons for reference. Notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC5
Bits7-0: The high byte of the ADC Greater-Than Data Word.
SFR Address:
Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC4
Bits7-0: The low byte of the ADC Greater-Than Data Word.
Definition: ADC Greater-Than Data Word = ADC0GTH:ADC0GTL
SFR Address:
Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC7
Bits7-0: The high byte of the ADC Less-Than Data Word.
SFR Address:
Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC6
Bits7-0: These bits are the low byte of the ADC Less-Than Data Word.
Definition: ADC Less-Than Data Word = ADC0LTH:ADC0LTL
SFR Address:
Page 36 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
ADC Data
Word
0x0FFF
REF x (512/4096)
REF x (256/4096)
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
0
0x0000
ADWINT not affected
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0200, ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0200 and > 0x0100.
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
ADC Data
Word
0x07FF
ADWINT not affected
REF x (256/2048)
REF x (-1/2048)
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
-REF
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0100 and > 0xFFFF. (Two’s Complement math, 0xFFFF = -1.)
0xF800
ADWINT not affected
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
REF x (512/4096)
REF x (256/4096)
0
ADC Data
Word
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0x0200.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0100 or > 0x0200.
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
REF x (256/2048)
REF x (-1/2048)
-REF
ADC Data
Word
0x07FF
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
0xF800
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTH = 0xFFFF, ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0xFFFF or > 0x0100. (Two’s Complement math, 0xFFFF = -1.)
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 37
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
REF x (512/4096)
REF x (256/4096)
ADC Data
Word
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
0
0x0000
ADWINT not affected
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0x1000.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x2000 and > 0x1000.
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
ADC Data
Word
0x7FF0
ADWINT not affected
REF x (256/2048)
REF x (-1/2048)
0x1010
0x1000
0x0FF0
0x0000
0xFFF0
0xFFE0
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
-REF
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0xFFF0.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x1000 and > 0xFFF0. (Two’s Complement math.)
0x8000
ADWINT not affected
Input Voltage
(AD0 - AGND)
REF x (4095/4096)
REF x (512/4096)
REF x (256/4096)
0
ADC Data
Word
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
0x0000
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0x2000.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x1000 or > 0x2000.
Input Voltage
(AD0 - AD1)
REF x (2047/2048)
REF x (256/2048)
REF x (-1/2048)
-REF
ADC Data
Word
0x7FF0
0x1010
0x1000
0x0FF0
0x0000
0xFFF0
0xFFE0
0x8000
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTH = 0xFFF0, ADC0GTH:ADC0GTL = 0x1000.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0xFFF0 or > 0x1000. (Two’s Complement math.)
Page 38 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Table 5.1. 12-Bit ADC Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 12 bits Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient
DYNAMIC PERFORMANCE (10kHz sine-wave input, 0 to –1dB of full scale, 100ksps)
Signal-to-Noise Plus Distortion Total Harmonic Distortion Up to the 5th harmonic -75 dB Spurious-Free Dynamic Range
CONVERSION RATE
Conversion Time in SAR Clocks SAR Clock Frequency C8051F000, ‘F001, ‘F002
Track/Hold Acquisition Time Throughput Rate 100 ksps
ANALOG INPUTS
Voltage Conversion Range Single-ended Mode (AINn – AGND)
Input Voltage Any AINn pin AGND AV+ V Input Capacitance 10 pF
TEMPERATURE SENSOR
Linearity Absolute Accuracy Gain PGA Gain = 1 2.86 Gain Error (±1σ) Offset Offset Error (±1σ) PGA Gain = 1, Temp = 0°C
POWER SPECIFICATIONS
Power Supply Current (AV+ supplied to ADC) Power Supply Rejection
66 69 dB
80 dB
16 clocks
C8051F005, ‘F006, ‘F007
1.5
0 VREF
Differential Mode |(AINn+) – (AINm-)|
PGA Gain = 1 PGA Gain = 1, Temp = 0°C
Operating Mode, 100ksps 450 900
-3 ± 1
-7 ± 3
± 0.25
2.0
± 0.20
± 3
± 33.5
776 mV
± 8.51
± 0.3
± 1 ± 1
LSB LSB
2.5
- 1LSB
mV
mV/V
LSB LSB
ppm/°C
MHz MHz
µs
V
°C °C
mV/°C
µV/°C
µA
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 39
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7

6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only)

The ADC subsystem for the C8051F010/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX), a programmable gain amplifier (PGA), and a 100ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram in Figure 6.1). The AMUX, PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Register’s shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the ADCEN bit in the ADC Control register (ADC0CN, Figure 6.7) is set to 1. The ADC subsystem is in low power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be set to 1 in order to supply bias to the ADC.
Figure 6.1. 10-Bit ADC Functional Block Diagram
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
+
-
+
-
+
-
+
-
9-to-1 AMUX (SE or
DIFF)
X
+
-
ADCEN
AV+
AGND
10-Bit
SAR
TEMP
SENSOR
AGND
AMX0CF
AIN01IC
AIN23IC
AIN45IC
AIN67IC
AMX0SL
AMXAD2
AMXAD3
AMXAD0
AMXAD1
ADCSC0
ADCSC1
ADCSC2
ADC0CF
AMPGN2
AMPGN1
AMPGN0

6.1. Analog Multiplexer and PGA

Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected to an on-board temperature sensor (temperature transfer function is shown in Figure 6.3). Note that the PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either the differential or single-ended mode. This allows the user to select the best measurement technique for each input channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 6.5), and the Configuration register AMX0CF (Figure 6.4). The table in Figure 6.5 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 6.6). The PGA can be software-programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.
ADC0LTLADC0LTHADC0GTLADC0GTH
AV+
ADC
ADCEN
ADCTM
ADCINT
ADSTM1
ADBUSY
ADC0CN
SYSCLK
ADWINT
ADSTM0
REF
10
Conversion Start
ADLJST
ADC0LADC0H
20
COMB LOGIC
10
M
T
T
C
N
A
D
ADWINT
O
3
R
O
V
2
T
R
S
V
B
U
S
Y
V
w
)
(
Page 40 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7
A
e
C8051F010/1/2/5/6/7

6.2. ADC Modes of Operation

The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or 16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate different system clock speeds.
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1. Writing a 1 to the ADBUSY bit of ADC0CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR;
4. A Timer 2 overflow (i.e. timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”. During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of ADBUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC0CN. Converted data is available in the ADC data word MSB and LSB registers, ADC0H, ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in Figure 6.9) depending on the programmed state of the ADLJST bit in the ADC0CN register.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2. Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;
3. Tracking is active only when the CNVSTR input is low;
4. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing
CNVSTR
(ADSTM[1:0]=10)
SAR Clocks
ADCTM=1
ADCTM=0
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
SAR Clocks
ADCTM=1
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 41
SAR Clocks
ADCTM=0
. ADC Timing for External Trigger Sourc
12345678910111213141516
Low Power or
Convert
Track Convert Low Power Mode
Track Or Convert
Convert Track
B. ADC Timing for Internal Trigger Sources
1234567891011121314151617 18 19
Low Power or
Convert
Track or Convert
Track Convert Low Power Mode
12345678910111213141516
Convert Track
C8051F000/1/2/5/6/7
N
C8051F010/1/2/5/6/7
Figure 6.3. Temperature Sensor Transfer Function
(Volts)
1.000
0.900
0.800
0.700
0.600
0.500
V
= 0.00286(TEMPC) + 0.776
TEMP
for PGA Gain = 1
0-50 50 100
(Celsius)
Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - AIN67IC AIN45IC AIN23IC AIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBA
Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: AIN67IC: AIN6, AIN7 Input Pair Configuration Bit
Bit2: AIN45IC: AIN4, AIN5 Input Pair Configuration Bit
Bit1: AIN23IC: AIN2, AIN3 Input Pair Configuration Bit
Bit0: AIN01IC: AIN0, AIN1 Input Pair Configuration Bit
0: AIN6 and AIN7 are independent singled-ended inputs 1: AIN6, AIN7 are (respectively) +, - differential input pair
0: AIN4 and AIN5 are independent singled-ended inputs 1: AIN4, AIN5 are (respectively) +, - differential input pair
0: AIN2 and AIN3 are independent singled-ended inputs 1: AIN2, AIN3 are (respectively) +, - differential input pair
0: AIN0 and AIN1 are independent singled-ended inputs 1: AIN0, AIN1 are (respectively) +, - differential input pair
OTE: The ADC Data Word is in 2’s complement format for channels configured as differential.
SFR Address:
Page 42 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7
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C8051F010/1/2/5/6/7
Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - -
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBB
Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMXAD3-0: AMUX Address Bits
0000-1111: ADC Inputs selected per chart below
AMXAD3-0
A
0000
X
0001
0 C
0010
F
0011
B I T
0100
S
0101
3
-
0110
0
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000 0001 0010 0011 0100 0101 0110 0111 1xxx
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN0 AIN1 AIN2 AIN3
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN0 AIN1 AIN2 AIN3
+(AIN0)
-(AIN1)
AIN0 AIN1
+(AIN0)
-(AIN1)
AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AIN2 AIN3
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AIN2 AIN3 AIN4 AIN5
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AIN2 AIN3
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
AMXAD3 AMXAD2 AMXAD1 AMXAD0
TEMP
SENSOR
TEMP
SENSOR
AIN4 AIN5 AIN6 AIN7
AIN4 AIN5 AIN6 AIN7
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
AIN4 AIN5
AIN4 AIN5
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
AIN6 AIN7
AIN6 AIN7
AIN6 AIN7
AIN6 AIN7
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
TEMP
SENSOR
00000000
SFR Address:
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 43
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ADCSC2 ADCSC1 ADCSC0 - - AMPGN2 AMPGN1 AMPGN0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBC
Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits
Bits4-3: UNUSED. Read = 00b; Write = don’t care Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain
000: SAR Conversion Clock = 1 System Clock 001: SAR Conversion Clock = 2 System Clocks 010: SAR Conversion Clock = 4 System Clocks 011: SAR Conversion Clock = 8 System Clocks 1xx: SAR Conversion Clock = 16 Systems Clocks (Note: Conversion clock should be ≤ 2MHz.)
000: Gain = 1 001: Gain = 2 010: Gain = 4 011: Gain = 8 10x: Gain = 16 11x: Gain = 0.5
01100000
SFR Address:
Page 44 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7
Figure 6.7. ADC0CN: ADC Control Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ADCEN ADCTM ADCINT ADBUSY ADSTM1 ADSTM0 ADWINT ADLJST 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7: ADCEN: ADC Enable Bit
Bit6: ADCTM: ADC Track Mode Bit
Bit5: ADCINT: ADC Conversion Complete Interrupt Flag (Must be cleared by software) 0: ADC has not completed a data conversion since the last time this flag was cleared
Bit4: ADBUSY: ADC Busy Bit Read
Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits
Bit1: ADWINT: ADC Window Compare Interrupt Flag (Must be cleared by software) 0: ADC Window Comparison Data match has not occurred 1: ADC Window Comparison Data match occurred Bit0: ADLJST: ADC Left Justify Data Bit 0: Data in ADC0H:ADC0L Registers is right justified 1: Data in ADC0H:ADC0L Registers is left justified
0: ADC Disabled. ADC is in low power shutdown. 1: ADC Enabled. ADC is active and ready for data conversions.
0: When the ADC is enabled, tracking is always done unless a conversion is in process 1: Tracking Defined by ADSTM1-0 bits ADSTM1-0: 00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks 01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks 10: ADC tracks only when CNVSTR input is logic low 11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
1: ADC has completed a data conversion
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled. 1: ADC Busy converting data Write 0: No effect 1: Starts ADC Conversion if ADSTM1-0 = 00b
00: ADC conversion started upon every write of 1 to ADBUSY 01: ADC conversions taken on every overflow of Timer 3 10: ADC conversion started upon every rising edge of CNVSTR 11: ADC conversions taken on every overflow of Timer 2
(bit addressable)
SFR Address:
0xE8
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 45
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Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBF
Bits7-0: ADC Data Word Bits For ADLJST = 1: Upper 8-bits of the 10-bit ADC Data Word. For ADLJST = 0: Bits7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2-bits of the
10-bit ADC Data Word.
SFR Address:
Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xBE
Bits7-0: ADC Data Word Bits For ADLJST = 1: Bits7-6 are the lower 2-bits of the 10-bit ADC Data Word. Bits5-0 will
For ADLJST = 0: Bits7-0 are the lower 8-bits of the 10-bit ADC Data Word.
always read 0.
NOTE: Resulting 10-bit ADC Data Word appears in the ADC Data Word Registers as follows:
ADC0H[1:0]:ADC0L[7:0], if ADLJST = 0
(ADC0H[7:2] will be sign extension of ADC0H.1 if a differential reading, otherwise = 000000b)
ADC0H[7:0]:ADC0L[7:6], if ADLJST = 1
(ADC0L[5:0] = 000000b)
EXAMPLE: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0CF=0x00, AMX0SL=0x00)
AIN0 – AGND (Volts)
REF x (1023/1024) 0x03FF 0xFFC0 REF x ½ 0x0200 0x8000 REF x (511/1024) 0x01FF 0x7FC0 0 0x0000 0x0000
EXAMPLE: ADC Data Word Conversion Map, AIN0-AIN1 Differential Input Pair
(AMX0CF=0x01, AMX0SL=0x00)
AIN0 – AIN1 (Volts)
REF x (511/512) 0x01FF 0x7FC0 0 0x0000 0x0000
-REF x (1/512) 0xFFFF 0xFFC0
-REF 0xFE00 0x8000
ADC0H:ADC0L
(ADLJST = 0)
ADC0H:ADC0L
(ADLJST = 0)
ADC0H:ADC0L
(ADLJST = 1)
ADC0H:ADC0L
(ADLJST = 1)
SFR Address:
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6.3. ADC Programmable Window Detector

The ADC programmable window detector is very useful in many applications. It continuously compares the ADC output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Figure 6.14 and Figure 6.15 show example comparisons for reference. Notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC5
Bits7-0: The high byte of the ADC Greater-Than Data Word.
SFR Address:
Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC4
Bits7-0: The low byte of the ADC Greater-Than Data Word.
Definition: ADC Greater-Than Data Word = ADC0GTH:ADC0GTL
SFR Address:
Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC7
Bits7-0: The high byte of the ADC Less-Than Data Word.
SFR Address:
Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xC6
Bits7-0: These bits are the low byte of the ADC Less-Than Data Word.
Definition: ADC Less-Than Data Word = ADC0LTH:ADC0LTL
SFR Address:
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 47
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Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data
Input Voltage
(AD0 - AGND)
REF x (1023/1024)
ADC Data
Word
0x03FF
REF x (512/1024)
REF x (256/1024)
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
0
0x0000
ADWINT not affected
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0200, ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0200 and > 0x0100.
Input Voltage
(AD0 - AD1)
REF x (511/512)
ADC Data
Word
0x01FF
ADWINT not affected
REF x (256/512)
REF x (-1/512)
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
-REF
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0100 and > 0xFFFF. (Two’s Complement math, 0xFFFF = -1.)
0xFE00
ADWINT not affected
Input Voltage
(AD0 - AGND)
REF x (1023/1024)
REF x (512/1024)
REF x (256/1024)
0
ADC Data
Word
0x03FF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0x0200.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0100 or > 0x0200.
Input Voltage
(AD0 - AD1)
REF x (511/512)
REF x (256/512)
REF x (-1/512)
-REF
ADC Data
Word
0x01FF
0x0101
0x0100
0x00FF
0x0000
0xFFFF
0xFFFE
0xFE00
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTH = 0xFFFF, ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0xFFFF or > 0x0100. (Two’s Complement math, 0xFFFF = -1.)
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Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data
Input Voltage
(AD0 - AGND)
REF x (1023/1024)
ADC Data
Word
0xFFC0
REF x (512/1024)
REF x (256/1024)
0x8040
0x8000
0x7FC0
0x4040
0x4000
0x3FC0
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
0
0x0000
ADWINT not affected
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1, ADC0LTH:ADC0LTL = 0x8000, ADC0GTH:ADC0GTL = 0x4000.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x8000 and > 0x4000.
Input Voltage
(AD0 - AD1)
REF x (511/512)
ADC Data
Word
0x7FC0
ADWINT not affected
REF x (128/512)
REF x (-1/512)
0x2040
0x2000
0x1FC0
0x0000
0xFFC0
0xFF80
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
-REF
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0xFFC0.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x2000 and > 0xFFC0. (Two’s Complement math.)
0x8000
ADWINT not affected
Input Voltage
(AD0 - AGND)
REF x (1023/1024)
REF x (512/1024)
REF x (256/1024)
0
ADC Data
Word
0xFFC0
0x8040
0x8000
0x7FC0
0x4040
0x4000
0x3FC0
0x0000
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1, ADC0LTH:ADC0LTL = 0x4000, ADC0GTH:ADC0GTL = 0x8000.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x4000 or > 0x8000.
Input Voltage
(AD0 - AD1)
REF x (511/512)
REF x (128/512)
REF x (-1/512)
-REF
ADC Data
Word
0x7FC0
0x2040
0x2000
0x1FC0
0x0000
0xFFC0
0xFF80
0x8000
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT not affected
ADC0LTH:ADC0LTL
ADWINT=1
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTH = 0xFFC0, ADC0GTH:ADC0GTL = 0x2000.
An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0xFFC0 or > 0x2000. (Two’s Complement math.)
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 49
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Table 6.1. 10-Bit ADC Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 10 bits Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode
Offset Temperature Coefficient
DYNAMIC PERFORMANCE (10kHz sine-wave input, 0 to –1dB of full scale, 100ksps)
Signal-to-Noise Plus Distortion Total Harmonic Distortion Up to the 5th harmonic -70 dB Spurious-Free Dynamic Range
CONVERSION RATE
Conversion Time in SAR Clocks SAR Clock Frequency C8051F000, ‘F001, ‘F002
Track/Hold Acquisition Time Throughput Rate 100 ksps
ANALOG INPUTS
Voltage Conversion Range Single-ended Mode (AINn – AGND)
Input Voltage Any AINn pin AGND AV+ V Input Capacitance 10 pF
TEMPERATURE SENSOR
Linearity Absolute Accuracy Gain PGA Gain = 1 2.86 Gain Error (±1σ) Offset Offset Error (±1σ) PGA Gain = 1, Temp = 0°C
POWER SPECIFICATIONS
Power Supply Current (AV+ supplied to ADC) Power Supply Rejection
59 61 dB
80 dB
16 clocks
2.0
C8051F005, ‘F006, ‘F007
1.5
0 VREF
Differential Mode |(AINn+) – (AINm-)|
PGA Gain = 1 PGA Gain = 1, Temp = 0°C
Operating Mode, 100ksps 450 900
776 mV
± ½ ± 1 ± ½ ± 1
± 0.5
-1.5 ±
0.5
± 0.25
- 1LSB
± 0.20
± 3
± 33.5
± 8.51
± 0.3
LSB LSB
2.5
mV
mV/V
LSB LSB
ppm/°C
MHz MHz
µs
V
°C °C
mV/°C
µV/°C
µA
Page 50 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
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7. DACs, 12 BIT VOLTAGE MODE

The C8051F000 MCU family has two 12-bit voltage-mode Digital to Analog Converters. Each DAC has an output swing of 0V to VREF-1LSB for a corresponding input code range of 0x000 to 0xFFF. Using DAC0 as an example, the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers. Data is latched into DAC0 after a write to the corresponding DAC0H register, so the write sequence should be DAC0L followed by DAC0H if the full 12-bit resolution is required. The DAC can be used in 8-bit mode by initializing DAC0L to the desired value (typically 0x00), and writing data to only DAC0H with the data shifted to the left. DAC0 Control Register (DAC0CN) provides a means to enable/disable DAC0 and to modify its input data formatting.
The DAC0 enable/disable function is controlled by the DAC0EN bit (DAC0CN.7). Writing a 1 to DAC0EN enables DAC0 while writing a 0 to DAC0EN disables DAC0. While disabled, the output of DAC0 is maintained in a high­impedance state, and the DAC0 supply current falls to 1µA or less. Also, the Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be set to 1 in order to supply bias to DAC0. The voltage reference for DAC0 must also be set properly (see Section 9).
In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data within the DAC input registers. This action would typically require one or more load and shift operations, adding software overhead and slowing DAC throughput. To alleviate this problem, the data-formatting feature provides a means for the user to program the orientation of the DAC0 data word within data registers DAC0H and DAC0L. The three DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data word orientations as shown in the DAC0CN register definition.
DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and DAC1 are given in Table 7.1.
Figure 7.1. DAC Functional Block Diagram
DAC0EN
DAC0DF2
DAC0CN
DAC0DF1 DAC0DF0
DAC1EN
DAC1DF2
DAC1CN
DAC1DF1 DAC1DF0
REF
8
DAC0HDAC0L
8
8
DAC1HDAC1L
8
Dig. MUX
Dig. MUX
12
12
DAC0
REF
DAC1
AV+
+
-
AGND
AV+
+
-
AGND
DAC0
DAC1
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 51
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Figure 7.2. DAC0H: DAC0 High Byte Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xD3
Bits7-0: DAC0 Data Word Most Significant Byte.
SFR Address:
Figure 7.3. DAC0L: DAC0 Low Byte Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xD2
Bits7-0: DAC0 Data Word Least Significant Byte.
SFR Address:
Figure 7.4. DAC0CN: DAC0 Control Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
DAC0EN
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xD4
Bit7: DAC0EN: DAC0 Enable Bit
Bits6-3: UNUSED. Read = 0000b; Write = don’t care Bits2-0: DAC0DF2-0: DAC0 Data Format Bits
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low power shutdown mode. 1: DAC0 Enabled. DAC0 Output is pin active; DAC0 is operational.
000: The most significant nybble of the DAC0 Data Word is in DAC0H[3:0], while the least
MSB LSB
001: The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least
MSB LSB
- - - -
significant byte is in DAC0L.
DAC0H DAC0L
significant 7-bits is in DAC0L[7:1].
DAC0H DAC0L
010: The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least
significant 6-bits is in DAC0L[7:2].
DAC0H DAC0L
MSB LSB
011: The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least
significant 5-bits is in DAC0L[7:3].
DAC0H DAC0L
MSB LSB
1xx: The most significant byte of the DAC0 Data Word is in DAC0H, while the least
significant nybble is in DAC0L[7:4].
DAC0H DAC0L
MSB LSB
DAC0DF2 DAC0DF1 DAC0DF0
00000000
SFR Address:
Page 52 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
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Figure 7.5. DAC1H: DAC1 High Byte Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xD6
Bits7-0: DAC1 Data Word Most Significant Byte.
Figure 7.6. DAC1L: DAC1 Low Byte Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xD5
Bits7-0: DAC1 Data Word Least Significant Byte.
SFR Address:
SFR Address:
Figure 7.7. DAC1CN: DAC1 Control Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
DAC1EN - - - - DAC1DF2 DAC1DF1 DAC1DF0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xD7
Bit7: DAC1EN: DAC1 Enable Bit
Bits6-3: UNUSED. Read = 0000b; Write = don’t care Bits2-0: DAC1DF2-0: DAC1 Data Format Bits
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low power shutdown mode. 1: DAC1 Enabled. DAC1 Output is pin active; DAC1 is operational.
000: The most significant nybble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.
MSB LSB
001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits is in DAC1L[7:1].
DAC1H DAC1L
DAC1H DAC1L
MSB LSB
010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits is in DAC1L[7:2].
DAC1H DAC1L
MSB LSB
011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits is in DAC1L[7:3].
DAC1H DAC1L
MSB LSB
1xx: The most significant byte of the DAC1 Data Word is in DAC1H, while the least
significant nybble is in DAC1L[7:4].
DAC1H DAC1L
MSB LSB
00000000
SFR Address:
4.2002; Rev. 1.4 CYGNAL Integrated Products, Inc. 2002 Page 53
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Table 7.1. DAC Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, REF = 2.40V (REFBE=0), No Output Load unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 12 bits Integral Nonlinearity For Data Word Range 0x014 to 0xFEB Differential Nonlinearity Guaranteed Monotonic (codes 0x014 to
0xFEB)
Output Noise No Output Filter
100kHz Output Filter
10kHz Output Filter Offset Error Data Word = 0x014 Offset Tempco 6 Gain Error Gain-Error Tempco 10
VDD Power-Supply Rejection Ratio
Output Impedance in Shutdown Mode
Output Current
Output Short Circuit Current
DYNAMIC PERFORMANCE
Voltage Output Slew Rate Load = 40pF 0.44 Output Settling Time To ½
LSB Output Voltage Swing 0 REF-
Startup Time DAC Enable asserted 10
ANALOG OUTPUTS
Load Regulation IL = 0.01mA to 0.3mA at code 0xFFF
CURRENT CONSUMPTION (each DAC)
Power Supply Current (AV+ supplied to DAC)
-60 dB
DACnEN=0 100
Data Word = 0xFFF 15 mA
Load = 40pF, Output swing from code
0xFFF to 0x014
Data Word = 0x7FF 110 400
250
10
60 ppm
±2
128
41
±3 ±30
±20 ±60
±300
LSB
±1
1LSB
LSB
µVrms
mV
ppm/°C
mV
ppm/°C
k
µA
V/µs
µs
V
µs
µA
Page 54 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
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8. COMPARATORS
The MCU family has two on-chip analog voltage comparators as shown in Figure 8.1. The inputs of each Comparator are available at the package pins. The output of each comparator is optionally available at the package pins via the I/O crossbar (see Section 15.1). When assigned to package pins, each comparator output can be programmed to operate in open drain or push-pull modes (see section 15.3).
The hysteresis of each comparator is software-programmable via its respective Comparator control register (CPT0CN, CPT1CN). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The output of the comparator can be polled in software, or can be used as an interrupt source. Each comparator can be individually enabled or disabled (shutdown). When disabled, the comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, its interrupt capability is suspended and its supply current falls to less than 1µA. Comparator 0 inputs can be externally driven from -0.25V to (AV+) + 0.25V without damage or upset.
The Comparator 0 hysteresis is programmed using bits 3-0 in the Comparator 0 Control Register CPT0CN (shown in Figure 8.3). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits. As shown in Figure 8.2, settings of 10, 4 or 2mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section 10.4). The CP0FIF flag is set upon a Comparator 0 falling-edge interrupt, and the CP0RIF flag is set upon the Comparator 0 rising-edge interrupt. Once set, these bits remain set until cleared by the CPU. The Output State of Comparator 0 can be obtained at any time by reading the CP0OUT bit. Note the comparator output and interrupt should be ignored until the comparator settles after power-up. Comparator 0 is enabled by setting the CP0EN bit, and is disabled by clearing this bit. Note there is a 20usec settling time for the comparator output to stabilize after setting the CP0EN bit or a power-up. Comparator 0 can also be programmed as a reset source. For details, see Section 13.
The operation of Comparator 1 is identical to that of Comparator 0, except the Comparator 1 is controlled by the CPT1CN Register (Figure 8.4). Comparator 1 can not be programmed as a reset source. Also, the input pins for Comparator 1 are not pinned out on the F002, F007, F012, or F017 devices. The complete electrical specifications for the Comparators are given in Table 8.1.
Figure 8.1. Comparator Functional Block Diagram
CPT0CN
CPT1CN
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
AV+
Reset
Decision
+
-
AGND
AV+
+
-
AGND
Tree
SET
SET
Q
D
D
Q
CLR
CLR
(SYNCHRONIZER)
SET
SET
D
D
Q
Q
CLR
CLR
(SYNCHRONIZER)
Q
Crossbar
Q
Interrupt
Handler
Q
Crossbar
Q
Interrupt
Handler
CP0+
CP0-
CP1+
CP1-
not available on F002, F007, F012, and F017
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Figure 8.2. Comparator Hysteresis Plot
VIN+
CP0+
CP0-
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYSP Bits)
INPUTS
VIN-
VIN+
OUTPUT
V
OL
Positive Hysteresis
Disabled
+
CP0
_
V
OH
OUT
Maximum
Positive Hysteresis
Negative Hysteresis
Disabled
Negative Hysteresis Voltage
(Programmed by CP0HYSN Bits)
Maximum
Negative Hysteresis
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Figure 8.3. CPT0CN: Comparator 0 Control Register
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7: CP0EN: Comparator 0 Enable Bit
Bit6: CP0OUT: Comparator 0 Output State Flag
Bit5: CP0RIF: Comparator 0 Rising-Edge Interrupt Flag
1: Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared Bit4: CP0FIF: Comparator 0 Falling-Edge Interrupt Flag
1: Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared Bit3-2: CP0HYP1-0: Comparator 0 Positive Hysteresis Control Bits
Bit1-0: CP0HYN1-0: Comparator 0 Negative Hysteresis Control Bits
0: Comparator 0 Disabled. 1: Comparator 0 Enabled.
0: Voltage on CP0+ < CP0- 1: Voltage on CP0+ > CP0-
0: No Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared
0: No Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared
00: Positive Hysteresis Disabled 01: Positive Hysteresis = 2mV 10: Positive Hysteresis = 4mV 11: Positive Hysteresis = 10mV
00: Negative Hysteresis Disabled 01: Negative Hysteresis = 2mV 10: Negative Hysteresis = 4mV 11: Negative Hysteresis = 10mV
SFR Address:
0x9E
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Figure 8.4. CPT1CN: Comparator 1 Control Register
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7: CP1EN: Comparator 1 Enable Bit
Bit6: CP1OUT: Comparator 1 Output State Flag
Bit5: CP1RIF: Comparator 1 Rising-Edge Interrupt Flag
1: Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared Bit4: CP1FIF: Comparator 1 Falling-Edge Interrupt Flag
1: Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared Bit3-2: CP1HYP1-0: Comparator 1 Positive Hysteresis Control Bits
Bit1-0: CP1HYN1-0: Comparator 1 Negative Hysteresis Control Bits
0: Comparator 1 Disabled. 1: Comparator 1 Enabled.
0: Voltage on CP1+ < CP1- 1: Voltage on CP1+ > CP1-
0: No Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared
0: No Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared
00: Positive Hysteresis Disabled 01: Positive Hysteresis = 2mV 10: Positive Hysteresis = 4mV 11: Positive Hysteresis = 10mV
00: Negative Hysteresis Disabled 01: Negative Hysteresis = 2mV 10: Negative Hysteresis = 4mV 11: Negative Hysteresis = 10mV
SFR Address:
0x9F
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Table 8.1. Comparator Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, -40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Response Time1 (CP+) – (CP-) = 100mV (Note 1) 4 Response Time2 (CP+) – (CP-) = 10mV (Note 1) 12 Common Mode Rejection
Ratio Positive Hysteresis1 CPnHYP1-0 = 00 0 1 mV Positive Hysteresis2 CPnHYP1-0 = 01 2 4.5 7 mV Positive Hysteresis3 CPnHYP1-0 = 10 4 9 13 mV Positive Hysteresis4 CPnHYP1-0 = 11 10 17 25 mV Negative Hysteresis1 CPnHYN1-0 = 00 0 1 mV Negative Hysteresis2 CPnHYN1-0 = 01 2 4.5 7 mV Negative Hysteresis3 CPnHYN1-0 = 10 4 9 13 mV Negative Hysteresis4 CPnHYN1-0 = 11 10 17 25 mV Inverting or Non-inverting Input Voltage Range Input Capacitance 7 pF Input Bias Current -5 0.001 +5 nA Input Offset Voltage -10 +10 mV
POWER SUPPLY
Power-up Time CPnEN from 0 to 1 20 Power Supply Rejection 0.1 1 mV/V Supply Current Operating Mode (each comparator) at DC 1.5 10
Note 1: CPnHYP1-0 = CPnHYN1-0 = 00.
1.5 4 mV/V
-0.25 (AV+) + 0.25
µs µs
V
µs
µA
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9. VOLTAGE REFERENCE
The voltage reference circuit consists of a 1.2V, 15ppm/°C (typical) bandgap voltage reference generator and a gain­of-two output buffer amplifier. The reference voltage on VREF can be connected to external devices in the system, as long as the maximum load seen by the VREF pin is less than 200µA to AGND (see Figure 9.1).
If a different reference voltage is required, an external reference can be connected to the VREF pin and the internal bandgap and buffer amplifier disabled in software. The external reference voltage must still be less than AV+ -0.3V. The Reference Control Register, REF0CN (defined in Figure 9.2), provides the means to enable or disable the bandgap and buffer amplifier. The BIASE bit in REF0CN enables the bias circuitry for the ADC and DACs while the REFBE bit enables the bandgap reference and buffer amplifier which drive the VREF pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1uA (typical) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator, BIASE and REFBE must both be set to 1. If an external reference is used, REFBE must be set to 0 and BIASE must be set to 1. If neither the ADC nor the DAC are being used, both of these bits can be set to 0 to conserve power. The electrical specifications for the Voltage Reference are given in Table 9.1.
The temperature sensor connects to the highest order input of the A/D converter’s input multiplexer (see Figure 5.1 and Figure 5.5 for details). The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the sensor while disabled result in meaningless data.
External Equivalent
Load Circuit
200uA
(max)
AV+
AGND
AGND
Figure 9.1. Voltage Reference Functional Block Diagram
R1
RLOAD
External
Voltage
Reference
Circuit
VREF
REF0CN
TEMPE
BIASE
REFBE
EN
EN
Bias
Generator
EN
2.4V
Reference
Temp
Sensor
AGND
AGND
(to Analog Mux)
(Bias to ADC and DAC)
(to ADC and DAC)
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Figure 9.2. REF0CN: Reference Control Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - TEMPE BIASE REFBE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits7-3: UNUSED. Read = 00000b; Write = don’t care Bit2: TEMPE: Temperature Sensor Enable Bit 0: Internal Temperature Sensor Off. 1: Internal Temperature Sensor On. Bit1: BIASE: Bias Enable Bit for ADC and DAC’s 0: Internal Bias Off. 1: Internal Bias On (required for use of ADC or DAC’s). Bit0: REFBE: Internal Voltage Reference Buffer Enable Bit
1: Internal Reference Buffer On. System reference provided by internal voltage reference.
0: Internal Reference Buffer Off. System reference can be driven from external source on
VREF pin.
SFR Address:
0xD1
Table 9.1. Reference Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, -40°C to +85°C unless otherwise specified.
PARAMETER
INTERNAL REFERENCE (REFBE = 1)
Output Voltage VREF Short Circuit Current 30 mA VREF Temperature
Coefficient Load Regulation VREF Turn-on Time1 VREF Turn-on Time2 VREF Turn-on Time3 no bypass cap 10
EXTERNAL REFERENCE (REFBE = 0)
Input Voltage Range 1.00 (AV+)
Input Current 0 1
Note 1: The reference can only source current. When driving an external load, it is recommended to add a load
resistor to AGND.
25°C ambient
15
Load = (0-to-200µA) to AGND (Note 1)
4.7µF tantalum, 0.1µF ceramic bypass
0.1µF ceramic bypass
CONDITIONS MIN TYP MAX UNITS
2.34 2.43 2.50 V
ppm/°C
0.5 2 ms 20
– 0.3V
ppm/µA
µs µs
V
µA
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10. CIP-51 CPU
The MCUs’ system CPU is the CIP-51. The CIP-51 is fully compatible with the MCS-51TM instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section
19), a full-duplex UART (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section 10.3), and four byte-wide I/O Ports (see description in Section 14). The CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces directly with the MCUs’ analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram). The CIP-51 includes the following features:
- Fully Compatible with MCS-51 Instruction Set
- 25 MIPS Peak Throughput with 25MHz Clock
- 0 to 25MHz Clock Frequency (on ‘F0x5/6/7)
- Four Byte-Wide I/O Ports
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Circuitry
- Program and Data Memory Security
Figure 10.1. CIP-51 Block Diagram
D8
ACCUMULATOR
D8
TMP1 TMP2
PSW
DATA BUS
ALU
D8
D8
RESET
CLOCK
STOP
IDLE
BUFFER
DATA POINTER
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
CONTROL
LOGIC
POWER CONTROL
REGISTER
DATA BUS
D8
DATA BUS
D8
D8
DATA BUS
D8
B REGISTER
ADDRESS
REGISTER
D8
INTERFACE
D8
MEMORY
A16
INTERFACE
D8
INTERRUPT
INTERFACE
D8
D8
SRAM
SFR BUS
D8
D8
STACK POINTER
SRAM
(256 X 8)
D8
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
MEM_ADDRESS
MEM_CONTROL
MEM_WRITE_DATA
MEM_READ_DATA
SYSTEM_IRQs
EMULATION_IRQ
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Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles required to execute them is as follows:
Instructions
Clocks to Execute
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the Flash program memory and communication with on-chip debug support circuitry. The reprogrammable Flash can also be read and changed a single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support circuitry facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints and watch points, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program’s call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers, or other on-chip resources.
The CIP-51 is supported by development tools from Cygnal Integrated Products and third party vendors. Cygnal provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE’s debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.
10.1. INSTRUCTION SET
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
10.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 10.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
10.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory. In the CIP-51, the MOVX instruction can access the on-chip program memory space implemented as reprogrammable Flash memory using the control bits in the PSCTL register (see Figure 11.1). This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. For the products with RAM mapped into external data memory space (C8051F005/06/07/15/16/17), MOVX is still used to read/write this memory with the PSCTL register configured for accessing the external data memory space. Refer to Section 11 (Flash Memory) for further details.
26 50 5 14 7 3 1 2 1
1 2 2/3 3 3/4 4 4/5 5 8
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Table 10.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes
ARITHMETIC OPERATIONS
ADD A,Rn Add register to A 1 1 ADD A,direct Add direct byte to A 2 2 ADD A,@Ri Add indirect RAM to A 1 2 ADD A,#data Add immediate to A 2 2 ADDC A,Rn Add register to A with carry 1 1 ADDC A,direct Add direct byte to A with carry 2 2 ADDC A,@Ri Add indirect RAM to A with carry 1 2 ADDC A,#data Add immediate to A with carry 2 2 SUBB A,Rn Subtract register from A with borrow 1 1 SUBB A,direct Subtract direct byte from A with borrow 2 2 SUBB A,@Ri Subtract indirect RAM from A with borrow 1 2 SUBB A,#data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC @Ri Increment indirect RAM 1 2 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC @Ri Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 8 DA A Decimal Adjust A 1 1
LOGICAL OPERATIONS
ANL A,Rn AND Register to A 1 1 ANL A,direct AND direct byte to A 2 2 ANL A,@Ri AND indirect RAM to A 1 2 ANL A,#data AND immediate to A 2 2 ANL direct,A AND A to direct byte 2 2 ANL direct,#data AND immediate to direct byte 3 3 ORL A,Rn OR Register to A 1 1 ORL A,direct OR direct byte to A 2 2 ORL A,@Ri OR indirect RAM to A 1 2 ORL A,#data OR immediate to A 2 2 ORL direct,A OR A to direct byte 2 2 ORL direct,#data OR immediate to direct byte 3 3 XRL A,Rn Exclusive-OR Register to A 1 1 XRL A,direct Exclusive-OR direct byte to A 2 2 XRL A,@Ri Exclusive-OR indirect RAM to A 1 2 XRL A,#data Exclusive-OR immediate to A 2 2 XRL direct,A Exclusive-OR A to direct byte 2 2 XRL direct,#data Exclusive-OR immediate to direct byte 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through carry 1 1
Clock
Cycles
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Mnemonic Description Bytes
RR A Rotate A right 1 1 RRC A Rotate A right through carry 1 1 SWAP A Swap nibbles of A 1 1
DATA TRANSFER
MOV A,Rn Move register to A 1 1 MOV A,direct Move direct byte to A 2 2 MOV A,@Ri Move indirect RAM to A 1 2 MOV A,#data Move immediate to A 2 2 MOV Rn,A Move A to register 1 1 MOV Rn,direct Move direct byte to register 2 2 MOV Rn,#data Move immediate to register 2 2 MOV direct,A Move A to direct byte 2 2 MOV direct,Rn Move register to direct byte 2 2 MOV direct,direct Move direct byte to direct 3 3 MOV direct,@Ri Move indirect RAM to direct byte 2 2 MOV direct,#data Move immediate to direct byte 3 3 MOV @Ri,A Move A to indirect RAM 1 2 MOV @Ri,direct Move direct byte to indirect RAM 2 2 MOV @Ri,#data Move immediate to indirect RAM 2 2 MOV DPTR,#data16 Load data pointer with 16-bit constant 3 3 MOVC A,@A+DPTR Move code byte relative DPTR to A 1 3 MOVC A,@A+PC Move code byte relative PC to A 1 3 MOVX A,@Ri Move external data (8-bit address) to A 1 3 MOVX @Ri,A Move A to external data (8-bit address) 1 3 MOVX A,@DPTR Move external data (16-bit address) to A 1 3 MOVX @DPTR,A Move A to external data (16-bit address) 1 3 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A,Rn Exchange register with A 1 1 XCH A,direct Exchange direct byte with A 2 2 XCH A,@Ri Exchange indirect RAM with A 1 2 XCHD A,@Ri Exchange low nibble of indirect RAM with A 1 2
BOOLEAN MANIPULATION
CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C,bit AND direct bit to carry 2 2 ANL C,/bit AND complement of direct bit to carry 2 2 ORL C,bit OR direct bit to carry 2 2 ORL C,/bit OR complement of direct bit to carry 2 2 MOV C,bit Move direct bit to carry 2 2 MOV bit,C Move carry to direct bit 2 2 JC rel Jump if carry is set 2 2/3 JNC rel Jump if carry not set 2 2/3 JB bit,rel Jump if direct bit is set 3 3/4 JNB bit,rel Jump if direct bit is not set 3 3/4 JBC bit,rel Jump if direct bit is set and clear bit 3 3/4
Clock
Cycles
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Mnemonic Description Bytes
PROGRAM BRANCHING
ACALL addr11 Absolute subroutine call 2 3 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 5 RETI Return from interrupt 1 5 AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4 SJMP rel Short jump (relative address) 2 3 JMP @A+DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if A equals zero 2 2/3 JNZ rel Jump if A does not equal zero 2 2/3 CJNE A,direct,rel Compare direct byte to A and jump if not equal 3 3/4 CJNE A,#data,rel Compare immediate to A and jump if not equal 3 3/4
CJNE Rn,#data,rel Compare immediate to register and jump if not
equal
CJNE @Ri,#data,rel Compare immediate to indirect and jump if not
equal DJNZ Rn,rel Decrement register and jump if not zero 2 2/3 DJNZ direct,rel Decrement direct byte and jump if not zero 3 3/4 NOP No operation 1 1
C8051F010/1/2/5/6/7
Clock
Cycles
3 3/4
3 4/5
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through register R0-R1
rel - 8-bit, signed (two’s compliment) offset relative to the first byte of the following instruction. Used by SJMP
and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data 16 - 16-bit constant
bit - Direct-addressed bit in Data RAM or SFR.
addr 11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte
page of program memory as the first byte of the following instruction.
addr 16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 64K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980.
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10.2. MEMORY ORGANIZATION
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. There are 256 bytes of internal data memory and 64K bytes of internal program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in Figure 10.2.
10.2.1. Program Memory
The CIP-51 has a 64K-byte program memory space. The MCU implements 32896 bytes of this program memory space as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x807F. Note: 512 bytes (0x7E00 – 0x7FFF) of this memory are reserved for factory use and are not available for user program storage.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section 11 (Flash Memory) for further details.
10.2.2. Data Memory
The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may be addressed as bytes or as 128 bit locations accessible with the direct-bit addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F will access the upper 128 bytes of data memory. Figure
10.2 illustrates the data memory organization of the CIP-51.
The C8051F005/06/07/15/16/17 also have 2048 bytes of RAM in the external data memory space of the CIP-51, accessible using the MOVX instruction. Refer to Section 12 (External RAM) for details.
10.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general­purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in Figure 10.6). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
10.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the user Carry flag.
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Figure 10.2. Memory Map
0x807F
0x8000
0x7FFF
0x7E00
0x7DFF
PROGRAM MEMORY
128 Byte ISP FLASH
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM (Direct and Indirect Addressing)
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
0xF800
(same 2048 byte RAM block )
0x17FF
0x1000
0x0FFF
0x0800
0x07FF
0x0000
(same 2048 byte RAM block )
(same 2048 byte RAM block )
RAM - 2048 Bytes
(accessable using MOVX
command)
The same 2048 byte RAM block can be addressed on 2k boundaries throughout the 64k External Data Memory space.
10.2.5. Stack
A programmer’s stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes.
The MCUs also have built-in hardware for a stack record. The stack record is a 32-bit shift register, where each Push or increment SP pushes one record bit onto the register, and each Call or interrupt pushes two record bits onto the register. (A Pop or decrement SP pops one record bit, and a Return pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the Stack, and can notify the debug software even with the MCU running full-speed debug.
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10.3. SPECIAL FUNCTION REGISTERS

The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51’s resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 10.3 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed any time the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 10.3, for a detailed description of each register.
Table 10.2. Special Function Register Memory Map
SPI0CN PCA0H PCA0CPH0 PCA0CPH1 PCA0CPH2 PCA0CPH3 PCA0CPH4 WDTCN
F8
B EIP1 EIP2
F0
ADC0CN PCA0L PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPL3 PCA0CPL4 RSTSRC
E8
ACC XBR0 XBR1 XBR2 EIE1 EIE2
E0 D8 D0
A8 A0
Bit Addressable
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
PSW REF0CN DAC0L DAC0H DAC0CN DAC1L DAC1H DAC1CN
T2CON RCAP2L RCAP2H TL2 TH2 SMB0CR
C8
SMB0CN SMB0STA SMB0DAT SMB0ADR ADC0GTL ADC0GTH ADC0LTL ADC0LTH
C0
IP AMX0CF AMX0SL ADC0CF ADC0L ADC0H
B8
P3 OSCXCN OSCICN FLSCL FLACL***
B0
IE PRT1IF EMI0CN***
P2 PRT0CF PRT1CF PRT2CF PRT3CF
SCON SBUF SPI0CFG SPI0DAT SPI0CKR CPT0CN CPT1CN
98
P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H
90
TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
88
P0 SP DPL DPH PCON
80
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
Table 10.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved. * Refers to a register in the C8051F000/1/2/5/6/7 only. ** Refers to a register in the C8051F010/1/2/5/6/7 only. *** Refers to a register in the C8051F005/06/07/15/16/17 only.
Address Register
0xE0 ACC Accumulator 75
0xBC ADC0CF ADC Configuration 33*, 42**
0xE8 ADC0CN ADC Control 34*, 45**
0xC5 ADC0GTH ADC Greater-Than Data Word (High Byte) 36*, 47**
0xC4 ADC0GTL ADC Greater-Than Data Word (Low Byte) 36*, 47**
0xBF ADC0H ADC Data Word (High Byte) 35*, 46**
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Description Page No.
C8051F000/1/2/5/6/7
Address Register
0xBE ADC0L ADC Data Word (Low Byte) 35*, 46**
0xC7 ADC0LTH ADC Less-Than Data Word (High Byte) 36*, 47**
0xC6 ADC0LTL ADC Less-Than Data Word (Low Byte) 36*, 47**
0xBA AMX0CF ADC MUX Configuration 31*, 42**
0xBB AMX0SL ADC MUX Channel Selection 32*, 43**
0xF0 B B Register 75
0x8E CKCON Clock Control 142
0x9E CPT0CN Comparator 0 Control 56
0x9F CPT1CN Comparator 1 Control 58
0xD4 DAC0CN DAC 0 Control 52
0xD3 DAC0H DAC 0 Data Word (High Byte) 52
0xD2 DAC0L DAC 0 Data Word (Low Byte) 52
0xD7 DAC1CN DAC 1 Control 53
0xD6 DAC1H DAC 1 Data Word (High Byte) 53
0xD5 DAC1L DAC 1 Data Word (Low Byte) 53
0x83 DPH Data Pointer (High Byte) 73
0x82 DPL Data Pointer (Low Byte) 73
0xE6 EIE1 Extended Interrupt Enable 1 80
0xE7 EIE2 Extended Interrupt Enable 2 81
0xF6 EIP1 External Interrupt Priority 1 82
0xF7 EIP2 External Interrupt Priority 2 83
0xAF EMI0CN External Memory Interface Control 91***
0xB7 FLACL Flash Access Limit 89***
0xB6 FLSCL Flash Memory Timing Prescaler 90
0xA8 IE Interrupt Enable 78
0xB8 IP Interrupt Priority Control 79
0xB2 OSCICN Internal Oscillator Control 99
0xB1 OSCXCN External Oscillator Control 100
0x80 P0 Port 0 Latch 108
0x90 P1 Port 1 Latch 109
0xA0 P2 Port 2 Latch 110
0xB0 P3 Port 3 Latch 111
0xD8 PCA0CN Programmable Counter Array 0 Control 158
0xFA PCA0CPH0 PCA Capture Module 0 Data Word (High Byte) 161
0xFB PCA0CPH1 PCA Capture Module 1 Data Word (High Byte) 161
0xFC PCA0CPH2 PCA Capture Module 2 Data Word (High Byte) 161
0xFD PCA0CPH3 PCA Capture Module 3 Data Word (High Byte) 161
0xFE PCA0CPH4 PCA Capture Module 4 Data Word (High Byte) 161
0xEA PCA0CPL0 PCA Capture Module 0 Data Word (Low Byte) 161
0xEB PCA0CPL1 PCA Capture Module 1 Data Word (Low Byte) 161
0xEC PCA0CPL2 PCA Capture Module 2 Data Word (Low Byte) 161
Description Page No.
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Address Register
0xED PCA0CPL3 PCA Capture Module 3 Data Word (Low Byte) 161
0xEE PCA0CPL4 PCA Capture Module 4 Data Word (Low Byte) 161
0xDA PCA0CPM0 Programmable Counter Array 0 Capture/Compare 0 160
0xDB PCA0CPM1 Programmable Counter Array 0 Capture/Compare 1 160
0xDC PCA0CPM2 Programmable Counter Array 0 Capture/Compare 2 160
0xDD PCA0CPM3 Programmable Counter Array 0 Capture/Compare 3 160
0xDE PCA0CPM4 Programmable Counter Array 0 Capture/Compare 4 160
0xF9 PCA0H PCA Counter/Timer Data Word (High Byte) 161
0xE9 PCA0L PCA Counter/Timer Data Word (Low Byte) 161
0xD9 PCA0MD Programmable Counter Array 0 Mode 159
0x87 PCON Power Control 85
0xA4 PRT0CF Port 0 Configuration 108
0xA5 PRT1CF Port 1 Configuration 109
0xAD PRT1IF Port 1 Interrupt Flags 109
0xA6 PRT2CF Port 2 Configuration 110
0xA7 PRT3CF Port 3 Configuration 111
0x8F PSCTL Program Store RW Control 87
0xD0 PSW Program Status Word 74
0xCB RCAP2H Counter/Timer 2 Capture (High Byte) 149
0xCA RCAP2L Counter/Timer 2 Capture (Low Byte) 149
0xD1 REF0CN Voltage Reference Control Register 61
0xEF RSTSRC Reset Source Register 96
0x99 SBUF Serial Data Buffer (UART) 134
0x98 SCON Serial Port Control (UART) 135
0xC3 SMB0ADR SMBus 0 Address 119
0xC0 SMB0CN SMBus 0 Control 117
0xCF SMB0CR SMBus 0 Clock Rate 118
0xC2 SMB0DAT SMBus 0 Data 119
0xC1 SMB0STA SMBus 0 Status 120
0x81 SP Stack Pointer 73
0x9A SPI0CFG Serial Peripheral Interface Configuration 126
0x9D SPI0CKR SPI Clock Rate 128
0xF8 SPI0CN SPI Bus Control 127
0x9B SPI0DAT SPI Port 1Data 128
0xC8 T2CON Counter/Timer 2 Control 148
0x88 TCON Counter/Timer Control 140
0x8C TH0 Counter/Timer 0 Data Word (High Byte) 143
0x8D TH1 Counter/Timer 1 Data Word (High Byte) 143
0xCD TH2 Counter/Timer 2 Data Word (High Byte) 149
0x8A TL0 Counter/Timer 0 Data Word (Low Byte) 143
0x8B TL1 Counter/Timer 1 Data Word (Low Byte) 143
Description Page No.
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Address Register
0xCC TL2 Counter/Timer 2 Data Word (Low Byte) 149
0x89 TMOD Counter/Timer Mode 141
0x91 TMR3CN Timer 3 Control 150
0x95 TMR3H Timer 3 High 151
0x94 TMR3L Timer 3 Low 151
0x93 TMR3RLH Timer 3 Reload High 151
0x92 TMR3RLL Timer 3 Reload Low 151
0xFF WDTCN Watchdog Timer Control 95
0xE1 XBR0 Port I/O Crossbar Configuration 1 104
0xE2 XBR1 Port I/O Crossbar Configuration 2 106
0xE3 XBR2 Port I/O Crossbar Configuration 3 107
0x84-86, 0x96-97, 0x9C, 0xA1-A3, 0xA9-AC, 0xAE, 0xB3-B5, 0xB9, 0xBD, 0xC9, 0xCE,
0xDF, 0xE4-E5, 0xF1-F5 * Refers to a register in the C8051F000/1/2/5/6/7 only. ** Refers to a register in the C8051F010/1/2/5/6/7 only. *** Refers to a register in the C8051F005/06/07/15/16/17 only.
Description Page No.
Reserved
C8051F010/1/2/5/6/7
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10.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature’s default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
Figure 10.3. SP: Stack Pointer
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0x81
Bits 7-0: SP: Stack Pointer.
The stack pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
Figure 10.4. DPL: Data Pointer Low Byte
SFR Address:
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0x82
SFR Address:
Bits 7-0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed RAM and Flash Memory.
Figure 10.5. DPH: Data Pointer High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0x83
Bits 7-0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed RAM and Flash Memory.
SFR Address:
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Figure 10.6. PSW: Program Status Word
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
CY AC F0 RS1 RS0 OV F1 PARITY 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(bit addressable)
SFR Address:
0xD0
Bit7: CY: Carry Flag.
Bit6: AC: Auxiliary Carry Flag.
Bit5: F0: User Flag 0.
Bits4-3: RS1-RS0: Register Bank Select.
Note: Any instruction which changes the RS1-RS0 bits must not be immediately followed
Bit2: OV: Overflow Flag.
Bit1: F1: User Flag 1.
Bit0: PARITY: Parity Flag.
This bit is set when the last arithmetic operation results in a carry (addition) or a borrow (subtraction). It is cleared to 0 by all other arithmetic operations.
This bit is set when the last arithmetic operation results in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
This is a bit-addressable, general purpose flag for use under software control.
These bits select which register bank is used during register accesses.
RS1 RS0 Register Bank Address
0 0 0 0x00-0x07 0 1 1 0x08-0x0F 1 0 2 0x10-0x17 1 1 3 0x18-0x1F
by the “MOV Rn, A” instruction.
This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). It is cleared to 0 by all other arithmetic operations.
This is a bit-addressable, general purpose flag for use under software control.
(Read only) This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even.
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Figure 10.7. ACC: Accumulator
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(bit addressable)
Bits 7-0: ACC: Accumulator
This register is the accumulator for arithmetic operations.
Figure 10.8. B: B Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(bit addressable)
Bits 7-0: B: B Register
This register serves as a second accumulator for certain arithmetic operations.
SFR Address:
0xE0
SFR Address:
0xF0
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10.4. INTERRUPT HANDLER
The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt’s enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt­pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction.
10.4.1. MCU Interrupt Sources and Vectors
The MCUs allocate 12 interrupt sources to on-chip peripherals. Up to 10 additional external interrupt sources are available depending on the I/O pin configuration of the device. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 10.4. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
10.4.2. External Interrupts
Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active-low edge-sensitive inputs depending on the setting of IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt’s input pin. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated.
The remaining four external interrupts (External Interrupts 4-7) are active-low, edge-sensitive inputs. The interrupt­pending flags for these interrupts are in the Port 1 Interrupt Flag Register shown in Figure 15.10.
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Table 10.4. Interrupt Summary
Interrupt Source
Reset 0x0000 Top None Always enabled
External Interrupt 0 (/INT0) 0x0003 0 IE0 (TCON.1) EX0 (IE.0)
Timer 0 Overflow 0x000B 1 TF0 (TCON.5) ET0 (IE.1)
External Interrupt 1 (/INT1) 0x0013 2 IE1 (TCON.3) EX1 (IE.2)
Timer 1 Overflow 0x001B 3 TF1 (TCON.7) ET1 (IE.3)
Serial Port (UART) 0x0023 4 RI (SCON.0)
Timer 2 Overflow (or EXF2) 0x002B 5 TF2 (T2CON.7) ET2 (IE.5)
Serial Peripheral Interface 0x0033 6 SPIF (SPI0CN.7) ESPI0 (EIE1.0)
SMBus Interface 0x003B 7 SI (SMB0CN.3) ESMB0 (EIE1.1)
ADC0 Window Comparison 0x0043 8 ADWINT (ADC0CN.2) EWADC0 (EIE1.2)
Programmable Counter Array 0 0x004B 9 CF (PCA0CN.7)
Comparator 0 Falling Edge 0x0053 10 CP0FIF (CPT0CN.4) ECP0F (EIE1.4)
Comparator 0 Rising Edge 0x005B 11 CP0RIF (CPT0CN.5) ECP0R (EIE1.5)
Comparator 1 Falling Edge 0x0063 12 CP1FIF (CPT1CN.4) ECP1F (EIE1.6)
Comparator 1 Rising Edge 0x006B 13 CP1RIF (CPT1CN.5) ECP1R (EIE1.7)
Timer 3 Overflow 0x0073 14 TF3 (TMR3CN.7) ET3 (EIE2.0)
ADC0 End of Conversion 0x007B 15 ADCINT (ADC0CN.5) EADC0 (EIE2.1)
External Interrupt 4 0x0083 16 IE4 (PRT1IF.4) EX4 (EIE2.2)
External Interrupt 5 0x008B 17 IE5 (PRT1IF.5) EX5 (EIE2.3)
External Interrupt 6 0x0093 18 IE6 (PRT1IF.6) EX6 (EIE2.4)
External Interrupt 7 0x009B 19 IE7 (PRT1IF.7) EX7 (EIE2.5)
Unused Interrupt Location 0x00A3 20 None Reserved (EIE2.6)
External Crystal OSC Ready 0x00AB 21 XTLVLD (OSCXCN.7) EXVLD (EIE2.7)
Interrupt
Vector
Priority
Order
Interrupt-Pending Flag Enable
ES (IE.4)
TI (SCON.1)
EPCA0 (EIE1.3)
CCFn (PCA0CN.n)
10.4.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate.
10.4.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction.
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10.4.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Figure 10.9. IE: Interrupt Enable
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
EA IEGF0 ET2 ES ET1 EX1 ET0 EX0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(bit addressable)
SFR Address:
0xA8
Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask
0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting.
Bit6: IEGF0: General Purpose Flag 0.
Bit5: ET2: Enable Timer 2 Interrupt.
0: Disable all Timer 2 interrupts. 1: Enable interrupt requests generated by the TF2 flag (T2CON.7)
Bit4: ES: Enable Serial Port (UART) Interrupt.
0: Disable all UART interrupts. 1: Enable interrupt requests generated by the R1 flag (SCON.0) or T1 flag (SCON.1).
Bit3: ET1: Enable Timer 1 Interrupt.
0: Disable all Timer 1 interrupts. 1: Enable interrupt requests generated by the TF1 flag (TCON.7).
Bit2: EX1: Enable External Interrupt 1.
0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 pin.
Bit1: ET0: Enable Timer 0 Interrupt.
1: Enable interrupt requests generated by the TF0 flag (TCON.5).
Bit0: EX0: Enable External Interrupt 0.
0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 pin.
settings.
This is a general purpose flag for use under software control.
This bit sets the masking of the Timer 2 interrupt.
This bit sets the masking of the Serial Port (UART) interrupt.
This bit sets the masking of the Timer 1 interrupt.
This bit sets the masking of external interrupt 1.
This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupts.
This bit sets the masking of external interrupt 0.
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Figure 10.10. IP: Interrupt Priority
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - PT2 PS PT1 PX1 PT0 PX0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(bit addressable)
Bits7-6: UNUSED. Read = 11b, Write = don’t care.
Bit5: PT2 Timer 2 Interrupt Priority Control.
0: Timer 2 interrupt priority determined by default priority order. 1: Timer 2 interrupts set to high priority level.
Bit4: PS: Serial Port (UART) Interrupt Priority Control.
0: UART interrupt priority determined by default priority order. 1: UART interrupts set to high priority level.
Bit3: PT1: Timer 1 Interrupt Priority Control.
0: Timer 1 interrupt priority determined by default priority order. 1: Timer 1 interrupts set to high priority level.
Bit2: PX1: External Interrupt 1 Priority Control.
0: External Interrupt 1 priority determined by default priority order. 1: External Interrupt 1 set to high priority level.
Bit1: PT0: Timer 0 Interrupt Priority Control.
0: Timer 0 interrupt priority determined by default priority order. 1: Timer 0 interrupt set to high priority level.
Bit0: PX0: External Interrupt 0 Priority Control.
0: External Interrupt 0 priority determined by default priority order. 1: External Interrupt 0 set to high priority level.
This bit sets the priority of the Timer 2 interrupts.
This bit sets the priority of the Serial Port (UART) interrupts.
This bit sets the priority of the Timer 1 interrupts.
This bit sets the priority of the External Interrupt 1 interrupts.
This bit sets the priority of the Timer 0 interrupts.
This bit sets the priority of the External Interrupt 0 interrupts.
SFR Address:
0xB8
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Figure 10.11. EIE1: Extended Interrupt Enable 1
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ECP1R ECP1F ECP0R ECP0F EPCA0 EWADC0 ESMB0 ESPI0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xE6
SFR Address:
Bit7: ECP1R: Enable Comparator 1 (CP1) Rising Edge Interrupt.
0: Disable CP1 Rising Edge interrupt. 1: Enable interrupt requests generated by the CP1RIF flag (CPT1CN.5).
Bit6: ECP1F: Enable Comparator 1 (CP1) Falling Edge Interrupt.
0: Disable CP1 Falling Edge interrupt. 1: Enable interrupt requests generated by the CP1FIF flag (CPT1CN.4).
Bit5: ECP0R: Enable Comparator 0 (CP0) Rising Edge Interrupt.
0: Disable CP0 Rising Edge interrupt. 1: Enable interrupt requests generated by the CP0RIF flag (CPT0CN.5).
Bit4: ECP0F: Enable Comparator 0 (CP0) Falling Edge Interrupt.
0: Disable CP0 Falling Edge interrupt. 1: Enable interrupt requests generated by the CP0FIF flag (CPT0CN.4).
Bit3: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0.
Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt.
0: Disable ADC0 Window Comparison Interrupt. 1: Enable Interrupt requests generated by ADC0 Window Comparisons.
Bit1: ESMB0: Enable SMBus 0 Interrupt.
1: Enable interrupt requests generated by the SI flag (SMB0CN.3).
Bit0: ESPI0: Enable Serial Peripheral Interface 0 Interrupt.
0: Disable all SPI0 interrupts. 1: Enable Interrupt requests generated by the SPIF flag (SPI0CN.7).
This bit sets the masking of the CP1 interrupt.
This bit sets the masking of the CP1 interrupt.
This bit sets the masking of the CP0 interrupt.
This bit sets the masking of the CP0 interrupt.
This bit sets the masking of the PCA0 interrupts.
This bit sets the masking of ADC0 Window Comparison interrupt.
This bit sets the masking of the SMBus interrupt. 0: Disable all SMBus interrupts.
This bit sets the masking of SPI0 interrupt.
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Figure 10.12. EIE2: Extended Interrupt Enable 2
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
EXVLD - EX7 EX6 EX5 EX4 EADC0 ET3 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xE7
Bit7: EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt.
0: Disable all XTLVLD interrupts. 1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7)
Bit6: Reserved. Must Write 0. Reads 0.
Bit5: EX7: Enable External Interrupt 7.
0: Disable External Interrupt 7. 1: Enable interrupt requests generated by the External Interrupt 7 input pin.
Bit4: EX6: Enable External Interrupt 6.
0: Disable External Interrupt 6. 1: Enable interrupt requests generated by the External Interrupt 6 input pin.
Bit3: EX5: Enable External Interrupt 5.
0: Disable External Interrupt 5. 1: Enable interrupt requests generated by the External Interrupt 5 input pin.
Bit2: EX4: Enable External Interrupt 4.
0: Disable External Interrupt 4. 1: Enable interrupt requests generated by the External Interrupt 4 input pin.
Bit1: EADC0: Enable ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt. 1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.
Bit0: ET3: Enable Timer 3 Interrupt.
0: Disable all Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3 flag (TMR3CN.7)
This bit sets the masking of the XTLVLD interrupt.
This bit sets the masking of External Interrupt 7.
This bit sets the masking of External Interrupt 6.
This bit sets the masking of External Interrupt 5.
This bit sets the masking of External Interrupt 4.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
This bit sets the masking of the Timer 3 interrupt.
SFR Address:
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Figure 10.13. EIP1: Extended Interrupt Priority 1
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PCP1R PCP1F PCP0R PCP0F PPCA0 PWADC0 PSMB0 PSPI0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xF6
SFR Address:
Bit7: PCP1R: Comparator 1 (CP1) Rising Interrupt Priority Control.
0: CP1 rising interrupt set to low priority level.
Bit6: PCP1F: Comparator 1 (CP1) Falling Interrupt Priority Control.
0: CP1 falling interrupt set to low priority level.
Bit5: PCP0R: Comparator 0 (CP0) Rising Interrupt Priority Control.
0: CP0 rising interrupt set to low priority level.
Bit4: PCP0F: Comparator 0 (CP0) Falling Interrupt Priority Control.
0: CP0 falling interrupt set to low priority level.
Bit3: PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
0: PCA0 interrupt set to low priority level.
Bit2: PWADC0: ADC0 Window Comparator Interrupt Priority Control.
0: ADC0 Window interrupt set to low priority level.
Bit1: PSMB0: SMBus 0 Interrupt Priority Control.
0: SMBus interrupt set to low priority level. 1: SMBus interrupt set to high priority level.
Bit0: PSPI0: Serial Peripheral Interface 0 Interrupt Priority Control.
0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level.
This bit sets the priority of the CP1 interrupt.
1: CP1 rising interrupt set to high priority level.
This bit sets the priority of the CP1 interrupt.
1: CP1 falling interrupt set to high priority level.
This bit sets the priority of the CP0 interrupt.
1: CP0 rising interrupt set to high priority level.
This bit sets the priority of the CP0 interrupt.
1: CP0 falling interrupt set to high priority level.
This bit sets the priority of the PCA0 interrupt.
1: PCA0 interrupt set to high priority level.
This bit sets the priority of the ADC0 Window interrupt.
1: ADC0 Window interrupt set to high priority level.
This bit sets the priority of the SMBus interrupt.
This bit sets the priority of the SPI0 interrupt.
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Figure 10.14. EIP2: Extended Interrupt Priority 2
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PXVLD - PX7 PX6 PX5 PX4 PADC0 PT3 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xF7
Bit7: PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control.
0: XTLVLD interrupt set to low priority level.
Bit6: Reserved: Must write 0. Reads 0.
Bit5: PX7: External Interrupt 7 Priority Control.
0: External Interrupt 7 set to low priority level. 1: External Interrupt 7 set to high priority level.
Bit4: PX6: External Interrupt 6 Priority Control.
0: External Interrupt 6 set to low priority level. 1: External Interrupt 6 set to high priority level.
Bit3: PX5: External Interrupt 5 Priority Control.
0: External Interrupt 5 set to low priority level. 1: External Interrupt 5 set to high priority level.
Bit2: PX4: External Interrupt 4 Priority Control.
0: External Interrupt 4 set to low priority level. 1: External Interrupt 4 set to high priority level.
Bit1: PADC0: ADC End of Conversion Interrupt Priority Control.
0: ADC0 End of Conversion interrupt set to low priority level. 1: ADC0 End of Conversion interrupt set to high priority level.
Bit0: PT3: Timer 3 Interrupt Priority Control.
0: Timer 3 interrupt priority determined by default priority order. 1: Timer 3 interrupt set to high priority level.
This bit sets the priority of the XTLVLD interrupt.
1: XTLVLD interrupt set to high priority level.
This bit sets the priority of the External Interrupt 7.
This bit sets the priority of the External Interrupt 6.
This bit sets the priority of the External Interrupt 5.
This bit sets the priority of the External Interrupt 4.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
This bit sets the priority of the Timer 3 interrupts.
SFR Address:
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10.5. Power Management Modes

The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 10.15 describes the Power Control Register (PCON) used to control the CIP-51’s power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or serial buses, draw little power whenever they are not in use. Turning off the oscillator saves even more power, but requires a reset to restart the MCU.
10.5.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU will resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section 13.8 Watchdog Timer for more information on the use and configuration of the WDT.
10.5.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes. In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100µsec.
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Figure 10.15. PCON: Power Control Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
SMOD GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0x87
Bit7: SMOD: Serial Port Baud Rate Doubler Enable.
Bits6-2: GF4-GF0: General Purpose Flags 4-0.
Bit1: STOP: Stop Mode Select.
Bit0: IDLE: Idle Mode Select.
0: Serial Port baud rate is that defined by Serial Port Mode in SCON. 1: Serial Port baud rate is double that defined by Serial Port Mode in SCON.
These are general purpose flags for use under software control.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. 1: Goes into power down mode. (Turns off oscillator).
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0. 1: Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
SFR Address:
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11. FLASH MEMORY
These devices include 32k + 128 bytes of on-chip, reprogrammable Flash memory for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the JTAG interface or by software using the MOVX instruction. Once cleared to 0, a Flash bit must be erased to set it back to 1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution. Data polling to determine the end of the write/erase operation is not required. The Flash memory is designed to withstand at least 20,000 write/erase cycles. Refer to Table 11.1 for the electrical characteristics of the Flash memory.

11.1. Programming The Flash Memory

The simplest means of programming the Flash memory is through the JTAG interface using programming tools provided by Cygnal or a third party vendor. This is the only means for programming a non-initialized device. For details on the JTAG commands to program Flash memory, see Section 21.2.
The Flash memory can be programmed by software using the MOVX instruction with the address and data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1. Writing to Flash remains enabled until the PSWE bit is cleared by software.
Writes to Flash memory can clear bits but cannot set them. Only an erase operation can set bits in Flash. Therefore, the byte location to be programmed must be erased before a new value can be written. The 32kbyte Flash memory is organized in 512-byte sectors. The erase operation applies to an entire sector (setting all bytes in the sector to 0xFF). Setting the PSEE Program Store Erase Enable bit (PSCTL.1) and PSWE (PSCTL.0) bit to logic 1 and then using the MOVX command to write a data byte to any byte location within the sector will erase an entire 512-byte sector. The data byte written can be of any value because it is not actually written to the Flash. Flash erasure remains enabled until the PSEE bit is cleared by software. The following sequence illustrates the algorithm for programming the Flash memory by software:
1. Enable Flash Memory write/erase in FLSCL Register using FLASCL bits.
2. Set PSEE (PSCTL.1) to enable Flash sector erase.
3. Set PSWE (PSCTL.0) to enable Flash writes.
4. Use MOVX to write a data byte to any location within the 512-byte sector to be erased.
5. Clear PSEE to disable Flash sector erase.
6. Use MOVX to write a data byte to the desired byte location within the erased 512-byte sector. Repeat until finished. (Any number of bytes can be written from a single byte to and entire sector.)
7. Clear the PSWE bit to disable Flash writes.
Write/Erase timing is automatically controlled by hardware based on the prescaler value held in the Flash Memory Timing Prescaler register (FLSCL). The 4-bit prescaler value FLASCL determines the time interval for write/erase operations. The FLASCL value required for a given system clock is shown in Figure 11.4, along with the formula used to derive the FLASCL values. When FLASCL is set to 1111b, the write/erase operations are disabled. Note that code execution in the 8051 is stalled while the Flash is being programmed or erased.
Table 11.1. FLASH Memory Electrical Characteristics
VDD = 2.7 to 3.6V, -40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Endurance 20k 100k Erase/Wr Erase Cycle Time 10 ms Write Cycle Time 40
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11.2. Non-volatile Data Storage

The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX instruction and read using the MOVC instruction.
The MCU incorporates an additional 128-byte sector of Flash memory located at 0x8000 – 0x807F. This sector can be used for program code or data storage. However, its smaller sector size makes it particularly well suited as general purpose, non-volatile scratchpad memory. Even though Flash memory can be written a single byte at a time, an entire sector must be erased first. In order to change a single byte of a multi-byte data set, the data must be moved to temporary storage. Next, the sector is erased, the data set updated and the data set returned to the original sector. The 128-byte sector-size facilitates updating data without wasting program memory space by allowing the use of internal data RAM for temporary storage. (A normal 512-byte sector is too large to be stored in the 256-byte internal data memory.)
11.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as prevent the viewing of proprietary program code and constants. The Program Store Write Enable (PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from accidental modification by software. These bits must be explicitly set to logic 1 before software can modify the Flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the JTAG interface or by software running on the system controller.
A set of security lock bytes stored at 0x7DFE and 0x7DFF protect the Flash program memory from being read or altered across the JTAG interface. Each bit in a security lock-byte protects one 4kbyte block of memory. Clearing a bit to logic 0 in a Read lock byte prevents the corresponding block of Flash memory from being read across the JTAG interface. Clearing a bit in the Write/Erase lock byte protects the block from JTAG erasures and/or writes. The Read lock byte is at location 0x7DFF. The Write/Erase lock byte is located at 0x7DFE. Figure 11.2 shows the location and bit definitions of the security bytes. The 512-byte sector containing the lock bytes can be written to, but not erased by software.
Figure 11.1. PSCTL: Program Store RW Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - - PSEE PSWE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0x8F
SFR Address:
Bits7-2: UNUSED. Read = 000000b, Write = don’t care.
Bit1: PSEE: Program Store Erase Enable.
Bit0: PSWE: Program Store Write Enable.
Setting this bit allows an entire page of the Flash program memory to be erased provided the PSWE bit is also set. After setting this bit, a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. 0: Flash program memory erasure disabled. 1: Flash program memory erasure enabled.
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX instruction. The location must be erased before writing data. 0: Write to Flash program memory disabled. 1: Write to Flash program memory enabled.
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Figure 11.2. Flash Program Memory Security Bytes
(This Block locked only if all
other blocks are locked)
Reserved
Read Lock Byte
Write/Erase Lock Byte
Program Memory
Space
Software Read Limit
FLASH Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.) 0: Read operations are locked (disabled) for corresponding block across the JTAG interface. 1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. 0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface. 1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Access Limit Register (FLACL)
The content of this register is used as the high byte of the 16-bit software read limit address. The 16-
bit read limit address value is calculated as 0xNN00 where NN is replaced by the contents of this register. Software running at or above this address is prohibited from using the MOVX or MOVC instructions to read, write, or erase, locations below this address. Any attempts to read locations below this limit will return the value 0x00.
The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the block containing the security bytes. This allows additional blocks to be protected after the block containing the security bytes has been locked. However, the only means of removing a lock once set is to erase the entire program memory space by performing a JTAG erase operation (i.e. cannot be done in user firmware). NOTE: Addressing either
security byte while performing a JTAG erase operation will automatically initiate erasure of the entire program memory space (except for the reserved area). This erasure can only be performed via JTAG. If a non-security byte in the 0x7C00-0x7DFF page is addressed during erasure, only that page (including the security bytes) will be erased.
The Flash Access Limit security feature (see Figure 11.3) protects proprietary program code and data from being read by software running on the C8051F005/06/07/15/16/17 MCUs. This feature provides support for OEMs that wish to program the MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later.
0x807F 0x8000 0x7FFF
0x7E00
0x7DFF
0x7DFE
0x7DFD
0x0000
Read and Write/Erase Security Bits. (Bit 7 is MSB.)
Bit Memory Block
7
0x7000 - 0x7DFD
6
0x6000 - 0x6FFF
5
0x5000 - 0x5FFF
4
0x4000 - 0x4FFF
3
0x3000 - 0x3FFF
2
0x2000 - 0x2FFF
1
0x1000 - 0x1FFF
0
0x0000 - 0x0FFF
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The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program memory space. The first is an upper partition consisting of all the program memory locations at or above the SRL address, and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but excluding) the SRL address. Software in the upper partition can execute code in the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruction. (Executing a MOVC instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00.) Software running in the lower partition can access locations in both the upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-added firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a predetermined location in the upper partition. If entry points are published, software running in the upper partition may execute program code in the lower partition, but it cannot read the contents of the lower partition. Parameters may be passed to the program code running in the lower partition either through the typical method of placing them on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition.
The SRL address is specified using the contents of the Flash Access Register. The 16-bit SRL address is calculated as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be located on 256-byte boundaries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a 512 boundary be used. The contents of a non-initialized SRL security byte is 0x00, thereby setting the SRL address to 0x0000 and allowing read access to all locations in program memory space by default.
Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xB7
SFR Address:
Bits 7-0: FLACL: Flash Access Limit.
This register holds the high byte of the 16-bit program memory read/write/erase limit address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This
register can only be written once after any reset. Any subsequent writes are ignored until the next reset.
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Figure 11.4. FLSCL: Flash Memory Timing Prescaler
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
FOSE FRAE - - FLASCL
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xB6
Bit7: FOSE: Flash One-Shot Timer Enable 0: Flash One-shot timer disabled.
Bit6: FRAE: Flash Read Always Enable 0: Flash reads per one-shot timer
Bits5-4: UNUSED. Read = 00b, Write = don’t care. Bits3-0: FLASCL: Flash Memory Timing Prescaler.
1: Flash One-shot timer enabled
1: Flash always in read mode
This register specifies the prescaler value for a given system clock required to generate the correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash write/erase operations are disabled. 0000: System Clock < 50kHz 0001: 50kHz System Clock < 100kHz 0010: 100kHz System Clock < 200kHz 0011: 200kHz System Clock < 400kHz 0100: 400kHz System Clock < 800kHz 0101: 800kHz System Clock < 1.6MHz 0110: 1.6MHz System Clock < 3.2MHz 0111: 3.2MHz System Clock < 6.4MHz 1000: 6.4MHz System Clock < 12.8MHz 1001: 12.8MHz System Clock < 25.6MHz 1010: 25.6MHz System Clock < 51.2MHz * 1011, 1100, 1101, 1110: Reserved Values 1111: Flash Memory Write/Erase Disabled
The prescaler value is the smallest value satisfying the following equation: FLASCL > log
* For test purposes. The C8051F000 family is not guaranteed for operation over 25MHz.
(System Clock / 50kHz)
2
10001111
SFR Address:
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12. EXTERNAL RAM (C8051F005/06/07/15/16/17)
The C8051F005/06/07/15/16/17 MCUs include 2048 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in Figure 12.1). Note: the MOVX instruction is also used for writes to the Flash
memory. See Section 11 for details. The MOVX instruction accesses XRAM by default (i.e. PSTCL.0 = 0).
For any of the addressing modes the upper 5-bits of the 16-bit external data memory address word are “don’t cares”. As a result, the 2048-byte RAM is mapped modulo style over the entire 64k external data memory address range. For example, the XRAM byte at address 0x0000 is also at address 0x0800, 0x1000, 0x1800, 0x2000, etc. This is a useful feature when doing a linear memory fill, as the address pointer doesn’t have to be reset when reaching the RAM block boundary.
Figure 12.1. EMI0CN: External Memory Interface Control
R R R R R R/W R/W R/W Reset Value
- - - - - PGSEL2 PGSEL1 PGSEL0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xAF
Bits 7-3: Not Used – reads 00000b Bits 2-0: PGSEL[2:0]: XRAM Page Select Bits
000: xxxxx000b 001: xxxxx001b
011: xxxxx011b
101: xxxxx101b
111: xxxxx111b
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. The upper 5-bits are “don’t cares”, so the 2k address blocks are repeated modulo over the entire 64k external data memory address space.
010: xxxxx010b
100: xxxxx100b
110: xxxxx110b
SFR Address:
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13. RESET SOURCES
The reset circuitry of the MCUs allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the CIP-51 halts program execution, forces the external port pins to a known state and initializes the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the program counter (PC) is reset, and program execution starts at location 0x0000.
All of the SFRs are reset to predefined values. The reset values of the SFR bits are defined in the SFR detailed descriptions. The contents of internal data memory are not changed during a reset and any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic ones), activating internal weak pull-ups which take the external I/O pins to a high state. If the source of reset is from the VDD Monitor or writing a 1 to PORSF, the /RST pin is driven low until the end of the VDD reset timeout.
On exit from the reset state, the MCU uses the internal oscillator running at 2MHz as the system clock by default. Refer to Section 14 for information on selecting and configuring the system clock source. The Watchdog Timer is enabled using its longest timeout interval. (Section 13.8 details the use of the Watchdog Timer.)
There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external CNVSTR signal, software commanded, Comparator 0, Missing Clock Detector, and Watchdog Timer. Each reset source is described below:
Figure 13.1. Reset Sources Diagram
(Port
I/O)
Crossbar
CP0+
CP0-
System
Comparator 0
Clock
CNVSTR
CNVRSEF
+
-
Missing
Clock
Detector
(one­shot)
C0RSEF
EN
MCD
Enable
WDT
PRE
EN
WDT
Enable
VDD
Supply Monitor
+
-
WDT
Strobe
CIP-51
Supply
Reset
Timeout
(Software Reset)
SWRSF
System Reset
(wired-OR)
Reset Funnel
/RST
Core
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13.1. Power-on Reset
The C8051F000 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the V Electrical Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the 100ms VDD Monitor timeout in order to allow the VDD supply to become stable.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by a reset from any other source. Since all resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset.

13.2. Software Forced Reset

Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 13.1.
Logic HIGH
Logic LOW
13.3. Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below V drive the /RST pin low and return the CIP-51 to the reset state (see Figure 13.2). When VDD returns to a level above V though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.
RST
level during power-up. (See Figure 13.2 for timing diagram, and refer to Table 13.1 for the
RST
Figure 13.2. VDD Monitor Timing Diagram
volts
2.70
2.40
2.0
1.0
, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even
/RST
V
RST
D
D
V
100ms 100ms
, the power supply monitor will
RST
t
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13.4. External Reset
The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting an active-low signal on the /RST pin will cause the MCU to enter the reset state. Although there is a weak internal pullup, it may be desirable to provide an external pull-up and/or decoupling of the /RST pin to avoid erroneous noise-induced resets. The MCU will remain in reset until at least 12 clock cycles after the active-low /RST signal is removed. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. The /RST pin is also 5V tolerant.

13.5. Missing Clock Detector Reset

The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If the system clock goes away for more than 100µs, the one-shot will time out and generate a reset. After a Missing Clock Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source; otherwise, this bit reads 0. The state of the /RST pin is unaffected by this reset. Setting the MSCLKE bit in the OSCICN register (see Figure 14.2) enables the Missing Clock Detector.

13.6. Comparator 0 Reset

Comparator 0 can be configured as an active-low reset input by writing a 1 to the C0RSEF flag (RSTSRC.5). Comparator 0 should be enabled using CPT0CN.7 (see Figure 8.3) at least 20µs prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. When configured as a reset, if the non­inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the MCU is put into the reset state. After a Comparator 0 Reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator 0 as the reset source; otherwise, this bit reads 0. The state of the /RST pin is unaffected by this reset. Also, Comparator 0 can generate a reset with or without the system clock.

13.7. External CNVSTR Pin Reset

The external CNVSTR signal can be configured as an active-low reset input by writing a 1 to the CNVRSEF flag (RSTSRC.6). The CNVSTR signal can appear on any of the P0, P1, or P2 I/O pins as described in Section 15.1. (Note that the Crossbar must be configured for the CNVSTR signal to be routed to the appropriate Port I/O.) The Crossbar should be configured and enabled before the CNVRSEF is set to configure CNVSTR as a reset source. When configured as a reset, CNVSTR is active-low and level sensitive. After a CNVSTR reset, the CNVRSEF flag (RSTSRC.6) will read 1 signifying CNVSTR as the reset source; otherwise, this bit reads 0. The state of the /RST pin is unaffected by this reset.

13.8. Watchdog Timer Reset

The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. The WDT will force the MCU into the reset state when the watchdog timer overflows. To prevent the reset, the WDT must be restarted by application software before the overflow occurs. If the system experiences a software/hardware malfunction preventing the software from restarting the WDT, the WDT will overflow and cause a reset. This should prevent the system from running out of control.
The WDT is automatically enabled and started with the default maximum time interval on exit from all resets. If desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by this reset.
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13.8.1. Watchdog Usage
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 13.3.
Enable/Reset WDT
The watchdog timer is both enabled and the countdown restarted by writing 0xA5 to the WDTCN register. The user’s application software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The WDT is enabled and restarted as a result of any system reset.
Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates disabling the WDT.
CLR EA ; disable all interrupts MOV WDTCN,#0DEh ; disable software MOV WDTCN,#0ADh ; watchdog timer SETB EA ; re-enable interrupts
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.
Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use the watchdog should write 0xFF to WDTCN in their initialization code.
Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
3+WDTCN[2:0]
4
For a 2MHz system clock, this provides an interval range of 0.032msec to 524msec. WDTCN.7 must be a 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] is 111b after a system reset.
x T
SYSCLK
, (where T
is the system clock period).
SYSCLK
Figure 13.3. WDTCN: Watchdog Timer Control Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
xxxxx111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xFF
SFR Address:
Bits7-0: WDT Control Writing 0xA5 both enables and reloads the WDT. Writing 0xDE followed within 4 clocks by 0xAD disables the WDT. Writing 0xFF locks out the disable feature. Bit4: Watchdog Status Bit (when Read) Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive 1: WDT is active Bits2-0: Watchdog Timeout Interval Bits The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits,
WDTCN.7 must be set to 0.
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Figure 13.4. RSTSRC: Reset Source Register
R R/W R/W R/W R R R/W R Reset Value
JTAGRST CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF xxxxxxxx
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xEF
SFR Address:
(Note: Do not use read-modify-write operations on this register.)
Bit7: JTAGRST. JTAG Reset Flag.
1: JTAG is in reset state. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write
1: CNVSTR is a reset source (active low) Read
1: Source of prior reset was from CNVSTR Bit5: C0RSEF: Comparator 0 Reset Enable and Flag Write
1: Comparator 0 is a reset source (active low) Read
1: Source of prior reset was from Comparator 0 Bit4: SWRSF: Software Reset Force and Flag Write 0: No Effect 1: Forces an internal reset. /RST pin is not effected.
0: Prior reset source was not from write to the SWRSF bit. 1: Prior reset source was from write to the SWRSF bit. Bit3: WDTRSF: Watchdog Timer Reset Flag 0: Source of prior reset was not from WDT timeout. 1: Source of prior reset was from WDT timeout. Bit2: MCDRSF: Missing Clock Detector Flag 0: Source of prior reset was not from Missing Clock Detector timeout. 1: Source of prior reset was from Missing Clock Detector timeout. Bit1: PORSF: Power-On Reset Force and Flag Write 0: No effect 1: Forces a Power-On Reset. /RST is driven low.
0: Source of prior reset was not from POR. 1: Source of prior reset was from POR. Bit0: PINRSF: HW Pin Reset Flag 0: Source of prior reset was not from /RST pin. 1: Source of prior reset was from /RST pin.
0: JTAG is not currently in reset state.
0: CNVSTR is not a reset source
0: Source of prior reset was not from CNVSTR
0: Comparator 0 is not a reset source
0: Source of prior reset was not from Comparator 0
Read
Read
Page 96 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
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Table 13.1. Reset Electrical Characteristics
-40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
/RST Output Low Voltage IOL = 8.5mA, VDD = 2.7 to 3.6V 0.6 V /RST Input High Voltage 0.7 x
VDD
/RST Input Low Voltage 0.3 x
/RST Input Leakage Current /RST = 0.0V 20 VDD for /RST Output Valid 1.0 V AV+ for /RST Output Valid 1.0 V VDD POR Threshold (V Reset Time Delay /RST rising edge after crossing reset
Missing Clock Detector Timeout
) 2.40 2.55 2.70 V
RST
80 100 120 ms threshold Time from last system clock to reset generation
100 220 500
V
V
VDD
µA
µs
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14. OSCILLATOR
Each MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate the system clock. The MCUs boot from the internal oscillator after any reset. The internal oscillator starts up instantly. It can be enabled/disabled and its frequency can be changed using the Internal Oscillator Control Register (OSCICN) as shown in Figure 14.2. The internal oscillator’s electrical specifications are given in Table 14.1.
Both oscillators are disabled when the /RST pin is held low. The MCUs can run from the internal oscillator or external oscillator, and switch between the two at will using the CLKSL bit in the OSCICN Register. The external oscillator requires an external resonator, parallel-mode crystal, capacitor, or RC network connected to the XTAL1/XTAL2 pins (see Figure 14.1). The oscillator circuit must be configured for one of these sources in the OSCXCN register. An external CMOS clock can also provide the system clock via overdriving the XTAL1 pin. The XTAL1 and XTAL2 pins are 3.6V (not 5V) tolerant. The external oscillator can be left enabled and running even when the MCU has switched to using the internal oscillator.
Figure 14.1. Oscillator Diagram
opt. 4 opt. 3
XTAL1
XTAL2
opt. 2
AV+
opt. 1
XTAL1XTAL1
XTAL1
XTAL2
AGND
VDD
AV+
OSCICN
MSCLKE
Internal Clock
Generator
Input
Circuit
XTLVLD
XOSCMD2
XOSCMD1
OSCXCN
IFCN1
CLKSL
EN
OSC
XFCN2
IOSCEN
IFCN0
SYSCLK
XFCN1
XFCN0
IFRDY
XOSCMD0
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Figure 14.2. OSCICN: Internal Oscillator Control Register
R/W R/W R/W R R/W R/W R/W R/W Reset Value
MSCLKE - - IFRDY CLKSL IOSCEN IFCN1 IFCN0 00000100
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xB2
Bit7: MSCLKE: Missing Clock Enable Bit 0: Missing Clock Detector Disabled 1: Missing Clock Detector Enabled; triggers a reset if a missing clock is detected Bits6-5: UNUSED. Read = 00b, Write = don’t care Bit4: IFRDY: Internal Oscillator Frequency Ready Flag 0: Internal Oscillator Frequency not running at speed specified by the IFCN bits. 1: Internal Oscillator Frequency running at speed specified by the IFCN bits. Bit3: CLKSL: System Clock Source Select Bit 0: Uses Internal Oscillator as System Clock. 1: Uses External Oscillator as System Clock. Bit2: IOSCEN: Internal Oscillator Enable Bit
Bits1-0: IFCN1-0: Internal Oscillator Frequency Control Bits
0: Internal Oscillator Disabled 1: Internal Oscillator Enabled
00: Internal Oscillator typical frequency is 2MHz. 01: Internal Oscillator typical frequency is 4MHz. 10: Internal Oscillator typical frequency is 8MHz. 11: Internal Oscillator typical frequency is 16MHz.
SFR Address:
Table 14.1. Internal Oscillator Electrical Characteristics
-40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Internal Oscillator Frequency
Internal Oscillator Current Consumption (from VDD) Internal Oscillator Temperature Stability Internal Oscillator Power Supply (VDD) Stability
OSCICN.[1:0] = 00 OSCICN.[1:0] = 01 OSCICN.[1:0] = 10 OSCICN.[1:0] = 11 OSCICN.2 = 1 200
4
6.4 %/V
1.5
3.1
6.2
12.3
2 4 8
16
2.4
4.8
9.6
19.2
MHz
µA
ppm/°C
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Figure 14.3. OSCXCN: External Oscillator Control Register
R R/W R/W R/W R/W R/W R/W R/W Reset Value
XTLVLD
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0xB1
Bit7: XTLVLD: Crystal Oscillator Valid Flag (Valid only when XOSCMD = 1xx.) 0: Crystal Oscillator is unused or not yet stable
Bits6-4: XOSCMD2-0: External Oscillator Mode Bits
010: System Clock from External CMOS Clock on XTAL1 pin. 011: System Clock from External CMOS Clock on XTAL1 pin divided by 2. 10x: RC/C Oscillator Mode with divide by 2 stage. 110: Crystal Oscillator Mode 111: Crystal Oscillator Mode with divide by 2 stage. Bit3: RESERVED. Read = undefined, Write = don’t care Bits2-0: XFCN2-0: External Oscillator Frequency Control Bits 000-111: see table below
CRYSTAL MODE (Circuit from Figure 14.1, Option 1; XOSCMD = 11x) Choose XFCN value to match the crystal or ceramic resonator frequency.
RC MODE (Circuit from Figure 14.1, Option 2; XOSCMD = 10x) Choose oscillation frequency range where: f = 1.23(10
C = capacitor value in pF R = Pull-up resistor value in k
C MODE (Circuit from Figure 14.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired: f = KF / (C * AV+), where
C = capacitor value on XTAL1, XTAL2 pins in pF AV+ = Analog Power Supply on MCU in volts
XOSCMD2 XOSCMD1 XOSCMD0
1: Crystal Oscillator is running and stable (should read 1ms after Crystal Oscillator is
enabled to avoid transient condition).
00x: Off. XTAL1 pin is grounded internally.
XFCN Crystal (XOSCMD = 11x) RC (XOSCMD = 10x) C (XOSCMD = 10x)
000 001 010 011 100 101 110 111 f > 6.74MHz
f = frequency of oscillation in MHz
f = frequency of oscillation in MHz
f 12.5kHz f 25kHz
12.5kHz < f 30.3kHz 25kHz < f 50kHz
30.35kHz < f 93.8kHz 50kHz < f 100kHz
93.8kHz < f 267kHz 100kHz < f 200kHz 267kHz < f 722kHz 200kHz < f 400kHz 722kHz < f 2.23MHz 400kHz < f 800kHz
2.23MHz < f 6.74MHz 800kHz < f 1.6MHz
3
) / (R * C), where
- XFCN2 XFCN1 XFCN0 00110000
K Factor = 0.44 K Factor = 1.4 K Factor = 4.4 K Factor = 13 K Factor = 38 K Factor = 100 K Factor = 420
1.6MHz < f 3.2MHz
K Factor = 1400
SFR Address:
Page 100 CYGNAL Integrated Products, Inc. 2002 4.2002; Rev. 1.4
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