Siemens SPD21N05L, SPU21N05L Datasheet

SIPMOS ® Power Transistor
• N channel
• Enhancement mode
• Logic Level
• dv/dt rated
• 175°C operating temperature
SPD21N05L SPU21N05L
Pin 1 Pin 2 Pin 3
G D S
Type
SPD21N05L 55 V 20 A 0.07 SPU21N05L 55 V 20 A 0.07
Maximum Ratings Parameter Symbol Values Unit
V
DS
I
D
R
DS(on
)
Ω Ω
Continuous drain current
T
= 25 °C
C
T
= 100 °C
C
Pulsed drain current
T
= 25 °C
C
Avalanche energy, single pulse
I
= 20 A, VDD = 25 V, RGS = 25
D
L = 450 µH, T
= 25 °C
j
Avalanche current,limited by T Avalanche energy,periodic limited by T
jmax
jmax
Reverse diode dv/dt
Package Ordering Code
P-TO252 Q67040 - S4137- A2 P-TO251 Q67040 - S4131 - A2
I
D
A 20 14
I
Dpuls
80
E
AS
mJ
90
I
AR
E
AR
dv/dt
20 A
5.5 mJ kV/µs
I
= 20 A, VDS = 40 V, diF/dt = 200 A/µs
S
T
= 175 °C
jmax
Gate source voltage V Power dissipation
T
= 25 °C
C
Semiconductor Group 1 29/Jan/1998
GS
P
tot
6
±
14 V
55
W
SPD21N05L SPU21N05L
Maximum Ratings Parameter Symbol Values Unit
Operating temperature T Storage temperature T Thermal resistance, junction - case R Thermal resistance, junction - ambient (PCB mount)** R Thermal resistance, junction - ambient R
j stg
thJC thJA thJA
-55 ... + 175 °C
-55 ... + 175
2.7 K/W
50
100
IEC climatic category, DIN IEC 68-1 55 / 175 / 56
** when mounted on 1 " square PCB ( FR4 );for recommended footprint
Electrical Characteristics,
Parameter Symbol Values Unit
Static Characteristics
Drain- source breakdown voltage
V
= 0 V, ID = 0.25 mA, Tj = 25 °C
GS
Gate threshold voltage
V
GS=VDS, ID
= 40 µA
Zero gate voltage drain current
V
= 50 V, VGS = 0 V, Tj = -40 °C
DS
V
= 50 V, VGS = 0 V, Tj = 25 °C
DS
V
= 50 V, VGS = 0 V, Tj = 150 °C
DS
Gate-source leakage current
V
= 20 V, VDS = 0 V
GS
Drain-Source on-resistance
V
= 4.5 V, ID = 14 A
GS
V
= 10 V, ID = 14 A
GS
at Tj = 25°C, unless otherwise specified
min. typ. max.
V
(BR)DSS
55 - -
V
GS(th)
1.2 1.6 2
I
DSS
-
-
-
I
GSS
- 10 100
R
DS(on)
-
-
-
0.1
-
0.057
0.034
V
µA
0.1 1 100
nA
0.07
0.04
Semiconductor Group 2 29/Jan/1998
SPD21N05L SPU21N05L
Electrical Characteristics,
at Tj = 25°C, unless otherwise specified
Parameter Symbol Values Unit
min. typ. max.
Dynamic Characteristics
Transconductance
V
2
DS
* ID * RDS(on)max, ID
= 14 A
Input capacitance
V
= 0 V, VDS = 25 V, f = 1 MHz
GS
Output capacitance
V
= 0 V, VDS = 25 V, f = 1 MHz
GS
Reverse transfer capacitance
V
= 0 V, VDS = 25 V, f = 1 MHz
GS
Turn-on delay time
V
= 30 V, VGS = 4.5 V, ID = 20 A
DD
R
= 10
G
Rise time
V
= 30 V, VGS = 4.5 V, ID = 20 A
DD
R
= 10
G
Turn-off delay time
V
= 30 V, VGS = 4.5 V, ID = 20 A
DD
R
= 10
G
Fall time
V
= 30 V, VGS = 4.5 V, ID = 20 A
DD
= 10
R
G
Gate charge at threshold
V
= 40 V, ID = 0.1 A, VGS =0 to 1 V
DD
Gate charge at 5.0 V
V
= 40 V, ID = 20 A, VGS =0 to 5 V
DD
Gate charge total
V
= 40 V, ID = 20 A, VGS =0 to 10 V
DD
Gate plateau voltage
V
= 40 V, ID = 20 A
DD
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g(th)
Q
g(5)
Q
g(total)
V
(plateau)
S
7 14 -
pF
- 560 700
- 170 215
- 95 120 ns
- 15 25
- 35 55
- 15 25
- 15 25 nC
- 0.8 1.2
- 15 23
- 24 36 V
- 4.06 -
Semiconductor Group 3 29/Jan/1998
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