Eight 0.145” (3.68 mm) High 5 x 5 Dot Matrix Characters in Red, Yellow, High Efficiency Red, Green,
or High Efficiency Green
Built-in 2 Page, 256 Character ROM. Both Pages
•
Mask Programmable for Custom Fonts
•
Built-in Decoders, Multiplexers and Drivers
Wide Viewing Angle, X Axis ± 50 ° , Y Axis ± 65 °
•
•
Programmable Features:
– Individual Flashing Character
– Full Display Blinking
– Multi-Level Dimming and Blanking
– Clear Function
– Lamp Test
•
Internal or External Clock
•
End Stackable Dual-In-Line Plastic Package
Low Power: 20% Less Power Consumption Than
•
5 X 7 Format
0.189
(4.79)
DESCRIPTION
The PLCD5580 (Red), PLCD5581 (Yellow), PLCD5582 (High Efficiency Red), PLCD5583 (Green), and PLCD5584 (High Efficiency
Green) are eight digit, 5x5 dot matrix, alphanumeric Programmable Displays. The 0.145 inch high digits are packaged in a rugged, high quality, optically transparent, standard 0.6 inch 28 pin
plastic DIP.
The on-board CMOS has a built-in two page, 256 character ROM.
Both pages are mask programmable for 256 custom characters.
The first page of ROM of the standard product contains 128 characters including ASCII, selected European and Scientific symbols. The second page contains Katakana Japanese characters,
more European characters, Avionics, and other graphic symbols.
The PLCD558X is designed for standard microprocessor interface techniques and is fully TTL compatible. The Clock I/O and
Clock Select pins allow the user to synchronize multiple display
modules.
0.018 typ.
(.46)
0.100
(2.54) typ.
0.160±.020
(4.06±.50)
2–131
)
.
Maximum Rating
DC Supply Voltage ........................................–0.5 to +7.0 Vdc
Input Voltage Levels Relative
to Ground...............................................–0.5 to V
Operating Temperature .................................–40 °
Display Access Time130ns
TasAddress Setup Time10ns
TcesChip Enable Hold Time0ns
TahAddress Hold Time20ns
TcehChip Enable Hold Time0ns
TwWrite Active Time100ns
TdsData Valid Prior to
50ns
Rising Edge of Write
TdhData Hold Time20ns
(1)
Trc
Tclr
(3)
Reset Active Time300ns
Clear Cycle Time3
µs
1. Wait 300 ns min. after the reset function is turned off.
2. Tacc=Tas + Tw + Tah
3. The Clear Cycle Time may be shortened by writing a
second Control Word with the Clear Bit disabled, 160 ns
after the first control word that enabled the Clear Bit.
Write Cycle Timing Diagram
Tas
FL, A3-A0
CE
Tces
WR
D7-D0
Tacc
Tw
Tds
Tah
Tdh
Tceh
Tbw
data wait data
write control
word-clear bit
enabled
wait 130 nswrite control
word-clear bit
enabled
The Flash RAM and Character RAM may not be accessed
until the Clear Cycle is complete.