Siemens HYM368025GS-50, HYM368025GS-60, HYM368025S-50, HYM368025S-60 Datasheet
8M x 36-Bit EDO - DRAM Module HYM 368025S/GS-50/-60
• SIMM modules with 8 388 608 words by 36-bit organization in two banks
for PC main memory applications
• Fast access and cycle time
50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)
• Hyper Page Mode (EDO) capability
20 ns cycle time (-50 version)
25 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
max. 6820 mW active (-50 version)
max. 6160 mW active (-60 version)
CMOS –132 mW standby
TTL –264 mW standby
• CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module (L-SIM-72-14) with 31.75 mm height
• Utilizes sixteen 4Mx4-EDO-DRAMs and eight 4M x 1 EDO-DRAMs
in 300 mil wide SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write parity applications
• Tin-Lead contact pads (S- version)
• Gold contact pads (GS - version)
Semiconductor Group 1
4.97
HYM 368025S/GS-50/-60
8M × 36-Bit EDO-Module
The HYM 368025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by 36Bit in two banks in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M × 4
EDO-DRAMs and eight HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages
mounted together with decoupling capacitors on a PC board.
Each HYB 5117405BJ and HYB 514105BJ is described in the data sheet and is fully electrical
tested and processed according to SIEMENS standard quality procedure prior to module assembly.
After assembly onto the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 368025S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type Ordering Code Package Description
HYM 368025S-50 L-SIM-72-14 EDO-DRAM Module
(access time 50 ns)
HYM 368025S-60 L-SIM-72-14 EDO-DRAM Module
(access time 60 ns)
HYM 368025GS-50 L-SIM-72-14 EDO-DRAM Module
(access time 50 ns)
HYM 368025GS-60 L-SIM-72-14 EDO-DRAM Module
(access time 60 ns)
Semiconductor Group 2
Pin Configuration
VSS 1 DQ0 2
DQ18 3 DQ1 4
DQ19 5 DQ2 6
DQ20 7 DQ3 8
DQ21 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
A10 19 DQ4 20
DQ22 21 DQ5 22
DQ23 23 DQ6 24
DQ24 25 DQ7 26
DQ25 27 A7 28
N.C. 29 VCC 30
A8 31 A9 32
RAS3
33 RAS2 34
DQ26 35 DQ8 36
HYM 368025S/GS-50/-60
8M × 36-Bit EDO-Module
Pin Names
A0-A10 Address Inputs
DQ0-DQ35 Data Input/Output
- CAS3 Column Address Strobe
CAS0
- RAS3 Row Address Strobe
RAS0
WE
V
CC
V
SS
PD Presence Detect Pin
N.C. No Connection
Read/Write Input
Power (+ 5 V)
Ground
DQ17 37 DQ35 38
VSS 39 CAS0
CAS2
41 CAS3 42
43 RAS0 44
CAS1
RAS1
45 N.C. 46
WE
47 N.C. 48
DQ9 49 DQ27 50
DQ10 51 DQ28 52
DQ11 53 DQ29 54
DQ12 55 DQ30 56
DQ13 57 DQ31 58
VCC 59 DQ32 60
DQ14 61 DQ33 62
DQ15 63 DQ34 64
DQ16 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
40
Presence Detect Pins
-50 -60
PD0 N.C. N.C.
PD1
PD2
PD3
V
SS
V
SS
V
SS
V
SS
N.C.
N.C.
Semiconductor Group 3
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