Siemens HYM328025GS-50, HYM328025GS-60, HYM328025S-50, HYM328025S-60 Datasheet

8M × 32-Bit EDO-DRAM Module HYM328025S/GS-50/-60

• SIMM modules with 8 388 608 words by 32-bit organization

for PC main memory applications

• Fast access and cycle time

50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)

• Hyper page mode (EDO) capability

20 ns cycle time (-50 version)
25 ns cycle time (-60 version)

• Single + 5 V (± 10 %) supply

• Low power dissipation

max. 5280 mW active (-50 version)
max. 4840 mW active (-60 version)
CMOS – 88 mW standby
TTL –176 mW standby

• CAS-before-RAS refresh

RAS-only-refresh
Hidden-refresh

• 16 decoupling capacitors mounted on substrate

• All inputs, outputs and clocks fully TTL compatible

• 72 pin Single in-Line Memory Module (L-SIM-72-15) with 25.40 mm height

• Utilizes sixteen 4Mx4-DRAMs in SOJ packages

• 2048 refresh cycles / 32 ms

• Optimized for use in byte-write non-parity applications

• Tin-Lead contact pads (S- version)

• Gold contact pads (GS -version)

Semiconductor Group 1

9.96

HYM328025S/GS-50/-60

8M × 32-Bit EDO-Module

The HYM 328025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by
32-bit in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M × 4 DRAMs in 300
mil wide SOJ-packages mounted together with sixteen 0.2 µF ceramic decoupling capacitors on a
PC board.

Each HYB 5117405BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.

The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 328025S/GS-60 dictates the use of early write cycles.

Ordering Information
Type Ordering Code Package Description

HYM 328025S-50 on request L-SIM-72-15 EDO-DRAM Module

(access time 50 ns)

HYM 328025S-60 Q67100-Q2330 L-SIM-72-15 EDO-DRAM Module

(access time 60 ns)

HYM 328025GS-50 Q67100-Q2098 L-SIM-72-15 EDO-DRAM Module

(access time 50 ns)

HYM 328025GS-60 Q67100-Q2099 L-SIM-72-15 EDO-DRAM Module

(access time 60 ns)

Semiconductor Group 2

Pin Configuration

VSS 1 DQ0 2
DQ16 3 DQ1 4
DQ17 5 DQ2 6
DQ18 7 DQ3 8
DQ19 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
A10 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
DQ23 27 A7 28
N.C 29 VCC 30
A8 31 A9 32
RAS3

33 RAS2 34

N.C. 35 N.C. 36

HYM328025S/GS-50/-60

8M × 32-Bit EDO-Module

Pin Names

A0-A10 Address Inputs
DQ0-DQ31 Data Input/Output

- CAS3 Column Address Strobe

CAS0

- RAS3 Row Address Strobe

RAS0
WE

V

CC

V

SS

PD Presence Detect Pin
N.C. No Connection

Read/Write Input
Power (+ 5 V)
Ground

N.C. 37 N.C. 38
VSS 39 CAS0

41 CAS3 42

CAS2
CAS1

43 RAS0 44

RAS1

45 N.C. 46

47 N.C. 48

WE
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72

40

Presence Detect Pins

-50 -60
PD0 N.C. N.C.
PD1
PD2
PD3

V

SS

V

SS

V

SS

V

SS

N.C.
N.C.

Semiconductor Group 3

HYM328025S/GS-50/-60

8M × 32-Bit EDO-Module

RAS0
CAS0

DQ0-DQ3

DQ4-DQ7

CAS1

DQ8-DQ11

DQ12-DQ15

RAS2
CAS2

DQ16-DQ19

DQ20-DQ23

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

CAS RAS

CAS RAS

CAS RAS

CAS RAS

CAS RAS

CAS RAS

D11

D0

D3

D4

D7

D8

RAS1

RAS3

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

I/O1-I/O4
OE

CAS RAS

D1

CAS RAS

D2

CAS RAS

D5

CAS RAS

D6

CAS RAS

D9

CAS RAS

D10

CAS3

CAS RAS

DQ24-DQ27

DQ28-DQ31

A0 - A10
WE
VCC

VSS

I/O1-I/O4
OE

CAS RAS
I/O1-I/O4
OE

D0 - D15
D0 - D15

C0 - C15

Block Diagram

Semiconductor Group 4

D12

D15

I/O1-I/O4
OE

I/O1-I/O4
OE

CAS RAS

D13

CAS RAS

D14