Siemens HYM324020GS-50, HYM324020S-50 Datasheet
4M x 32-Bit Dynamic RAM Module HYM 324020S/GS-50/-60
Advanced Information
• 4 194 304 words by 32-bit organization (alternative 8 388 608 words by 16-bit)
• Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
• Fast page mode capability
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
max. 5280 mW active (HYM 324020S/GS-50)
max. 4840 mW active (HYM 324020S/GS-60)
CMOS – 44 mW standby
TTL –88 mW standby
• CAS-before-RAS refresh
-only-refresh
RAS
Hidden-refresh
• 8 decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module with 22.86 mm (900 mil) height
• Utilizes eight 4Mx4-DRAMs in 300mil wide SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write non-parity applications
• Tin-Lead contact pads (S - version)
• Gold contact pads (GS - version)
Semiconductor Group 1
12.95
HYM 324020S/GS-50/-60
4M x 32-Bit
The HYM 324020S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by
32-bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRA Ms in 300
mil wide SOJ-packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a PC
board.
The HYM 324020S/GS-50/-60 can also be use d as a 8 388 608 words by 16-bi ts dynamic RAM
module by means of connectin g DQ0 and DQ16, DQ 1 and DQ17, DQ2 and DQ18, … , DQ15 an d
DQ31, respectively.
Each HYB 5117400BJ is described in the data sheet and is fully electrical tes ted and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324020S/GS-50/-60 dictates the use of ear ly write cyc les.
Ordering Information
Type Ordering Code Package Description
HYM 324020S-50 on request L-SIM-72-12 DRAM Module
(access time 50 ns)
HYM 324020S-60 Q67100-Q979 L-SIM-72-12 DRAM Module
(access time 60 ns)
HYM 324020GS-50 on request L-SIM-72-12 DRAM Module
(access time 50 ns)
HYM 324020GS-60 Q67100-Q2005 L-SIM-72-12 DRAM Module
(access time 60 ns)
Semiconductor Group 2
Pin Configuration
VSS 1 DQ0 2
DQ16 3 DQ1 4
DQ17 5 DQ2 6
DQ18 7 DQ3 8
DQ19 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
A10 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
DQ23 27 A7 28
N.C. 29 VCC 30
A8 31 A9 32
N.C. 33 RAS2
N.C. 35 N.C. 36
34
HYM 324020S/GS-50/-60
4M x 32-Bit
Pin Names
A0-A10 Address Inputs for
HYM 324020S/GS
DQ0-DQ31 Data Input/Output
CAS0
- CAS3 Column Address Strobe
RAS0
, RAS2 Row Address Stro be
WE
V
CC
V
SS
PD Presence Detect Pin
N.C. No Connection
Read/Write Input
Power (+ 5 V)
Ground
N.C. 37 N.C. 38
VSS 39 CAS0
41 CAS3 42
CAS2
CAS1
43 RAS0 44
N.C. 45 N.C. 46
47 N.C. 48
WE
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
40
Presence Detect Pins
-50 -60
PD0
V
SS
V
SS
PD1 N.C. N.C.
PD2
PD3
V
V
SS
SS
N.C.
N.C.
Semiconductor Group 3
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